Application_Note_QVL_Usage

Application_Note_QVL_Usage - Rev 5.0 03/04/09 Page 1 of 22...

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Unformatted text preview: Rev 5.0 03/04/09 Page 1 of 22 Overview This application note describes the usage for the Questa™ Verification Library (QVL) Monitors and Checkers in QuestaSim™ Verilog and VHDL simulation. This usage includes the instantiation, compilation, simulation and debug with the QVL monitors and checkers. AppNote 10031 Questa™ Verification Library (QVL) Monitor and Checker Usage By QuestaSim Support Questa release: 6.4d Last Modified: March 4, 2009 Copyright© 1995-2008 Mentor Graphics Corporation. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are trademarks of their respective owners. Rev 5.0 03/04/09 Page 2 of 22 Table of Contents Overview.................................................................................................................................................. 1 Table of Contents ..................................................................................................................................... 2 Introduction.............................................................................................................................................. 3 Step 1: Instantiating a QVL monitor or checker......................................................................................... 3 Step 2 (for VHDL; optional for Verilog): Compiling the QVL monitor and checker libraries ..................... 6 Step 3 (VHDL): Compiling & simulating your design with the QVL monitor or checker ........................... 7 Step 3 (Verilog): Compiling & simulating your design with the QVL monitor or checker .......................... 7 Step 4: Verifying & troubleshooting your QVL monitor (or checker) setup................................................ 8 Step 5: Reviewing and debugging simulation results with the QVL monitor .............................................. 9 Step 6: QVL monitor and checker coverage ............................................................................................ 10 Summary................................................................................................................................................ 11 Appendix A: Disabling QVL Monitor Assertions & Coverage................................................................. 12 Appendix B: Customizing QVL Monitor Assertions & Coverage ............................................................ 14 Appendix C: SystemVerilog Bind Example............................................................................................. 16 Appendix D: Compiling SystemVerilog Bind.......................................................................................... 19 Appendix D: Compiling SystemVerilog Bind....
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Application_Note_QVL_Usage - Rev 5.0 03/04/09 Page 1 of 22...

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