assert_timing_diagrams

assert_timing_diagrams - Timing Diagrams for Accellera...

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Unformatted text preview: Timing Diagrams for Accellera Standard OVL V2.1 assert_<checker> modules Mike Turpin / ARM 15 th September 2007 Contents s Introduction to OVL s Types of OVL s OVL Release History & Major Changes s pre-Accellera Apr 2003 s v1.0 May 2005 s v1.1, v1.1a, b Aug 2005 s v1.5 Dec 2005 s v1.6 Mar 2006 s v1.7 July 2006 s v1.8 Oct 2006 s V2.0 Jun 2007 (Beta in April) s V2.1 Sep 2007 s Introduction to Timing Diagrams s Timing Diagram Syntax & Semantics s Timing Diagram Template s Assert Timing Diagrams (alphabetical order) Types of OVL Assertion Combinatorial Assertions s assert_proposition, assert_never_unknown_async Single-cycle Assertions s assert_always, assert_implication, assert_range, … Sequential over 2 cycles s assert_always_on_edge, assert_decrement, … Sequential over num_cks cycles s assert_change, assert_cycle_sequence, assert_next, … Sequential between two events s assert_win_change, assert_win_unchange, assert_window Single-Cycle Combinatorial 2-Cycles n-Cycles Event-bound OVL Release History and Major Changes s pre-Accellera, April 2003 s Verilog updated in April, but VHDL still October 2002 s v1.0, May 2005 s Changed: s assert_change (window can no longer finish before num_cks-1 cycles) s assert_fifo_index (property_type removed from functionality) s assert_time/unchange (RESET_ON_NEW_START corner case) s v1.1, July 2005 s New: assert_never_unknown s Changed: s assert_implication: antece n dent_expr typo fixed s assert_change: window length fixed to num_cks s v1.1a, August 2005 s Fixed: assert_width s v1.1b, August 2005 (minor updates to doc) (page 1 of 4) OVL Release History and Major Changes s v1.5, December 2005 s New: s Preliminary PSL support s `OVL_IGNORE property_type s Fixed: assert_always_on_edge (startup delayed by 1 cycle) s v1.6, March 2006 s New: assert_never_unknown_async s v1.7, July 2006 s Consistent X Semantics & Coverage Levels s PSL support s v1.8, Oct 2006 s Bug fixes (page 2 of 4) OVL Release History and Major Changes s v2.0-Beta, April 2007 s ovl_<checker> modules (not documented here) s enable input & fire output (tied low in beta) s clock_edge, reset_polarity & gating_type parameters s 17 new ovl_<checker> modules (in SVA) s Preliminary VHDL release (10 checkers) s Bug fixes s v2.0, June 2007 s fire output implemented in top-10 Verilog OVLs s Also implemented in VHDL checkers s Still tied low in SVA & PSL versions s `OVL_ASSERT_2STATE & `OVL_ASSUME_2STATE s property_type values for local X-checking disable s Bug fixes (page 3 of 4) OVL Release History and Major Changes s v2.1, Sept 2007 s Bug fixes (page 4 of 4) Introduction to Timing Diagrams s Timing Diagram Syntax & Semantics s Timing Diagram Template clk Assertion Timing Diagram t t + 1 start_event test_expr “forall t” means timestep t can be any clock cycle “forall t” means timestep t can be any clock cycle Must Always Hold ASSERT forall t....
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This note was uploaded on 02/01/2012 for the course ING 101 taught by Professor James during the Spring '11 term at Universidad del Cauca.

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assert_timing_diagrams - Timing Diagrams for Accellera...

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