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Unformatted text preview: Questa™ Verification Library Checkers Data Book Software Version 2010.1a © 1991-2010 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND 03/97 U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.72023(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable. Contractor/manufacturer is: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Telephone: 503.685.7000 Toll-Free Telephone: 800.592.2210 Website: www.mentor.com SupportNet: supportnet.mentor.com/ Send Feedback on Documentation: supportnet.mentor.com/user/feedback_form.cfm TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a thirdparty Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’ trademarks may be viewed at: www.mentor.com/terms_conditions/trademarks.cfm. Table of Contents Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 7 Chapter 2 QVL Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QVL Use Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specify Global Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiate QVL Checkers/Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compile QVL Checker/Monitor Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compile and Simulate the DUT and QVL Components . . . . . . . . . . . . . . . . . . . . . . . . . . Troubleshoot the QVL Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Review and Debug Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Review Checker/Monitor Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Run Formal Verification with QVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QVL Checker Type Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checker Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checker Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checker Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checker Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assertion Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cover Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 10 12 15 16 17 18 19 21 22 22 22 23 24 25 25 Chapter 3 QVL Checker Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_assert_follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_assert_leader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_assert_timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_assert_together . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_back_pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_bits_off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_bits_on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_bus_driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_bus_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_change_timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_channel_data_integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_content_addressable_memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 28 35 39 44 48 50 53 55 57 61 67 71 80 82 92 95 Questa Verification Library Checkers Data Book, 2010.1a 3 Table of Contents qvl_data_loaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_data_used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_decoder_8b10b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_encoder_8b10b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_fifo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_gray_code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_hamming_distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_known . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_memory_access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_minimum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_multi_clock_fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_multi_clock_multi_enq_deq_fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_multi_clock_multi_port_memory_access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_multi_enq_deq_fifo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_multiplexor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_mutex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_outstanding_id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_parallel_to_serial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_req_ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_resource_share . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_same . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_same_bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_same_word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_scoreboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_serial_to_parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_state_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_three_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_value_coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_xproduct_bit_coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qvl_xproduct_value_coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 108 113 116 123 125 129 138 147 150 154 156 159 167 170 179 188 199 210 215 218 232 241 248 254 258 262 266 279 286 292 299 301 304 308 311 316 Appendix A QVL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Global Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macros Common to All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 323 323 324 Index End-User License Agreement 4 Questa Verification Library Checkers Data Book, 2010.1a Chapter 1 Introduction Syntax Conventions This manual uses the following command usage line syntax conventions. Table 1-1. Conventions for Command Line Syntax Convention Example Usage Boldface SET COMmand Editing A boldface font indicates a required argument. -Off | -Vi | -Emacs | -Gmacs EXIt [-Discard] Square brackets enclose optional arguments. Do not enter the brackets. Italic DOFile filename An italic font indicates a user-supplied argument. {} ADD LFsrs lfsr_name {Prpg | Misr} length seed [-Out | -In] Braces enclose arguments to show grouping. Do not enter the braces. | ADD LFsrs lfsr_name {Prpg | Misr} length seed [-Out | -In] The vertical bar indicates an either/or choice between items. Do not include the bar in the command. … ADD LFsr Connections primary_pin lfsr_name position… An ellipsis follows an argument that may appear more than once. Do not include the ellipsis when entering commands. The following examples demonstrate these syntax conventions. signal… One or more occurrences of signal. [-var req_signal] Zero or one occurrences of -var req_signal. -var {req_signal…} -var followed by one or more occurrences of req_signal. [std_option]… Zero or more occurrences of std_option. {arg1 arg2}… One or more occurrences of arg1 arg2. Questa Verification Library Checkers Data Book, 2010.1a 5 Introduction Syntax Conventions var1 | var2 | var3 constant | val1 val2 One occurrence of constant or val1 val2. {[var1][var2][var3]}… 6 One occurrence of var1or var2 or var3. Zero or more occurrences of any of var1, var2, and var3. Questa Verification Library Checkers Data Book, 2010.1a Introduction Mentor Graphics Support Mentor Graphics Support Mentor Graphics software support includes software enhancements, technical support, access to comprehensive online services with SupportNet, and the optional On-Site Mentoring service. For details, see: http://www.mentor.com/supportnet/options If you have questions about this software release, please log in to SupportNet. You may search thousands of technical solutions, view documentation, or open a Service Request online at: http://www.mentor.com/supportnet If your site is under current support and you do not have a SupportNet login, you may easily register for SupportNet by filling out the short form at: http://www.mentor.com/supportnet/quickaccess/SelfReg.do All customer support contact information can be found on our web site at: http://www.mentor.com/supportnet/support_offices.html Questa Verification Library Checkers Data Book, 2010.1a 7 Introduction Mentor Graphics Support 8 Questa Verification Library Checkers Data Book, 2010.1a Chapter 2 QVL Basics The Questa™ Verification Checkers Library (QVL checkers) is a set of assertion checkers that verify specific properties of a design. These checkers are instantiated in the design establishing a single interface for design validation. QVL checkers are instances of modules whose purpose in the design is to guarantee that certain conditions hold true. Assertion checkers are composed of one or more properties, a message, a severity and cover points. • A property is a design attribute that is being verified by an assertion. A property is classified as a combinational or temporal property. • A combinational property defines relations between signals during the same clock cycle. • A temporal property describes the relation between the signals over several (possibly infinitely many) cycles. • Message is the string that is displayed when an assertion fails. • Severity represents how serious a problem the error captured by the assertion is. • Cover points are flags, counters or variables that indicate whether or not (or how many times) specific events occur. QVL component instances maintain two types of cover points: statistics and corner cases. • Statistics measure activity of various parts of the circuit that the checker monitors. For example, the number of cycles the checker performs its checks. • Corner cases flag or count various oblique states of the circuit. These are unusual, hard to reach, or untypical events that represent the limits of the behavior of the part of the circuit the checker is analyzing. Robust simulation should cover all corner case events because these are typical sources of design bugs. Questa Verification Library Checkers Data Book, 2010.1a 9 QVL Basics QVL Use Model QVL Use Model To use QVL checkers in Questa simulation, perform the following steps: 1. Specify Global Macros 2. Instantiate QVL Checkers/Monitors 3. Compile QVL Checker/Monitor Libraries 4. Compile and Simulate the DUT and QVL Components 5. Troubleshoot the QVL Setup 6. Review and Debug Simulation Results 7. Review Checker/Monitor Coverage 8. Run Formal Verification with QVL Specify Global Macros You specify preferred control settings with standard global macros in either of the following ways: • Specify settings using the standard Verilog +define options in a simulation arguments file or at the command line. • Specify settings in a Verilog file loaded before the libraries. Note If you reference QVL_ defines in a Verilog file, you should have a ‘include "<qvl_install_dir>/qvl_src/qvl_checkers/std_qvl_defines.h" statement in the file. Otherwise, you must specify the -mfcu option to vlog. Enabling Assertion and Coverage Logic The QVL consists of two types of logic: assertion logic and coverage logic. These capabilities are enabled by defining the following standard global macros: QVL_ASSERT_ON QVL_COVER_ON Activates QVL assertion logic. Default: not defined. Activates QVL coverage logic. Default: not defined. If neither of these constants is defined, the QVL checkers are not activated. The instantiations of these checkers will have no influence on the verification performed. 10 Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Use Model Creating Cover Groups By default, when QVL coverage logic is enabled (by specifying QVL_COVER_ON), SystemVerilog cover groups are created. To disable cover groups, specify the following global macro: QVL_SV_COVERGROUP_OFF Disables creation of SystemVerilog covergroup logic. Default: not defined. Displaying Final Coverage Information When QVL coverage logic is enabled (by specifying QVL_COVER_ON), accumulated cover point data can be displayed for each QVL checker and monitor at the end of simulation. For example, the following output shows a sample mutex checker’s final coverage information: ------------------- Coverage for Mutex Checker -----------------Assertion instance is : dut.arbiter.fifo1.qvl_mutex_chx ------------------- Statistics for Mutex Checker ---------------Values Checked : 12027 ------------------- Cornercases for Mutex Checker --------------All Zero : 18 All Mutex Checked :1 By default, final coverage information is displayed for monitors, but not for checkers. To change this behavior, specify one or both of the following global macros: QVL_CW_FINAL_COVER Turns on the display of final coverage information for QVL checkers. Default: final coverage not displayed. QVL_MW_FINAL_COVER_OFF Turns off the display of final coverage information for QVL monitors. Default: final coverage is displayed. Instantiation in an SVA Interface Construct If QVL checkers are instantiated in a SystemVerilog interface construct, define the following global variable: QVL_SVA_INTERFACE Instantiates QVL assertion checkers in a SystemVerilog interface construct. Default: not defined. Resolving Race Conditions at QVL Inputs By default, the input signals of QVL checkers and monitors are sampled directly. In some cases, this results in race conditions on the sampled data. To resolve this problem, define the following global variable: QVL_RACE_AVOID Adds one resolution unit of delay (i.e., Verilog #1) to all QVL input signals. Default: zero delay. Questa Verification Library Checkers Data Book, 2010.1a 11 QVL Basics QVL Use Model Instantiate QVL Checkers/Monitors Instance Templates Directory questasim_install_dir/qvl_src/templates The QVL instance templates directory contains templates (Example 2-1) for specifying all checker and monitor instances from the QVL libraries. To instantiate a QVL checker or monitor into a design, it is easiest to cut and paste the instantiation from the associated template. The template lists the instance’s ports and the Verilog parameters or VHDL generics. Starting from the QVL template, set the parameters or generic mapping and modify the port mapping to point to local signals. Example 2-1. QVL Instance Templates Verilog qvl_change_timer #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .width(1), .min_check(0), .max_check(0)) qvl_change_timer_instance( .clk(dut_clk), .reset_n(dut_reset_n), .active(dut_active), .test_expr(dut_test_expr), .max(dut_max), .min(dut_min) ); Since you are using standard QVL defines (QVL_ERROR, QVL_ASSERT and so on), you must also include the std_qvl_defines.h file: ‘include "qvl_install_dir/qvl_src/qvl_checkers/std_qvl_defines.h" VHDL qvl_change_timer_instance: qvl_change_timer generic map( severity_level => QVL_ERROR, property_type => QVL_ASSERT, msg => "QVL_VIOLATION : ", coverage_level => QVL_COVER_ALL, width => 1, min_check => 0, max_check => 0) port map ( clk => dut_clk, reset_n => dut_reset_n, active => dut_active, test_expr => dut_test_expr, max => dut_max, min => dut_min ); 12 Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Use Model Adding Checker/Monitor Instances Add QVL checker/monitor instances to the simulation environment in any of the following ways: • Specify the instance in the testbench or DUT. To make the instance visible only during simulation: • • • Verilog — use an ‘ifdef. VHDL — use a conditional generate or an empty architecture. Specify the instance as a separate module, then use SVA bind to wire the DUT to the instance’s signals (see Example 2-2). SystemVerilog declares that by default, each file is a separate compilation unit. When bind is specified outside the module file that the program instance is being bound to, the elaboration process does not recognize the dependency to the bound module and the bind is not elaborated with the bound module. Therefore, you must use the -cuname option to name the compilation unit. Then, specify the compilation unit name to vsim to enable the bind statements to be elaborated as shown in the following example: vlog assertion_module.v bind.sv -cuname bind_cu vsim top bind_cu • Specify the instance in a PSL vunit, then bind the vunit to the target module (which connects the signals from the target module to the instance) as described in the Questa SV/AFV User’s Manual, chapter 18: Verification with Assertions and Cover Directives. • Specify the instance in a separate module, then connect the DUT to the instance’s ports using one of the following methods: • Verilog hierarchical references in wire declarations, for example: wire wire wire wire [2:0] • clk reset_n wr_en max = = = = TB.DUT.clk; TB.DUT.reset_n; TB_DUT.wr_en; TB.DUT.wr_hold_max; VHDL signal spy, for example: init_signal_driver init_signal_driver init_signal_driver init_signal_driver ("/TB/DUT/clk", "/clk", open, open, 0); ("/TB/DUT/reset_n", "/reset_n", open, open, 0); ("/TB/DUT/wr_en", "/wr_en", open, open, 0); ("/TB/DUT/wr_hold_max", "/max", open, open, 0); Be sure to specify the ModelSim library and package: library modelsim_lib; use modelsim_lib.util.all; Questa Verification Library Checkers Data Book, 2010.1a 13 QVL Basics QVL Use Model • Specify the instance as a SystemVerilog interface. • Set the +define+QVL_SVA_INTERFACE macro in the filelist.qvl file list or on the simulator command line. For example: vlog +define+QVL_SVA_INTERFACE... This replaces the instance’s module keyword with the interface keyword. • Add the QVL instance to a ANSI port declaration. and use hierarchical port references to wire the port signals to your DUT. For example: module cpu_top ( qvl_pci_monitor pci_mon_if, ... assign pci_mon_if.pci_ad_en_n assign pci_mon_if.pci_cbe_en_n = AD_enb; = 1’b0; If QVL checkers and monitors are instantiated in a VHDL design, you must specify the QVL library and QVL packages: library qvl_lib; use qvl_lib.qvl_checkers.all; use qvl_lib.qvl_monitors.all; Exclude the QVL components from code coverage by adding source code pragmas (coverage off/coverage on) around the QVL component instantiations as described in the Questa SV/AFV User’s Manual, chapter 16: Coverage. Example 2-2. Binding an Assertion Module to the DUT in SVA module assertion_module (clk, reset_n, wr_en, wr_hold_max); input clk; input reset_n; input wr_en; input [2:0] wr_hold_max; wire qvl_clk = clk; wire qvl_reset_n = reset_n; wire qvl_wr_en = wr_en; wire [2:0] qvl_max = wr_hold_max; // include define file to allow use of QVL defines ‘include "std_qvl_defines.h" qvl_change_timer #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .width(1), .min_check(1), .max_check(1)) qvl_change_timer_instance( .clk(qvl_clk), .reset_n(qvl_reset_n), 14 Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Use Model .active(1’b1), .test_expr(qvl_wr_en), .max(qvl_max), .min(1)); endmodule // Bind assertion_module to DUT with implicit port connections (.* syntax) module sample_bind; bind DUT assertion_module bind_instance (.*); endmodule Compile QVL Checker/Monitor Libraries VHDL simulation environments require a compiled version of the QVL checker/monitor library. This step is optional for Verilog simulation environments. To compile a version if the QVL library, modify and run the standard compile_qvl_lib C-shell script: questasim_dir/qvl_src/bin/compile_qvl_lib #!/bin/csh # Compile QVL packages into qvl_lib vlib qvl_lib vcom -work qvl_lib \ questasim_dir/qvl_src/vhdl_pkgs/qvl_checkers.vhd \ questasim_dir/qvl_src/vhdl_pkgs/qvl_monitors.vhd # Compile Verilog QVL Checker components into qvl_lib vlog -work qvl_lib +define+QVL_ASSERT_ON+QVL_COVER_ON \ +incdir+questasim_dir/qvl_src/qvl_checkers \ questasim_dir/qvl_src/qvl_checkers/*.sv # Compile Verilog QVL Monitor components into qvl_lib foreach mon ( questasim_dir/qvl_src/qvl_monitors/* ) vlog -work qvl_lib +define+QVL_ASSERT_ON+QVL_COVER_ON \ +incdir+questasim_dir/qvl_src/qvl_checkers \ questasim_dir/qvl_src/qvl_checkers/std_qvl_defines.h\ +incdir+$mon $mon/*.sv end To compile a protected (read-only) QVL library to be shared by your project team, add the -novopt option to the vlog and vcom commands. Users can then compile simulation environments both with, and without, vopt. Typically, questasim_dir is the same as the install directory of the Questa executables. However, it can be the install directory of a later Questa release (for example, if you are frozen into a particular Questa release, but want to use features/enhancements of the later QVL release). Caution Starting with QVL 2009.1, QVL was de-coupled from Questa releases. From this release onward, QVL directs vlog to print the QVL version. However, when using QVL with vlog version 6.5c (or earlier), you must specify +define+QVL_VERSION_PRINT_OFF as a vlog argument to prevent a vlog error. Questa Verification Library Checkers Data Book, 2010.1a 15 QVL Basics QVL Use Model Compile and Simulate the DUT and QVL Components Verilog Add the QVL Verilog arguments to your Verilog compilation arguments. Example 2-3 shows a sample simulator arguments file that references the QVL checkers and the AMBA monitor. The checkers are located in a single directory (qvl_src/qvl_checkers), but each monitor directory must be specified separately (for example: qvl_src/qvl_monitors/amba, qvl_src/qvl_monitors/amba_axi and so on). For example: >vlog compile_arguments -f filelist.qvl Once the design and testbench are compiled, your vsim simulation command needs no modifications. Run your vsim simulation command and the QVL components run in simulation similar to other SVA assertions. Example 2-3. Sample Verilog Simulator Arguments File // QVL Simulator Arguments File // Command line switches // ‘DEFINES +define+QVL_ASSERT_ON // Turn on QVL assertions +define+QVL_COVER_ON // Turn on QVL coverage //+define+QVL_SV_COVERGROUP_OFF // Turn off SV cover groups //+define+QVL_CW_FINAL_COVER // Display final checker cover info //+define+QVL_MW_FINAL_COVER_OFF // Don’t display final monitor cover info // File extensions +libext+.v +libext+.sv // Verilog wrapper files // SystemVerilog wrapper files // Include directories // -- QVL checkers +incdir+questasim_dir/qvl_src/qvl_checkers // -- QVL monitors (specify each monitor type). +incdir+questasim_dir/qvl_src/qvl_monitors/amba // // -y // -y Library directories -- QVL checkers questasim_dir/qvl_src/qvl_checkers -- QVL monitors questasim_dir/qvl_src/qvl_monitors/amba VHDL Compile your simulation environment as you would normally, using the vcom and vlog commands. Then add references to the QVL library to your simulation arguments. For example: >vsim simulation_arguments -L qvl_lib Run your vsim simulation command and the QVL components run in simulation similar to other SVA assertions. 16 Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Use Model Troubleshoot the QVL Setup Check your coverage. Verify that the checkers are recognizing the design logic functionality and monitors are recognizing transactions on the protocol interfaces. The checker coverage and monitor transactions are tracked in SystemVerilog cover groups, which you can track from the coverage report. If a checker or monitor is not recognizing DUT activity properly, troubleshoot the QVL setup as follows: 1. Check the connections to the checker/monitor instance and the instance’s generics/parameters. Check that the two resets (asynchronous and synchronous reset) are connected with the correct polarity. Typically, the DUT’s reset signal is connected to one reset and the other reset is tied to an inactive value. 2. View the simulation waveforms for the checker/monitor instance’s resets and clock. Ensure the reset polarities are correct and the resets are deasserting properly. Ensure the clock is toggling. 3. View the simulation waveforms for the checker/monitor instance’s ports. Ensure the driving signals are not unknown. 4. Check the instance’s coverage data. For a checker, ensure the design logic functionality exercised in simulation is consistent with the recorded coverage. For a monitor, ensure the protocol transactions exercised in simulation are consistent with the transactions recorded by the monitor. Questa Verification Library Checkers Data Book, 2010.1a 17 QVL Basics QVL Use Model Review and Debug Simulation Results During simulation checker/monitor violations are written to the simulation log file. Violation messages include the time, instance name and violation description. Violation messages are not generated for SVA assume properties that are set to constraints for formal verification. Viewing & Debugging Violations From the QuestaSim viewer, review the violations by checking the Assertions tab in the Analysis window (select View > Coverage > Assertions). The enabled value in the Failure column indicates that the failures are being tracked. The number of violations is shown in the Failure Count column. To view waveforms associated with a specific violation do one of the following: • Right-click on the violation in the Assertions tab and select Add to Wave > Selected Objects. • Find the instance name of the violation in the Assertions tab, select the same instance in the Workspace window, right-click in the Objects window and select Add to Wave > Signals in Region. To view internal signals for checkers and monitors, disable QuestaSim global optimization (vopt). For example, disable QuestaSim optimization during vopt using the +acc option or during vsim using the +acc or -novopt options. For example: >vopt +acc+qvl_amba_axi_monitor vopt_arguments Disables QuestaSim optimizations during vopt for all instances of qvl_amba_axi_monitor. >vsim -voptargs="+acc+qvl_amba_axi_monitor" vsim_arguments Disables QuestaSim optimizations during vsim for all instances of qvl_amba_axi_monitor. >vsim -novopt vsim_arguments Disables QuestaSim optimization during vsim for the entire simulation environment (it is not recommended to disable all optimizations). Note To run vsim with the -novopt option with pre-compiled libraries, the libraries must have been compiled with the -novopt option (or you must have write privileges to the compiled libraries). If not, vsim generates vcom-19 (“Failed to access library”) errors. 18 Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Use Model Disabling QVL Violations QVL checkers and monitors use SVA properties, so disabling violations is consistent with how QuestaSim handles SVA properties. From the QuestaSim command line, disable specific checker/monitor violations with the assertion fail command (see the Questa AFV User’s Manual): assertion fail [-action {continue | break | exit}] \ [-disable] [-enable] [-limit {count | none}] \ [-log {on | off}] [-recursive] path... For example, assume you get the following error: # ** Error: Assertion error. # Time: 140 ns Started: 140 ns Scope: ahb_tb.ahb_master_mon.qvl_ahb_master.qvl_assume_ASSERT_NEVER.M_AHB_M17 File:/questasim/qvl_src/qvl_monitors/amba/ qvl_ahb_master_monitor_assertions.inc Line: 365 You can disable this error with the following command: assertion fail -disable \ /ahb_tb. ahb_master_mon/qvl_ahb_master/qvl_assume_ASSERT_NEVER/M_AHB_M17\ -recursive Note Assertion and coverage information is saved to the UCDB and is not saved to the wlf file. Review Checker/Monitor Coverage Use the vsim command coverage report to generate a text report of the SystemVerilog and PSL assertion coverage results. For example: coverage report -details -file coverage.rpt -r /* For Verilog tests that use $finish, simulation might exit before the coverage report command executes. Add vsim commands that prevent simulation exit and resume vsim command execution. For example: set NoQuitOnFinish 1; onbreak {resume}; run -all; coverage report -details -file coverage.rpt -r /* After simulation, save the results to a unified coverage database (UCDB). For example: coverage save coverage.ucdb View assertion and coverage results in the QuestaSim viewer. For example: >vsim -viewcov coverage.ucdb Questa Verification Library Checkers Data Book, 2010.1a 19 QVL Basics QVL Use Model From the QuestaSim viewer, view the coverage and statistics information specific to the QVL checkers and monitors. Select the QVL instance in the Workspace window and select View > Coverage > Covergroups. Disabling QVL Cover Points The QVL checkers and monitors use SVA cover points to track coverage, so the mechanism for controlling coverage collection is consistent with all SVA cover points in Questa. To turn off specific cover points for a QVL checker, set their weights and goals to 0. For example, suppose tb/dut contains the following qvl_fifo instantiation: qvl_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .depth(2**DEPTH_POWER), .width(WIDTH), .pass(1), .registered(1), .high_water(15), .full_check(1), .empty_check(1), .value_check(1), .latency(0), .preload_count(0)) fifo_valid( .clk(CLK), .reset_n(reset_n), .active(1’b1), .enq(DIN_VALID), .deq(rd_en_i), .full(full_i), .empty(empty_i), .enq_data(din_un_i), .deq_data(dout_un_i), .preload(24’b0)); The cover groups for the qvl_fifo checker type are defined in the following file: questasim_dir/qvl_src/qvl_checkers/qvl_fifo_cover.inc This file shows the Simultaneous Enqueues and Dequeues cover point is defined in the fifo_cornercases cover group and has the name C3: covergroup fifo_cornercases @ (posedge clock); ... C3 : coverpoint (!($stable(simultaneous_enq_deq, @ (posedge clock)))) iff (enable_coverpoint){ bins Simultaneous_Enqueues_and_Dequeues = {1}; type_option.comment = "Simultaneous Enqueues and Dequeues"; } endgroup : fifo_cornercases 20 Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Use Model For this example, assume the logic driving the FIFO cannot produce a simultaneous enqueue/dequeue. So, the fifo_cornercases.C3 cover point for fifo_valid always has coverage 0% and the maximum possible coverage for the fifo_cornercases cover group is 75% (i.e., at most 3 out of 4 cover points can be hit). The following code in tb disables the Simultaneous Enqueues and Dequeues cover point (qvl_fifo_chx is the instance in the qvl_fifo module used to configure an internal version of the checker): initial begin dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.goal = 0; dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.weight = 0; end Setting the cover point weight to 0 removes the cover point from the calculation of the coverage for the parent cover group, so fifo_cornercases can attain 100% coverage. Setting the cover point goal to 0 makes the % of goal measure for the cover point 100% (instead of 0%). You should not disable all the cover points for a particular cover group. In this case, the weights of all the cover group’s cover points are 0. The calculation for cover group coverage divides by the total weight of the cover points (in this case 0), which results in a NaN value for the coverage. Run Formal Verification with QVL The QVL checkers and monitors are used as assumptions and assertion targets in formal verification (see the 0-In Formal Verification User Guide). The 0-In formal tool supports the inline specification, SVA bind and PSL vunit methods of QVL checker/monitor instantiation specified in “Instantiate QVL Checkers/Monitors” on page 12 — i.e., it does not support hierarchical references and VHDL signal spy connections. QVL components are pre-compiled in the 0-In formal verification tool installation, so you do not need to compile the QVL libraries. To compile a DUT with QVL components, add the -qvl option to the csl command line. The following example compiles a SystemVerilog bind module with the DUT using single-step compilation: >0in -cmd csl -d DUT DUT.v assertion_module.v bind.sv . . . The following example compiles a SystemVerilog bind module with the DUT using 2-step compilation: >0in -cmd analyze -vhdl DUT.vhdl -work work >0in -cmd analyze \ assertion_module.v bind.sv -cuname bind_cu -work work -qvl >0in -cmd csl -d DUT -cuname bind_cu -work work -qvl Questa Verification Library Checkers Data Book, 2010.1a 21 QVL Basics QVL Checker Type Specifications QVL Checker Type Specifications The data sheet for each checker type shows the following characteristics for checkers of that type: • Checker Schematic • Checker Class • Checker Syntax • Checker Parameters • Checker Ports • Assertion Checks • Cover Points • Statistics • Corner Cases Checker Schematic The schematic for a checker type shows the checker type name, the standard ports (clk, reset_n, and active) and other ports. port port ... port clk checker_type reset_n active Checker Class The checker class of a checker type indicates how a checker of that type behaves in relation to its clock input. QVL checkers are grouped in the following classes: • • Combinational assertions — behavior checked with combinational logic. • 22 Single-cycle assertions — behavior checked in the current cycle. 2-cycle assertions — behavior checked for transitions from the current cycle to the next. Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Checker Type Specifications • n-cycle assertions — behavior checked for transitions over a fixed number of cycles. • Event-bounded assertions — behavior is checked between two events. Checker Syntax checker_type [#(checker_parameters)] instance_name (checker_ports); Checker Parameters Each QVL checker has its own set of parameters as described in its corresponding data sheet. The standard parameters (severity_level, property_type, msg, and coverage_level) are common to all checkers. These are always the first four parameters for every checker (in that order). Parameters specific to the checker type (for example, a width parameter for a test expression) are listed after the standard parameters. Determinate values for parameters are defined in the standard macros header file (std_qvl_defines.h). severity_level The severity level determines how to handle an assertion violation. Possible values are: QVL_FATAL Runtime fatal error. QVL_ERROR (default) Runtime error. QVL_WARNING Runtime warning. QVL_INFO No improper design functionality. If QVL_ASSERT_ON is defined and severity_level is not one of these values, the checker issues the following message: Illegal option used in parameter ’severity_level’ property_type The property type determines whether to use the assertion as an assert property, an assume property (for example, a property that a formal tool uses to determine legal stimulus) or to ignore the assertion. Possible values are: QVL_ASSERT (default) All the assertion checker’s checks are asserts. QVL_ASSUME All the assertion checker’s checks are assumes. QVL_IGNORE All the assertion checker’s checks are ignored. Questa Verification Library Checkers Data Book, 2010.1a 23 QVL Basics QVL Checker Type Specifications If QVL_ASSERT_ON is defined and property_type is not one of these values, an assertion violation occurs and the checker issues the following message: Illegal option used in parameter ’property_type’ A single assertion checker cannot have some checks asserts and other checks assumes. However, you often can implement this behavior by specifying two checkers. msg The default message issued when a QVL assertion fails is “QVL_VIOLATION”. The msg parameter changes the message for the checker. coverage_level The coverage level is whether or not to enable coverage monitoring for the checker. Possible values are: QVL_COVER_ALL (default) Enable coverage monitoring. QVL_COVER_NONE Disable coverage monitoring. If QVL_ASSERT_ON is defined and coverage_level is not one of these values, an assertion violation occurs and the checker issues the following message: Illegal option used in parameter ’coverage_level’ For future enhancement, the following coverage levels are reserved: QVL_COVER_SANITY 1 QVL_COVER_BASIC 2 QVL_COVER_CORNER 4 QVL_COVER_STATISTIC 8 Checker Ports clk Port All QVL edge-triggered checkers have a clock port named clk. All sampling and assertion checking of these checkers is performed on the rising-edge of clk. 24 Questa Verification Library Checkers Data Book, 2010.1a QVL Basics QVL Checker Type Specifications reset_n Port All QVL checkers have an active-low reset port named reset_n. Reset on all edge-triggered assertion checkers is active-low, and is synchronous to clk. When the signal driving a checker’s reset port is sampled FALSE (i.e. asserted), the checker’s internal state is reset—however, cover point data are not cleared. active Port All QVL checkers have an activation port named active. Unless in a reset state, a checker performs assertion checks (if enabled) and collects cover point data (if enabled) only during cycles when its active input is sampled TRUE. For those cycles that a checker is inactive, the checker retains existing cover point data (even when the checker is reset). Assertion Checks When QVL_ASSERT_ON is defined, each assertion checker verifies that its parameter values are legal. If an illegal option is specified, the assertion fails. The assertion checker also checks at least one assertion. Violation of any of these assertions is an assertion failure. The “Assertion Check” section of a checker’s data sheet shows the various failure types for the assertion checker (except for incorrect option values for severity_level, property_type and coverage_level). For example, the mutex checker data sheet shows the following assertion failure: QVL_MUTEX Bits of test_expr are not mutually exclusive. Cover Points Each checker data sheet shows the cover points monitored by the checker when coverage is enabled (QVL_COVER_ON) and coverage_level for the checker is QVL_COVER_ALL. Checkers maintain two sets of cover points: statistics and corner cases. A checker’s cover points retain accumulation data after initialization, even when the checker is reset or becomes inactive. Statistics Statistics are cover points that measure the accumulation of particular standard events. For example, the following is a statistic for the mutex checker: Values Checked Number of times test_expr contained a new value when active was TRUE. Questa Verification Library Checkers Data Book, 2010.1a 25 QVL Basics QVL Checker Type Specifications Corner Cases Corner cases are cover points that indicate or count the occurrences of certain non-standard events of interest. Whereas statistics measure the activity of the relevant circuit, corner cases are targets for exercising oblique behavior of the circuit. For example, the following cover points are corner cases for the mutex checker: All Mutex Checked If non-zero, every test_expr bit was sampled 1 at some point. All Zero Number of times test_expr was sampled when no bits were 1. 26 Questa Verification Library Checkers Data Book, 2010.1a Chapter 3 QVL Checker Data Sheets Each QVL assertion checker type has a data sheet that provides the specification for checkers of that type. This chapter lists the checker data sheets in alphabetical order by checker type. Data sheets contain the following information: • Syntax Syntax statement for specifying a checker of the type, with: • • • Parameters — parameters that configure the checker. Ports — checker ports. Description Description of the functionality and usage of checkers of the type, with: • • Cover Points — cover messages with descriptions. • Errors* — possible errors that are not assertion failures. • • Assertion Checks — violation types (or messages) with descriptions of failures. Notes* — notes describing any special features or requirements. See also List of other similar QVL checker types. • Examples Examples of assertion checker instances and applications. * not applicable to all checker types. Questa Verification Library Checkers Data Book, 2010.1a 27 QVL Checker Data Sheets qvl_arbiter qvl_arbiter Ensures that an arbiter conforms to a specified arbitration scheme and that no more than one grant asserts at any time. req[width-1:0] qvl_arbiter gnt[width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width req_type gnt_type deassert_count park min max max_gnt_cycles no_simultaneous_req_gnt Class: event-bounded assertion Application: control and interface Syntax qvl_arbiter [#(severity_level, property_type, msg, coverage_level,width, req_type, gnt_type, deassert_count, park, min, max, max_gnt_cycles, no_simultaneous_req_gnt)] instance_name (clk, reset_n, active, req, gnt); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg coverage_level width req_type 28 Error message printed when assertion fails. Default: "QVL_VIOLATION : ". Coverage level. Default: ‘QVL_COVER_ALL Width of the req and gnt ports. Default: 2 bits. Type of behavior req signals use to indicate valid outstanding requests. req_type = 0 (Default) A channel has an outstanding request any cycle that its req signal is asserted and its gnt signal is deasserted. If a channel’s req signal deasserts while gnt is deasserted, the request is no longer outstanding. Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_arbiter req_type = 1 A channel has an outstanding request from the cycle its req signal asserts to the cycle its gnt signal is asserted. If a channel’s req signal deasserts in a cycle before the arbiter asserts gnt, the request is still outstanding. In addition, this parameter value turns on the single_req_per_channel check. If a channel has an outstanding request and reasserts req, then a single_req_per_channel violation occurs. req_type = 2 A channel has an outstanding request from the cycle its req signal asserts to the cycle its gnt signal is asserted. In addition, this parameter value turns on the req_until_gnt check. If a channel’s req signal deasserts while gnt is deasserted, then a req_until_gnt violation occurs. gnt_type Arbitration scheme used by the arbiter. This parameter turns on the corresponding check for the arbitration scheme. gnt_type = 0 (Default) no scheme gnt_type = 1 priority gnt_type = 2 fair gnt_type = 3 queue gnt_type = 4 round robin gnt_type = 5 least-recently used deassert_count Count (in cycles) to use for the deassert check. deassert_count = 0 (Default) Turns off the deassert check. deassert_count > 0 Turns on the deassert check if req_type = 2. park Type of grant parking behavior the arbiter uses for cycles with no outstanding requests. park = 0 (Default) Park check is turned off. width ≥ park > 0 Specified-grant park check is turned on. If no request is outstanding, the channel matching the value of park should receive the grant. Known_grant checks for the parking channel are turned off. park > width Any-grant park check is turned on. If no request is outstanding, one of the channels should receive the grant. Known_grant checks are turned off for all channels. Questa Verification Library Checkers Data Book, 2010.1a 29 QVL Checker Data Sheets qvl_arbiter min Lower limit on the number of cycles it takes for an outstanding request to receive a grant. min = 0 (Default) Min check is turned off. min > 0 Min check is turned on. Each request should be outstanding for at least min cycles before receiving a grant. max Upper limit on the number of cycles it takes for an outstanding request to receive a grant. If min is specified and max < min, then a compile error occurs and the checker is not created. max = 0 (Default) Max check is turned off. max > 0 Max check is turned on. Each request should be outstanding for no more than max cycles before receiving a grant. max_gnt_cycles Upper limit on the number of cycles a gnt signal should assert when servicing a request. (Parked grants do not service requests.) max_gnt_cycles = 0 (Default) Max_gnt_cycles check is turned off. max_gnt_cycles > 0 Max_gnt_cycles check is turned on. A grant issued in response to a request should not be held asserted for more than max_gnt_cycles cycles. no_simultaneous_ req_gnt How to handle the simultaneous assertion of a gnt signal and its requesting req signal. no_simultaneous_req_gnt = 0 (Default) Asserting a gnt signal in response to a request initiated in the same cycle is considered a grant issued to the channel. no_simultaneous_req_gnt = 1 Asserting a gnt signal in response to a request initiated in the same cycle is not considered a grant issued to the channel. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check arbitration. req[width-1:0] Concatenation of request signals. gnt[width-1:0] Concatenation of grant signals. 30 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_arbiter Description The qvl_arbiter assertion ensures that an arbiter conforms to a specified arbitration scheme and that no more than one grant asserts at any time. The widths of the req and gnt inputs are defined by the width parameter. Since at least 2 requests and grants are needed to perform arbitration, the default width of req and gnt signals is 2. When the active input of the checker is asserted, the checker performs these checks depending on the parameters used to configure the checker. Assertion Checks SINGLE_GRANT More than one grant issued in the same cycle. Multiple grants should not be issued. KNOWN_GRANT Grant is issued to a channel which had no request. width ≥ park Grants should not be issued to a channel that did not request one. If the specific-grant park check is on (width ≥ park > 0), the known grant check for the parking channel is turned off. PRIORITY Grant is issued to a different channel when a request from a channel with higher priority was outstanding. gnt_type = 1 Highest priority request should receive the grant. Priority of the requests is decided by the order of each req signal. LSB has highest priority and MSB has lowest priority. FAIR Grant is issued to a different channel when the request from a fair channel was outstanding. gnt_type = 2 No channel should receive more than one grant while another channel has an outstanding request. QUEUE Grant is issued to a different channel when the request from a channel next in the queue was outstanding. gnt_type = 3 Requests should be granted in the order received. Questa Verification Library Checkers Data Book, 2010.1a 31 QVL Checker Data Sheets qvl_arbiter ROUND_ROBIN Grant is issued to a different channel when the request from a channel next in the round robin was outstanding. gnt_type = 4 Grants to the requested channels should follow a round-robin arbitration scheme. Channel ordering defines the initial round-robin priority. Round-robin arbitration is similar to priority arbitration, but it is also fair. Round-robin arbitration assigns request channel priority dynamically after each channel grant. Once a request is granted, that channel becomes the lowest priority and the next channel has the highest priority. Priority order wraps from the last channel in the req argument list to the first channel in the list. For example, for {req4,req3,req2,req1} the initial channel priority order is: (high) req1 —> req2 —> req3 —> req4 (low) When req1 is granted, channel priority order becomes: (high) req2 —> req3 —> req4 —> req1 (low) LEAST_RECENTLY_ USED Grant is issued to a different channel when the request from a least recently used channel was outstanding. gnt_type = 5 Grants to the requested channels should follow an LRU (least-recently used) arbitration scheme. Channel ordering defines the initial LRU priority. Once all of the channels have been granted, the grant order depends on the least-recently used channels. For example, for {req4,req3,req2,req1} the initial channel priority order is: (least) req1 —> req2 —> req3 —> req4 (most) Assume that channels were granted in the order: req1 –> req2 –> req3 –> req4 and then req1 and req3 become outstanding. The next grant goes to gnt1 because req1 is the least-recently used channel. 32 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_arbiter PARK No grant is issued to the specified park channel. width ≥ park > 0 Specified-grant parking: A grant should be issued at all times. If no request is outstanding, the channel matching the value of park should receive the grant. This check disables the known_grant check for the specified parking channel. No channel is parked when any_park is specified. park > width Any-grant parking: A grant should be issued at all times. If no request is outstanding, any channel can receive the grant. This check disables the known_grant check. SINGLE_REQ_PER_ CHANNEL More than one request on a single channel without a grant for the previous request on that channel. req_type = 1 A channel with an outstanding request should not issue a new request. When this check is on, request signals are latched. A request is outstanding until the channel receives a grant, even if the request signal deasserts. When this check is off, a request is outstanding only if the req signal is asserted. REQ_UNTIL_GRANT Request on the channel deasserted before the corresponding grant was issued. req_type = 2 A channel with an outstanding request should not deassert the request before receiving a grant. This check fires at most once per request. DEASSERT Request was not deasserted before the specified number of cycles after the corresponding grant deasserted. (req_type = 2) and (deassert_count > 0) Starting the cycle after its gnt signal deasserts, a channel’s req signal should not remain asserted for longer than deassert_count cycles. This check fires each cycle a violation occurs. MIN Grant for the channel was asserted before the specified minimum number of cycles after the corresponding request. min > 0 A channel’s request should be outstanding for at least min cycles. This check fires at most once per request. Questa Verification Library Checkers Data Book, 2010.1a 33 QVL Checker Data Sheets qvl_arbiter MAX Grant for the channel was not asserted before the specified maximum number of cycles after the corresponding request. ≥ min) A channel’s request should not be outstanding for more than max cycles. This check fires each cycle a violation occurs. (max > 0) and (max MAX_GRANT Grant for a channel asserted for more than the specified maximum grant cycles. max_gnt_cycles > 0 Starting the cycle its gnt signal asserts, a channel’s gnt signal should not remain asserted for longer than max_gnt_cycles cycles. This check fires each cycle a violation occurs. Except if the park check is on, the parked grant is allowed to stay asserted longer than max_gnt_cycles cycles to the cycle a new request is made. If the parked grant is still asserted, a max_grant violation occurs. Cover Points Corner Cases All Requests Asserted If non-zero, all requests asserted. All Grants Asserted If non-zero, all grants asserted. Requests Outstanding for Max Cycles Number of times a request was outstanding for max cycles. Valid only if max check is on. Requests Outstanding for Min Cycles Number of times a request was outstanding for only min cycles. Valid only when min check is on. Grant Asserted for Max Grant Cycles Number of times a grant was asserted for max_gnt_cycles cycles. Valid only when max_grant check is on. Statistics Requests Number of cycles in which at least one request was asserted. Grants Number of cycles in which a grant was asserted. Simultaneous Requests and Grants Number of cycles in which both a request and a grant were asserted. See also qvl_req_ack 34 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_follower qvl_assert_follower Ensures that a follower signal asserts after its leader within a specified time window. Parameters: severity_level property_type msg coverage_level leader qvl_assert_follower follower clk reset_n min max max_leaders known_follower_check active Class: event-bounded assertion Application: interface Syntax qvl_assert_follower [#( severity_level, property_type, msg, coverage_level, max_leaders, max, min, known_follower_check)] instance_name (clk, reset_n, active, leader, follower); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. min Minimum number of clock cycles after a leader signal asserts that the corresponding follower signal can assert. Default: 0 (follower can assert in the same cycle its leader asserts). max Maximum number of clock cycles after a leader signal asserts that the corresponding follower signal can assert. If specified, max must be ≥ min. Default: 0 (follower must assert in the same cycle its leader asserts). max_leaders Maximum number of leaders that can be outstanding. Default: 16. known_follower_ check Whether or not to perform known_follower checks. known_follower_check = 0 (Default) Turns off the known_follower check. known_follower_check = 1 Turns on the known_follower check. Questa Verification Library Checkers Data Book, 2010.1a 35 QVL Checker Data Sheets qvl_assert_follower Ports clk Clock event for the assertion. The assertion samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. leader Leader signal. Leader and follower are single-bit paired variables. Each cycle that a leader signal is sampled asserted constitutes a unique leader and an associated time window (which opens min cycles after the current cycle and closes max cycles after the current cycle). follower Follower signal. Description The qvl_assert_follower checker ensures that follower asserts after leader within a specified time window. The checker checks the leader and follower signals at each rising edge of clk whenever active is TRUE. If leader is TRUE, a time window opens min cycles after the current cycle. The window closes when follower is TRUE or max cycles after the current cycle, whichever comes first. If follower is TRUE before the window opens or if the window closes and follower is not TRUE, an assert_follower check violation occurs. If an instance of the leader is already outstanding and leader is TRUE, a new instance of the leader becomes outstanding. However, if the number of outstanding leaders exceeds max_leaders (after any follower is processed) , a max_leaders check violation occurs and the leader is not considered outstanding. Setting the known_follower_check to 1 turns on the known_follower check. If no leaders are pending and follower is TRUE, a known_follower check violation occurs (unless min is 0 and leader is TRUE). Uses: Handshake, req_ack, request, acknowledge, ready, take, hold, wait, bridge, transactions, switch, packet, IDs, tokens, interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (IOs), pipeline, dataflow, datapath, temporal, time, window. 36 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_follower Assertion Checks ASSERT_FOLLOWER Follower asserted before the minimum cycles after leader. min > 0 Leader was TRUE and then its corresponding follower asserted before min cycles after the leader. Follower did not assert within the maximum cycles after leader. max = 0 Leader is TRUE but follower is FALSE. max > 0 Leader was TRUE but its corresponding follower did not assert for max cycles after the leader. MAX_LEADERS Leader asserted when the maximum number of leaders was outstanding, but its follower did not assert in the same cycle. Max_leaders leaders were outstanding and both leader and follower were FALSE. KNOWN_FOLLOWER Follower asserted when no leaders were outstanding, but its leader did not assert in the same cycle. No leaders were outstanding and follower was TRUE, but leader was FALSE. Cover Points Corner Cases Minimum Response Time Equals ‘min’ Number of times the associated follower asserted at min clock cycles after the corresponding leader asserted. Maximum Response Time Equals ‘max’ Number of times the associated follower asserted at max clock cycles after the corresponding leader asserted. Statistics Windows checked Number of windows checked. See also qvl_assert_leader qvl_assert_together Questa Verification Library Checkers Data Book, 2010.1a 37 QVL Checker Data Sheets qvl_assert_follower Examples qvl_assert_follower #( .max(0)) U0 ( .clk(clk), .reset_n(reset === 1’b0), .active(active === 1’b1), .leader(ldr), .follower(flwr)); Checks that flwr asserts during the same clock cycle in which ldr asserts. qvl_assert_follower #( .max(2), .min(1), .known_follower_check(1)) U1 ( .clk(clk), .reset_n(reset === 1’b0), .active(active === 1’b1), .leader(ldr), .follower(flwr)); Checks that flwr asserts within at least one clock cycle and at most two clock cycles after ldr asserts. qvl_assert_follower #( .max(3), .max_leaders(2)) U1 ( .clk(clk), .reset_n(reset === 1’b0), .active(active === 1’b1), .leader(ldr), .follower(flwr)); Checks that flwr asserts within three clock cycles after ldr asserts. This directive shows the pipelined behavior of the checker where ldr asserted on consecutive clocks must match assertions of flwr on succeeding clock cycles. The assertion of ldr for three consecutive clock cycles (that is, cycle 2, 3 and 4) cause the max_leaders check to fire on cycle 5. The assertion of ldr on cycle 2 is matched with the assertion of flwr on cycle 5. Similarly, the assertion of ldr on cycle 3 is matched to flwr on cycle 6. 38 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_leader qvl_assert_leader Ensures that a leader signal asserts before its follower within a specified time window. Parameters: severity_level property_type msg leader qvl_assert_leader follower clk reset_n active coverage_level min max max_leaders Class: event-bounded assertion Application: interface Syntax qvl_assert_leader [#(severity_level, property_type, msg, coverage_level, min, max, max_leaders)] instance_name (clk, reset_n, active, leader, follower); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. min Minimum number of clock cycles before a follower signal asserts that the corresponding leader signal can assert. Default: 0 (leader can assert in the same cycle its follower asserts). max Maximum number of clock cycles before a follower signal asserts that the corresponding leader signal can assert. Any leader that asserts before max cycles is not considered outstanding. If specified, max must be ≥ min. Default: 0 (leader must assert in the same cycle its follower asserts). max_leaders Maximum number of leaders that can be outstanding. Any leader that asserts when max_leaders leaders are outstanding is not considered outstanding. This parameter is typically specified when max is not specified. max = 0 Default max_leaders is 16. max > 0 Default max_leaders is 0 (i.e., no leaders can be assumed outstanding). Questa Verification Library Checkers Data Book, 2010.1a 39 QVL Checker Data Sheets qvl_assert_leader Ports clk Clock event for the assertion. The assertion samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. leader Leader signal. follower Follower signal. Leader and follower are single-bit paired variables. Each cycle that a follower signal is sampled asserted constitutes a unique follower and an associated time window (which opened max cycles before the current cycle and closed min cycles before the current cycle). Description The qvl_assert_leader checker ensures that leader asserted before follower within a specified time window. The checker checks the leader and follower signals at each rising edge of clk whenever active is TRUE. If leader is TRUE, the checker verifies that the last cycle leader was sampled TRUE occurred in the time window beginning max cycles before the current cycle and ending min cycles before the current cycle. The default case where neither min nor max are specified, the time window is the current cycle. If leader was not TRUE in the time window, an assert_leader check violation occurs. The qvl_assert_leader checker can handle multiple leaders as “outstanding.” When you specify a positive value for max_leaders, the checker identifies each cycle in which leader is TRUE as an outstanding leader. The first currently-outstanding leader is the leader used for the assert_leader check. At most, max_leaders leaders can be outstanding. If leader is sampled TRUE when max_leaders leaders already are outstanding, the new leader is ignored (unless follower is TRUE also). The special case where both max and max_leaders are zero (i.e., the defaults) but min is non-zero, correspond to the case where max is arbitrarily large and max_leaders is 16. Uses: Handshake, req_ack, request, acknowledge, ready, take, hold, wait, bridge, transactions, switch, packet, IDs, tokens, interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (IOs), pipeline, dataflow, datapath, temporal, time, window. 40 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_leader Assertion Checks ASSERT_LEADER Leader was not asserted within the window. max = min = 0 Follower is TRUE but leader is FALSE. max > min = 0 Follower is TRUE but leader was always FALSE, or the outstanding leader corresponding to follower asserts more than max cycles before the current cycle. max ≥ min > 0 Follower is TRUE but leader was always FALSE, or the outstanding leader corresponding to follower asserts before max cycles before the current cycle or after min cycles before the current cycle. Cover Points Corner Cases Minimum Response Time Equals ‘min’ Number of times the associated leader asserted at min clock cycles before the corresponding follower asserted. Maximum Response Time Equals ‘max’ Number of times the associated leader asserted at max clock cycles before the corresponding follower asserted. Statistics Windows Checked Number of windows checked. See also qvl_assert_follower qvl_assert_together Examples qvl_assert_leader #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL)) AL1( .clk(clock), .reset_n(1’b1), .active(1’b1), .leader(ldr), .follower(flwr)); Checks that ldr asserts during the same clock cycle in which flwr asserts. Questa Verification Library Checkers Data Book, 2010.1a 41 QVL Checker Data Sheets qvl_assert_leader qvl_assert_leader #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .min(2)) AL2 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .leader(ldr), .follower(flwr)); Checks that ldr asserts at least 2 cycles before flwr asserts. qvl_assert_leader #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .max_leaders(2)) AL3 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .leader(ldr), .follower(flwr)); Checks that flwr is preceded or asserted together by a ldr. At the most 2 leaders can be considered outstanding. qvl_assert_leader #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .min(1), .max(2)) AL4 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .leader(ldr), .follower(flwr)); Checks that ldr asserts at least one clock cycle and at most two clock cycles before flwr asserts. 42 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_leader qvl_assert_leader #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .min(1), .max_leaders(4)) AL5 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .leader(ldr), .follower(flwr)); Checks that ldr asserts at least one clock cycle before flwr asserts and a maximum of four leaders can be outstanding. Questa Verification Library Checkers Data Book, 2010.1a 43 QVL Checker Data Sheets qvl_assert_timer qvl_assert_timer Ensures that a signal asserts for specified times. test_expr qvl_assert_timer min[31:0] max[31:0] clk reset_n active Parameters: severity_level property_type msg coverage_level min_check max_check Class: event-bounded assertion Application: interface Syntax qvl_assert_timer [#(severity_level, property_type, msg, coverage_level, min_check, max_check)] instance_name (clk, reset_n, active, test_expr, min, max); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. min_check Whether or not to perform min checks. min_check = 0 (Default) Turns off the min check. min_check = 1 Turns on the min check. max_check Whether or not to perform max checks. max_check = 0 (Default) Turns off the max check. max_check = 1 Turns on the max check. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. 44 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_timer test_expr Variable or expression to check. min[31:0] Minimum number of cycles test_expr must be held asserted if min_check is 1. max[31:0] Maximum number of cycles test_expr can be held asserted if max_check is 1. Description The qvl_assert_timer checker ensures that test_expr asserts for a specified time. By default, the checker performs no assertion checks. Setting min_check to 1 turns on the min check and setting max_check to 1 turns on the max check. Turning min and max checks on also turns on the min_gt_max check. If all checks are on, the checker checks the test_expr signal and the min/max values at each rising edge of clk whenever active is TRUE. If min > max, a min_gt_max check violation occurs. Otherwise, unless both min and max are 0, an event window opens if any of the following occur: • Test_expr has transitioned to TRUE. • Test_expr is TRUE and a check violation occurred in the previous cycle. • Test_expr is TRUE and min and max were both 0 in the previous cycle. When the event window opens, the values of min and max are stored and no new event window can open. Then, the checker checks test_expr each subsequent cycle until one of the following events occurs: • Test_expr is FALSE. If the number of subsequent cycles ≥ min, a min check violation occurs. • The number of subsequent cycles = max + 1. If test_expr is still TRUE a max check violation occurs. When one of these events occurs, the event window closes and the checker returns to the state of monitoring test_expr, min and max in the next clock cycle. The qvl_assert_timer checker can be configured to perform only the min or the max checks. Uses: Bridge, transactions, switch, packet, IDs, tokens, interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (I/Os), pulse width, temporal, time, window. Questa Verification Library Checkers Data Book, 2010.1a 45 QVL Checker Data Sheets qvl_assert_timer Assertion Checks MIN Expression asserted for less than the minimum number of cycles. min_check = 1 Test_expr was TRUE for fewer than min consecutive cycles, then transitioned to FALSE. MAX Expression asserted for more than the maximum number of cycles. max_check = 1 Test_expr was TRUE for max + 1 consecutive cycles. MIN_GT_MAX Min value was greater than max value. min_check = 1 and max_check = 1 Test_expr was TRUE when the event window was closed, but min was > max. Cover Points Corner Cases Signal Asserted for ‘min’ Cycles Number of times test_expr asserted for min cycles. Meaningful only if min_check is 1. Signal Asserted for ‘max’ Cycles Number of times test_expr asserted for max cycles. Meaningful only if max_check is 1. Statistics Assertions Checked Number of times test_expr transitioned to TRUE (i.e., number of event windows). See also qvl_change_timer 46 qvl_timeout Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_timer Examples qvl_assert_timer #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_ASSERT_TIMER Violation"), .coverage_level(‘QVL_COVER_ALL), .min_check(1)) QVL_ASSERT_TIMER ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr(a>b), .max(1), .min(2)); Checks that the signal (passed as a>b to test_expr) asserts for at least two cycles. qvl_assert_timer #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_ASSERT_TIMER Violation"), .coverage_level(‘QVL_COVER_ALL), .max_check(1)) QVL_ASSERT_TIMER ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr(a>b), .max({{28’b{1’b0}}, bus[3:0]}), .min(1)); Checks that the signal (passed as a>b to test_expr) does not assert longer than the number of clock cycles that was sampled on bus[3:0] when the signal (passed as a>b to test_expr) asserted. qvl_assert_timer #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_ASSERT_TIMER Violation"), .coverage_level(‘QVL_COVER_ALL), .max_check(1), .min_check(1)) QVL_ASSERT_TIMER ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr(valid_data), .max(4), .min(2)); Checks that signal valid_data asserts for at least two cycles and no more than four cycles. Questa Verification Library Checkers Data Book, 2010.1a 47 QVL Checker Data Sheets qvl_assert_together qvl_assert_together Ensures that two signals assert together. test_expr1 qvl_assert_together msg coverage_level Class: single-cycle assertion test_expr2 clk Parameters: severity_level property_type reset_n active Application: control and interface Syntax qvl_assert_together [#(severity_level, property_type, msg, coverage_level)] instance_name (clk, reset_n, active, test_expr1, test_expr2); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. test_expr1 Signal that should assert when test_expr2 asserts. test_expr2 Signal that should assert when test_expr1 asserts. 48 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_assert_together Description The qvl_assert_together checker ensures two expressions always assert together. The checker evaluates test_expr1 and test_expr2 at each rising edge of clk whenever active is TRUE. If one expression is TRUE and the other expression is not, an assert_together check violation occurs. Uses: Handshake, req_ack, request, acknowledge, ready, take, hold, wait, bridge, transactions, switch, packet, INDs, tokens, interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (IOs), temporal, time, window. Assertion Checks ASSERT_TOGETHER Specified signals did not assert together. One of the specified expressions was FALSE when the other expression was TRUE. Cover Points Statistics Transitions Checked Number of transitions checked See also qvl_assert_follower qvl_assert_leader Examples qvl_assert_together #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL),) AT1 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1(sig1), .test_expr2(sig2)); Checks that sig1 and sig2 are always asserted together. Questa Verification Library Checkers Data Book, 2010.1a 49 QVL Checker Data Sheets qvl_back_pressure qvl_back_pressure Ensures that a transmitter turns off relative to a specified multiple-cycle time window after a receiver indicates back pressure. back_pressure qvl_back_pressure transmit_ready clk reset_n active Parameters: severity_level property_type msg coverage_level min max Class: n-cycle assertion Application: control and interface Syntax qvl_back_pressure [#(severity_level, property_type, msg, coverage_level, min, max)] instance_name (clk, reset_n, active, back_pressure, transmit_ready); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. min Minimum number of clock cycles after back_pressure asserts at which transmit_ready can deassert. Must be > 0. Default: 1. max Maximum number of clock cycles after back_pressure asserts during which transmit_ready must deassert. Must be ≥ min. Default: 1. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. back_pressure Signal from the receiver indicating it is almost full. transmit_ready Signal from the transmitter indicating it is transmitting. 50 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_back_pressure Description The qvl_back_pressure checker ensures that transmit_ready deasserts after back_pressure asserts within a specified time window. The checker checks the back_pressure and transmit_ready signals at each rising edge of clk whenever active is TRUE. If back_pressure is TRUE, a time window opens min cycles after the current cycle. The window closes when transmit_ready is FALSE or max cycles after the current cycle, whichever comes first. If transmit_ready is FALSE before the window opens (including the current cycle) or if the window closes and transmit_ready is not FALSE, a back_pressure check violation occurs. While a back pressure transaction is pending, the value of back_pressure is ignored, so no new back pressure transaction can initiate until the pending window closes (when transmit_ready transitions to FALSE or max cycles transpire). If back_pressure is TRUE when the window closes, a new back pressure transaction is initiated. Uses: Interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (IOs), temporal, time, window. Assertion Checks BACK_PRESSURE The transmit_ready signal deasserted before the minimum number of hold cycles after back_pressure asserted. The back_pressure signal was TRUE, but in the same cycle or fewer than min cycles later, transmit_ready was FALSE. The transmit_ready signal asserted longer than the maximum number of hold cycles after back_pressure asserted. The back_pressure signal was TRUE, but for the next max cycles, transmit_ready was TRUE. Cover Points Corner Cases ‘transmit_ready’ Deasserted at Minimum Cycles Number of times transmit_ready deasserted min clock cycles after back_pressure asserted. ‘transmit_ready’ Deasserted at Maximum Cycles Number of times transmit_ready deasserted max clock cycles after back_pressure asserted. Statistics Windows Checked Number of windows checked. Questa Verification Library Checkers Data Book, 2010.1a 51 QVL Checker Data Sheets qvl_back_pressure Examples qvl_back_pressure #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL)) BP1 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .back_pressure(full), .transmit_ready(rdy)); Checks that if full is TRUE, then rdy is TRUE and in the next cycle rdy is FALSE. qvl_back_pressure #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .min(1), .max(2)) BP2 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .back_pressure(full), .transmit_ready(rdy)); Checks that if full is TRUE, then rdy is TRUE and then transitions to FALSE within the next 2 cycles. 52 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_bits_off qvl_bits_off Ensures values of an expression have the specified numbers of bits deasserted. Parameters: severity_level property_type msg test_expr[width-1:0] qvl_bits_off clk reset_n active coverage_level width min max Class: single-cycle assertion Application: user Syntax qvl_bits_off [#(severity_level, property_type, msg, coverage_level, width, min, max)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: `QVL_ERROR. property_type Property type. Default: `QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: `QVL_COVER_ALL. width Width of the test_expr argument. Default: 1. min Whether or not to perform min checks. min = 0 (Default) Turns off the min check. min ≥ 1 Minimum number of bits in test_expr that should be deasserted. max Whether or not to perform max checks. Default: 1. max = 0 Turns off the max check. ≥1 Maximum number of bits in test_expr that should be deasserted. Max must be ≥ min. max Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. Questa Verification Library Checkers Data Book, 2010.1a 53 QVL Checker Data Sheets qvl_bits_off reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. Description The qvl_bits_off checker ensures that a minimum number of bits of test_expr are FALSE when the checker is active. The checker checks the multiple-bit expression test_expr at each rising edge of clk whenever active is TRUE. If the test_expr has fewer than min bits equal to FALSE, a min check violation occurs. The assertion fails each active cycle that the value of test_expr has fewer than min deasserted bits, even if test_expr has not changed from the previous value. The checker also performs a max check, which fails if the number of FALSE bits is greater than max. Assertion Checks MIN The expression had fewer than the specified minimum number of bits deasserted. min > 0 Test_expr should not have fewer than min bits equal to 0. MAX The expression had more than the specified maximum number of bits deasserted. ≥ min Test_expr should not have more than max bits equal to 0. max > 0 and max Cover Points Corner Cases Minimum Bits Deasserted Number of times test_expr was sampled when exactly min bits were deasserted. Maximum Bits Deasserted Number of times test_expr was sampled when exactly max bits were deasserted. Statistics Values Checked Number of cycles test_expr was checked. See also qvl_bits_on 54 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_bits_on qvl_bits_on Ensures that values of an expression have the specified numbers of bits asserted. Parameters: severity_level property_type msg test_expr[width-1:0] qvl_bits_on clk reset_n active coverage_level width min max Class: single-cycle assertion Application: user Syntax qvl_bits_on [#(severity_level, property_type, msg, coverage_level, width, min, max)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: `QVL_ERROR. property_type Property type. Default: `QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: `QVL_COVER_ALL. width Width of the test_expr argument. Default: 1. min Whether or not to perform min checks. min = 0 (Default) Turns off the min check. min ≥ 1 Minimum number of bits in test_expr that should be asserted. max Whether or not to perform max checks. Default: 1. max = 0 Turns off the max check. max ≥ 1 Maximum number of bits in test_expr that should be asserted. Max must be ≥ min. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. Questa Verification Library Checkers Data Book, 2010.1a 55 QVL Checker Data Sheets qvl_bits_on reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. Description The qvl_bits_on checker ensures that a minimum number of bits of test_expr are TRUE when the checker is active. The checker checks the multiple-bit expression test_expr at each rising edge of clk whenever active is TRUE. If the test_expr has fewer than min bits equal to TRUE, a min check violation occurs. The assertion fails each active cycle that the value of test_expr has fewer than min asserted bits, even if test_expr has not changed from the previous value. The checker also performs a max check, which fails if the number of TRUE bits is greater than max. Assertion Checks MIN The expression had fewer than the specified minimum number of bits asserted. min > 0 Test_expr should not have fewer than min bits equal to 1. MAX The expression had more than the specified maximum number of bits asserted. max > 0 and max ≥ min Test_expr should not have more than max bits equal to 1. Cover Points Corner Cases Minimum Bits Asserted Number of times test_expr was sampled when exactly min bits were asserted. Maximum Bits Asserted Number of times test_expr was sampled when exactly max bits were asserted. Statistics Values Checked Number of cycles test_expr was checked. See also qvl_bits_off 56 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_bus_driver qvl_bus_driver Ensures that the shared tri-stated bus has exactly one driver. test_expr[width-1:0] qvl_bus_driver driver_enables[width-1:0] clk reset_n Parameters: severity_level property_type msg coverage_level width num_drivers max_undriven_cycles no_driver_check active Class: event-bounded assertion Application: Syntax qvl_bus_driver [#(severity_level, property_type, msg, coverage_level,width, num_drivers, max_undriven_cycles, no_driver_check)] instance_name (clk, reset_n, active, test_expr, driver_enables); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default : 1. num_drivers Number of signals that drive a value into test_expr. Default : 1. max_undriven_cycles Maximum number of cycles that test_expr can be undriven. . Default : 0 (test_expr must always be driven). no_driver_check Whether or not to perform no_driver checks. no_driver_check = 0 (Default) Turns off the no_driver check. no_driver_check = 1 Turns on the no_driver check. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. Questa Verification Library Checkers Data Book, 2010.1a 57 QVL Checker Data Sheets qvl_bus_driver active Expression that indicates whether or not to check the inputs. test_expr[width-1:0] Bus variable. driver_enables [drivers -1:0] Concatenated list of the enable signals that flag the bus drivers when to drive the bus. Signals can be concatenated in any order. Description The qvl_bus_driver checker ensures a tristate bus (test_expr) never has multiple drivers. The checker monitors test_expr and the enable signals to the drivers of test_expr at each active edge of clk when the checker is active. A violation occurs if two enable signals are TRUE. The checker also can be configured to ensure the bus is undriven for a limited number of cycles. Assertion Checks MULTIPLE_DRIVER Multiple sources driving the bus. Two or more sources should not drive test_expr. NO_DRIVER No sources driving the bus. (no_driver_check = 1) and (max_undriven_cycles = 0) Test_expr should not be sampled undriven. (no_driver_check = 1) and (max_undriven_cycles > 0) Test_expr should not be sampled undriven for more than max_undriven_cycles consecutive cycles. Cover Points Corner Cases All Drivers Enabled Non-zero if every driver was enabled in at least one cycle. Max Undriven Cycles Elapsed Number of times test_expr was undriven for exactly max_undriven_cycles cycles. Statistics Cycles Checked Number of cycles checked. Cycles Undriven Number of cycles test_expr was undriven. Cycles Driven Number of cycles test_expr was driven. 58 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_bus_driver See also qvl_mutex Examples qvl_bus_driver #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: ibus drivers”), .coverage_level(‘QVL_COVER_ALL), .width(16), .num_drivers(4), .no_driver_check(1)) qvl_valid_ibus_driver( .clk(clk), .reset_n(reset_n), .active(ibus_data_rdy), .test_expr(ibus), .driver_enables(ibus_den)); Ensures that each cycle ibus_data_rdy is sampled TRUE, exactly one bit of ibus_den is TRUE. clk reset_n ibus_data_rdy ibus_den 1111 0000 0100 0100 1001 1000 QVL_BUS_DRIVER_NO_DRIVER QVL_BUS_DRIVER_MULTIPLE_DRIVER No sources driving the bus. Multiple sources driving the bus. Questa Verification Library Checkers Data Book, 2010.1a 59 QVL Checker Data Sheets qvl_bus_driver qvl_bus_driver #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: ibus drivers”), .coverage_level(‘QVL_COVER_ALL), .width(16), .num_drivers(4), .max_undriven_cycles(2), .no_driver_check(1)) qvl_valid_ibus_driver( .clk(clk), .reset_n(reset_n), .active(sleep_n), .test_expr(ibus), .driver_enables(ibus_den)); Ensures that each cycle sleep_n is sampled TRUE, at most one bit of ibus_den_n is TRUE and that for at most 2 consecutive cycles, sleep_n is TRUE and no bit of ibus_den is TRUE. clk reset_n 1 2 3 sleep_n ibus_den 1111 0000 0100 1001 1111 QVL_BUS_DRIVER_NO_DRIVER No sources driving the bus. 60 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_bus_id qvl_bus_id Ensures that all IDs returned match the IDs issued and that no more than a specified number of IDs are outstanding at any time. qvl_bus_id ret ret_id[width-1:0] clk reset_n max_ids allow_simultaneous_ req_ret disallow_req_when_full unique_ids_check known_ids_check Parameters: severity_level property_type msg coverage_level width req req_id[width-1:0] active Class: event-bounded assertion Application: control and interface Syntax qvl_bus_id [#(severity_level, property_type, msg, coverage_level, width, max_ids, allow_simultaneous_req_ret, disallow_req_when_full, unique_ids_check, known_ids_check)] instance_name (clk, reset_n, active, req, req_id, ret, ret_id); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL width Width of req_id and ret_id. Default: 4. max_ids Value to use for the max_ids check. max_ids = 0 Turns off the max_ids check. (Default: max_ids = 16) Turns on the max_ids check. To minimize simulation overhead, set max_ids to the maximum expected value and no more (even if the maximum is less than 16). max_ids > 0 allow_simultaneous_ req_ret How the known_ids check handles request and return transactions with the same ID that occur in the same cycle. allow_simultaneous_req_ret = 0 (Default) Return ID is matched only with previously outstanding IDs. allow_simultaneous_req_ret = 1 Return ID is first matched with previously outstanding IDs, then is matched with the current request. Questa Verification Library Checkers Data Book, 2010.1a 61 QVL Checker Data Sheets qvl_bus_id disallow_req_when_full How the unique_ids check handles request and return transactions with the same ID that occur in the same cycle. disallow_req_when_full = 0 (Default) Request ID is matched only with previously outstanding IDs. disallow_req_when_full = 1 Request ID is first considered outstanding, then the return ID is matched with the previously outstanding IDs. So, if the requested ID is previously outstanding, a unique_ids check violation occurs. unique_ids_check Whether or not to perform unique_ids checks. unique_ids_check = 0 Turns off the unique_ids check. (Default) Turns on the unique_ids check. unique_ids_check = 1 known_ids_check Whether or not to perform known_ids checks. known_ids_check = 0 Turns off the known_ids check. (Default) Turns on the known_ids check. known_ids_check = 1 Ports clk Clock event for the assertion. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. req Signal that indicates req_id is valid. req_id[width-1:0] Register or wire containing the request ID sent out on the bus. ret Signal that indicates ret_id is valid. ret_id[width-1:0] Register or wire containing the ID returned from the bus. 62 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_bus_id Description The qvl_bus_id checker ensures bus IDs are issued and returned properly. The checker evaluates ret and req signals at each rising edge of clk whenever active is TRUE. By default, the following verification is performed: 1. If req is TRUE: An ID request is assumed. If the request ID is already outstanding, a unique_ids check violation occurs. 2. If ret is TRUE: An ID return is assumed. If the ID is not outstanding, a known_ids check violation occurs. 3. If req is TRUE: The value of req_id is added to the list of outstanding bus IDs. 4. If ret is TRUE: The value of ret_id is removed from the list of outstanding bus IDs. If a request and return both occur in the same cycle but the request ID does not match the return ID, these checks are still unambiguous. The corner case where a request and return having the same ID occur in the same cycle can be adjusted using the disallow_req_when_full and allow_simultaneous_req_ret parameter flags. Setting the disallow_req_when_full parameter to 1 changes the unique_ids check to fail if the ID is outstanding. Setting the allow_simultaneous_req_ret to 1 changes the known_ids assertion to not fail if the ID is not outstanding. For performance reasons, the qvl_bus_id assertion tracks up to 16 outstanding IDs at a time. If the checker is at this limit and a request occurs without a return, a max_ids check violation occurs. The original outstanding IDs are saved but the new request ID is lost. So, if that ID subsequently is returned, a known_ids violation might occur. Or, if that ID is requested, a unique_ids violation might not occur, even though it would be expected. The maximum number of outstanding IDs can be adjusted by setting the max_ids parameter. Setting this value to the smallest viable value is recommended. Uses: Bridge, transactions, switch, packet, IDs, tokens, interface, input ports (inputs), output ports (out puts), inout ports (inouts), I/O (IOs), temporal, time, window. Assertion Checks UNIQUE_IDS Request ID was already outstanding. (unique_ids_check = 1) and (disallow_req_when_full = 0) Request ID matches an outstanding ID but not the return ID. (unique_ids_check = 1) and (disallow_req_when_full = 1) Request ID matches an outstanding ID or the return ID. Questa Verification Library Checkers Data Book, 2010.1a 63 QVL Checker Data Sheets qvl_bus_id KNOWN_IDS Return ID was not outstanding. (known_ids_check = 1) and (allow_simultaneous_req_ret = 0) Return ID does not match an outstanding ID. (known_ids_check = 1) and (allow_simultaneous_req_ret = 1) Return ID does not match an outstanding ID or the request ID if one is requested in the current cycle. MAX_IDS ID was requested when the maximum number of IDs were outstanding = 0) The maximum number of IDs were outstanding and another ID was requested without a simultaneous return ID. (max_ids > 0) and (disallow_req_when_full = 1) The maximum number of IDs were outstanding and another ID was requested. (max_ids > 0) and (disallow_req_when_full When a max_ids violation occurs, the request ID is ignored (i.e., not added to the outstanding IDs list). If the ID subsequently is returned, a known_ids check violation might occur. Similarly, if the ID is subsequently requested, a unique_ids check violation might not occur, even if it was expected. Cover Points Corner Cases IDs Requested Number of IDs requested. IDs Returned Number of IDs returned. Outstanding IDs Equal ‘max_ids’ Number of times the number of outstanding IDs equalled max_ids. Meaningful only if max_ids is not 0. Statistics Unique IDs Issued Number of unique IDs issued. See also qvl_outstanding_id 64 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_bus_id Examples qvl_bus_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_BUS_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4)) U1 ( .clk(system_clock), .reset_n(system_reset), .active(bid_active), .req(req_sig), .req_id(send_id), .ret(back_sig), .ret_id(back_id)); Checks that IDs requested on send_id are not already outstanding and that only issued IDs are returned on back_id. qvl_bus_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_BUS_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .max_ids(12)) U2 ( .clk(system_clock), .reset_n(system_reset), .active(bid_active), .req(issue_sig), .req_id(issue_id), .ret(back_sig), .ret_id(back_id)); Checks that IDs issued on issue_id are not already outstanding and that no more than 12 total IDs are outstanding. Questa Verification Library Checkers Data Book, 2010.1a 65 QVL Checker Data Sheets qvl_bus_id qvl_bus_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_BUS_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(8), .max_ids(8), .disallow_req_when_full(1)) U3 ( .clk(system_clock), .reset_n(system_reset), .active(bid_active), .req(req), .req_id(out_id), .ret(ret), .ret_id(ret_sig)); Checks that at most eight unique IDs are outstanding and that no ID is requested if it is already outstanding even if ID is simultaneously returned. 66 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_change_timer qvl_change_timer Ensures that an expression remains constant for specified times. test_expr[width-1:0] qvl_change_timer min[31:0] max[31:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width min_check max_check Class: event-bounded assertion Application: interface Syntax qvl_change_timer [#(severity_level, property_type, msg, coverage_level, width, max_check, min_check)] instance_name (clk, reset_n, active, test_expr, min, max); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of the test_expr. Default: 1. min_check Whether or not to perform min checks. min_check = 0 (Default) Turns off the min check. min_check = 1 Turns on the min check. max_check Whether or not to perform max checks. max_check = 0 (Default) Turns off the min check. max_check = 1 Turns on the min check. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. Questa Verification Library Checkers Data Book, 2010.1a 67 QVL Checker Data Sheets qvl_change_timer active Expression that indicates whether or not to check the inputs. test_expr[width-1:0] Variable or expression to check. min[31:0] Minimum number of cycles test_expr must be held constant if min_check is 1. max[31:0] Maximum number of cycles test_expr can be held asserted if max_check is 1. Description The qvl_change_timer checker ensures that test_expr remains constant for a specified time and only for the specified time. By default, the checker performs no assertion checks. Setting min_check to 1 turns on the min check and setting max_check to 1 turns on the max check. Turning min and max checks on also turns on the min_gt_max check. If all checks are on, the checker checks the test_expr signal and the min/max values at each rising edge of clk whenever active is TRUE. If min > max, a min_gt_max check violation occurs. Otherwise, unless both min and max are 0, an event window opens if any of the following occur: • Test_expr has changed value. • A check violation occurred in the previous cycle. • Min and max were both 0 in the previous cycle. When the event window opens, the values of test_expr, min and max are stored and no new event window can open. Then, the checker checks test_expr each subsequent cycle until one of the following events occurs: • Test_expr does not equal the stored value of test_expr. If the number of subsequent cycles ≥ min, a min check violation occurs. • The number of subsequent cycles = max + 1. If test_expr is still equal to the stored value of test_expr, a max check violation occurs. When one of these events occurs, the event window closes and the checker returns to the state of monitoring test_expr, min and max in the next clock cycle. The qvl_assert_timer checker can be configured to perform only the min or the max checks. Uses: Bridge, transactions, switch, packet, IDs, tokens, interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (I/Os), temporal, time, window. 68 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_change_timer Assertion Checks MIN Expression changed value before the minimum number of cycles. min_check = 1 Test_expr was constant for fewer than min consecutive cycles, then changed value. MAX Expression was constant for more than the maximum number of cycles. max_check = 1 Test_expr was constant for max + 1 consecutive cycles. MIN_GT_MAX Min value was greater than max value. min_check = 1 and max_check = 1 Test_expr was TRUE when the event window was closed, but min was > max. Cover Points Corner Cases Value Changed at ‘min’ Cycles Number of times the value of test_expr changed at min cycles. Meaningful only if min_check is 1. Value Changed at ‘max’ Cycles Number of times the value of test_expr changed at max cycles. Meaningful only if max_check is 1. Statistics Values Checked Number of values checked (i.e., number of event windows). See also qvl_assert_timer Questa Verification Library Checkers Data Book, 2010.1a 69 QVL Checker Data Sheets qvl_change_timer Examples qvl_ change_timer #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_CHANGE_TIMER Violation"), .coverage_level(‘QVL_COVER_ALL), .width(3), .min_check(1)) QVL_CHANGE_TIMER ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr(a>b ? 3’d3 : 3’d4), .max(1), .min(2)); Checks that the test expression value (passed as a>b ? 3’d3 : 3’d4 ) remains constant for at least two cycles. qvl_ change_timer #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_CHANGE_TIMER Violation"), .coverage_level(‘QVL_COVER_ALL), .width(1), .max_check(1)) QVL_CHANGE_TIMER ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr(a>b), .max({{28’b{1’b0}}, bus[3:0]}), .min(1)); Checks that the value of the test expression (passed as a>b ) remains constant for the number of clock cycles that was sampled on the bus[3:0] when the test expression changed. 70 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_channel_data_integrity qvl_channel_data_integrity Ensures the integrity of data in a channel and that data are not corrupted or lost; that additional data are not added; that data are not inserted when the channel is full and that data are not removed when the channel is empty. insert[insert_count-1:0] remove[remove_count-1:0] cancel[cancel_count-1:0] empty qvl_channel_data_integrity insert_data [width*insert_count-1:0] remove_data [width*remove_count-1:0] cancel_data [width*cancel_count-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width depth insert_count remove_count cancel_count pass registered latency high_water insert_check cancel_check empty_check Class: event-bounded assertion Application: control and interface Syntax qvl_channel_data_integrity [#(severity_level, property_type, msg, coverage_level, width, depth, insert_count, remove_count, cancel_count, pass, registered, latency, high_water, insert_check, cancel_check, empty_check)] instance_name (clk, reset_n, active, insert, remove, cancel, empty, insert_data, remove_data, cancel_data); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width Width of a data item. Default: 1. depth Channel depth. Must be > 0. Default: 1. insert_count Number of bits in insert and data items in insert_data. Default: 1. remove_count Number of bits in remove and data items in remove_data. Default: 1. cancel_count Number of bits in cancel and data items in cancel_data. Default: 1. Questa Verification Library Checkers Data Book, 2010.1a 71 QVL Checker Data Sheets qvl_channel_data_integrity pass How the channel handles removes/cancels and inserts in the same cycle when the channel is almost empty. Used for the cancel and remove checks. pass = 0 (Default) No pass mode. If the channel if almost empty, cancels and removes are performed before inserts. A cancel violation (if enabled) occurs if the channel has fewer data items (not including items to insert) than the cancel operation. A remove cancel violation (if enabled) occurs if the channel has fewer data items (not including items to insert) than the remove operation. pass = 1 Pass mode. If the channel is almost empty, inserts are performed before cancels. registered How the channel handles removes/cancels and inserts in the same cycle when the channel is almost full. Used for the insert check. registered = 0 (Default) No registered mode. If the channel if almost full, inserts are performed before cancels and removes. An insert violation occurs if the number of data items in the channel plus the number of inserted data items exceeds depth. registered = 1 Registered mode. If the channel is almost full, cancels and removes are performed before inserts. latency Latency for the data check. latency = 0 (Default) Data check is performed in the same cycle that the channel is emptied. latency> 0 Data check is performed latency cycles after the channel is emptied. high_water Channel high-water mark. Must be < depth. A value of 0 sets the high-water mark to depth - 1 (or 1 if depth is 1). Default: 0. insert_check Whether or not to perform insert checks. insert_check = 0 (Default) Turns off the insert check. insert_check = 1 Turns on the insert check. cancel_check Whether or not to perform cancel checks. cancel_check = 0 (Default) Turns off the cancel check. cancel_check = 1 Turns on the cancel check. 72 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_channel_data_integrity empty_check Whether or not to perform empty checks. empty_check = 0 (Default) Turns off the empty check. empty_check = 1 Turns on the empty check. Ports clk Clock event for the assertion. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. insert [insert_count-1:0] Concatenated list of signals indicating which data items in insert_data are being inserted into the channel. remove [remove_count-1:0] Concatenated list of signals whose corresponding data items (latency cycles later) in remove_data are removed from the channel. cancel [cancel_count-1:0] Concatenated list of signals whose corresponding data items in cancel_data indicate which data items in the channel are being canceled. insert_data [width * insert_count -1:0] Concatenated list of variables whose data values are being inserted into the channel whenever their corresponding bits of insert assert. remove_data [width * remove_count -1:0] Concatenated list of variables whose data values are being removed from the channel latency cycles after their corresponding bits of remove assert. cancel_data [width * cancel_count -1:0] Concatenated list of variables whose data values are being canceled from the channel whenever their corresponding bits of cancel assert. empty Signal from the channel indicating it is empty. Description The qvl_channel_data_integrity checker ensures the integrity of data inserted and removed from a channel by monitoring the checksums of data inserted with the checksums of data removed. The TRUE bits of insert indicate their corresponding data items in insert_data are being inserted into the channel. Similarly, the TRUE bits of remove indicate their corresponding data items in remove_data are being removed from the channel. Data items are inserted into the channel and are subsequently removed from the channel without regard to order. Questa Verification Library Checkers Data Book, 2010.1a 73 QVL Checker Data Sheets qvl_channel_data_integrity On reset, the checker assumes the channel is empty. The checker checks the expressions insert and remove at each rising edge of clk whenever active is TRUE. The checker assumes the data items of insert_data with corresponding TRUE bits in insert are inserted to the channel and assumes the data items of remove_data with corresponding TRUE bits in remove are removed from the channel. The checker does not track the actual values passing through the channel, it just counts the number data items inserted and removed and calculates the running checksums of the inserted and removed data streams. By default, if the number of removed data items is greater than the number of items calculated to be in the channel, a remove check violation occurs and any pending inserted data items are ignored. Or, if the channel is empty after processing removes and inserts, the checker compares the current checksums of the inserted and removed data streams. If they do not match, a data check violation occurs. If a remove violation occurs or the channel is empty, the checker starts the process over again in the next cycle. The qvl_channel_data_integrity checker can be configured to behave differently and also perform additional checks: • Cancel operations If the cancel_check parameter is 1, the checker monitors cancel and cancel_data for data items canceled from the channel. Cancel operations cancel data items in the channel so they do not appear in the remove data stream. If after a remove operation, the number of data items in the channel is less than the number of TRUE bits of cancel, a cancel check violation occurs. Also, the data check compares the current checksum of the inserted data stream with the current checksum of the combined removed and canceled data streams. • Empty signal If the empty_check parameter is 1, the checker monitors the empty signal. If empty is TRUE and the channel is not empty after processing pending insert, remove and cancel operations, an empty check violation occurs and the checker assumes the channel is empty. • Pass mode If the pass parameter is 1, the checker checks for remove check and cancel check violations after insert, remove and cancel operations. (By default, the checker checks for remove check and cancel check violations after remove and cancel operations.) • Registered mode If the registered parameter is 1, the checker checks for insert check violations after insert, remove and cancel operations. (By default, the checker checks for insert check violations after insert operations.) 74 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_channel_data_integrity • Latency If the latency parameter is specified, the data check is delayed for latency cycles after the channel is empty. Data items removed during those cycles are included in the calculation of the current checksum. Uses: FIFO, queue, data channel, bus bridge. Assertion Checks DATA Checksum of the channel’s output data stream did not match the checksum of the channel’s input data stream. latency = 0 At the end of the current cycle, the channel was empty and the checksum of all data items removed or canceled since the previous cycle in which the channel was empty does not equal the checksum of the data items inserted. latency> 0 At the end of a cycle, the channel was empty and latency cycles later the checksum of all data items removed or canceled since the previous cycle the channel was empty does not equal the checksum of the data items inserted. The channel is empty when empty is TRUE or when the total number of TRUE bits of insert sampled since the last time the channel was empty equals the total number of TRUE bits of remove and cancel sampled since the last time the channel was empty. REMOVE Data were removed when the channel was empty. pass = 0 After processing the current cancel operation, the number of data items in the channel was less than the number of TRUE bits of remove. pass = 1 After processing the current insert and cancel operations, the number of data items in the channel was less than the number of TRUE bits of remove. Questa Verification Library Checkers Data Book, 2010.1a 75 QVL Checker Data Sheets qvl_channel_data_integrity CANCEL Data were canceled when the channel was empty. cancel_check = 1 and pass = 0 The number of data items in the channel was less than the number of TRUE bits of cancel. cancel_check = 1 and pass = 1 After processing the current insert operation, the number of data items in the channel was less than the number of TRUE bits of cancel. INSERT Data were inserted when the channel was full. insert_check = 1 and registered = 0 The number of data items in the channel plus the number of TRUE bits of insert was > depth. insert_check = 1 and registered = 1 After processing the current cancel and remove operations, the number of data items in the channel plus the number of TRUE bits of insert was > depth. EMPTY Empty asserted but the channel was not empty. empty_check = 1 After processing the current cancel, remove and insert operations, the number of data items in the channel was > 0. Cover Points Corner Cases Channel is Full Number of times the channel was full. Meaningful only if the insert check is on. Channel is Empty Number of times the channel was empty. Channel is Over High-water Mark Number of times the channel was over the high-water mark. Meaningful only if the insert check is on. Each Bit Set to One If non-zero, each bit of insert has been TRUE. Each Bit Set to Zero If non-zero, each bit of insert has been FALSE. Statistics Simultaneous Inserts and Removes Number of cycles both insert and remove operations were performed. Inserts Number of data items inserted. Removes Number of data items removed. Cancels Number of data items canceled. 76 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_channel_data_integrity Examples qvl_channel_data_integrity #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Channel Data Integrity Violation : ”), .coverage_level(‘QVL_COVER_NONE), .width(8), .empty_check(1)) cdi_chx_1( .clk(clk), .reset_n(~reset), .active(active), .insert(in), .insert_data(in_data[7:0]), .remove(out), .remove_data(out_data[7:0]), .cancel(1’b0), .cancel_data(8’b0), .empty(channel_empty)); Checks the data integrity of the channel, that data are not removed when the channel is empty and that the channel is empty when channel_empty asserts. qvl_channel_data_integrity #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Channel Data Integrity Violation : ”); .coverage_level(‘QVL_COVER_NONE), .width(8), .depth(10), .insert_check(1), .empty_check(1)) cdi_chx_2( .clk(clk), .reset_n(~reset), .active(active), .insert(in), .insert_data(in_data[7:0]), .remove(out), .remove_data(out_data[7:0]), .cancel(1’b0), .cancel_data(8’b0), .empty(channel_empty)); Checks the data integrity of the channel, that data are not removed when the channel is empty, that data are not inserted when the channel is full (10 data items) and that the channel is empty when channel_empty asserts. Questa Verification Library Checkers Data Book, 2010.1a 77 QVL Checker Data Sheets qvl_channel_data_integrity qvl_channel_data_integrity #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Channel Data Integrity Violation : ”); .coverage_level(‘QVL_COVER_NONE), .width(8), .depth(10), .pass(1), .registered(1), .insert_check(1), .empty_check(1)) cdi_chx_3( .clk(clk), .reset_n(~reset), .active(active), .insert(in), .insert_data(in_data[7:0]), .remove(out), .remove_data(out_data[7:0]), .cancel(1’b0), .cancel_data(8’b0), .empty(channel_empty)); Checks the data integrity of the channel, that data are not removed when the channel is empty (inserted items are added first), that data are not inserted when the channel is full (removed items are removed first) and that the channel is empty when channel_empty asserts. qvl_channel_data_integrity #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Channel Data Integrity Violation : ”); .coverage_level(‘QVL_COVER_NONE), .width(8), .pass(1), .registered(1), .insert_check(1), .cancel_check(1), .empty_check(1)) cdi_chx_4( .clk(clk), .reset_n(~reset), .active(active), .insert(in), .insert_data(in_data[7:0]), .remove(out), .remove_data(out_data[7:0]), .cancel(cancel), .cancel_data(cancel_data[7:0]), .empty(channel_empty)); Checks the data integrity of the channel, that data are not removed or canceled when the channel is empty (inserted items are added first), that data are not inserted when the channel is full (removed/canceled items are removed first) and that the channel is empty when channel_empty asserts. 78 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_channel_data_integrity qvl_channel_data_integrity #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Channel Data Integrity Violation : ”); .coverage_level(‘QVL_COVER_NONE), .width(8), .insert_count(4)) cdi_chx_5( .clk(clk), .reset_n(~reset), .active(active), .insert({in,in,in,in}), .insert_data({in_data[31:24], in_data[23:16], in_data[15:8], in_data[7:0]}), .remove(out), .remove_data(out_data[7:0]), .cancel(1’b0), .cancel_data(8’b0), .empty(1’b0)); Checks the data integrity of the channel and that data are not removed when the channel is empty. Data are inserted as 4 8-bit items and removed as single 8-bit data items. Questa Verification Library Checkers Data Book, 2010.1a 79 QVL Checker Data Sheets qvl_constant qvl_constant Ensures that values of an expression remain constant. Parameters: severity_level property_type test_expr[width-1:0] qvl_constant msg coverage_level width Class: single-cycle assertion clk reset_n active Application: user Syntax qvl_constant [#(severity_level, property_type, msg, coverage_level, width)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: `QVL_ERROR. property_type Property type. Default: `QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: `QVL_COVER_ALL. width Width of test_expr. Default: 4. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. 80 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_constant Description The qvl_constant checker ensures that the value of test_expr is constant when the checker is active. The checker evaluates the multiple-bit expression test_expr at the first rising edge of clk that active is TRUE following a reset or start of simulation. This value is the constant value of the expression. Subsequently, the checker evaluates test_expr at each rising edge of clk whenever active is TRUE. If the value of test_expr is different from the constant value, a constant check violation occurs. The value of test_expr then becomes the new constant value for subsequent constant checks. Assertion Checks CONSTANT The expression changed value but should have remained constant. Test_expr should not change value. Cover Points Corner Cases none Statistics Values Checked Number of cycles test_expr was checked. See also qvl_value Questa Verification Library Checkers Data Book, 2010.1a 81 QVL Checker Data Sheets qvl_content_addressable_memory qvl_content_addressable_memory Ensures that a match signal asserts when a match to a specified data value is present in contentaddressable memory and that the output match address is correct. Parameters: severity_level property_type msg coverage_level depth width addr_enable write addr[addr_width-1:0] data[width-1:0] match qvl_content_addressable_ memory match_found data_mask[width-1:0] match_data[width-1:0] match_addr[addr_width-1:0] clk reset_n active match_data_enable latency allow_x addr_encoding lowest_addr single_match_check address_check Class: event-bounded assertion Application: control and interface addr_width = (addr_encoding == 2) ? log2(depth) : depth: Syntax qvl_content_addressable_memory #(severity_level, property_type, msg, coverage_level, width, depth, addr_enable, match_data_enable, latency, allow_x, addr_encoding, lowest_addr,single_match_check, address_check) instance_name (clk, reset_n, active, write, addr, data, match, match_found, data_mask, match_data, match_addr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width Width of a data item. Default: 1. depth Memory depth. Must be > 0. Default : 1. addr_enable = 0 Once the number of data items written to memory equals the depth, assertion checks are turned off until the checker is reset; but, cover point information is maintained. addr_enable = 1 Number of locations in the range of addr equals the depth. If a write operation is performed on a location with an existing data item, the new data item replaces the old item. 82 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_content_addressable_memory addr_enable How to determine the memory write address. addr_enable = 0 (Default) Data items are written to consecutive addresses. The addr port is ignored. addr_enable = 1 The addr port contains the memory location for each memory write operation. match_data_enable Which data port contains the data item to check for a match when match asserts. match_data_enable = 0 (Default) Data port contains the data item to match. match_data_enable = 1 Match_data port contains the data item to match. latency Latency for data matching information. latency = 0 (Default) Match_found and match_addr are valid in the same cycle match asserts. latency > 0 Match_found and match_addr are valid latency cycles after match asserts. allow_x How to handle X bits in data items. allow_x = 0 (Default) Checker is inactive if a write data item or match data item has an X bit. allow_x = 1 X bits in write data items and match data items are considered don’t care bits. addr_encoding Encoding of addresses. addr_encoding = 0 (Default) Addresses are bitmaps of the memory’s locations. Each TRUE bit of addr indicates the write data item is being written to the corresponding memory location. Each TRUE bit of match_addr indicates a copy of the matched data item is stored in the corresponding location. addr_encoding = 1 and lowest_addr = 0 Addresses are one-hot bitmaps of the memory’s locations. The highest-order TRUE bit of addr indicates the write data item is being written to the corresponding memory location. If a match occurs match_addr should have exactly one TRUE bit and the bit’s associated location should be the highest address with a match. Questa Verification Library Checkers Data Book, 2010.1a 83 QVL Checker Data Sheets qvl_content_addressable_memory lowest_addr = 1 Addresses are one-hot bitmaps of the memory’s locations. The lowest-order TRUE bit of addr indicates the write data item is being written to the corresponding memory location. If a match occurs match_addr should have exactly one TRUE bit and the bit’s associated location should be the lowest address with a match. addr_encoding = 2 and lowest_addr = 0 Addresses are binary encoded values. Addr is the location to put the associated write data item. If a match occurs, the value of match_addr should be the highest address with a match. addr_encoding = 2 and lowest_addr = 1 Addresses are binary encoded values. Addr is the location to put the associated write data item. If a match occurs, the value of match_addr should be the lowest address with a match. addr_encoding = 1 and lowest_addr How to interpret addr and match_addr if addr_encoding is 1 or 2. lowest_addr = 0 (Default) Write location corresponds to the highest order TRUE bit of addr if addr_enable is 1 and addr_encoding is 1. Match_addr contains the highest address with a matching data item if address_check is 1. lowest_addr = 1 Write location corresponds to the lowest order TRUE bit of addr if addr_enable is 1 and addr_encoding is 1. Match_addr contains the lowest address with a matching data item if address_check is 1. single_match_check Whether or not to perform single_match checks. single_match_check = 0 (Default) Turns off the single_match check. single_match_check = 1 Turns on the single_match check. address_check Whether or not to perform address checks. address_check = 0 (Default) Turns off the address check. address_check = 1 Turns on the address check. Ports clk Clock event for the assertion. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. 84 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_content_addressable_memory write Memory write signal that asserts when the value of write_data is written to memory. addr[addr_width-1:0] Memory address bus used if addr_enable is 1. When write asserts, the value of data is assumed to be written to the location (or locations) corresponding to the encoded address (or addresses) specified by addr. If addr_enable is 0, set addr to 1’b0. data[width-1:0] Memory data bus. match_data_enable = 0 When write asserts, data contains the data item written to memory. When match asserts, data contains the data item to check for a matching item in memory. If both write and match assert together, the write operation is performed and a match with that data item is assumed. match_data_enable = 1 When write asserts, match_data contains the data item written to memory. match Memory compare signal. match_data_enable = 0 When match asserts, the checker checks the memory for data items that match the value of data. data_enable = 1 When match asserts, the checker checks the memory for data items that match the value of match_data. match_found Match found signal. latency = 0 When match asserts, the value of data (or match_data, if match_data_enable is 1) should match a data item in memory if and only if match_found asserts. latency > 0 When match asserts, the value of data (or match_data, if match_data_enable is 1) should match a data item in memory if and only if match_found asserts latency cycles later. data_mask[width-1:0] Data mask bus. TRUE bits in data_mask indicate corresponding bits in data items are don’t care bits that are ignored. If not used, set to width{1’b0}. match_data[width-1:0] Match data bus if match_data_enable is 1. When match asserts, the checker checks its memory for a data item that matches the value of match_data. If match_data_enable is 0, set data to width{1’b0}. Questa Verification Library Checkers Data Book, 2010.1a 85 QVL Checker Data Sheets qvl_content_addressable_memory match_addr [addr_width-1:0] Match address bus if address_check is 1. Match_addr width is depth if addr_encoding is 0 or 1. Match_addr width is log2(depth) if addr_encoding is 2. If address_check is 0, set match_addr to 1’b0. latency = 0 When match asserts and the checker finds a matching data item, the value of match_addr should match the encoded address of the matching data item. latency > 0 When match asserts and the checker finds a matching data item, latency cycles later the value of match_addr should match the encoded address of the matching data item. Description The qvl_content_addressable_memory checker ensures the integrity of data in a contentaddressable memory. On reset, the checker assumes the memory is empty. Then, the checker checks the write and match signals at each rising edge of clk whenever active is TRUE. If write is TRUE, a memory write operation has occurred; if match is TRUE, a data matching operation has occurred: • Memory write operation When write is TRUE, the value of data was written to memory. If the number of data items written to memory is depth, the checker turns off all checks (but maintains cover point information) until the checker is reset. Memory write operations can be changed as follows: If the addr_enable parameter is 1, the addr port contains an encoded memory address to write one or more copies of the data item. Here, data items written to locations overwrite the previous data items, so assertion checks are performed even when the memory is full. In this case, depth only determines the size of the address ports. The addr_encoding parameter (and sometimes the lowest_addr parameter) selects the encoding mechanism. The default encoding mechanism (addr_encoding = 0) supports writes to multiple locations. Otherwise, only single-location writes occur. • Data matching operation When match is TRUE, a matching operation was performed. The value of data_mask was used to mask the data item values: Two data items match if the bits corresponding to the FALSE bits of data_mask are the same (i.e., TRUE bits of data_mask indicate don’t care bits of the data items). If match_found is TRUE, the value of data should match a data item in memory, so if a matching data item is not found, a match check violation occurs. Or, if match_found is FALSE, the value of data should not match a data item in memory, so if a matching data item is found, a match check violation occurs. Data matching operations can be changed 86 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_content_addressable_memory as follows: If the match_data_enable parameter is 1, the match value is taken from the match_data port instead of the data port. The following additional assertion checks can be turned on: • Single_match check If single_match_check is 1, a single_match check violation occurs when a matching operation finds more than one data items in memory that match the match value. • Address check If address_check is 1, an address check violation occurs if the value of match_addr does not equal the encoded address of the matching data item (or items, if addr_encoding is 0) in memory. The following characteristics of some content-addressable memories can be modeled by the qvl_content_addressable_memory checker: • Latency By default, the checker samples match_found and match_addr and applies the match and address checks in the same cycle the match operation is performed. However, if the latency parameter is > 0, the checker delays sampling match_found and match_addr by latency cycles before applying the match and address checks. • Ternary bit values By default, if the data value in a write operation or the match value in a matching operation has an X bit, the checker is inactive for the cycle and write/match operations are not performed. However, if the allow_x parameter is 1, X bits in write values are written to memory as-is. For matching purposes, an X bit in a data item or a match value always matches (i.e., X bits are don’t care bits). Z bits are treated the same as X bits in the default case. If the data value in a write operation or the match value in a matching operation has a Z bit, the checker is inactive for the cycle and write/match operations are not performed. Uses: CAM, content-addressable memory. Questa Verification Library Checkers Data Book, 2010.1a 87 QVL Checker Data Sheets qvl_content_addressable_memory Assertion Checks MATCH Specified value matched a data item in memory, but match_found did not assert. latency = 0 Match was TRUE and memory contained a data item that matched the value of data (or match_data if match_data_enable is 1), but match_found was FALSE. latency > 0 Match was TRUE and memory contained a data item that matched the value of data (or match_data if match_data_enable is 1), but latency cycles later match_found was FALSE. Specified value did not match a data item in memory, but match_found asserted. latency = 0 Match was TRUE and memory did not contain a data item that matched the value of data (or match_data if match_data_enable is 1), but match_found was TRUE. latency > 0 Match was TRUE and memory did not contain a data item that matched the value of data (or match_data if match_data_enable is 1), but latency cycles later match_found was TRUE. SINGLE_MATCH Specified value matched more than one data item in memory. single_match_check = 1 Match was TRUE and memory contained multiple data items that matched the value of data (or match_data if match_data_enable is 1). 88 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_content_addressable_memory ADDRESS Specified location in match_addr was not the address of the matching data item. address_check = 1 and latency = 0 Match was TRUE and memory contained a data item that matched the value of data (or match_data if match_data_enable is 1), but the encoded memory address of matching data items did not equal the value of match_addr. address_check = 1 and latency > 0 Match was TRUE and memory contained a data item that matched the value of data (or match_data if match_data_enable is 1), but latency cycles later the encoded memory address of matching data items did not equal the value of match_addr. Cover Points Corner Cases Single Matches Number of cycles a data matching operation found exactly one matching data item. Multiple Matches Number of cycles a data matching operation found more than one matching data item. Not meaningful if single_match_check is 1. No Matches Number of cycles a data matching operation found no matching data item. Statistics Memory Writes Number of cycles a memory write operation was performed. Match Cycles Number of cycles a data matching operation was performed. Questa Verification Library Checkers Data Book, 2010.1a 89 QVL Checker Data Sheets qvl_content_addressable_memory Examples qvl_content_addressable_memeory #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Content Addressable Memory Violation: “); .coverage_level(‘QVL_COVER_ALL), .width(8), .depth(256)) cam ( .clk(clk), .reset_n(~reset), .active(active), .write(write_signal), .addr(1’b0), .data(write_reg), .match(compare), .match_found(match_found), .data_mask({8{1’b0}}), .match_data({8{1’b0}}), .match_addr(1’b0)); Checks that match_found is asserted if and only if a data item matching the value of write_reg is found in the content-addressable memory during a match cycle. qvl_content_addressable_memory #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Content Addressable Memory Violation: “); .coverage_level(‘QVL_COVER_ALL), .width(8), .depth(256), .latency(2)) cam ( .clk(clk), .reset_n(~reset), .active(active), .write(write_signal), .addr(1’b0), .data(write_reg), .match(compare), .match_found(match_found), .data_mask({8{1’b0}}), .match_data({8{1’b0}}), .match_addr(1’b0)); Checks that match_found is asserted 2 cycles after a match cycle if and only if a data item matching the value of write_reg is found in the content-addressable memory during a match cycle. 90 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_content_addressable_memory qvl_content_addressable_memory #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Content Addressable Memory Violation: “), .coverage_level(‘QVL_COVER_ALL), .width(8), .depth(256), .single_match_check(1)) cam ( .clk(clk), .reset_n(~reset), .active(active), .write(write_signal), .addr(1’b0), .data(write_reg), .match(compare), .match_found(match_found), .data_mask({8{1’b0}}), .match_data({8{1’b0}}), .match_addr(1’b0)); Checks that match_found is asserted if and only if a data item matching the value of write_reg is found in the content-addressable memory during a match cycle. Also checks that no more than one match is found during a match cycle. qvl_content_addressable_memory #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Content Addressable Memory Violation: “), .coverage_level(‘QVL_COVER_ALL), .width(8), .depth(256), .addr_enable(1), .address_check(1), .addr_encoding(2)) cam ( .clk(clk), .reset_n(~reset), .active(active), .write(write_signal), .addr(addr), .data(write_reg), .match(compare), .match_found(match_found), .match_data_mask({8{1’b0}}), .match_data({8{1’b0}}), .match_addr(match_addr)); Checks that match_found is asserted if and only if a data item matching the value of write_reg is found in the content-addressable memory during a match cycle. Also checks that when a match is found, match_address contains the address of the matching entry with the highest address. Questa Verification Library Checkers Data Book, 2010.1a 91 QVL Checker Data Sheets qvl_coverage qvl_coverage Ensures that an HDL statement is covered during simulation. Parameters: severity_level property_type test_expr qvl_coverage msg coverage_level Class: single-cycle assertion clk reset_n active Application: coverage Syntax qvl_coverage [#(severity_level, property_type, msg, coverage_level)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: `QVL_ERROR. property_type Property type. Default: `QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: `QVL_COVER_ALL. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr Signal or expression to check. 92 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_coverage Description The test_expr must not be 1 when the checker is active. The checker checks the single-bit expression test_expr at each rising edge of clk whenever active is TRUE. If test_expr is 1, the assertion fails and msg is printed. This checker is used to determine coverage of the test_expr and to gather coverpoint data. As such, the sense of the assertion is reversed. Unlike other QVL checkers (which verify assertions that are not expected to fail), qvl_coverage checkers’ assertions are intended to fail. You can set property_type to `QVL_IGNORE to disable the QVL_COVERED assertion check, but retain the collection of cover point data. Assertion Checks COVERAGE The HDL statement was covered. Expression evaluated to 1. Cover Points Corner Cases All Subexpressions Covered If 1, test_expr was covered at least once when the checker was active. This cover point is for compatibility with a future enhancement of this checker. Statistics Covered Count Number of times test_expr was 1 when active was TRUE. See also qvl_value_coverage Example qvl_coverage #( .severity_level(‘QVL_INFO), .property_type(‘QVL_ASSERT), .msg(“QVL_COVERAGE: queue full”), .coverage_level(‘QVL_COVER_ALL)) qvl_cover_queue_state_full( .clk(clk), .reset_n(reset_n), .active(accept_requests), .test_expr(cur_state == FULL)); Issues a coverage message when accept_requests is TRUE and cur_state is FULL at the rising edge of clk. Questa Verification Library Checkers Data Book, 2010.1a 93 QVL Checker Data Sheets qvl_coverage clk reset_n accept_requests cur_state EMPTY Q2 FULL Q3 Q2 Q1 QVL_COVERAGE The HDL statement was covered 94 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_crc qvl_crc Ensures that the CRC checksum values for a specified expression are calculated properly. test_expr[width-1:0] initialize valid qvl_crc compare crc[crc_width-1:0] crc_latch clk reset_n active Parameters: severity_level property_type msg coverage_level width data_width crc_width crc_enable crc_latch_enable polynomial initial_value lsb_first big_endian reverse_endian invert combinational Class: event-bounded assertion Application: datapath Syntax qvl_crc [#(severity_level, property_type, msg, coverage_level, width, data_width, crc_width, crc_enable, crc_latch_enable, polynomial, initial_value, lsb_first, big_endian, reverse_endian, invert, combinational)] instance_name (clk, reset_n, active, test_expr, initialize, valid, compare, crc, crc_latch); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width Width of test_expr. Default: 1. data_width Width of a data item in the message stream. data_width = 0 Data item width is width bits (i.e., test_expr holds a complete data item). data_width = n × width (n > 0) Data item width is n times the width of test_expr. Each data item is the concatenation of the values of test_expr collected over n valid cycles. For example, if test_expr has the values 2’b11, 2’b10, 2’b01 and 2’b10 over 4 consecutive valid cycles, then the corresponding data item is 8’b11100110. Questa Verification Library Checkers Data Book, 2010.1a 95 QVL Checker Data Sheets qvl_crc crc_width Degree of the CRC generator polynomial, width of the CRC checksum and width of the crc port (if crc_enable is 1). Default: 5. crc_enable Which data port contains the input CRC value. crc_enable = 0 (Default) Test_expr contains the input CRC value. Crc_width cannot be < width, or a CRC check violation occurs each compare cycle. The crc port is ignored. crc_enable = 1 The crc port contains the complete input CRC value. crc_latch_enable Whether or not to latch the internal CRC register value. crc_latch_enable = 0 (Default) The current value of the CRC register is compared with the input CRC value when compare asserts. The crc_latch port is ignored. crc_latch_enable = 1 The current value of the CRC register is latched if crc_latch is TRUE. The latched CRC value is compared with the input CRC value when compare asserts. polynomial Normal representation of the CRC generator polynomial. Equal to the concatenation of the polynomial coefficients in descending order, skipping the high-order coefficient. For example, the polynomial value representing: x 16 +x 12 5 +x +1 is 4h'1021 (16'b0001 0000 0010 0001). Default: 5'b00101 ( x5 + x2 + 1 ) initial_value Initial value of the internal CRC register. initial_value = 0 (Default) All 0’s, for example: 8'h00000000. initial_value = 1 All 1’s, for example: 8'b11111111. initial_value = 2 Alternating 10’s, for example: 8'b10101010. initial_value = 3 Alternating 01’s, for example: 8'b01010101. lsb_first Bit order in the CRC register. lsb_first = 0 (Default) MSB first bit order. lsb_first = 1 LSB first bit order (i.e., reflected). 96 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_crc big_endian Byte order of a message data item. big_endian = 0 (Default) Little-endian byte order. big_endian = 1 Big-endian byte order. reverse_endian Byte order in the CRC value. reverse_endian = 0 (Default) Byte order is the same as the byte order of a message data item (i.e., same as the big_endian parameter). reverse_endian = 1 Byte order is the opposite of the byte order of a message data item (i.e., inverse of big_endian parameter). invert Sense of the input CRC value. invert = 0 (Default) Input CRC value is the CRC checksum. invert = 1 Input CRC value is the inverted CRC checksum. combinational Type of logic used to calculate CRC values. combinational = 0 (Default) CRC is calculated sequentially. The input CRC value is the CRC checksum for the previous cycle. combinational = 1 CRC is calculated combinationally. The input CRC value is the CRC checksum for the current cycle. Ports clk Clock event for the checker. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. test_expr[width-1:0] Variable or expression containing the input data. initialize Initialization signal. If TRUE, the checker loads its internal CRC register with the initial value specified by the initial_value parameter (before reading test_expr). valid Data valid signal. If TRUE, the checker loads the next group of bits from the message stream (or the input CRC value if compare is TRUE and the crc_enable parameter is 0) from test_expr. compare CRC check signal. If TRUE, the checker initiates a crc assertion check in the current cycle. Questa Verification Library Checkers Data Book, 2010.1a 97 QVL Checker Data Sheets qvl_crc crc[crc_width-1:0] Variable or expression containing the input CRC value if the crc_enable parameter is 1. If crc_enable is 0, this port is ignored. crc_latch Internal CRC register latch signal. If TRUE, the checker loads and processes the test_expr value (if valid) and latches the value of the internal CRC register for comparison with an input CRC value (the next cycle compare asserts). This input is ignored unless crc_latch_enable is 1. Description The qvl_crc checker ensures CRC checksums are calculated properly. The checker evaluates the initialize signal at each rising edge of clk whenever active is TRUE. If initialize is TRUE, the checker restarts its CRC calculation algorithm, which initializes the internal CRC register to the initial value specified by the initial_value parameter. After that, in the current cycle and in each subsequent cycle, the checker checks the valid signal. If valid is TRUE and compare is FALSE, the value of test_expr is taken as the next group of bits in the message stream. By default, this group is shifted into the internal CRC register, displacing the group at the opposite end and the internal CRC register is then updated with the CRC register value XORed with a value from a lookup table. This internal CRC value is the calculated CRC checksum for the message stream read from test_expr since initialization. After initialization, the checker also checks the compare signal each cycle. By default: • width ≥ crc_width If compare and valid are both TRUE, the checker compares the value of test_expr with the internal CRC value. If they do not match, a CRC check violation occurs. • width < crc_width If compare and valid are both TRUE, the checker compares the value of test_expr with the first width bits of the internal CRC value. If they do not match, a CRC check violation occurs. Then, each successive cycle in which compare and valid are both TRUE, the checker compares the value of test_expr with the corresponding bits of the internal CRC value. If they do not match, a CRC check violation occurs. Because applications for CRC checking are so diverse, the qvl_crc checker contains a generic CRC calculator adaptable to virtually any CRC scheme and implementation. The following information is required to configure the calculator properly: • Data stream handling The algorithm shifts data into the CRC register and generates the internal CRC value one data item at a time. By default, the test_expr port contains an entire data item. However, the checker can support serial input and systems where data items are loaded in multibit pieces. In these cases, specify the width of a data item with the data_width parameter. The checker will accumulate the data item from test_expr over consecutive 98 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_crc valid cycles and on the last cycle (i.e., when the data item is complete) shift the data item onto the CRC register. • Algorithm controls The standard variations on CRC computation are configured with checker parameters. The CRC generator polynomial is specified by setting the polynomial parameter to its normal representation. LSB first and big-endian data representation conventions are selected by setting the lsb_first and big_endian parameters respectively to 1. • CRC comparison By default, the input CRC values are embedded in the data stream seen at the test_expr port. Setting the crc_enable parameter to 1 configures the checker to take the input CRC value from the crc port instead, so message data load and CRC compare operations can overlap. Input CRC transformations that invert the sense and flip the endian nature of CRC values are controlled with the invert and reverse_endian parameters respectively. • CRC computation timing CRC comparison can be adjusted to handle the different time requirements for various implementations. By default, the current internal CRC register value is used when comparing input and expected CRC values. Setting the crc_latch_enable parameter to 1 configures the checker to latch the current internal CRC register value each cycle crc_latch is TRUE (and then initialize the register). In the next cycle compare is TRUE, the input CRC value is compared with the latched value (even as a new message is being accumulated and a new CRC is being calculated). By default, the checker assumes the input CRC is calculated sequentially, so the input CRC value reflects the message accumulated up to the previous clock cycle. Setting the combinational parameter to 1 configures the checker to assume the computation is combinational. The input CRC value reflects the message accumulated up to the current clock cycle. Questa Verification Library Checkers Data Book, 2010.1a 99 QVL Checker Data Sheets qvl_crc Standard CRC polynomials: Name crc_width Generator Polynomial 5 7 polynomial 2 3 CRC-5USB 5 x +x +1 CRC-7 7 x +x +1 CRC-16CCITT 16 x CRC-32IEEE802.3 32 x x CRC-64ISO 64 x 16 32 10 64 +x +x 12 26 2'h05 2'h09 5 +x +1 23 +x 8 7 4 +x 3 4'h1021 22 5 +x 4 16 +x 12 +x 11 8'h04C11DB7 2 +x +x +x +x +x +x+1 +x +x +x+1 16'h000000000 000001B Uses: CRC, error detection, data path, interface. Assertion Checks CRC Input CRC value did not match the expected CRC value. =0 Compare was TRUE, but the value of test_expr (or inverted value if invert is 1) does not match the internal CRC value calculated for the associated message stream. crc_enable = 1 Compare was TRUE, but the value of crc (or inverted value if invert is 1) does not match the internal CRC value calculated for the associated message stream. crc_enable Cover Points Corner Cases Cycles Checked Number of cycles CRC checksum comparisons were performed. Statistics Total CRC Computations 100 Number of cycles the internal CRC register was updated. Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_crc See also none Examples qvl_crc #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(8), .crc_width(4), .crc_enable(1), .polynomial(4’b0101), .initial_value(0)) CRC1( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr(data_in), .initialize(start_crc), .valid(1’b1), .compare(1’b1), .crc(crc_out), .crc_latch(1’b0)); Checks that CRC checksums are calculated properly on all active edges of the clock. The CRC generator polynomial is x4 + x2 + 1 . qvl_crc #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(8), .crc_width(4), .crc_enable(1), .crc_latch_enable(1), .polynomial(4’b0101), .initial_value(0)) CRC2( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr(data_in), .initialize(start_crc), .valid(1’b1), .compare(!sel_data), .crc(crc_out), .crc_latch(data_block_rdy)); Checks that CRC checksums (latched when data_block_rdy asserts) are equal to the input CRC checksums on crc_out when sel_data deasserts. The CRC generator polynomial is x4 + x2 + 1 . Questa Verification Library Checkers Data Book, 2010.1a 101 QVL Checker Data Sheets qvl_crc qvl_crc #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(32), .crc_width(32), .polynomial(8’h04C11DB7), .initial_value(1) .reverse_endian(1)) CRC3( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr(data_in), .initialize(start_crc), .valid(data_in_valid), .compare(crc_valid), .crc(32’b0), .crc_latch(1’b0)); Checks that reverse-endian transformations of the CRC checksums equal the values on data_in when data_in_valid and crc_valid both assert. The CRC generator polynomial is: x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 8 7 5 4 2 +x +x +x +x +x +x+1 qvl_crc #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(7), .crc_width(7), .crc_latch_enable(1), .polynomial(7’b0001001), .initial_value(1), .big_endian(1), .reverse_endian(1)) CRC4( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr(data_in), .initialize(start_crc), .valid(data_in_valid), .compare(sel_crc), .crc(7’b0), .crc_latch(data_block_rdy)); Checks that CRC checksums (latched when data_block_rdy asserts) are equal to the input CRC checksums on data_in when sel_crc asserts. Data values of data_in are big endian and CRC values of data_in are little endian. The CRC generator polynomial is x7 + x3 + 1 . 102 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_crc qvl_crc #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(4), .data_width(16), .crc_width(16), .polynomial(16’h1021), .initial_value(1)) CRC5( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr(data_in), .initialize(start_crc), .valid(data_in_valid), .compare(compare), .crc(16’b0), .crc_latch(1’b0)); Checks that the associated bits of CRC checksums equal the values on data_in when data_in_valid and compare both assert. Each 16-bit data item is composed of 4-bit groups accumulated over 4 consecutive valid data cycles. Each cycle a data item is complete, its value is shifted onto the CRC register and the register is updated with the internal CRC value. The input CRC value is also accumulated from data_in in consecutive valid data cycles (i.e., when data_in_valid is TRUE) if compare is TRUE. However, since the internal CRC value is known, a CRC check violation occurs each cycle the current group of data_in bits does not match the corresponding bits in the internal CRC value. The CRC generator polynomial is 16 12 5 x + x + x + 1. Questa Verification Library Checkers Data Book, 2010.1a 103 QVL Checker Data Sheets qvl_crc qvl_crc #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(112), .crc_width(16), .crc_enable(1), .polynomial(16’h1021), .initial_value(3), .combinational(1)) CRC5( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr(data_in[127:16), .initialize(valid), .valid(valid), .compare(valid), .crc(data_in[15:0]), .crc_latch(1’b0)); Checks that every cycle valid is TRUE, data_in[15:0] equals the CRC checksum for the current value of data_in[127:16] with an initial value of 4’h5555. The CRC generator polynomial is 16 12 5 x + x + x + 1. qvl_crc #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(128), .crc_width(16), .crc_enable(1), .polynomial(16’h1021)) CRC5( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr(data_in), .initialize(1’b1), .valid(1’b1), .compare(1’b1), .crc(crc), .crc_latch(1’b0)); Checks that every active clock cycle, the value of crc equals the CRC checksum of the value of data_in sampled in the previous cycle. The CRC generator polynomial is x 16 + x 12 + x 5 + 1 . 104 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_data_loaded qvl_data_loaded Ensures that a register is loaded within a specified event window. start stop qvl_data_loaded load_condition clk reset_n active Parameters: severity_level property_type msg coverage_level start_count stop_count restart no_restart_check Class: event-bounded assertion Application: datapath Syntax qvl_data_loaded [#(severity_level, property_type, msg, coverage_level, start_count, stop_count, restart, no_restart_check)] instance_name (clk, reset_n, active, start, stop, load_condition); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. start_count Number of cycles after start asserts that the event window opens (unless a window is open and window restarts are not enabled). Default: 0 (window opens in the cycle start asserts). stop_count Number of cycles after start asserts that an event window closes if it is still open. Stop_count must be ≥ start_count. Default: 0 (open window closes in the same cycle start asserts). restart How to handle event window restarts. restart = 0 (Default) Window restarts are disabled. Asserting start is ignored if it would cause an event window to open in a cycle in which an existing window is open or is closing. restart = 1 Window restarts are enabled. Asserting start causes a new window to open, even if the window opens in a cycle in which an existing window is open or is closing. The pending data_loaded check is discarded (even when the window closes and restarts in the same cycle). Questa Verification Library Checkers Data Book, 2010.1a 105 QVL Checker Data Sheets qvl_data_loaded no_restart_check Whether or not to perform no_restart checks. no_restart_check = 0 (Default) Turns off the no_restart check. no_restart_check = 1 Turns on the no_restart check. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to sample the inputs and conduct data_loaded and no_restart checks. The checker remains in its last state when inactive (i.e., the event window state is preserved and any pending checks remain in effect). start Expression that indicates a start event. The checker opens an event window start_count cycles after start asserts, except when one of the following is true for that cycle: • stop = TRUE • restart = 0 and an event window is open or is closing stop Expression that closes an open window. Other events that close an open window in a cycle are: • Cycle is stop_count cycles after the cycle in which the window opened. • Cycle has a no_restart check violation. • Load_condition is TRUE. load_condition Load condition for the register. Description The qvl_data_loaded checker ensures a register loads data in specified event windows. The checker evaluates the expression start at each rising edge of clk whenever active is TRUE. If the value of start is TRUE, an event window opens start_count rising edges of clk later. The window closes when one of the following occurs: • Load_condition is TRUE at the rising edge of clk (i.e., the register loads data). • Stop is TRUE at the rising edge of clk. • Stop_count rising edges of clk elapse after the cycle start asserted. • A no_restart check violation occurs. The checker returns to the state of checking start in the next cycle that stop is FALSE. 106 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_data_loaded If load_condition is not TRUE when the window closes, a data_loaded violation occurs. Note that if the register loads data in the cycle a multicycle window opens, the loading is considered to be outside the window. If the register loads data in the cycle a window closes, the loading is considered inside the window. By default, a restart cannot occur. That is, start is ignored from the cycle it is sampled TRUE to the cycle the window closes. However, setting the restart parameter to 1 configures the checker to sample start every cycle. If start is TRUE, the checker closes the previous window (without issuing a data_loaded violation) and a new event window is opened start_count cycles later. However, if no_restart_check is 1, a no_restart violation also occurs. Assertion Checks DATA_LOADED The register was not loaded before stop_count cycles after start asserted. stop = 0 Event window closes stop_count cycles after start asserts, but the register does not load a value while the event window is open. The register was not loaded before stop asserted. stop = 1 NO_RESTART Event window closes when stop asserts, but the register does not load a value while the event window is open. Illegal restart, start asserted before the window closed. no_restart_check = 1 and start = 1 Start is TRUE and the event window is open or is closing. Cover Points Corner Cases Data Loaded at the Beginning of the Window Data Loaded at the End of the Window If non-zero, then the register loaded data in the cycle following the cycle an event window opened. If non-zero, then the register loaded data in the same cycle an event window closed. Statistics Windows Checked Number of event windows checked. See also qvl_data_used Questa Verification Library Checkers Data Book, 2010.1a 107 QVL Checker Data Sheets qvl_data_used qvl_data_used Ensures that valid register data are used within a specified event window. test_expr[width-1:0] load_condition used_condition valid qvl_data_used flush start stop clk reset_n active Parameters: severity_level property_type msg coverage_level width any_load start_enable restart no_restart_check start_count stop_enable stop_count Class: event-bounded assertion Application: datapath Syntax qvl_data_used [#(severity_level, property_type, msg, coverage_level, width, any_load, start_enable, restart, no_restart_check, start_count, stop_enable, stop_count)] instance_name (clk, reset_n, active, test_expr, valid, load_condition, used_condition, flush, start, stop); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default: 2. any_load What is considered a data load for the register. any_load = 0 (Default) Register is considered loaded if it loads a value different from the existing value. any_load = 1 Register is considered loaded if it loads any value, whether or not the value is different from the existing value. start_enable How to open an event window. start_enable = 0 (Default) Window opens when the register is loaded with a valid value (start, start_count and restart are ignored). start_enable = 1 Window opens start_count cycles after start asserts. 108 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_data_used restart How to handle event window restarts. restart = 0 (Default) Window restarts are disabled. Asserting start is ignored if it would cause an event window to open in a cycle in which an existing window is open or is closing. restart = 1 Window restarts are enabled. Asserting start causes a new window to open, even if the window opens in a cycle in which an existing window is open or is closing. The pending data_used check is discarded (even when the window closes and restarts in the same cycle). no_restart_check Whether or not to perform no_restart checks. no_restart_check = 0 (Default) Turns off the no_restart check. no_restart_check = 1 Turns on the no_restart check. start_count Number of cycles after start asserts that the event window opens (unless a window is open and window restarts are not enabled). Start_count is ignored if start_enable is 0. Default: 0 (window opens in the cycle start asserts if start_enable is 1). stop_enable Whether or not to sample stop. stop_enable = 0 (Default) Stop is ignored. stop_enable = 1 Asserting stop closes an open window. A new window cannot open while stop is asserted. stop_count Number of cycles after start asserts that an event window closes if it is still open. Stop_count must be ≥ start_count. Default: 0 (open window closes in the same cycle the window opens). Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to sample the inputs and conduct data_used and no_restart checks. The checker remains in its last state when inactive (i.e., the event window state is preserved and any pending checks remain in effect). test_expr[width-1:0] Register containing the data to be used. Questa Verification Library Checkers Data Book, 2010.1a 109 QVL Checker Data Sheets qvl_data_used Flag indicating the status of the value loaded into the register. valid valid= 0 Register value is not valid. valid = 1 Register value is valid. Ignored if start_enable is 1. load_condition Load condition for the register. used_condition Used condition for the register. start Expression that indicates a start event (ignored unless start_enable is 1). The checker opens an event window start_count cycles after start asserts, except when one of the following is true for that cycle: • stop = TRUE • restart = 0 and an event window is open or is closing stop Expression that closes an open window (if stop_enable is 1). Other events that close an open window in a cycle are: • Cycle is stop_count cycles after the cycle in which the window opened. • Cycle has a no_restart check violation. • Used_condition is TRUE. Description The qvl_data_used checker ensures that valid data loaded into a register are used in specified event windows. The checker evaluates load_condition, test_expr and valid at each rising edge of clk whenever active is TRUE. If load_condition and valid are TRUE and the value of test_expr is different from its previous value (or if test_expr has not been evaluated since reset), the event window opens. The window closes when one of the following occurs: • Used_condition is TRUE at the rising edge of clk (i.e., valid register data are used). • Load_condition is TRUE, used_condition is FALSE and the value of test_expr is different from the previous valid data value at the rising edge of clk (i.e., valid register data are overwritten). • Stop is TRUE at the rising edge of clk (and stop_enable is set to 1). • Stop_count rising edges of clk elapse after valid data are loaded (or after start asserts, if start_enable is 1). The checker returns to the state of checking load_condition, test_expr and valid in the next cycle (or the next cycle that stop is FALSE , if stop_enable is 1). 110 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_data_used If used_condition is not TRUE when the window closes, a data_used violation occurs. Note that if the register uses data in the cycle a multicycle window opens, it is not considered to be inside the window. If the register uses data in the cycle a window closes, it is considered to be inside the window. The checker can be configured to use a different mechanism for opening an event window. By setting start_enable to 1, the checker evaluates the expression start (in addition to load_condition and test_expr) at each rising edge of clk whenever active is TRUE. If the value of start is TRUE, an event window opens start_count rising edges of clk later. For this mechanism, by default, a restart cannot occur. That is, start is ignored from the cycle it is sampled TRUE to the cycle the window closes. However, setting the restart parameter to 1 configures the checker to sample start every cycle. If start is TRUE, the checker closes the previous window (without issuing a data_used violation) and a new event window is opened start_count cycles later. However, if no_restart_check is 1, a no_restart violation also occurs. The checker also can be configured (any_load = 1) to consider any loading of test_expr to be a load, even if the value of test_expr does not change. Assertion Checks DATA_USED The register data was not used before the event window closed. stop = 0 Event window closes but used_cond is always FALSE in the event window. The register was loaded with new data before the previous contents of the register were used. stop = 1 Load_condition is TRUE while a data_used check is pending. NO_RESTART Illegal restart, start asserted before the window closed (no_ restart_check = 1) and (start = 1) and (start_enable = 1) Start is TRUE and the event window is open or is closing. Cover Points Corner Cases Data Used at the Beginning of the Window If non-zero, then the register data was used in the cycle following the cycle an event window opened. Data Used at the End of the Window If non-zero, then the register data was used in the same cycle an event window closed. Questa Verification Library Checkers Data Book, 2010.1a 111 QVL Checker Data Sheets qvl_data_used Statistics Values Checked Number of values checked. See also qvl_data_loaded 112 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_decoder qvl_decoder Ensures that values are properly decoded by a binary decoder. Parameters: severity_level property_type msg in_data[width-1:0] qvl_decoder out_data[width-1:0] clk reset_n active coverage_level in_width out_width msb Class: single-cycle assertion Application: datapath Syntax qvl_decoder [#(severity_level, property_type, msg, coverage_level, in_width, out_width, msb)] instance_name (clk, reset_n, active, in_data, out_data); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. in_width Width of the input to the decoder. Default : 1. out_width Width of the decoded output from the decoder. The out_width parameter must be ≥ 2**in_width. Default: 2. msb Direction to perform the decoding: msb = 0 (Default) LSB decoding: least-significant bit corresponds to 0. For example, 3‘b011 is decoded to 8‘b0000_1000. msb = 1 MSB decoding: most-significant bit corresponds to 0. For example, 3‘b011 is decoded to 8‘b0001_0000. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. Questa Verification Library Checkers Data Book, 2010.1a 113 QVL Checker Data Sheets qvl_decoder active Expression that indicates whether or not to check the inputs. in_data[in_width-1:0] Encoded input to the decoder. out_data [out_width-1:0] Decoded output from the decoder. Description The qvl_decoder assertion ensures the output of a binary decoder is properly decoded from its input. The checker evaluates in_data and out_data at each rising edge of clk whenever active is TRUE. If the value of out_data does not equal the decoded value of in_data, a decode check violation occurs. Binary decoding takes the input value and returns a one-hot binary value where the ordinal value of the input is the bit position (starting with value 0). By default, the least-significant bit (LSB) is the first bit position. So, 0 is decoded to 1; 1 is decoded to 10; 2 is decoded to 100; and so on. A reversed order (msb) decoding can be specified where the most-significant bit is the first bit position. So, if out_width is 8, 0 is decoded to 1000_0000, 1 is decoded to 100_0000, 2 is decoded to 10_0000 and so on. Uses: FSM, state machine, controller, multiplexer (MUX), encoder, decoder, memory, register array. Assertion Checks DECODE Decoded value was not valid. The value of out_data did not equal the decoded value of in_data. Cover Points Corner Cases All Decodes Checked If non-zero, all possible input values have been decoded. Statistics Decode Count Number of times in_data is decoded. Decodes Checked Number of unique decodes checked. See also qvl_encoder 114 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_decoder Examples qvl_decoder #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_DECODER_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .in_width(3), .out_width(8), .msb(0)) U1 ( .active(active), .clk(clock), .reset_n(!(areset || reset)), .in_data(decode_in), .out_data(decode_out)); Checks that the decoded value of in_data is equal to out_data. qvl_decoder #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_DECODER_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .in_width(3), .out_width(8), .msb(1)) U2 ( .active(active), .clk(clock), .reset_n(!(areset || reset)), .in_data(decode_in), .out_data(decode_out)); Checks that the decoded value of in_data is equal to out_data. Also checks the most significant bit decoding. Questa Verification Library Checkers Data Book, 2010.1a 115 QVL Checker Data Sheets qvl_decoder_8b10b qvl_decoder_8b10b Ensures that data streams of 8B/10B encoded symbols are properly decoded by a decoder. in_10b[10*num_decoders-1:0] out_k[num_decoders-1:0] out_8b[8*num_decoders-1:0] rd[rd_width*-1:0] qvl_decoder_8b10b force_rd_enable[num_decoders-1:0] force_rd[num_decoders-1:0] reserved_k_codes [reserved_k_width**-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level num_decoders cascade reserved_k_codes_count disparity_check Class: n-cycle assertion Application: datapath *rd_width = cascade ? 1 : num_decoders **reserved_k_width = num_reserved_k_codes ? (8*num_reserved_k_codes) : 1 Syntax qvl_decoder_8b10b [#(severity_level, property_type, msg, coverage_level, num_decoders, cascade, reserved_k_codes_count, disparity_check)] instance_name (clk, reset_n, active, in_10b, out_k, out_8b, rd, force_rd_enable, force_rd, reserved_k_codes); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: “QVL_VIOLATION : ” coverage_level Coverage level. Default: ‘QVL_COVER_NONE num_decoders Number of 8B/10B decoder units in the decoder. For a multibyte decoder, specify multiple 8B/10B decoder units. Default: 1. 116 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_decoder_8b10b cascade Internal connectivity used to encode the data (when encoding a multibyte data stream). Ignored if num_decoders is 1 or disparity_check is 0. cascade = 0 (Default) Non-cascading encoder configuration. The output running disparity bit feeds back to the same encoder after a 1-cycle delay. cascade = 1 Cascading encoder configuration. The output running disparity bit cascades combinationally to the next higherorder encoder unit. The output running disparity bit for the high-order encoder feeds back to the low order encoder unit after a 1-cycle delay. reserved_k_codes_count Number of reserved special control characters. reserved_k_codes_count = 0 (Default) Turns off the reserved_k_code check. reserved_k_codes_count > 0 Turns on the reserved_k_code check. Sets the width of the reserved_k_codes port to 8 * reserved_k_codes_count. Each cycle, the reserved_k_codes port contains a concatenated list of reserved (8-bit) special control characters. disparity_check Whether or not to perform disparity checks. disparity_check = 0 (Default) Turns off the disparity check. disparity_check = 1 Turns on the disparity check. Ports clk Clock event for the assertion. The assertion samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the decoder. in_10b [10*num_decoders-1:0] Concatenated list of 10-bit symbols input to the decoder. out_k [num_decoders-1:0] Concatenated list of K bits output from the decoder. A K bit determines whether the corresponding decoded byte contains data (k-bit = 0) or a special control character (k-bit = 1). out_8b [8*num_decoders-1:0] Concatenated list of 8-bit bytes output from the decoder. Questa Verification Library Checkers Data Book, 2010.1a 117 QVL Checker Data Sheets qvl_decoder_8b10b rd[rd_width-1:0] Running disparity bit (or bits) from the decoder. cascade = 0 Rd_width is num_decoders and rd is a concatenated list of output running disparity bits from the decoder units. cascade = 1 Rd_width is 1 and rd is the output running disparity bit from the high-order decoder unit. force_rd_enable [num_decoders-1:0] Concatenated list of force-rd-enable bits. If a force_rd_enable [n-1] bit is TRUE, the disparity input to the nth decoder unit is force_rd [n-1]. force_rd [num_decoders-1:0] Concatenated list of force-rd bits. Description The qvl_decoder_8b10b assertion ensures the output of an 8B/10B decoder is properly decoded from its input. Input to an 8B/10B decoder is a data stream of one or more 10-bit symbols reconstructed from the output of an 8B/10B encoder. The decoder is composed of decoder units that decode the 10-bit symbols in parallel. Each decoder unit decodes the input 10-bit symbol into a 1-bit K bit and an 8-bit byte. The value of the byte is a data byte if the K bit is 0 or a special control character if the K bit is 1. The decoder output is a port with the concatenated K bits and a port with the concatenated bytes in the corresponding order. Once a decoder has decoded a symbol, it calculates the running disparity from the decoding. Using this running disparity when analyzing the next symbol, the decoder can detect if it is a valid code for the disparity. If not, a transmission error has occurred. To perform this type of error detection, the decoder must implement the same number of decoders with the same (cascaded or non-cascaded) connectivity as the original encoder. in_10b low order force_rd_en[0] force_rd[0] byte 8B10B decoder unit out_8b out_k rd_out in_10b force_rd_en[0] force_rd[0] 8B10B decoder unit 1-cycle delay in_10b high force_rd_en[n] order force_rd[n] byte 8B10B decoder unit out_8b out_k rd_out 1-cycle delay non-cascading 8B/10B decoders out_8b out_k rd_out combinational in_10b force_rd_en[n] force_rd[n] 8B10B decoder unit out_8b out_k rd_out 1-cycle delay cascading 8B/10B decoders The qvl_decoder_8b10b assertion checker evaluates in_10b at each rising edge of clk whenever active is TRUE. The value of in_10b is a concatenated list of num_decoders 10-bit symbols. The checker analyzes each in_10b symbol in turn and checks that the symbol is a valid symbol 118 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_decoder_8b10b for the current running disparity. If it is not, an invalid_10b_symbol check violation occurs and no decode or disparity checks are performed for the cycle. Otherwise, the checker decodes the symbol to a 1-bit K bit and an 8-bit byte and compares the results with the corresponding K bit in out_k and byte in out_8b. If they do not match, a decode violation occurs. The checker can be configured to perform two additional checks: • reserved_k_codes check Setting the reserved_k_codes_count parameter > 0 turns on the reserved_k_codes check. Each cycle the checker reads reserved_k_codes_count 8-bit special character codes from the reserved_k_codes port. These are prohibited special characters for the current cycle. So if out_k is TRUE and out_8b matches one of the reserved special characters, a reserved_k_codes check violation occurs. • disparity check Each cycle, the checker calculates running disparity from the current encoding (to use for the invalid_10b_symbol check). Setting the disparity_check parameter to 1 turns on the disparity check. When the checker calculates the running disparity from an encoding, it compares the calculated disparity with the rd port value (single bit for cascading configurations or num_decoders bits for non-cascading configurations). If they do not match, a disparity check violation occurs. The checker also can be configured to model the following extension to the architecture: • The force_rd and force_rd_enable ports are used to override the input disparities of individual decoder units on a cycle-by-cycle basis (used for the invalid_10b_code and disparity checks). Uses: Ethernet PHY, PCI Express PHY, SERDES, SAS, 8B/10B decoders. Assertion Checks DECODE Decoder 8-bit output byte did not match the decoded 10-bit input symbol. Value of an 8-bit byte in out_8b did not equal the correctly decoded data byte or special control character for the corresponding 10-bit symbol in in_10b. Decoder output K bit did not match the decoded 10-bit input symbol. Value of a K bit in out_k did not equal the correctly decoded K bit for the corresponding 10-bit symbol in in_10b. Questa Verification Library Checkers Data Book, 2010.1a 119 QVL Checker Data Sheets qvl_decoder_8b10b INVALID_10B_SYMBOL Decoder 10-bit input symbol was not a valid 10B code value for the running disparity. Value of a 10-bit symbol in in_10b was not a valid 10B code value for the current running disparity. The decode and reserved_k_codes checks for invalid 10B symbols are turned off for the current cycle. RESERVED_K_CODE Decoder 8-bit output special control code was a reserved K code. reserved_k_codes_count > 0 Value of an 8-bit byte in out_8b matched a byte in reserved_k_codes and the corresponding decoded K bit was TRUE. DISPARITY Running disparity was not correct. disparity_check = 1 Bit value in rd did not match the calculated running disparity. For a cascaded decoder the value of rd is a single bit. For a non-cascaded decoder the value of rd is a concatenation of num_decoders bits. Cover Points Corner Cases All Data Codes Checked If non-zero, all possible data byte values have been decoded. All K Codes Checked If non-zero, all possible special control character values have been decoded (excluding reserved K codes). Statistics Decode Count Number of cycles the checker was active. Data Code Count Number of cycles out_8b contained a valid data value. K Code Count Number of cycles out_8b contained a valid special control character. Force Running Disparity Count Number of cycles force_rd_enable had a TRUE bit. Running Disparity Toggle Count Number of cycles a running disparity was toggled (i.e., an rd bit was TRUE or an force_rd_enable and corresponding force_rd bits were both TRUE). 120 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_decoder_8b10b Notes 1. The checker does not perform complete invalid_10b_symbol checks for some symbols. The next cycle after a reset or check violation, the low-order symbol (cascaded configuration) or all symbols (non-cascaded configuration) have indeterminate input disparities (except for forced disparities). For such a symbol, an invalid_10b_symbol check violation indicates the symbol is not valid for both -1 and +1 disparities. If the symbol is invalid for one, but not the other, a possible invalid_10b_symbol check violation is not reported. However, unless an unlikely immediate mirroring error occurs, the problem will surface in subsequent cycles. See also qvl_decoder qvl_encoder qvl_encoder_8b10b Examples qvl_decoder_8b10b #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Decoder Violation : "), .coverage_level(‘QVL_COVER_ALL), .num_decoders(1)) QVL_DE1 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .in_10b(symbol), .out_k(kbit), .out_8b(byte), .rd(1’b0), .force_rd_enable(1’b0), .force_rd(1’b0), .reserved_k_codes(1’b0)); Checks that values of kbit and byte are properly decoded from the value of symbol and that symbol contains a 10B symbol that is valid for the current running disparity. Questa Verification Library Checkers Data Book, 2010.1a 121 QVL Checker Data Sheets qvl_decoder_8b10b qvl_decoder_8b10b #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Decoder Violation : "), .coverage_level(‘QVL_COVER_ALL), .num_decoders(1), .reserved_k_codes_count(3), .disparity_check(1)) QVL_DE2 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .in_10b(symbol), .out_k(kbit), .out_8b(byte), .rd(rd), .force_rd_enable(1’b0), .force_rd(1’b0), .reserved_k_codes({8’h9C, 8’hDC, 8’hFC})); Checks that values of kbit and byte are properly decoded from the value of symbol, that symbol contains a 10B symbol that is valid for the current running disparity and that byte is not equal to a reserved special character (8h9C, 8hDC or 8hFC) when kbit is TRUE (i.e., encoding is not K28.4, K28.6 or K28.7). Also checks that rd matches the calculated running disparity for the decoding. qvl_decoder_8b10b #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Encoder Violation : "), .coverage_level(0), .num_decoders(4), .cascade(1), .disparity_check(1)) QVL_EN3 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .in_10b({symbol4, symbol3,symbol2,symbol1}), .out_k({kbit4, kbit3,kbit2,kbit1}), .out_8b({byte4, byte3,byte2,byte1}), .rd(rd), .force_rd_enable(3’b0), .force_rd(3’b0), .reserved_k_codes(1’b0)); Checks that byte1/kbit1, byte2/kbit2, … byte4/kbit4 are properly decoded values for their corresponding symbol1, symbol2, … symbol4 encodings. Checks that symbol1, symbol2, … symbol4 contain symbol values that are valid for the running disparities. (The running disparity for symbol1 combinationally drives the input disparity for byte2; the running disparity for symbol2 combinationally drives the input disparity for byte3; the running disparity for symbol3 combinationally drives the input disparity for byte4; and the running disparity for symbol4 sequentially drives the input disparity for byte1.) Checks that rd matches the correct running disparity. 122 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_driven qvl_driven Ensures that all bits of an expression are driven (not Z). Parameters: severity_level property_type test_expr[width-1:0] qvl_driven msg coverage_level width Class: single-cycle assertion clk reset_n active Application: user Syntax qvl_driven [#(severity_level, property_type, msg, coverage_level, width)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: `QVL_ERROR. property_type Property type. Default: `QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: `QVL_COVER_ALL. width Width of the test_expr argument. Default: 4. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. Description The qvl_driven checker ensures that all bits of the value of test_expr are driven when the checker is active. The checker evaluates the multiple-bit expression test_expr at each rising edge of clk whenever active is TRUE. If the value of any bit of test_expr is Z, a driven check violation occurs. A violation occurs each cycle test_expr has an Z bit. Questa Verification Library Checkers Data Book, 2010.1a 123 QVL Checker Data Sheets qvl_driven Assertion Checks DRIVEN The value contained undriven (Z) bits. Test_expr contained one or more Z bits. Cover Points Corner Cases none Statistics Values Checked Number of cycles test_expr was checked. See also qvl_known 124 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_encoder qvl_encoder Ensures that values are properly encoded by a priority or binary encoder. Parameters: severity_level property_type msg coverage_level in_data[width-1:0] qvl_encoder out_data[width-1:0] clk reset_n in_width out_width lsb multibit_check active Class: single-cycle assertion Application: datapath Syntax qvl_encoder [#(severity_level, property_type, msg, coverage_level, in_width, out_width, lsb, multibit_check)] instance_name (clk, reset_n, active, in_data, out_data); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. in_width Width of the input to the encoder. The in_width parameter must be ≥ 2**out_width. Default : 2. out_width Width of the encoded output from the encoder. Default: 1. lsb Direction to perform the encoding: lsb = 0 (Default) MSB encoding: most-significant bit corresponds to 0. For example, 8‘b0000_1000 is encoded to 3‘b100. lsb = 1 LSB encoding: least-significant bit corresponds to 0. For example, 8‘b0000_1000 is encoded to 3‘b011. multibit_check Whether or not to perform multibit checks. (Default) Turns off the multibit check. Use for a priority encoder. multibit_check = 0 multibit_check = 1 Turns on the multibit check. Use for a binary encoder. Questa Verification Library Checkers Data Book, 2010.1a 125 QVL Checker Data Sheets qvl_encoder Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. in_data[in_width-1:0] Input to the encoder. out_data [out_width-1:0] Encoded output from the encoder. Description The qvl_encoder assertion ensures a priority or binary encoder properly encodes its input values. The checker evaluates in_data and out_data at each rising edge of clk whenever active is TRUE. If in_data has no 1 bits, a zero check violation occurs. If the value of out_data does not equal the encoded value of in_data, an encode check violation occurs. (Encoding corresponds to the bit position of a 1 bit, so the input value cannot be 0. Therefore, a zero check is performed prior to the encoding check.) By default, the checker verifies an MSB priority encoder. The bit position of the first 1 bit is returned as a binary value at the encoder output. The most-significant bit (MSB) is the first bit position. So if in_width is 8, 1111_1111 is encoded as 0; 0111_1111 is encoded as 1; 0011_111 is encoded as 2; and so on. For priority encoding, only the first 1 bit is relevant, for example, the encoded values of 0000_1111, 0000_1001, 0000_1000 and so on are the same (4). A reversed order (lsb) encoding can be specified where the least-significant bit is the first bit position. So, 1 is encoded to 0, 10 is decoded to 1, 100 is encoded to 2 and so on. Also, binary encoding uses the same encoding scheme as priority encoding. However, priority encoding allows multiple 1 bits in the encoder input, whereas binary encoding requires that the encoder input has only one 1 bit. For binary encoders, you can enable the multibit check, which verifies that not input value has more than one 1 bit. Uses: FSM, state machine, controller, multiplexer (MUX), encoder, decoder, memory, register array. Assertion Checks ENCODE Encoded value was not valid. The value of out_data did not equal the encoded value of in_data. 126 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_encoder ZERO Input value had no bits asserted. All bits of in_data were 0. MULTIBIT Input value had more than one bit asserted. More than one bit of in in_data was equal to 1. Cover Points Corner Cases All Encodes Checked If non-zero, all input values have been encoded. Statistics Encode Count (Evals) Number of times the in variable is encoded and the encode check with out variable is performed. Encodes Checked Number of encodes checked. See also qvl_decoder Examples qvl_encoder #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_ENCODER_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .in_width(8), .out_width(3), .lsb(0), .multibit_check(0)) U1 ( .active(active), .clk(clock), .reset_n(!(areset || reset)), .in_data(enpr_in), .out_data(encpr_out)); Checks that in_data is properly priority encoded and that the coded value is equal to out_data. Questa Verification Library Checkers Data Book, 2010.1a 127 QVL Checker Data Sheets qvl_encoder qvl_encoder #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_ENCODER_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .in_width(8), .out_width(3), .lsb(1), .multibit_check(0)) U2 ( .active(active), .clk(clock), .reset_n(!(areset || reset)), .in_data(en_in), .out_data(enc_out)); Checks that in_data is properly encoded. Also checks the least significant bit encoding. 128 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_encoder_8b10b qvl_encoder_8b10b Ensures that data streams of byte or multibyte values are properly encoded by an 8B/10B encoder. in_8b[10*num_encoders-1:0] in_k[num_encoders-1:0] out_10b[8*num_encoders-1:0] rd[rd_width*-1:0] qvl_encoder_8b10b force_rd_enable[num_encoders-1:0] force_rd[num_encoders-1:0] reserved_k_codes [reserved_k_width**-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level num_encoders initial_rd cascade reserved_k_codes_count disparity_check Class: n-cycle assertion Application: datapath *rd_width = cascade ? 1 : num_encoders **reserved_k_width = reserved_k_codes_count ? (8*reserved_k_codes_count) : 1 Syntax qvl_encoder_8b10b [#(severity_level, property_type, msg, coverage_level, num_encoders, initial_rd, cascade, reserved_k_codes_count, disparity_check)] instance_name (clk, reset_n, active, in_8b, in_k, out_10b, rd, force_rd_enable, force_rd, reserved_k_codes); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: “QVL_VIOLATION : ” coverage_level Coverage level. Default: ‘QVL_COVER_NONE num_encoders Number of 8B/10B encoder units in the encoder. For a multibyte encoder, specify multiple 8B/10B encoder units. Num_encoders must be > 0. Default: 1. initial_rd Initial disparity used in the first cycle after reset. A value of 1 starts the encoder (or each encoder unit for a multibyte noncascaded encoder) with positive disparity. A value of 0 starts the encoder (or each encoder unit) with negative disparity. Default: 0. Questa Verification Library Checkers Data Book, 2010.1a 129 QVL Checker Data Sheets qvl_encoder_8b10b cascade Internal connectivity for a multibyte encoder. Ignored if num_encoders is 1. cascade = 0 (Default) Non-cascading encoder configuration. The output running disparity bit feeds back to the same encoder after a one-cycle delay. cascade = 1 Cascading encoder configuration. The output running disparity bit cascades combinationally to the next higherorder encoder unit. The output running disparity bit for the high-order encoder feeds back to the low order encoder unit after a one-cycle delay. reserved_k_codes_count Number of reserved special control characters. reserved_k_codes_count = 0 (Default) Turns off the reserved_k_code check. reserved_k_codes_count > 0 Turns on the reserved_k_code check. Sets the width of the reserved_k_codes port to 8 * reserved_k_codes_count. Each cycle, the reserved_k_codes port contains a concatenated list of reserved (8-bit) special control characters. disparity_check Whether or not to perform disparity checks. disparity_check = 0 (Default) Turns off the disparity check. disparity_check = 1 Turns on the disparity check. Ports clk Clock event for the assertion. The assertion samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the encoder. in_8b [8*num_encoders-1:0] Concatenated list of 8-bit bytes input to the encoder. in_k [num_encoders-1:0] Concatenated list of K bits input to the encoder. A K bit determines whether the corresponding byte contains data (k-bit = 0) or a special control code (k-bit = 1). out_10b [10*num_encoders-1:0] Concatenated list of 10-bit symbols output from the encoder. 130 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_encoder_8b10b rd[rd_width-1:0] Running disparity bit (or bits) from the encoder. cascade = 0 Non-cascading encoder configuration. Each output running disparity bit feeds back to the same encoder unit as the rd input disparity for the next cycle (unless external disparity is forced). Here, rd_width is num_encoders and rd is a concatenated list of output running disparity bits from the encoder units. cascade = 1 Cascading encoder configuration. Each output running disparity bit cascades to the next encoder unit (combinationally) and the output running disparity bit for the high-order encoder cascades to the low order encoder unit (sequentially). Here, rd_width is 1 and rd is the output running disparity bit from the high-order encoder unit. force_rd_enable [num_encoders-1:0] Concatenated list of force-rd-enable bits. If a force_rd_enable [n-1] bit is TRUE, the disparity input to the nth encoder unit is force_rd [n-1]. force_rd [num_encoders-1:0] Concatenated list of force-rd bits. reserved_k_codes [reserved_k_width-1:0] Concatenated list of prohibited special control characters for the current cycle (in any order). Used for the reserved_k_code check. If reserved_k_codes_count is 0, the width of this port is 1 (connect this port to 1’b0). Otherwise, the width of this port is 8 * reserved_k_codes_count. Description The qvl_encoder_8b10b assertion ensures the output of an 8B/10B encoder is properly encoded from its input. The 8B/10B encoding scheme is designed to equalize the proportions of 0 and 1 bits in a serial transmission. To do this, a measure of the imbalance between the proportions of 0’s and 1’s is tracked when encoding data units. This disparity determines whether to use the same encoding scheme for the next unit or to switch to an alternate encoding scheme designed to correct the local imbalance. The resulting 8B/10b encoding assures no more than 4 consecutive serially transmitted bits have the same value. An encoding unit encodes an 8-bit byte and a 1-bit control flag (called the K bit) into a 10-bit symbol. The K bit indicates whether the byte is a data value or a special control character. An initial disparity bit is injected into the start of a data stream and the running disparity is calculated after each encoding. An 8B/10B encoding is actually a pair of 4B/5B encodings: the 8-bit byte is broken into two 4-bit pieces and these are converted into two 5-bit pieces that are combined to form a 10-bit symbol. The 4B/5B encodings are performed with four mapping tables, which are selected by the K bit and the running disparity. If the K bit is 0, the two data mapping tables are used; if the K bit is 1, the two special control character tables are used. To map a 4-bit value, the table that produces the opposite or neutral disparity from the current Questa Verification Library Checkers Data Book, 2010.1a 131 QVL Checker Data Sheets qvl_encoder_8b10b running disparity is the one used. The encoding mechanism always produces a positive or negative (i.e., non-neutral) running disparity at the symbol boundaries and the size of this disparity is exactly 1. The running disparity from encoding an 8-bit byte is fed back as the input disparity for the next encoded byte. An encoding unit encodes 8-bit bytes to 10-bit symbols. Typically, encoders are intended to encode multibyte data streams in parallel, so they are implemented with multiple encoder units, one unit per data byte. The connectivity of these units inside the encoder depends on how the encoder units’ outputs are transmitted. • Non-cascaded configuration Parallel symbol streams are serialized in separate, independent bit streams. Running disparity output from each encoder unit feeds sequentially back to the same unit to be used as the disparity for the next cycle. in_8b in_k force_rd_en[0] force_rd[0] out_10b 8B10B encoder unit low order byte rd_out 1-cycle delay in_8b in_k force_rd_en[n] force_rd[n] out_10b 8B10B encoder unit high order byte rd_out 1-cycle delay non-cascading 8B/10B encoders • Cascaded configuration Parallel symbol streams are serialized in a single, linked bit stream. Running disparity output from each encoder unit cascades combinationally to the next (higher-order byte) encoder unit to be used as the current disparity for the unit. The running disparity output bit from the highest-order byte encoder unit feeds sequentially back to the lowest-order byte encoder unit to be used as the disparity for the next cycle. 132 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_encoder_8b10b in_8b in_k force_rd_en[0] force_rd[0] out_10b 8B10B encoder unit rd_out low order byte combinational in_8b in_k force_rd_en[n] force_rd[n] out_10b 8B10B encoder unit rd_out high order byte 1-cycle delay cascading 8B/10B encoders Some encoders allow the input running disparity to be overridden on a cycle-by-cycle basis. A force-running-disparity input port provides the alternate disparity to apply instead of the running disparity output from the previous cycle. A force-running-disparity-enable port selects whether or not to override the actual running disparity bits with the forced bits. For single-byte and cascaded configuration encoders, each of these ports is 1 bit wide. For non-cascaded configuration encoders, these ports have one bit per encoder unit. The qvl_encoder_8b10b assertion checker evaluates in_k and in_8b at each rising edge of clk whenever active is TRUE. If the in_k bit is TRUE and the in_8b value is not a special control character, a k_code check violation occurs. Otherwise, the checker evaluates out_8b. By default, the input disparity used for the first cycle after reset is negative (-1). Also by default, each subsequent cycle uses the running disparity computed from the previous cycle as the input disparity. The checker uses this input disparity with in_8b and the in_k bit to determine the encoded value. If this value does not match the value of out_10b, an encode check violation occurs. The checker can be configured to perform two additional checks: • reserved_k_codes check Setting the reserved_k_codes_count parameter > 0 turns on the reserved_k_codes check. Each cycle the checker reads reserved_k_codes_count 8-bit special character codes from the reserved_k_codes port. These are prohibited special characters for the current cycle. So if in_k is TRUE and in_8b matches one of the reserved special characters, a reserved_k_codes check violation occurs. • disparity check Each cycle, the checker calculates running disparity from the current encoding to use as the input disparity in the next cycle. Setting the disparity_check parameter to 1 turns on the disparity check. When the checker calculates the running disparity from an encoding, it compares the calculated disparity with the rd port value. If they do not match, a disparity check violation occurs. Questa Verification Library Checkers Data Book, 2010.1a 133 QVL Checker Data Sheets qvl_encoder_8b10b The checker also can be configured to model the following extensions to the architecture: • Setting the initial_rd parameter to 1 sets the initial disparity to positive (+1). • Setting the num_encoders parameter > 1 configures the checker to monitor a multibyte encoder containing num_encoders encoder units. The in_k port contains a concatenated list of the K bits, the in_8b port contains a concatenated list of the input bytes and out_10b contains a concatenated list of the output symbols. By default, a non-cascaded configuration is assumed, so rd is a concatenated list of the num_encoders running disparity outputs from the encoder units. Setting the cascade parameter to 1 configures the checker for cascaded running disparities. • The force_rd and force_rd_enable ports are used to override the input disparities of individual encoder units on a cycle-by-cycle basis. Uses: Ethernet PHY, PCI Express PHY, SERDES, SAS, 8B/10B encoders. Assertion Checks ENCODE Encoder output 10-bit symbol did not match encoded value of corresponding 8-bit input byte. Value of a 10-bit symbol in out_10b did not equal the correctly encoded data or control byte for the corresponding 8-bit byte in in_10b, 1-bit K bit in in_k and the input disparity for the encoder unit. K_CODE Encoder input K bit was asserted, but the corresponding 10-bit output symbol was not an encoded special character. An in_k bit is TRUE but the corresponding in_8b value is not a special control character. K_code check violations turn off the encode and disparity checks for the corresponding encoder units. RESERVED_K_CODE Encoder input K bit was asserted, but the corresponding 8-bit input byte was a reserved special control character. reserved_k_codes_count > 0 Value of an 8-bit byte in in_8b matched a byte in reserved_k_codes and the corresponding in_k bit was TRUE. 134 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_encoder_8b10b DISPARITY Running disparity was not correct. disparity_check = 1 Value of the rd port was not correct. For a single-byte encoder or a cascaded multibyte encoder, the value of rd is a single-bit rd output from the high-order byte encoder unit. For a non-cascaded multibyte encoder, the value of rd is a concatenation of the rd bit outputs from the encoder units. If the corresponding force_rd_enable bit was TRUE, the rd bit did not equal the corresponding force_rd value. If the corresponding force_rd_enable bit was FALSE, the rd bit did not equal the feedback running disparity value (latched for the next cycle). Cover Points Corner Cases All Data Codes Checked If non-zero, all possible data byte values have been encoded. All K Codes Checked If non-zero, all possible special control character values have been encoded (excluding reserved K codes). Statistics Encode Count Number of cycles the checker was active. Data Code Count Number of cycles a bit in in_k was FALSE and the corresponding out_10b symbol was properly encoded from its in_8b data byte. K Code Count Number of cycles a bit in in_k was TRUE and the corresponding out_10b symbol was properly encoded from its in_8b special control character. Force Running Disparity Count Number of cycles force_rd_enable had a TRUE bit. Running Disparity Toggle Count Number of cycles a running disparity was toggled (i.e., an rd bit was TRUE or an force_rd_enable and corresponding force_rd bits were both TRUE). See also qvl_decoder qvl_decoder_8b10b Questa Verification Library Checkers Data Book, 2010.1a qvl_encoder 135 QVL Checker Data Sheets qvl_encoder_8b10b Examples qvl_encoder_8b10b #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("8B/10B Encoder Violation : "), .coverage_level(0), .num_encoders(1)) QVL_EN1 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .in_8b(byte), .in_k(kbit), .out_10b(symbol), .rd(1’b0), .force_rd_enable(1’b0), .force_rd(1’b0), .reserved_k_codes(1’b0)); Checks that the value of in_8b is a special control character when kbit is TRUE. Checks that the value of symbol is properly encoded from the current running disparity (initial running disparity is -1), the value of byte and the value of kbit. qvl_encoder_8b10b #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("8B/10B Encoder Violation : "), .coverage_level(‘QVL_COVER_ALL), .num_encoders(1), .num_reserved_k_codes(3), .disparity_check(1)) QVL_EN2 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .in_8b(byte), .in_k(kbit), .out_10b(symbol), .rd(rd), .force_rd_enable(1’b0), .force_rd(1’b0), .reserved_k_codes({8’h9C, 8’hDC, 8’hFC})); Checks that the value of symbol is properly encoded, that the byte value is a special control character when kbit is TRUE, that rd matches the correct running disparity when kbit is TRUE, and that byte does not equal a reserved code 8’h9C, 8’hDC, 8’hFC (i.e., encoding is not K28.4, K28.6 or K28.7). The initial running disparity is -1. 136 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_encoder_8b10b qvl_encoder_8b10b #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Encoder Violation : "), .coverage_level(0), .num_encoders(4), .initial_rd(1), .cascade(1), .disparity_check(1)) QVL_EN3 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .in_8b({byte4, byte3,byte2,byte1}), .in_k({kbit4, kbit3,kbit2,kbit1}), .out_10b({symbol4, symbol3,symbol2,symbol1}), .rd(rd), .force_rd_enable(3’b0), .force_rd(3’b0), .reserved_k_codes(1’b0)); Checks that byte1, byte2, … byte4 values are special control characters when the corresponding kbit1, kbit2, … kbit4 bits are TRUE. Checks that symbol1, symbol2, … symbol4 are properly encoded symbols for their corresponding byte1/kbit1, byte2/kbit2, … byte4/kbit4 values. Checks that rd matches the correct running disparity. The running disparity for symbol1 combinationally drives the input disparity for byte2; the running disparity for symbol2 combinationally drives the input disparity for byte3; the running disparity for symbol3 combinationally drives the input disparity for byte4; and the running disparity for symbol4 sequentially drives the input disparity for byte1. The initial disparity for byte1 is +1. Questa Verification Library Checkers Data Book, 2010.1a 137 QVL Checker Data Sheets qvl_fifo qvl_fifo Ensures the data integrity of a FIFO and ensures that the FIFO does not overflow or underflow. enq deq full empty qvl_fifo enq_data[width-1:0] deq_data[width-1:0] preload[preload_count*width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width depth pass registered high_water latency preload_count full_check empty_check value_check Class: event-bounded assertion Application: control and interface Syntax qvl_fifo [#(severity_level, property_type, msg, coverage_level, width, depth, pass, registered, latency, preload_count, high_water, full_check, empty_check, value_check)] instance_name (clk, reset_n, active, enq, deq, full, empty, enq_data, deq_data, preload); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of a data item. Default: 1. depth FIFO depth. The depth must be > 0. Default: 1. pass How the FIFO handles a dequeue and enqueue in the same cycle if the FIFO is empty. pass = 0 (Default) No pass mode. Simultaneous dequeue/enqueue of an empty FIFO is a dequeue violation. pass = 1 Pass mode. Simultaneous dequeue/enqueue of an empty FIFO is not a dequeue violation. 138 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_fifo registered How the FIFO handles an enqueue and dequeue in the same cycle if the FIFO is full. registered = 0 (Default) No registered mode. Simultaneous enqueue/dequeue of a full FIFO is an enqueue violation. registered = 1 Registered mode. Simultaneous enqueue/dequeue of a full FIFO is not an enqueue violation. latency Latency for dequeued data. If the value check is on, the value of deq_data has the dequeued FIFO data latency cycles after deq asserts. Default: 0 (deq_data is valid in the same cycle that deq asserts). preload_count Number of items to preload the FIFO on reset. The preload port is a concatenated list of items to be preloaded into the FIFO. Default: 0 (FIFO empty on reset). high_water FIFO high-water mark. Must be < depth. A value of 0 sets the high-water mark to depth - 1 (or 1 if depth is 1). Default: 0. full_check Whether or not to perform full checks. full_check = 0 (Default) Turns off the full check. full_check = 1 Turns on the full check. empty_check Whether or not to perform empty checks. empty_check = 0 (Default) Turns off the empty check. empty_check = 1 Turns on the empty check. value_check Whether or not to perform value checks. value_check = 0 (Default) Turns off the value check. value_check = 1 Turns on the value check. Ports clk Clock event for the checker. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. enq FIFO enqueue input. When enq asserts, the FIFO performs an enqueue operation in that cycle. A data item is enqueued onto the FIFO and the FIFO counter increments by 1. Questa Verification Library Checkers Data Book, 2010.1a 139 QVL Checker Data Sheets qvl_fifo deq FIFO dequeue input. When deq asserts, the FIFO performs a dequeue operation. A data item is dequeued from the FIFO (latency cycles later) and the FIFO counter decrements by 1. full Output status flag from the FIFO. full = 0 FIFO not full. full = 1 FIFO full. empty Output status flag from the FIFO. empty = 0 FIFO not empty. empty = 1 FIFO empty. enq_data[width-1:0] FIFO enqueue data input. Contains the data item to enqueue when enq is asserted. deq_data[width-1:0] FIFO dequeue data output. Contains the dequeued data item latency cycles after deq is asserted. preload [(preload_count * width)-1 : 0] Concatenated preload data to enqueue on reset. preload_count = 0 No preloading of the FIFO is assumed. The width of preload should be width, however, no values from preload are used. The FIFO is assumed to be empty on reset. preload_count > 0 Checker assumes the value of preload is a concatenated list of items to enqueue on the FIFO on reset (or simulation start). The width of preload should be preload_count * width (preload items are the same width). Preload values are enqueued from the low order item to the high order item. Description The qvl_fifo checker ensures a FIFO functions legally. A FIFO is a memory structure that stores and retrieves data items based on a first-in first-out queueing protocol. The FIFO has configured properties specified as parameters to the qvl_fifo checker: width of the data items (width), capacity of the FIFO (depth), and the high-water mark that identifies the point at which the FIFO is almost full (high_water). Control and data signals to and from the FIFO are connected to the qvl_fifo checker. The checker checks enq and deq at the active edge of clk each cycle the checker is active. If enq is TRUE, the FIFO has enqueued a data item onto the FIFO. If deq is TRUE, the FIFO is in the process of dequeuing a data item. The dequeue operation can take more than one cycle. The FIFO latency is the number of cycles it takes for the dequeued data item to appear at the deq_data output from the FIFO, after the cycle that deq is sampled TRUE. 140 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_fifo The checker ensures the FIFO does not enqueue an item when it is supposed to be full (enqueue check) and the FIFO does not dequeue an item when it is supposed to be empty (dequeue check). The checker can be configured to perform various additional checks such as verifying the data integrity of dequeued FIFO data (value check) and verifying that the FIFO’s full and empty status flags operate correctly (full and empty checks). The checker also can be configured to handle other FIFO characteristics such as preloading items on reset and allowing passthrough operations and registered enqueue/dequeues. Assertion Checks ENQUEUE An enqueue occurred while the FIFO was full. registered = 0 Enq was TRUE, but FIFO contained depth items. While the FIFO was full, an enqueue occurred without a dequeue in the same cycle. registered = 1 Enq was TRUE and deq was FALSE, but FIFO contained depth items. DEQUEUE A dequeue occurred while the FIFO was empty. pass = 0 Deq was TRUE, but FIFO contained 0 items. While the FIFO was empty, a dequeue occurred without an enqueue in the same cycle. pass = 1 Deq was TRUE and enq was FALSE, but FIFO contained 0 items. Questa Verification Library Checkers Data Book, 2010.1a 141 QVL Checker Data Sheets qvl_fifo FULL The FIFO was not full when the full signal was asserted. full_check = 1 Full was TRUE, but the FIFO contained fewer than depth items. The full signal was not asserted when the FIFO was full. full_check = 1 Full was FALSE, but the FIFO contained depth items. The checker expects the full signal to be sequential (i.e., it asserts the cycle following the cycle that the FIFO becomes full and deasserts the cycle following the cycle that the FIFO becomes less than full). EMPTY The FIFO was not empty when the empty signal was asserted. empty_check = 1 Empty was TRUE, but the FIFO contained at least one item. The empty signal was not asserted when the FIFO was empty. empty_check = 1 Empty was FALSE, but the FIFO contained no items. The checker expects the empty signal to be sequential (i.e., it asserts the cycle following the cycle that the FIFO becomes empty and deasserts the cycle following the cycle that the FIFO holds an item). 142 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_fifo VALUE Dequeued FIFO value did not equal the corresponding enqueued value. value_check = 1 and latency = 0 Deq was TRUE, but deq_data did not equal the corresponding enqueued item. value_check = 1 and latency > 0 Deq was TRUE, but latency cycles later deq_data did not equal the corresponding enqueued item. This check automatically turns off if an enqueue or dequeue check violation occurs since it is no longer possible to correspond enqueued with dequeued values. The check turns back on when the checker resets. Cover Points Corner Cases FIFO is Full Number of cycles the FIFO was full. FIFO is Empty Number of cycles the FIFO was empty. Simultaneous Enqueues and Dequeues Number of cycles the FIFO enqueued a value and dequeued a value together. FIFO is Over High-water Mark Number of cycles the number of FIFO items exceeded the highwater mark. Statistics Enqueues Number of cycles the FIFO enqueued a value. Dequeues Number of cycles the FIFO dequeued a value. See also qvl_multi_clock_multi_enq_deq_fifo Examples qvl_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: FIFO access violation”), .coverage_level(‘QVL_COVER_ALL), .depth(6), .width(16), .high_water(5), .full_check(1), Questa Verification Library Checkers Data Book, 2010.1a 143 QVL Checker Data Sheets qvl_fifo .empty_check(1), .preload_count(5)) qvl_valid_FIFO_access( .clk(clk), .reset_n(reset_n), .active(1’b1), .enq(fifo_enq), .deq(fifo_deq), .full(fifo_full), .empty(fifo_empty), .enq_data(4’hFFFF), .deq_data(4’hFFFF), .preload(80{1’b1})); Ensures that the FIFO does not enqueue when it is full or dequeue when it is empty. When an enqueue and dequeue occur in the same cycle, an enqueue violation occurs if the FIFO was full or a dequeue violation occurs if the FIFO was empty. Also ensures fifo_full is TRUE if (and only if) the FIFO is full and fifo_empty is TRUE if (and only if) the FIFO is empty. The FIFO is assumed to be initialized to hold 5 items (all 4’hFFFF) each time the checker is reset. clk reset_n fifo_enq fifo_deq FIFO count 5 6 5 6 5 4 fifo_full fifo_empty QVL_FIFO_FULL The FIFO was not full when the full signal was asserted. 144 QVL_FIFO_ENQUEUE An enqueue occurred while the FIFO was full. Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_fifo qvl_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: FIFO access violation”), .coverage_level(‘QVL_COVER_ALL), .depth(6), .width(16), .high_water(5), .pass(1), .registered(1), .preload_count(5)) qvl_valid_FIFO_access( .clk(clk), .reset_n(reset_n), .active(1’b1), .enq(fifo_enq), .deq(fifo_deq), .full(1’b0), .empty(1’b0), .enq_data(4’hFFFF), .deq_data(4’hFFFF), .preload(80{1’b1})); Ensures that the FIFO does not enqueue an item when it is full or dequeue an item when it is empty, except in cycles where both an enqueue (registered) and dequeue (pass) occur together. The FIFO is assumed to be initialized to hold 5 items (all 4’hFFFF) each time the checker is reset. clk reset_n fifo_enq fifo_deq FIFO count 5 6 5 6 7 QVL_ERROR: FIFO access violation An enqueue occurred while the FIFO was full. Questa Verification Library Checkers Data Book, 2010.1a 145 QVL Checker Data Sheets qvl_fifo qvl_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: FIFO access violation”), .coverage_level(‘QVL_COVER_ALL), .depth(6), .width(16), .high_water(5), .value_check(1), .latency(1), .preload_count(3)) qvl_valid_FIFO_access( .clk(clk), .reset_n(reset_n), .active(1’b1), .enq(fifo_enq), .deq(fifo_deq), .full(1’b0), .empty(1’b0), .enq_data(fifo_data_in), .deq_data(fifo_data_out), .preload(48{1’b1})); Ensures that the FIFO does not enqueue an item when it is full or dequeue an item when it is empty, except in cycles where both an enqueue (registered) and dequeue (pass) occur.together. Also ensures values dequeued (with a 1-cycle latency) equal the values enqueued The FIFO is assumed to be initialized to hold 3 items (all 4’hFFFF) each time the checker is reset. clk reset_n fifo_enq fifo_deq fifo_data_in f33f f22f 1 fifo_data_out f11f 2 3 ffff f33f f11f QVL_ERROR: FIFO access violation Dequeued FIFO value did not equal the corresponding enqueued value. 146 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_gray_code qvl_gray_code Ensures that only one bit of a specified expression changes. test_expr[width-1:0] qvl_gray_code Parameters: severity_level property_type msg coverage_level width Class: single-cycle assertion clk reset_n active Application: user Syntax qvl_gray_code [#(severity_level, property_type, msg, coverage_level, width)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of the test_expr argument. Default: 1. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. Questa Verification Library Checkers Data Book, 2010.1a 147 QVL Checker Data Sheets qvl_gray_code Description The qvl_gray_code checker ensures that test_expr is gray coded: successive values of test_expr differ by a hamming distance of 1. That is, only one bit of test_expr can change in any cycle. The checker checks test_expr at the active edge of clk (except for the first cycle after a reset and the first cycle the checker is activated or reactivated). It fires each time a gray_code violation occurs. Assertion Checks GRAY_CODE The value did not change by one bit when it changed. More than one bit of test_expr changes value in a cycle, Cover Points Statistics Values Checked Number of cycles the value of test_expr changed. See also qvl_hamming_distance Example qvl_gray_code #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: ptr_gray not gray-coded”), .coverage_level(‘QVL_COVER_ALL), .width(4)) qvl_valid_gray_coded_ptr( .clk(clk), .reset_n(reset_n), .active(!config), .test_expr(ptr_gray)); Ensures that when the value of ptr_gray changes, only 1 bit has changed. 148 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_gray_code clk reset_n !config ptr_gray 0000 1111 0001 0000 1000 1100 1010 1110 0110 QVL_GRAY_CODE The value did not change by one bit when it changed. Questa Verification Library Checkers Data Book, 2010.1a 149 QVL Checker Data Sheets qvl_hamming_distance qvl_hamming_distance Ensures that an expression changes only by a specified distance. test_expr[width-1:0] qvl_hamming_distance clk reset_n Parameters: severity_level property_type msg coverage_level width distance min max active Class: two-cycle assertion Application: user Syntax qvl_hamming_distance [#(severity_level, property_type, msg, coverage_level, width, distance, min, max)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL width Width of test_expr. Default: 1. distance Hamming distance to use for the equal check. distance = 0 (Default) Equal check is turned off. distance > 0 Equal check is turned on. Each time test_expr changes value, the old and new values should differ by exactly a hamming distance specified by distance. That is, exactly distance bits of test_expr change when test_expr changes. min Hamming distance to use for the min check. min = 0 (Default) Min check is turned off. min > 0 Min check is turned on. Each time test_expr changes value, the old and new values should differ by at least a hamming distance specified by min. That is, at least min bits of test_expr change when test_expr changes. 150 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_hamming_distance max Hamming distance to use for the max check. max = 0 (Default) Max check is turned off. max > 0 Max check is turned on. Each time test_expr changes value, the old and new values should not differ by more than a hamming distance specified by max. That is, at most max bits of test_expr change when test_expr changes. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. Description The qvl_hamming_distance checker ensures test_expr changes value by a hamming distance equal to a specified value or by a hamming distance within a range of values. The check occurs at the active clock edge except for the first cycle after a checker reset and any cycle the active input asserts. To ensure test_expr changes by the same hamming distance each time it changes value, set distance to that hamming distance (and leave min and max set to 0). This configuration turns on the equal check. Each time test_expr changes, exactly distance bits should change. To ensure test_expr changes by the hamming distance in a specific range each time it changes value, set min and max to the lower and upper bound of the range (and set distance to 0). A positive min turns on the min check and a positive max turns on the max check. (If both min and max are positive and min > max, a compiler error occurs and the checker is not compiled.) Each time test_expr changes, the number of changed bits should be in the specified range. Assertion Checks EQUAL The value of test_expr has a distance not equal to the specified distance from the previous value. distance > 0 test_expr changed value, but the number of changed bits does not equal distance. Questa Verification Library Checkers Data Book, 2010.1a 151 QVL Checker Data Sheets qvl_hamming_distance MIN The value of test_expr has a distance less than the specified minimum from the previous value. min > 0 test_expr changed value, but the number of changed bits is less than min. MAX The value of test_expr has a distance greater than the specified maximum from the previous value. max > 0 test_expr changed value, but the number of changed bits is greater than max. Cover Points Corner Cases Exactly ‘distance’ Bits Changed Number of times exactly distance bits changed. Only valid if equal check is on. Exactly ‘min’ Bits Changed Number of times exactly min bits changed. Only valid if min check is on. Exactly ‘max’ Bits Changed Number of times exactly max bits changed. Only valid if max check is on. Statistics Number of Cycles Checked Number of cycles the checker was active. Number of Equal Distance Cycles Number of times the distance computed was equal to the distance specified. See also qvl_gray_code 152 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_hamming_distance Examples qvl_hamming_distance #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: ptr hamming distance not 1”), .coverage_level(‘QVL_COVER_ALL), .width(4), .distance(1)) qvl_valid_distance_ptr( .clk(clk), .reset_n(reset_n), .active(!config), .test_expr(ptr)); Ensures that each time ptr changes, it changes by a hamming distance of 1. clk reset_n !config ptr 0000 1111 0001 0000 1000 1100 1010 1110 0110 QVL_HAMMING_DISTANCE_EQUAL The value of test_expr has a distance not equal to the specified distance from the previous value. qvl_hamming_distance #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: state hamming distance > 2”), .coverage_level(‘QVL_COVER_ALL), .width(4), .max(2)) qvl_valid_distance_ptr( .clk(clk), .reset_n(reset_n), .active(!config), .test_expr(state)); Ensures that each time state changes, it changes by a hamming distance ≤ 2. clk reset_n !config ptr 0000 1111 0001 1000 1110 1100 QVL_HAMMING_DISTANCE_MAX The value of test_expr has a distance greater than the specified maximum from the previous value. Questa Verification Library Checkers Data Book, 2010.1a 1011 1110 0110 153 QVL Checker Data Sheets qvl_known qvl_known Ensures that all bits of an expression are known (not X). Parameters: severity_level property_type test_expr[width-1:0] qvl_known msg coverage_level width Class: single-cycle assertion clk reset_n active Application: user Syntax qvl_known [#(severity_level, property_type, msg, coverage_level, width)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: `QVL_ERROR. property_type Property type. Default: `QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: `QVL_COVER_ALL. width Width of the test_expr argument. Default: 4. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. Description The qvl_known checker ensures that all bits of the value of test_expr are known when the checker is active. The checker evaluates the multiple-bit expression test_expr at each rising edge of clk whenever active is TRUE. If the value of any bit of test_expr is X, a known check violation occurs. A violation occurs each cycle test_expr has an X bit. 154 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_known Assertion Checks KNOWN The value contained unknown (X) bits. Test_expr contained one or more X bits. Cover Points Corner Cases none Statistics Values Checked Number of cycles test_expr was checked. See also qvl_driven Questa Verification Library Checkers Data Book, 2010.1a 155 QVL Checker Data Sheets qvl_maximum qvl_maximum Ensures that values of a variable are not more than the specified maximum value. Parameters: severity_level property_type msg test_expr[width-1:0] qvl_maximum val[val_width-1:0] clk reset_n active coverage_level width val_width twos_complement Class: single-cycle assertion Application: datapath Syntax qvl_maximum [#(severity_level, property_type, msg, coverage_level, width, val_width, twos_complement)] instance_name (clk, reset_n, active, test_expr, val); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default : 4. val_width Width of val. Default : 4. twos_complement Whether or not values of test_expr and val can be negative. (Default) Test_expr and val are assumed to be non-negative. twos_complement = 0 twos_complement = 1 Test_expr and val are assumed to be expressed in two’s complement notation. Ports clk Clock event for the checker. The checker samples test_expr on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. 156 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_maximum test_expr[width-1:0] Variable or expression to check. val[val_width-1:0] Variable or expression containing the maximum value allowed for test_expr. Description The qvl_maximum assertion ensures the value of one expression is never greater than the value of another expression. The checker evaluates test_expr and val at each rising edge of clk whenever either expression has changed value and active is TRUE. If test_expr > val a maximum check violation occurs. By default, both expressions are assumed to be non-negative values. Setting the twos_complement parameter to 1 indicates the expressions should be evaluated as two’s complement values. Uses: Arithmetic, adder, Subtractor, multiplier, divider, incrementer, decrementer, shifter, operator, parity, register, latch, wire, signal. Assertion Checks MAXIMUM The test expression had a value greater than the maximum value. The value of test_expr was > the value of val. Cover Points Corner Cases Values at Maximum Number of times test_expr was equal to the value of val. Statistics Values Checked Number of cycles test_expr or val changed value. See also qvl_minimum Questa Verification Library Checkers Data Book, 2010.1a 157 QVL Checker Data Sheets qvl_maximum Examples qvl_maximum #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg ("QVL_MAXIMUM_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .width(3), .val_width(3), .twos_complement(0)) U1 ( .active(active), .clk(clock), .reset_n(reset), .test_expr(zi_var), .val(3’b101)); Checks that the values in zi_var are not more than 5 . qvl_maximum #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_MAXIMUM_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .val_width(4), .twos_complement(1)) U2 ( .active(active), .clk(clock), .reset_n(reset), .test_expr(zi_var), .val(val)); Checks that values in zi_var are not more than -3. 158 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_memory_access qvl_memory_access Ensures that the memory reads only initialized locations, that precious memory data is not overwritten before being read and that temporary memory data is not re-used. read_addr[addr_width-1:0] read_data[data_width-1:0] read start_addr[addr_width-1:0] qvl_memory_access end_addr[addr_width-1:0] write_addr[addr_width-1:0] write_data[data_width-1:0] write clk reset_n active Parameters: severity_level property_type msg coverage_level data_width addr_width read_old_data latency initialized_check single_access_check single_write_check single_read_check data_check Class: event-bounded assertion Application: control Syntax qvl_memory_access [#(severity_level, property_type, msg, coverage_level, data_width, addr_width, read_old_data, latency, initialized_check, single_access_check,single_write_check, single_read_check, data_check)] instance_name (clk, reset_n, active, read, read_addr, read_data, write, write_addr, write_data, start_addr, end_addr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. data_width Width of read_data and write_data. Default : 1. addr_width Width of read_addr and write_addr. For performance reasons, maximum address width is 11. Default : 2. read_old_data How to handle read and write operations from/to the same address in the same cycle. read_old_data = 0 (Default) Read occurs after the write (new data is returned). read_old_data = 1 Read occurs before the write (old data is returned). Also turns off the single_access check. Questa Verification Library Checkers Data Book, 2010.1a 159 QVL Checker Data Sheets qvl_memory_access latency Number of cycles to wait after read asserts before performing the data check. latency = 0 (Default) No latency. A data check is performed in the same cycle read asserts. latency > 0 Latency. A data check is performed latency cycles after the cycle read asserts. initialized_check Whether or not to perform initialized checks. initialized_check = 0 (Default) Turns off the initialized check. initialized_check = 1 Turns on the initialized check. single_access_check Whether or not to perform single_access checks. single_access_check = 0 Turns off the single_access check. (Default) Turns on the single_access check. single_access_check = 1 single_read_check Whether or not to perform single_read checks. single_read_check = 0 (Default) Turns off the single_read check. single_read_check = 1 Turns on the single_read check. single_write_check Whether or not to perform single_write checks. single_write_check = 0 (Default) Turns off the single_write check. single_write_check = 1 Turns on the single_write check. data_check Whether or not to perform data checks. data_check = 0 (Default) Turns off the data check. data_check = 1 Turns on the data check. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check inputs. 160 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_memory_access read Read operation qualifier. Each cycle this signal is sampled TRUE, a read operation is performed. If latency is 0, the read operation completes in the same cycle. If latency is > 0, the read_data bus will have the read data latency cycles after the read operation is initiated. read_addr [addr_width-1:0] Read address bus. read_data [data_width-1:0] Read data bus. write Write operation qualifier. Each cycle this signal is sampled TRUE, a write operation is performed. The data on write_data are written to the memory location specified in write_addr. write_addr [addr_width-1:0] Write address bus. write_data [data_width-1:0] Write data bus. start_addr [addr_width-1:0] Start address for the read_range and write_range checks. Value should not change after reset. end_addr [addr_width-1:0] End address for the read_range and write_range checks. Value should not change after reset. End_addr must be ≥ start_addr. Description The qvl_memory_access checker ensures access operations to a memory obey specified properties. The checker monitors the read, read_addr and read_data signals used for read operations and the write, write_addr and write_data signals used for write operations. At each active clock edge, the checker checks the read and write inputs. If read is asserted, the checker assumes a read operation is initiated. The read lasts latency cycles after it is initiated and the checker assumes read_data contains the returned data in the last cycle of the latency period. If write is asserted, the checker assumes a write operation was performed. The write is completed in the same cycle. The checker performs the configured checks (those started in the current cycle and those pending from previous cycles) at the active clock edge using the data sampled from the checker inputs. Questa Verification Library Checkers Data Book, 2010.1a 161 QVL Checker Data Sheets qvl_memory_access Assertion Checks READ_RANGE Memory address falls outside the specified address range. The memory location in read_addr is outside the legal range specified by [start_addr : end_addr]. All other checks initiated in this cycle are turned off. WRITE_RANGE Memory address falls outside the specified address range. The memory location in write_addr is outside the legal range specified by [start_addr : end_addr]. All other checks initiated in this cycle are turned off. SINGLE_ACCESS Memory location was read and written in the same cycle. single_access_check = 1 Both a read and a write operation were initiated in the same cycle to the same memory location. If this check is violated, the memory access is invalid and all other checks initiated in the cycle are turned off. SINGLE_WRITE Memory location was written more than once without an intervening read. single_write_check = 1 Two write operations were performed to the same memory location without an intervening read. A violation occurs each time a subsequent write is made to the location without a read. For example, a series of three writes to the same location with no reads from that location cause two single_write check violations. SINGLE_READ Memory location was read more than once without an intervening write. single_read_check = 1 Two read operations were performed to the same memory location without an intervening write. A violation occurs each time a subsequent read is made from the location without a read. For example, a series of three reads from the same location with no writes to that location cause two single_read check violations. 162 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_memory_access INITIALIZED Memory location was read before it was written. initialized_check = 1 A read from an uninitialized memory location was initiated (i.e., the read was performed before any write to the location). The checker only considers write operations to locations using the write/write_addr/write_data signals to be valid write operations. Other memory initialization methods (for example PLI calls) are invalid. DATA Data read from memory location does not match the expected data. data_check = 1 The data returned in read_data as the result of a read operation does not match the expected data (from a previous write to that memory location). If turned on, this check initiates each time read is sampled asserted. If latency is 0, the check is performed immediately. If latency is > 0, the check is performed latency cycles later. If a read data miscompare occurs in a cycle after the read operation is initiated, then the error still is reported as a data check violation, even if other violations (e.g., single_access or range) occur in that cycle. Cover Points Corner Cases Memory Reads* Number of memory read operations. Memory Writes* Number of memory write operations. Same Addr Reads and Writes* Number of cycles a simultaneous read and write were performed in the same cycle. * includes data for illegal memory accesses. Statistics Simultaneous Reads and Writes* Number of simultaneous read and write operations on the memory. Locations Read* Number of different locations read. Locations Written* Number of different locations written. * does not include data for illegal memory accesses. Questa Verification Library Checkers Data Book, 2010.1a 163 QVL Checker Data Sheets qvl_memory_access See also qvl_multi_clock_multi_port_memory_access Examples qvl_memory_access #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: memory access violation”), .coverage_level(‘QVL_COVER_ALL), .addr_width(8), .single_access_check(1)) qvl_valid_memory_access( .clk(clk), .reset_n(reset_n), .active(gnt), .read_addr(addr_rd), .read_data(1’b0), .read(read), .write_addr(addr_wr), .write_data(1’b0), .write(write), .start_addr(2’h00), .end_addr(2’hEF)); Ensures that for cycles in which gnt, read and write are all sampled TRUE, the values of addr_rd and addr_wr are different (single_access check). Also ensures accessed addresses are in the range from 2’h00 to 2’hEF (read_range and write_range checks). clk reset_n gnt read write addr_rd addr_wr f0 e9 ea QVL_MEMORY_ACCESS_READ_RANGE Memory address falls outside the specified address range. 164 ec a0 eb ec ed ee ef QVL_MEMORY_ACCESS_SINGLE_ACCESS Memory location was read and written in the same cycle. Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_memory_access qvl_memory_access #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: memory access violation”), .coverage_level(‘QVL_COVER_ALL), .addr_width(3), .read_old_data(1), .single_read_check(1), .initialized_check(1)) qvl_valid_memory_access( .clk(clk), .reset_n(reset_n), .active(1’b0), .read_addr(addr_rd), .read_data(1’b0), .read(read), .write_addr(addr_wr), .write_data(1’b0), .write(write), .start_addr(4’b000), .end_addr(4’b111)); Ensures that two consecutive writes to the same address have an intervening read access from that address (single_read check). Read and write accesses in the same cycle do not count as an intervening write access (the old data is read before the location is overwritten). Also ensures that all read accesses are from initialized locations (initialized check). clk reset_n read write addr_rd addr_wr 101 111 111 011 001 000 011 111 110 111 QVL_MEMORY_ACCESS_INITIALIZED Memory location was read before QVL_MEMORY_ACCESS_SINGLE_READ Memory location was read more than it was written. once without an intervening write. Questa Verification Library Checkers Data Book, 2010.1a 165 QVL Checker Data Sheets qvl_memory_access qvl_memory_access #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: memory access violation”), .coverage_level(‘QVL_COVER_ALL), .addr_width(4), .data_check(1), .data_width(16), .latency(1)) qvl_valid_memory_access( .clk(clk), .reset_n(reset_n), .active(gnt), .read_addr(addr_rd), .read_data(data_rd), .read(read), .write_addr(addr_wr), .write_data(data_write), .write(write), .start_addr(2’h00), .end_addr(2’hFF)); Ensures that values read from memory (after a 1-cycle latency) are the same as the values written to memory (data check). Read and write accesses in the same cycle should read and write the same data value, because the new data is read after the location is overwritten (read_old_data is 0). clk reset_n gnt read write addr_rd 1100 1011 44 data_rd 1100 1110 a4 addr_wr 1100 1011 1110 data_wr 44 a4 1b 0100 ec 44 1b 0001 1100 1001 4e aa a6 QVL_MEMORY_ACCESS_DATA Data read from memory location does not match the expected data. 166 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_minimum qvl_minimum Ensures that values of a variable are not less than the specified minimum value. Parameters: severity_level property_type msg test_expr[width-1:0] qvl_minimum val[val_width-1:0] clk reset_n active coverage_level width val_width twos_complement Class: single-cycle assertion Application: datapath Syntax qvl_minimum [#(severity_level, property_type, msg, coverage_level, width, val_width, twos_complement)] instance_name (clk, reset_n, active, test_expr, val); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default : 4. val_width Width of val. Default : 4. twos_complement Whether or not values of test_expr and val can be negative. (Default) Test_expr and val are assumed to be non-negative. twos_complement = 0 twos_complement = 1 Test_expr and val are assumed to be expressed in two’s complement notation. Ports clk Clock event for the checker. The checker samples test_expr on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. Questa Verification Library Checkers Data Book, 2010.1a 167 QVL Checker Data Sheets qvl_minimum test_expr[width-1:0] Variable or expression to check. val[val_width-1:0] Variable or expression containing the minimum value allowed for test_expr. Description The qvl_minimum assertion ensures the value of one expression is never less than the value of another expression. The checker evaluates test_expr and val at each rising edge of clk whenever either expression has changed value and active is TRUE. If test_expr < val a minimum check violation occurs. By default, both expressions are assumed to be non-negative values. Setting the twos_complement parameter to 1 indicates the expressions should be evaluated as two’s complement values. Uses: Arithmetic, adder, Subtractor, multiplier, divider, incrementer, decrementer, shifter, operator, parity, register, latch, wire, signal. Assertion Checks MINIMUM The test expression had a value less than the minimum value. The value of test_expr was < the value of val. Cover Points Corner Cases Values at Minimum Number of times test_expr was equal to the value of val. Statistics Values Checked Number of cycles test_expr or val changed value. See also qvl_maximum 168 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_minimum Examples qvl_minimum #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_MINIMUM_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .width(3), .val_width(3), .twos_complement(0)) U1 ( .active(active), .clk(clock), .reset_n(reset), .test_expr(zi_var), .val(3’b101)); Checks that the values in zi_var are not less than 5 . qvl_minimum #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_MINIMUM_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .val_width(4), .twos_complement(1)) U2 ( .active(active), .clk(clock), .reset_n(reset), .test_expr(zi_var), .val(4’b1101)); Checks that values in zi_var are not less than -3. Questa Verification Library Checkers Data Book, 2010.1a 169 QVL Checker Data Sheets qvl_multi_clock_fifo qvl_multi_clock_fifo Ensures that a FIFO with separate enqueue and dequeue clocks does not overflow or underflow, and validates data integrity. enq_clk enq_reset_n enq deq active enq_active deq_active qvl_multi_clock_fifo full empty enq_data[width-1:0] deq_data[width-1:0] preload [preload_count*width-1:0] deq_clk Parameters: severity_level property_type msg coverage_level width depth latency preload_count high_water full_check empty_check value_check Class: event-bounded assertion Application: control and interface deq_reset_n Syntax qvl_multi_clock_fifo [#(severity_level, property_type, msg, coverage_level, width, depth, latency, preload_count, high_water, full_check, empty_check, value_check)] instance_name (enq_clk, deq_clk, enq_reset_n, deq_reset_n, active, enq_active, deq_active, enq, deq, full, empty, enq_data, deq_data, preload); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of enq_data and deq_data. Default: 1. depth FIFO depth. The depth must be > 0 . Default : 1. latency Latency for dequeued data used for the value check. latency = 0 (Default) Deq_data is valid in the same deq_clk cycle that deq asserts. latency> 0 Deq_data is valid latency cycles of deq_clk after deq asserts. 170 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_fifo preload_count Number of items to preload the FIFO on reset. The preload port is a concatenated list of items to be preloaded into the FIFO. Default: 0 (FIFO empty on reset). high_water FIFO high-water mark. Must be < depth. A value of 0 sets the high-water mark to depth - 1 (or 1 if depth is 1). Default: 0. full_check Whether or not to perform full checks. full_check = 0 (Default) Turns off the full check. full_check = 1 Turns on the full check. empty_check Whether or not to perform empty checks. empty_check = 0 (Default) Turns off the empty check. empty_check = 1 Turns on the empty check. value_check Whether or not to perform value checks. value_check = 0 (Default) Turns off the value check. value_check = 1 Turns on the value check. Ports enq_clk Enqueue clock event for the checker. The checker samples the enqueue inputs on the rising edge of enq_clk. deq_clk Dequeue clock event for the checker. The checker samples the dequeue inputs on the rising edge of deq_clk. enq_reset_n Active low synchronous reset signal indicating the FIFO is reset with respect to enq_clk. deq_reset_n Active low synchronous reset signal indicating indicating the FIFO is reset with respect to deq_clk. active Expression that indicates whether or not to check the inputs. enq_active Expression that indicates whether or not to activate checks of enqueue operations. deq_active Expression that indicates whether or not to activate checks of dequeue operations. enq Enqueue enable input to the FIFO. When enq is sampled TRUE at the active edge of enq_clk, the FIFO counter increments by 1 and if the value check is on, enq_data contains the value enqueued to the FIFO. Questa Verification Library Checkers Data Book, 2010.1a 171 QVL Checker Data Sheets qvl_multi_clock_fifo deq Dequeue enable input to the FIFO. When deq is sampled TRUE at the active edge of deq_clk, the FIFO counter decrements by 1. If the value check is on, then latency active edges of deq_clk later deq_data contains the value dequeued from the FIFO. full Output status flag from the FIFO. full = 0 FIFO not full. full = 1 FIFO full. empty Output status flag from the FIFO. empty = 0 FIFO not empty. empty = 1 FIFO empty. enq_data[width-1:0] Value enqueued to the FIFO at the active edge of enq_clk when enq is TRUE. deq_data[width-1:0] Value dequeued from the FIFO at the active edge of deq_clk when deq is TRUE. preload [preload_count * width -1:0] Concatenated preload data to enqueue on reset. preload_count = 0 No preloading of the FIFO is assumed. The width of preload should be width, however, no values from preload are used. The FIFO is assumed to be empty on reset. preload_count > 0 Checker assumes the value of preload is a concatenated list of items to enqueue on the FIFO on reset (or simulation start). Preload values are enqueued from the low order item to the high order item. Description The qvl_multi_clock_fifo assertion ensures a multiclock FIFO functions legally. A multiclock FIFO is a memory structure that stores and retrieves data items based on a first-in first-out queueing protocol. The FIFO’s enqueuing logic and dequeuing logic can be clocked by different clocks and can be reset by different reset signals. The FIFO has an enqueue data port and an enqueue signal that indicates the data port’s value should be enqueued in the current enqueue clock cycle. Similarly, The FIFO has a dequeue data port and a corresponding dequeue signal that indicates a data item from the FIFO should be dequeued to the port. A FIFO can also have a dequeue latency constant. This is the number of dequeue clock cycles it takes for a dequeue operation to produce results at the dequeue port. The qvl_multi_clock_multi_enq_deq_fifo checker has two clocks (enq_clk and deq_clk), two resets (enq_reset_n and deq_reset_n) and two activation signals (enq_active and deq_active). In addition, a single activation signal (active) can deactivate the entire checker. The FIFO has 172 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_fifo configured properties specified as parameters to the checker: width of the data items (width), capacity of the FIFO (depth) and high-water mark that identifies the point at which the FIFO is almost full (high_water). Control and data signals to and from the FIFO also are connected to the checker. The checker checks enq at the active edge of enq_clk if both the checker is active (active is TRUE) and the enqueue domain is active (enq_active is TRUE) to ensure an enqueue operation does not overflow the FIFO. An enqueue violation occurs each enqueue cycle the number of items stored in the FIFO plus 1 exceeds the FIFO depth. Similarly, the checker checks deq at the active edge of deq_clk if both the checker is active (active is TRUE) and the dequeue domain is active (deq_active is TRUE) to ensure a dequeue operation does not underflow the FIFO. A dequeue violation occurs each cycle a dequeue operation is made when the FIFO has no items.. The checker is conservative when the active edges of enq_clk and deq_clk align: no violation occurs if the result of the combined enqueue/dequeue operation is in the range of the FIFO, even if an overflow or underflow occurs during the operation. The checker can be configured to perform various additional checks such as verifying the data integrity of dequeued FIFO data (value check) and verifying that the FIFO’s full and empty status flags operate correctly (full and empty checks). The checker also can be configured to preload items on reset. Uses: FIFO, queue, buffer, ring buffer, elasticity buffer. Assertion Checks ENQUEUE An enqueue occurred while the FIFO was full. Number of FIFO items after an enqueue is > depth. DEQUEUE A dequeue occurred while the FIFO was empty. FIFO contained no items when a dequeue was initiated. Questa Verification Library Checkers Data Book, 2010.1a 173 QVL Checker Data Sheets qvl_multi_clock_fifo FULL The FIFO was not full when the full signal was asserted. full_check = 1 Full is TRUE, but the FIFO contained fewer than depth items. The full signal was not asserted when the FIFO was full. full_check = 1 Full is FALSE, but the FIFO contained depth items. The checker expects the full signal to be sequential—i.e., it asserts the cycle (of enq_clk) following the cycle that the FIFO becomes full and deasserts the cycle following the cycle that the FIFO becomes less than full. EMPTY The FIFO was not empty when the empty signal was asserted. empty_check = 1 Empty is TRUE, but the FIFO contained at least one item. The empty signal was not asserted when the FIFO was empty. empty_check = 1 Empty is FALSE, but the FIFO contained no items. The checker expects the empty signal to be sequential—i.e., it asserts the cycle (of deq_clk) following the cycle that the FIFO becomes empty and deasserts the cycle following the cycle that the FIFO holds an item. 174 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_fifo VALUE Dequeued FIFO value did not equal the corresponding enqueued value. (value_check = 1) and (latency = 0) Deq is TRUE, but deq_data does not equal the corresponding enqueued item. If an enqueue or dequeue violation occurs, this check is turned off until the checker is reset. Otherwise, a violation occurs each deq_clk cycle the deq_data value does not match the expected value. (value_check = 1) and (latency > 0) Deq is TRUE, but latency deq_clk cycles later deq_data does not equal the corresponding enqueued item. If an enqueue or dequeue violation occurs, this check is turned off until the checker is reset. Otherwise, a violation occurs each deq_clk cycle the deq_data value does not match the expected value. This check automatically turns off if an enqueue or dequeue check violation occurs since it is no longer possible to correspond enqueued with dequeued values. The check turns back on when the checker resets. Cover Points Corner Cases FIFO Is Full Number of enq_clk cycles the FIFO was full. FIFO Is Empty Number of deq_clk cycles the FIFO was empty. FIFO Is Over High-water Mark Number of enq_clk cycles the FIFO had more data items than the high-water mark. Statistics Enqueues Number of enq_clk cycles enqueue operations were initiated. Dequeues Number of deq_clk cycles dequeue operations were initiated. Notes 1. Deasserting enq_reset_n or deq_reset_n resets the associated domain synchronously at the next active edge of its clock and then resets the other domain synchronously at the following active edge of its clock. When the reset signal re-asserts, the domain activates at the next active clock edge or the next active clock edge after the other domain is reset, whichever comes last. Then the other clock domain activates after the next active edge of its clock. All enqueues and dequeues in this period and for the next cycle of the slowest clock are ignored. Questa Verification Library Checkers Data Book, 2010.1a 175 QVL Checker Data Sheets qvl_multi_clock_fifo See also qvl_fifo qvl_multi_clock_multi_enq_deq_fifo qvl_multi_enq_deq_fifo qvl_stack Examples qvl_multi_clock_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“FIFO Violation: ”), .coverage_level(‘QVL_COVER_ALL), .depth(6)) questa_mcf ( .enq_clock(enq_clk), .deq_clock(deq_clk), .enq_reset_n(enq_reset), .deq_reset_n(deq_reset), .active(system_active), .enq_active(enqueue_active), .deq_active(dequeue_active), .enq(enq_sig), .deq(deq_sig), .full(1’b0), .empty(1’b0), .enq_data(1’b0), .deq_data(1’b0), .preload(1’b0)); Checks that FIFO does not dequeue when empty and does not enqueue when full (i.e., when there are six entries). 176 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_fifo qvl_multi_clock_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“FIFO Violation: ”), .coverage_level(‘QVL_COVER_ALL), .depth(6), .full_check(1), .empty_check(1)) questa_mcf ( .enq_clock(enq_clk), .deq_clock(deq_clk), .enq_reset_n(enq_reset), .deq_reset_n(deq_reset), .active(system_active), .enq_active(enqueue_active), .deq_active(dequeue_active), .enq(enq_sig), .deq(deq_sig), .full(full), .empty(empty), .enq_data(1’b0), .deq_data(1’b0), .preload(1’b0)); Checks that FIFO does not enqueue when full (i.e., when there are six entries) and does not dequeue when empty. It also checks if the FIFO was full when the full signal was asserted and if the FIFO was empty when the empty signal was asserted. qvl_multi_clock_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“FIFO Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(8), .depth(6), .value_check(1)) questa_mcf ( .enq_clock(eclk), .deq_clock(dclk), .enq_reset_n(enq_reset), .deq_reset_n(deq_reset), .active(system_active), .enq_active(enqueue_active), .deq_active(dequeue_active), .enq(enq_sig), .deq(deq_sig), .full(1’b0), .empty(1’b0), .enq_data(in), .deq_data(out), .preload(8’b00000000)); Checks that FIFO does not dequeue when empty and does not enqueue when full (that is, when there are six entries). It also checks that all dequeued values equal the corresponding enqueued values. Questa Verification Library Checkers Data Book, 2010.1a 177 QVL Checker Data Sheets qvl_multi_clock_fifo qvl_multi_clock_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“FIFO Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(3), .depth(8), .preload_count(3), .value_check(1)) questa_mcf ( .enq_clock(enq_clk), .deq_clock(deq_clk), .enq_reset_n(enq_reset), .deq_reset_n(deq_reset), .active(system_active), .enq_active(enqueue_active), .deq_active(dequeue_active), .enq(enq_sig), .deq(deq_sig), .full(1’b0), .empty(1’b0), .enq_data(in), .deq_data(out), .preload({3’b110, 3’b101, 3’b100})); Checks that FIFO correctly dequeues and the preloaded values enqueued after a reset. Also checks that the FIFO does not dequeue when empty and does not enqueue when full. 178 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo qvl_multi_clock_multi_enq_deq_fifo Ensures that a multi clock FIFO with multiple enqueue and dequeue ports does not underflow or overflow and validates data integrity. enq_clk enq_reset_n enq[enq_count-1:0] deq[enq_count-1:0] active enq_active deq_active qvl_multi_clock_ full multi_enq_deq_fifo empty enq_data [enq_count*width-1:0] deq_data [deq_count*width-1:0] preload[preload_width-1:0] deq_clk deq_reset_n Parameters: severity_level property_type msg coverage_level width depth enq_count deq_count latency preload_count high_water low_water full_check empty_check value_check Class: event-bounded assertion Application: control and interface preload_width = preload_count ? preload_count*width : width Syntax qvl_multi_clock_multi_enq_deq_fifo [#(severity_level, property_type, msg, coverage_level, width, depth, enq_count,deq_count, latency, preload_count, high_water, low_water, full_check, empty_check, value_check)] instance_name (enq_clk, deq_clk, enq_reset_n, deq_reset_n, active, enq_active, deq_active, enq, deq, full, empty, enq_data, deq_data, preload); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of a data item. Default: 4. depth FIFO depth. The depth must be > 1. Default: 2. enq_count Number of enqueue ports. Default: 1. deq_count Number of dequeue ports. Default: 1. Questa Verification Library Checkers Data Book, 2010.1a 179 QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo latency Latency for dequeued data. The value of a data item in deq_data has the dequeued FIFO data latency cycles of deq_clk after its corresponding dequeue bit in deq asserts. Default: 0 (deq_data item is valid in the same deq_clk cycle that the corresponding deq signal asserts). preload_count Number of items to preload the FIFO on reset. The preload port is a concatenated list of items to be preloaded into the FIFO. Default: 0 (FIFO empty on reset). high_water FIFO high-water mark. Must be < depth. A value of 0 sets the high-water mark to depth - 1. Default: 0. low_water FIFO low-water mark. Default: 1. full_check Whether or not to perform full checks. full_check = 0 (Default) Turns off the full check. full_check = 1 Turns on the full check. empty_check Whether or not to perform empty checks. empty_check = 0 (Default) Turns off the empty check. empty_check = 1 Turns on the empty check. value_check Whether or not to perform value checks. value_check = 0 (Default) Turns off the value check. value_check = 1 Turns on the value check. Ports enq_clk Enqueue clock event for the checker. The checker samples the enqueue inputs on the rising edge of enq_clk. deq_clk Dequeue clock event for the checker. The checker samples the dequeue inputs on the rising edge of deq_clk. enq_reset_n Active low synchronous reset signal indicating the FIFO is reset with respect to enq_clk. deq_reset_n Active low synchronous reset signal indicating indicating the FIFO is reset with respect to deq_clk. active Expression that indicates whether or not to check the inputs. enq_active Expression that indicates whether or not to activate checks of enqueue operations. 180 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo deq_active Expression that indicates whether or not to activate checks of dequeue operations. enq[enq_count-1:0] Concatenation of FIFO enqueue inputs. When one or more enq bits are sampled TRUE, the FIFO performs an enqueue operation from the asserted bits’ corresponding enqueue data ports in that enqueue cycle. Data items are enqueued in order from the leastto most-significant bits and the FIFO counter increments by the number of TRUE enq bits. deq[deq_count-1:0] Concatenation of FIFO dequeue inputs. When one or more deq bits are sampled TRUE, the FIFO performs a dequeue operation from the asserted bits’ corresponding dequeue data ports (latency dequeue cycles later). Data items are dequeued in order from the most- to least-significant bits and the FIFO counter decrements by the number of TRUE deq bits. full Output status flag from the FIFO. full = 0 FIFO not full. full = 1 FIFO full. empty Output status flag from the FIFO. empty = 0 FIFO not empty. empty = 1 FIFO empty. enq_data [(enq_count*width)-1: 0] Concatenation of enqueue data inputs. If the value check is on, this port contains the data items to enqueue when an enq bit is asserted. deq_data [(deq_count*width)-1: 0] Concatenation of dequeue data outputs. If the value check is on, this port contains the dequeued data items latency cycles after deq bits are asserted. preload [preload_count*width -1:0] Concatenated preload data to enqueue on reset. preload_count = 0 No preloading of the FIFO is assumed. The width of preload should be width, however, no values from preload are used. The FIFO is assumed to be empty on reset. preload_count > 0 Checker assumes the value of preload is a concatenated list of items to enqueue on the FIFO on reset (or simulation start). Preload items are the same width. Preload values are enqueued from the low order item to the high order item. Questa Verification Library Checkers Data Book, 2010.1a 181 QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo Description The qvl_multi_clock_multi_enq_deq_fifo assertion ensures a multiclock, multi-enqueuedequeue FIFO functions legally. A multiclock, multi-enqueue-dequeue FIFO is a memory structure that stores and retrieves data items based on a first-in first-out queueing protocol. The FIFO’s enqueuing logic and dequeuing logic can be clocked by different clocks and can be reset by different reset signals. The FIFO can have multiple enqueue data ports and multiple dequeue data ports (the number of each does need to match). Each enqueue data port has a corresponding enqueue signal that indicates the data port’s value should be enqueued in the current enqueue clock cycle. Similarly, each dequeue data port has a corresponding dequeue signal that indicates a data item from the FIFO should be dequeued to the port. A FIFO with multiple enqueue ports can enqueue from any combination of the ports each enqueue clock cycle. Similarly, a FIFO with multiple dequeue ports can dequeue to any combination of the ports each dequeue clock cycle. A FIFO with multiple enqueue (dequeue) ports assumes a constant port priority for multiple enqueues (dequeues). That is, when multiple ports are enqueued (dequeued) in a cycle, the order their contents are enqueued (dequeued) is always the same. A FIFO can also have a dequeue latency constant. This is the number of dequeue clock cycles it takes for a dequeue operation to produce results at the relevant dequeue ports. The qvl_multi_clock_multi_enq_deq_fifo checker has two clocks (enq_clk and deq_clk), two resets (enq_reset_n and deq_reset_n) and two activation signals (enq_active and deq_active). In addition, a single activation signal (active) can deactivate the entire checker. The checker monitors the enqueue signals concatenated into a single port (enq). The enq bits must be arranged in priority order from high priority (least-significant bit) to low priority (most significant bit). Similarly, the checker monitors the dequeue signals concatenated into a single port (deq). The deq bits must be arranged in priority order from low priority (least-significant bit) to high priority (most significant bit). The FIFO has configured properties specified as parameters to the checker: width of the data items (width), capacity of the FIFO (depth), high-water mark that identifies the point at which the FIFO is almost full (high_water) and low-water mark that identifies the point at which the FIFO is almost empty (low_water). Control and data signals to and from the FIFO also are connected to the checker. The checker checks enq at the active edge of enq_clk if both the checker is active (active is TRUE) and the enqueue domain is active (enq_active is TRUE) to ensure an enqueue operation does not overflow the FIFO. An enqueue violation occurs each cycle the number of items stored in the FIFO plus the number of TRUE bits of enq exceeds the FIFO depth. Similarly, the checker checks deq at the active edge of deq_clk if both the checker is active (active is TRUE) and the dequeue domain is active (deq_active is TRUE) to ensure a dequeue operation does not underflow the FIFO. A dequeue violation occurs each cycle the number of items stored in the FIFO is less than the number of TRUE bits of deq. The checker is not conservative when the active edges of enq_clk and deq_clk align: no violation occurs if the result of the combined 182 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo enqueue/dequeue operation is in the range of the FIFO, even if an overflow or underflow occurs during the operation. The checker can be configured to perform various additional checks such as verifying the data integrity of dequeued FIFO data (value check) and verifying that the FIFO’s full and empty status flags operate correctly (full and empty checks). The checker also can be configured to preload items on reset. Assertion Checks ENQUEUE An enqueue occurred while the FIFO was full. Number of FIFO items plus the number of TRUE enq bits is > depth. DEQUEUE A dequeue occurred while the FIFO was empty. Number of FIFO items minus the number of TRUE deq bits is < 0. FULL The FIFO was not full when the full signal was asserted. full_check = 1 Full is TRUE, but the FIFO contained fewer than depth items. The full signal was not asserted when the FIFO was full. full_check = 1 Full is FALSE, but the FIFO contained depth items. The checker expects the full signal to be sequential—i.e., it asserts the cycle (of enq_clk) following the cycle that the FIFO becomes full and deasserts the cycle following the cycle that the FIFO becomes less than full. Questa Verification Library Checkers Data Book, 2010.1a 183 QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo EMPTY The FIFO was not empty when the empty signal was asserted. empty_check = 1 Empty is TRUE, but the FIFO contained at least one item. The empty signal was not asserted when the FIFO was empty. empty_check = 1 Empty is FALSE, but the FIFO contained no items. The checker expects the empty signal to be sequential—i.e., it asserts the cycle (of deq_clk) following the cycle that the FIFO becomes empty and deasserts the cycle following the cycle that the FIFO holds an item. VALUE Dequeued FIFO value did not equal the corresponding enqueued value. (value_check = 1) and (latency = 0) A deq bit is TRUE, but its corresponding deq_data item does not equal the corresponding enqueued item. If an enqueue or dequeue violation occurs, this check is turned off until the checker is reset. Otherwise, a violation occurs each deq_clk cycle the deq_data value does not match the expected value. (value_check = 1) and (latency > 0) A deq bit is TRUE, but latency deq_clk cycles later its corresponding deq_data item does not equal the corresponding enqueued item. If an enqueue or dequeue violation occurs, this check is turned off until the checker is reset. Otherwise, a violation occurs each deq_clk cycle the deq_data value does not match the expected value. This check automatically turns off if an enqueue or dequeue check violation occurs since it is no longer possible to correspond enqueued with dequeued values. The check turns back on when the checker resets. Cover Points Corner Cases FIFO is Full Number of enq_clk cycles the FIFO was full. FIFO is Empty Number of deq_clk cycles the FIFO was empty. FIFO is Over High-water Mark Number of enq_clk cycles the FIFO had more data items than the high-water mark. 184 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo FIFO is Below Low-water Mark Number of deq_clk cycles the FIFO had fewer data items than the low-water mark. Statistics Enqueues Number of enq_clk cycles enqueue operations were initiated. Dequeues Number of deq_clk cycles dequeue operations were initiated. Notes 1. Deasserting enq_reset_n or deq_reset_n resets the associated domain synchronously at the next active edge of its clock and then resets the other domain synchronously at the following active edge of its clock. When the reset signal re-asserts, the domain activates at the next active clock edge or the next active clock edge after the other domain is reset, whichever comes last. Then the other clock domain activates after the next active edge of its clock. All enqueues and dequeues in this period and for the next cycle of the slowest clock are ignored. See also qvl_fifo qvl_multi_enq_deq_fifo qvl_multi_clock_fifo Examples qvl_multi_clock_multi_enq_deq_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: FIFO access violation”), .coverage_level(‘QVL_COVER_ALL), .enq_count(2), .deq_count(1), .depth(6), .width(8), .full_check(1), .empty_check(1), .high_water(4), .low_water(2), .preload_count(4)) qvl_valid_FIFO_access( .enq_clk(clk), .deq_clk(clk), .enq_reset_n(reset_n), .deq_reset_n(reset_n), .active(1’b1), .enq_active(1’b1), .deq_active(1’b1), .enq({fifo_enq1, fifo_enq0}), .deq(fifo_deq), .full(fifo_full), Questa Verification Library Checkers Data Book, 2010.1a 185 QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo .empty(fifo_empty), .enq_data(4’hFFFF), .deq_data(2’hFF), .preload(32{1’b1})); Ensures that the FIFO does not enqueue when it is full or dequeue when it is empty. When an enqueue and dequeue occur in the same cycle, an enqueue violation occurs if the FIFO was full or a dequeue violation occurs if the FIFO was empty. Also ensures fifo_full is TRUE if (and only if) the FIFO is full and fifo_empty is TRUE if (and only if) the FIFO is empty. The FIFO is assumed to be initialized to hold 4 items (all 2’hFF) each time the checker is reset. clk reset_n fifo_enq0 fifo_enq1 fifo_deq FIFO count 4 6 5 6 5 7 4 fifo_full fifo_empty QVL_MCMEDFIFO_FULL The full signal was not asserted when the FIFO was full. QVL_MCMEDFIFO_ENQUEUE An enqueue occurred while the FIFO was full. QVL_MCMEDFIFO_FULL The FIFO was not full when the full signal was asserted. qvl_multi_clock_multi_enq_deq_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: FIFO access violation”), .coverage_level(‘QVL_COVER_ALL), .enq_count(2), .deq_count(1), .depth(6), .width(8), .value_check(1), .latency(1), .high_water(4), .low_water(2), .preload_count(3)) qvl_valid_FIFO_access( .enq_clk(clk), .deq_clk(clk), .enq_reset_n(reset_n), .deq_reset_n(reset_n), .active(1’b1), .enq_active(1’b1), .deq_active(1’b1), .enq({fifo_enq1, fifo_enq0}), .deq(fifo_deq), 186 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_enq_deq_fifo .full(1’b0), .empty(1’b0), .enq_data({fifo_data1_in, fifo_data0_in}), .deq_data(fifo_data_out), .preload(24{1’b1})); Ensures that the FIFO does not enqueue when it is full or dequeue when it is empty. When an enqueue and dequeue occur in the same cycle, an enqueue violation occurs if the FIFO was full or a dequeue violation occurs if the FIFO was empty. Also ensures values dequeued (with a 1cycle latency) equal the values enqueued The FIFO is assumed to be initialized to hold 3 items (all 2’hFF) each time the checker is reset. clk reset_n fifo_enq0 fifo_enq1 fifo_deq fifo_data0_in 1 f3 fifo_data1_in 3f 2 3 f2 f1 2f 1f fifo_data_out ff f3 3f 2f QVL_MCMEDFIFO_VALUE Dequeued FIFO value did not equal the corresponding enqueued value. Questa Verification Library Checkers Data Book, 2010.1a 187 QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access qvl_multi_clock_multi_port_memory_access Ensures that a multi port memory with separate read and write clocks, reads only initialized locations, that memory data is not overwritten before being read and that temporary data is not re-used. read_clk read_reset_n active read_active write_active read_addr [read_count*addr_width-1:0] read_data [read_count*data_width-1:0] read qvl_multi_clock_multi_port_ memory_access write_addr [write_count*addr_width-1:0] write_data [write_count*data_width-1:0] write start_addr[addr_width-1:0] end_addr[addr_width-1:0] Parameters: severity_level property_type msg coverage_level read_count write_count addr_width data_width latency write_lock_period read_lock_period multiple_read_check single_read_check single_write_check initialized_check data_check Class: event-bounded assertion Application: control and interface write_clk write_reset_n Syntax qvl_multi_clock_multi_port_memory_access [#(severity_level, property_type, msg, coverage_level, read_count, write_count, addr_width, data_width, latency, write_lock_period, read_lock_period, initialized_check, multiple_read_check, single_read_check, single_write_check, data_check)] instance_name (read_clk, write_clk, read_reset_n, write_reset_n, active, read_active, write_active, read, read_addr, read_data, write, write_addr, write_data, start_addr, end_addr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL read_count Number of read ports. Default: 1. write_count Number of write ports. Default: 1. 188 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access addr_width Width of each address port. Default: 4. data_width Width of each data port. Default: 4. latency Number of read_clk cycles a read access takes. Default: 0 (read_data values are valid in the same cycle the data read access is requested). write_lock_period Number of read_clk cycles to lock a memory address against a read access after a write is initiated (i.e., read_clk is faster than write_clk). Default: 0 (lock is 1 write_clk cycle). read_lock_period Number of write_clk cycles to lock a memory address against a write access after a read is initiated. (i.e., write_clk is faster than read_clk). Default: 0 (lock is 1 read_clk cycle). initialized_check Whether or not to perform initialized checks. initialized_check = 0 (Default) Turns off the initialized check. initialized_check = 1 Turns on the initialized check. multiple_read_check Whether or not to perform multiple_read checks. multiple_read_check = 0 (Default) Turns off the multiple_read check. multiple_read_check = 1 Turns on the multiple_read check. single_read_check Whether or not to perform single_read checks. single_read_check = 0 (Default) Turns off the single_read check. single_read_check = 1 Turns on the single_read check. single_write_check Whether or not to perform single_write checks. single_write_check = 0 (Default) Turns off the single_write check. single_write_check = 1 Turns on the single_write check. data_check Whether or not to perform data checks. data_check = 0 (Default) Turns off the data check. data_check = 1 Turns on the data check. Ports read_clk Read clock event for the checker. The checker samples the read domain on the rising edge of read_clk. Questa Verification Library Checkers Data Book, 2010.1a 189 QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access write_clk Write clock event for the checker. The checker samples the write domain on the rising edge of write_clk. read_reset_n Active low synchronous reset signal indicating the FIFO is reset with respect to read_clk. write_reset_n Active low synchronous reset signal indicating indicating the FIFO is reset with respect to write_clk. active Expression that indicates whether or not to check the memory interface. read_active Expression that indicates whether or not to activate checks of read operations. write_active Expression that indicates whether or not to activate checks of write operations. read[read_count-1:0] Concatenated list of read enable signals. read_addr [read_count*addr_width -1:0] Concatenated list of read address ports. read_data [read_count*data_width -1:0] Concatenated list of read data ports. write[write_count-1:0] Concatenated list of write enable signals. write_addr[write_count *addr_width-1:0] Concatenated list of write address ports. write_data[write_count *data_width)-1:0] Concatenated list of write data ports. start_addr [addr_width-1:0] Start address for the read_range and write_range checks. Value should not change after reset. end_addr [addr_width-1:0] End address for the read_range and write_range checks. Value should not change after reset. End_addr must be ≥ start_addr. 190 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access Description The qvl_multi_clock_multi_port_memory_access checker ensures read and write accesses to a multiclock, multiport memory obey a memory access protocol. A multiclock, multiport memory has two port banks: one set of ports for read accesses and another set of ports for write accesses. Each port bank has one or more port groups and each port group consists of ports used to access one memory location in a single access operation: an access enable signal, a memory address port and a data port. So, with this type of memory, a single read or write operation can access multiple memory locations. The memory’s read and write logic are clocked by different clocks (read_clk and write_clk). The checker connects to the memory read logic by concatenating the read enable signals into read, concatenating the read address ports into read_addr and concatenating the read data ports into read_data. Similarly, the checker connects to the memory write logic by concatenating the write enable signals into write, concatenating the write address ports into write_addr and concatenating the write data ports into write_data. The order ports are concatenated is not important except that the relative orders of enable signals, addresses and data ports must match, The checker performs write access checks on the active edge of write_clk when write_active is TRUE. It ensures that no write access is initiated to an address that is read locked by a pending read operation and that no single write access writes multiple data items to the same address. Similarly, the checker performs read access checks on the active edge of read_clk when read_active is TRUE. It ensures that no read access is initiated from an address that is write locked by a pending write operation. The checker also ensures all memory addresses fit in a legal address range. The checker can be configured to perform additional checks: • Multiple reads from the same address are not performed in the same cycle. • Successive reads from an address have an intervening write. • Successive writes to an address have an intervening read. • Reads are not made to uninitialized addresses. • Data read from memory match the data written to memory. Questa Verification Library Checkers Data Book, 2010.1a 191 QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access Assertion Checks READ_WHILE_WRITE Memory location was read during its write lock period. A read access from a memory location is initiated while a write lock is in effect for the location. The check occurs at the active edge of read_clk each cycle the checker is active. The violation is reported each time a read is initiated. For example, if read_clk is faster than write_clk, multiple reads during the same read lock period are reported as multiple violations. write_lock_period = 0 Write lock period is one write_clk cycle. write_lock_period > 0 Write lock period is write_lock_period cycles of read_clk. Shortens the write lock period to a fraction of a write_clk cycle when read_clk is faster than write_clk. WRITE_WHILE_READ Memory location was written during its read lock period. A write access to a memory location is initiated while a read lock is in effect for the location. The check occurs at the active edge of write_clk each cycle the checker is active. The violation is reported each time a write is initiated. For example, if write_clk is faster than read_clk, multiple writes during the same write lock period are reported as multiple violations. read_lock_period = 0 Read lock period is one read_clk cycle. read_lock_period > 0 Read lock period is read_lock_period cycles of write_clk. Shortens the read lock period to a fraction of a read_clk cycle when write_clk is faster than read_clk. MULTIPLE_WRITE Memory location was written through multiple write ports in the same cycle. Two or more addresses in write_addr are the same in a single write access. 192 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access MULTIPLE_READ Memory location was read through multiple read ports in the same cycle. multiple_read_check = 1 Two or more addresses in read_addr are the same in a single read access. SINGLE_READ Memory location was read more than once without an intervening write. single_read_check = 1 A read access is made to an address, but the previous access at that address was another read. A violation occurs each time a read access is made to a data item that was previously read (for example, a series of three consecutive reads from the same address results in two violations). A violation also occurs if the same address is read by multiple ports in a cycle. This check is useful for memories used as data buffers where data are not held for processing (for example where the temporary data are packets sent or received on a network). SINGLE_WRITE Memory location was written more than once without an intervening read. single_write_check = 1 A write access is made to an address, but the previous access at that address was another write. This check ensures data written to memory are not overwritten before being read. A violation occurs each time a write access is made to overwrite an unread data item (for example, a series of three consecutive writes to the same address results in two violations). INITIALIZED Memory location was read before it was written. initialized_check = 1 A read access is made to an address, but the location was not previously initialized by a write access to the address. A violation occurs each time a read access is made from an uninitialized location. The checker only recognizes memory writes through ports and cannot detect other means of memory initialization (for example, PLI calls). READ_RANGE Memory address falls outside the specified address range. One of the memory locations in read_addr is outside the legal range specified by [start_addr : end_addr]. All other checks initiated in this cycle are turned off. Questa Verification Library Checkers Data Book, 2010.1a 193 QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access WRITE_RANGE Memory address falls outside the specified address range. One of the memory locations in write_addr is outside the legal range specified by [start_addr : end_addr]. All other checks initiated in this cycle are turned off. DATA Data read through the read port do not match the expected data. data_check = 1 A data item returned in the read port does not match the data item written in the previous write access to the corresponding address (this check is performed only on initialized memory locations). A violation occurs each time the returned value for a read access does not match the expected value. By default, a data check is performed on the active edge of read_clk when a read enable signal is TRUE. However, for memories with multi-cycle latencies, the latency parameter specifies the number of cycles after a read access is initiated to wait before performing the data check. Cover Points Corner Cases All Ports Read Number of times a read access was performed on all the ports in the same cycle. All Ports Written Number of times a write access was performed on all the ports in the same cycle. All Locations Read If non-zero, all locations in the memory were read at least once. All Locations Written If non-zero, all locations in the memory were written at least once. Statistics Memory Reads Number of read_clk cycles a read access was performed. Memory Writes Number of write_clk cycles a write access was performed. Single Location Multiple Read Number of read_clk cycles a location was read simultaneously by multiple ports. Concurrent Reads Number of times multiple locations were read in the same cycle. Concurrent Writes Number of times multiple locations were written in the same cycle. Notes 194 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access 1. Deasserting read_reset_n or write_reset_n resets the associated domain synchronously at the next active edge of its clock and then resets the other domain synchronously at the following active edge of its clock. When the reset signal re-asserts, the domain activates at the next active clock edge or the next active clock edge after the other domain is reset, whichever comes last. Then the other clock domain activates after the next active edge of its clock. All reads and writes in this period and for the next cycle of the slowest clock are ignored. See also qvl_memory_access Examples qvl_multi_clock_multi_port_memory_access #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: memory access violation”), .coverage_level(‘QVL_COVER_ALL), .read_count(1), .write_count(2), .addr_width(8), .write_lock_period(1)) qvl_valid_memory_access( .read_clk(read_clk), .write_clk(write_clk), .read_reset_n(read_reset_n), .write__reset_n(read_reset_n), .active(1’b1), .read_active(1’b1), .write_active(1’b1), .read_addr(addr_rd), .read_data(4’b0000), .read(read), .write_addr({addr_wr1, addr_wr0}), .write_data(8’b00000000), .write({write1, write0}), .start_addr(2’h00), .end_addr(2’hEF)); Checks that each read access from an address locks the address from write accesses for 1 read_clk cycle (write_while_read check), that each write access to an address locks the address from read accesses for 1 read_clk cycle (read_while_write check), and all write accesses in the same cycle are to different addresses (multiple_write check). Also ensures accessed addresses are in the range from 2’h00 to 2’hEF (read_range and write_range checks). Questa Verification Library Checkers Data Book, 2010.1a 195 QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access write_clk read_clk read_reset_n read write0 write1 addr_rd ea addr_wr0 ea addr_wr1 2c 3d 55 1c e5 d3 fe 5d 1c QVL_MCMPMEMACC_READ_RANGE QVL_MCMPMEMACC_WRITE_WHILE_READ Memory address falls Memory location was written outside the specified during its read lock period. address range. QVL_MCMPMEMACC_MULTIPLE_WRITE Memory location was written through multiple write ports in the same cycle. qvl_multi_clock_multi_port_memory_access #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: memory access violation”), .coverage_level(‘QVL_COVER_ALL), .read_count(1), .write_count(2), .addr_width(8), .single_write_check(1), .initialized_check(1)) qvl_valid_memory_access( .read_clk(read_clk), .write_clk(write_clk), .read_reset_n(read_reset_n), .write__reset_n(write_reset_n), .active(1’b1), .read_active(1’b1), .write_active(1’b1), .read_addr(addr_rd), .read_data(4’b0000), .read(read), .write_addr({addr_wr1, addr_wr0}), .write_data(8’b00000000), .write({write1, write0}), .start_addr(2’h00), .end_addr(2’hFF)); 196 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access Checks that each read access from an address locks the address from write accesses for 1 read_clk cycle (write_while_read check), that each write access to an address locks the address from read accesses for 1 write_clk cycle (read_while_write check), and all write accesses in the same cycle are to different addresses (multiple_write check). Also ensures two write accesses to the same address have an intervening read from that address (single_read check) and each read access is from a location that had a previous write access (initialized check). write_clk read_clk read_reset_n read write0 write1 addr_rd ea addr_wr0 ea addr_wr1 55 ba 55 1c 55 d3 ba 1c QVL_MCMPMEMACC_INITIALIZED QVL_MCMPMEMACC_SINGLE_WRITE Memory location was read before Memory location was written more it was written. than once without an intervening read. qvl_multi_clock_multi_port_memory_access #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: memory access violation”), .coverage_level(‘QVL_COVER_ALL), .read_count(1), .write_count(2), .addr_width(8), .data_width(4), .data_check(1), .latency(1)) qvl_valid_memory_access( .read_clk(read_clk), .write_clk(write_clk), .read_reset_n(read_reset_n), .write__reset_n(write_reset_n), .active(1’b1), .read_active(1’b1), .write_active(1’b1), .read_addr(addr_rd), .read_data(data_rd), .read(read), .write_addr({addr_wr1, addr_wr0}), .write_data({data_wr1, data_wr0}), .write({write1, write0}), .start_addr(2’h00), .end_addr(2’hFF)); Questa Verification Library Checkers Data Book, 2010.1a 197 QVL Checker Data Sheets qvl_multi_clock_multi_port_memory_access Ensures that each read access from an address locks the address from write accesses for 1 read_clk cycle (write_while_read check), that each write access to an address locks the address from read accesses for 1 write_clk cycle (read_while_write check), and all write accesses in the same cycle are to different addresses (multiple_write check). Also ensures that the value of a data item returned in read_data 1 cycle after a read access is initiated to an address equals the value written to that address (data check, 1-cycle latency). write_clk read_clk read_reset_n read write0 write1 addr_rd ea ba 1111 data_rd 55 0010 addr_wr0 ea 1c data_wr0 1111 1001 addr_wr1 55 0000 0000 ba data_wr1 55 0010 0010 d3 0101 4a 1101 QVL_MCMPMEMACC_DATA Data read through the read port do not match the expected data. 198 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_enq_deq_fifo qvl_multi_enq_deq_fifo Ensures the data integrity of a FIFO with multiple enqueue and dequeue ports, and ensures that the FIFO does not overflow or underflow. enq[enq_count-1:0] deq[deq_count-1:0] full empty qvl_multi_enq_deq_fifo enq_data[enq_count*width-1:0] deq_data[deq_count*width-1:0] preload [preload_count*width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width depth enq_count deq_count pass registered latency preload_count high_water full_check empty_check value_check Class: n-cycle assertion Application: control and interface Syntax qvl_multi_enq_deq_fifo [#(severity_level, property_type, msg, coverage_level, width, depth, enq_count, deq_count, pass, registered, latency, preload_count, high_water, full_check, empty_check, value_check)] instance_name (clk, reset_n, active, enq, deq, full, empty, enq_data, deq_data, preload); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of a data item. Default: 1. depth FIFO depth. The depth must be > 1. Default: 2. enq_count Number of FIFO enqueue signals. Default : 1. deq_count Number of FIFO dequeue signals. Default : 1. Questa Verification Library Checkers Data Book, 2010.1a 199 QVL Checker Data Sheets qvl_multi_enq_deq_fifo pass How the FIFO handles a dequeue and enqueue in the same cycle if the FIFO is empty. pass = 0 (Default) No pass mode. Simultaneous dequeue/enqueue of an empty FIFO is a dequeue violation. pass = 1 Pass mode. Simultaneous dequeue/enqueue of an empty FIFO is not a dequeue violation. registered How the FIFO handles an enqueue and dequeue in the same cycle if the FIFO is full. registered = 0 (Default) No registered mode. Simultaneous enqueue/dequeue of a full FIFO is an enqueue violation. registered = 1 Registered mode. Simultaneous enqueue/dequeue of a full FIFO is not an enqueue violation. latency Latency for dequeued data used for the value check. latency = 0 (Default) Deq_data is valid in the same cycle that deq asserts. latency> 0 Deq_data is valid latency cycles after deq asserts. preload_count Number of items to preload the FIFO on reset. The preload port is a concatenated list of items to be preloaded into the FIFO. Default: 0 (FIFO empty on reset). high_water FIFO high-water mark. Must be < depth. A value of 0 sets the high-water mark to depth - 1. Default: 0. full_check Whether or not to perform full checks. full_check = 0 (Default) Turns off the full check. full_check = 1 Turns on the full check. empty_check Whether or not to perform empty checks. empty_check = 0 (Default) Turns off the empty check. empty_check = 1 Turns on the empty check. value_check Whether or not to perform value checks. value_check = 0 (Default) Turns off the value check. value_check = 1 Turns on the value check. 200 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_enq_deq_fifo Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. enq[enq_count-1:0] Concatenation of FIFO enqueue inputs. When one or more enq bits are sampled TRUE, the FIFO performs an enqueue operation from the asserted bits’ corresponding enqueue data ports in that enqueue cycle. Data items are enqueued in order from the leastto most-significant bits and the FIFO counter increments by the number of TRUE enq bits. deq[deq_count-1:0] Concatenation of FIFO dequeue inputs. When one or more deq bits are sampled TRUE, the FIFO performs a dequeue operation from the asserted bits’ corresponding dequeue data ports (latency dequeue cycles later). Data items are dequeued in order from the most- to least-significant bits and the FIFO counter decrements by the number of TRUE deq bits. full Output status flag from the FIFO. full = 0 FIFO not full. full = 1 FIFO full. empty Output status flag from the FIFO. empty = 0 FIFO not empty. empty = 1 FIFO empty. enq_data [(enq_count*width)-1: 0] Concatenation of enqueue data inputs. If the value check is on, this port contains the data items to enqueue when an enq bit is asserted. deq_data [(deq_count*width)-1: 0] Concatenation of dequeue data outputs. If the value check is on, this port contains the dequeued data items latency cycles after deq bits are asserted. Questa Verification Library Checkers Data Book, 2010.1a 201 QVL Checker Data Sheets qvl_multi_enq_deq_fifo preload [preload_count*width -1:0] Concatenated preload data to enqueue on reset. preload_count = 0 No preloading of the FIFO is assumed. The width of preload should be width, however, no values from preload are used. The FIFO is assumed to be empty on reset. preload_count > 0 Checker assumes the value of preload is a concatenated list of items to enqueue on the FIFO on reset (or simulation start). Preload items are the same width. Preload values are enqueued from the low order item to the high order item. Description The qvl_multi_enq_deq_fifo assertion ensures a multi-enqueue-dequeue FIFO functions legally. A multi-enqueue-dequeue FIFO is a memory structure that stores and retrieves data items based on a first-in first-out queueing protocol. The FIFO can have multiple enqueue data ports and multiple dequeue data ports (the number of each does need to match). Each enqueue data port has a corresponding enqueue signal that indicates the data port’s value should be enqueued in the current enqueue clock cycle. Similarly, each dequeue data port has a corresponding dequeue signal that indicates a data item from the FIFO should be dequeued to the port. A FIFO with multiple enqueue ports can enqueue from any combination of the ports each enqueue clock cycle. Similarly, a FIFO with multiple dequeue ports can dequeue to any combination of the ports each dequeue clock cycle. A FIFO with multiple enqueue (dequeue) ports assumes a constant port priority for multiple enqueues (dequeues). That is, when multiple ports are enqueued (dequeued) in a cycle, the order their contents are enqueued (dequeued) is always the same. A FIFO can also have a dequeue latency constant. This is the number of clock cycles it takes for a dequeue operation to produce results at the relevant dequeue ports. The qvl_multi_enq_deq_fifo checker monitors the enqueue signals concatenated into a single port (enq). The enq bits must be arranged in priority order from high priority (least-significant bit) to low priority (most significant bit). Similarly, the checker monitors the dequeue signals concatenated into a single port (deq). The deq bits must be arranged in priority order from low priority (least-significant bit) to high priority (most significant bit). The FIFO has configured properties specified as parameters to the checker: width of the data items (width), capacity of the FIFO (depth) and high-water mark that identifies the point at which the FIFO is almost full. Control and data signals to and from the FIFO also are connected to the checker. The checker checks enq and deq at the active edge of clk each cycle the checker is active. An enqueue violation occurs each cycle the number of items stored in the FIFO plus the number of TRUE bits of enq exceeds the FIFO depth. Similarly, a dequeue violation occurs each cycle the number of items stored in the FIFO is less than the number of TRUE bits of deq. The checker is conservative when enqueues and dequeues occur in the same cycle: a violation occurs if the 202 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_enq_deq_fifo FIFO can overflow or underflow during a combined enqueue/dequeue, even when the net result is within the FIFO’s range. The pass and registered parameters can be used to modify this effect. The checker can be configured to perform various additional checks such as verifying the data integrity of dequeued FIFO data (value check) and verifying that the FIFO’s full and empty status flags operate correctly (full and empty checks). The checker also can be configured to preload items on reset. Uses: FIFO, queue, buffer, ring buffer, elasticity buffer. Assertion Checks ENQUEUE An enqueue occurred while the FIFO was full. registered = 0 Number of FIFO items plus the number of TRUE enq bits was > depth. While the FIFO was full, an enqueue occurred without a dequeue in the same cycle. registered = 1 Number of FIFO items plus the number of TRUE enq bits minus the number of TRUE deq bits was > depth. DEQUEUE A dequeue occurred while the FIFO was empty. pass = 0 Number of FIFO items minus the number of TRUE deq bits was < 0. While the FIFO was empty, a dequeue occurred without an enqueue in the same cycle. pass = 1 Number of FIFO items plus the number of TRUE enq bits minus the number of TRUE deq bits is < 0. Questa Verification Library Checkers Data Book, 2010.1a 203 QVL Checker Data Sheets qvl_multi_enq_deq_fifo FULL The FIFO was not full when the full signal was asserted. full_check = 1 Full is TRUE, but the FIFO contains fewer than depth items. The full signal was not asserted when the FIFO was full. full_check = 1 Full is FALSE, but the FIFO contains depth items. The checker expects the full signal to be sequential (i.e., it asserts the cycle following the cycle that the FIFO becomes full and deasserts the cycle following the cycle that the FIFO becomes less than full). EMPTY The FIFO was not empty when the empty signal was asserted. empty_check = 1 Empty is TRUE, but the FIFO contains at least one item. The empty signal was not asserted when the FIFO was empty. empty_check = 1 Empty is FALSE, but the FIFO contains no items. The checker expects the empty signal to be sequential (i.e., it asserts the cycle following the cycle that the FIFO becomes empty and deasserts the cycle following the cycle that the FIFO holds an item). 204 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_enq_deq_fifo VALUE Dequeued FIFO value did not equal the corresponding enqueued value. (value_check = 1) and (latency = 0) A deq bit is TRUE, but its corresponding deq_data item does not equal the corresponding enqueued item. If an enqueue or dequeue violation occurs, this check is turned off until the checker is reset. Otherwise, a violation occurs each cycle the deq_data value does not match the expected value. (value_check = 1) and (latency > 0) A deq bit is TRUE, but latency cycles later its corresponding deq_data item does not equal the corresponding enqueued item. If an enqueue or dequeue violation occurs, this check is turned off until the checker is reset. Otherwise, a violation occurs each cycle the deq_data value does not match the expected value. This check automatically turns off if an enqueue or dequeue check violation occurs since it is no longer possible to correspond enqueued with dequeued values. The check turns back on when the checker resets. Cover Points Corner Cases FIFO Is Full Number of cycles the FIFO was full. FIFO Is Empty Number of cycles the FIFO was empty. Simultaneous Enqueues and Dequeues Number of cycles the FIFO enqueued a value and dequeued a value together. FIFO Is Over High-water Mark Number of cycles the FIFO had more data items than the highwater mark. Questa Verification Library Checkers Data Book, 2010.1a 205 QVL Checker Data Sheets qvl_multi_enq_deq_fifo Statistics Enqueues Number of cycles the FIFO enqueued values. Dequeues Number of cycles the FIFO dequeued values. See also qvl_fifo qvl_multi_clock_fifo qvl_multi_clock_multi_enq_deq_fifo Examples qvl_multi_enq_deq_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("MEDFIFO Violation"), .coverage_level(‘QVL_COVER_ALL), .depth(6), .enq_count(2), .deq_count(1)) MEDFIFO ( .clk(clock), .reset_n(1’b1), .active(1’b1), .enq({enq_sig2, enq_sig1}), .deq(deq_sig), .full(1’b0), .empty(1’b0), .enq_data(1’b0), .deq_data(1’b0), .preload(1’b0)); Checks that the FIFO, with two enqueue ports and one dequeue port, does not dequeue when empty and does not enqueue when full (i.e, when there are six entries). 206 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_enq_deq_fifo qvl_multi_enq_deq_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("MEDFIFO Violation"), .coverage_level(‘QVL_COVER_ALL), .depth(6), .width(4), .enq_count(2), .deq_count(1), .pass(1), .value_check(1)) MEDFIFO ( .clk(clock), .reset_n(1’b1), .active(1’b1), .enq({enq_sig2, enq_sig1}), .deq(deq_sig), .full(1’b0), .empty(1’b0), .enq_data({in2, in1}), .deq_data(out), .preload(1’b0)); Checks that the FIFO does not dequeue when empty unless it also enqueues and does not enqueue when full. It also checks that all dequeued values equal the corresponding enqueued values. qvl_multi_enq_deq_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("MEDFIFO Violation"), .coverage_level(‘QVL_COVER_ALL), .depth(6), .enq_count(2), .deq_count(1), .preload_count(3)) MEDFIFO ( .clk(clock), .reset_n(1’b1), .active(1’b1), .enq({enq_sig2, enq_sig1}), .deq(deq_sig), .full(1’b0), .empty(1’b0), .enq_data({in2, in1}), .deq_data(out), .preload({3’b110, 3’b101, 3’b100})); Checks that the FIFO correctly dequeues the preload values enqueued after a reset. Also checks that the FIFO does not dequeue when empty and does not enqueue when full. Questa Verification Library Checkers Data Book, 2010.1a 207 QVL Checker Data Sheets qvl_multi_enq_deq_fifo qvl_multi_enq_deq_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("MEDFIFO Violation"), .coverage_level(‘QVL_COVER_ALL), .depth(64), .width(8), .enq_count(4), .deq_count(1), .value_check(1)) MEDFIFO ( .clk(clock), .reset_n(1’b1), .active(1’b1), .enq({enq_simple_fifo, enq_simple_fifo, enq_simple_fifo, enq_simple_fifo}), .deq(transmit_from_unpack_logic), .full(1’b0), .empty(1’b0), .enq_data({rx_simple_fifo_data[31:24], .rx_simple_fifo_data[23:16], .rx_simple_fifo_data[15:8], .rx_simple_fifo_data[7:0]}), .deq_data(tx_data[7:0]), .preload(1’b0)); Checks that a simple 32-bit FIFO with unpacking logic coverts 32-bit received data into 8-bit transmit data. The unpacking logic should split the 32-bit output of the simple FIFO into four 8bit slices to be transmitted in sequence, starting with least significant slice. 208 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multi_enq_deq_fifo qvl_multi_enq_deq_fifo #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("MEDFIFO Violation"), .coverage_level(‘QVL_COVER_ALL), .depth(64), .width(8), .enq_count(1), .deq_count(4), .value_check(1)) MEDFIFO ( .clk(clock), .reset_n(1’b1), .active(1’b1), .enq(enq_simple_fifo), .deq({transmit_from_pack_logic, transmit_from_pack_logic, transmit_from_pack_logic, transmit_from_pack_logic), .full(1’b0), .empty(1’b0), .enq_data(rx_data[7:0]), .deq_data({tx_data_from_pack_logic[31:24], tx_data_from_pack_logic[23:16], tx_data_from_pack_logic[15:8], tx_data_from_pack_logic[7:0]]}), .preload(1’b0)); Checks that a simple 8-bit FIFO with packing logic converts 8-bit received data into 32-bit transmit data. The packing should read four 8-bit slices in sequence, starting with least significant slice and transmit as 32-bit data. Questa Verification Library Checkers Data Book, 2010.1a 209 QVL Checker Data Sheets qvl_multiplexor qvl_multiplexor Ensures that the output of the multiplexor is equal to the selected input and that at most one input is selected. in_data[in_width-1:0] select[select_width-1:0] qvl_multiplexor out_data[out_width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level in_width out_width select_width item_count binary Class: single-cycle assertion Application: datapath Syntax qvl_multiplexor [#(severity_level, property_type, msg, coverage_level, in_width, out_width, select_width, item_count, binary)] instance_name (clk, reset_n, active, in_data, mux_select, out_data); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. in_width Total width of the input variables. This should be equal to the item_count times the maximum input width. Default: 1. out_width Width of the multiplexor output port. Default: 1. select_width Width of the multiplexor select input port. Default: 1. item_count Number of multiplexor input variables. Default: 1. binary How to handle the mux_select input. binary = 0 (Default) One-hot selector. Exactly one asserted bit of the mux_select input selects the corresponding input value. The onehot_select_input check is turned on. binary = 1 Binary selector. Mux_select input is a binary value indicating the selected input value. The onehot_select_input check is turned off. 210 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multiplexor Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. in_data[in_width-1:0] Concatenated list of data inputs to the multiplexor. The low-order input of the multiplexor is the least significant input and the highorder input of the multiplexor is the most significant input. mux_select [select_width-1:0] Select inputs to the multiplexor. out_data [out_width-1:0] Multiplexed output from the multiplexor. Description The qvl_multiplexor checker ensures that the output of a multiplexor is equal to the value of the selected input when the checker is active. This check occurs at the active clock edge. It fires each cycle that the value of the selected input to the multiplexor does not equal the value of the multiplexor output. The mux_select input to the multiplexor selects which input to multiplex to the output. By default, the mux_select value is a one-hot encoding of the selected input’s rank. Each bit of the mux_select input corresponds to a unique input value to multiplex to the output. The number of bits in the mux_select input equals the number of input values concatenated into the in_data input. Since this encoding should be one-hot, the checker also performs a onehot_select_input check each time it performs the out_not_equal_to_in check. If the mux_select input is binary encoded, set the binary parameter to 1. This turns off the onehot_select_input check and uses the binary value of the mux_select input to select the input value to multiplex to the output. Assertion Checks ONEHOT_SELECT_INPUT The number of asserted bits of ’mux_select’ is not 1. binary = 0 Multiplexor has a one-hot-encoded selector and the select input is not one-hot encoded. Questa Verification Library Checkers Data Book, 2010.1a 211 QVL Checker Data Sheets qvl_multiplexor ONEHOT_OUT_NOT_EQUAL_ TO_IN The output of the one-hot multiplexor is not equal to the selected input. binary = 0 Multiplexor has a one-hot-encoded selector and the output does not equal the selected input. BINARY_OUT_NOT_EQUAL_ TO_IN The output of the binary-encoded multiplexor is not equal to the selected input. binary = 1 Multiplexor has a binary-encoded selector and the output does not equal the selected input. Cover Points Corner Cases All Inputs Selected Every input was selected during simulation. Statistics Selects Checked Number of mux_select values checked. Inputs Selected Number of the inputs selected. Inputs Not Selected Number of inputs not selected. See also none Examples qvl_multiplexor #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: addr multiplexor”), .coverage_level(‘QVL_COVER_ALL), .in_width(16), .select_width(2), .out_width(8), .item_count(2)) qvl_valid_addr_multiplexor( .clk(clk), .reset_n(reset_n), .active(read | write), .in_data({addr_lo, addr_hi}), .mux_select({sel_lo, sel_hi}), .out_data(addr)); 212 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_multiplexor Ensures that the value of {sel_lo, sel_hi} is one-hot and the value of addr is the same as the selected input (addr_lo or addr_hi) each cycle read or write is TRUE. clk reset_n read | write addr 03 F6 B4 XX 12 11 AB A8 addr_lo 03 B4 12 AB addr_hi F6 32 11 B8 sel_lo sel_hi QVL_MULTIPLEXOR_ONEHOT_SELECT_INPUT The number of asserted bits of ’select’ is not 1. QVL_MULTIPLEXOR_ONEHOT_OUT_ NOT_EQUAL_TO_IN The output of the one-hot multiplexor is not equal to the selected input. qvl_multiplexor #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: data src multiplexor”), .coverage_level(‘QVL_COVER_ALL), .in_width(4), .select_width(2), .item_count(4), .binary(1)) qvl_valid_addr_multiplexor( .clk(clk), .reset_n(reset_n), .active(state == ‘SEND), .in_data(data_src), .mux_select(sel_data_src), .out_data(data_out)); Ensures that the value of data_out is the same as the selected input (data_src[0], data_src[1], data_src[2] or data_src[3]) each cycle state is ‘SEND. Questa Verification Library Checkers Data Book, 2010.1a 213 QVL Checker Data Sheets qvl_multiplexor clk reset_n state == ‘SEND data_out sel_data_src 00 11 data_src[0] data_src[1] data_src[2] data_src[3] QVL_MULTIPLEXOR_BINARY_OUT_NOT_EQUAL_TO_IN The output of the binary multiplexor is not equal to the selected input. 214 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_mutex qvl_mutex Ensures that bits of an expression are mutually exclusive. Parameters: severity_level property_type test_expr[width-1:0] qvl_mutex msg coverage_level width Class: single-cycle assertion clk reset_n active Application: user Syntax qvl_mutex [#(severity_level, property_type, msg, coverage_level, width)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: `QVL_ERROR. property_type Property type. Default: `QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: `QVL_COVER_ALL. width Width of the test_expr argument. Default: 4. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. Questa Verification Library Checkers Data Book, 2010.1a 215 QVL Checker Data Sheets qvl_mutex Description The qvl_mutex checker ensures bits of test_expr are mutually exclusive when the checker is active. For this checker, bits of a variable are mutually exclusive when at most one bit is 1. The checker checks the multiple-bit expression test_expr at each rising edge of clk whenever active is TRUE. If the test_expr has more than one bit equal to 1, a mutex violation occurs. The assertion fails each active cycle that the test_expr bits are not mutually exclusive, even if test_expr has not changed from the previous value. This checker is useful for verifying FSMs, state machines, controllers, registers, and latches. Assertion Checks MUTEX Bits of test_expr are not mutually exclusive. Test_expr has more than one bit equal to 1. Cover Points Corner Cases All Mutex Checked If non-zero, every test_expr bit was sampled 1 at some point during simulation. All Zero Number of times test_expr was sampled when no bits were 1. Statistics Values Checked Number of times test_expr contained a new value when active was TRUE. See also none 216 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_mutex Example qvl_mutex #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: multiple grants”), .coverage_level(‘QVL_COVER_ALL), .width(3)) assert_grant_mutex( .clk(clk), .reset_n(reset_n), .active(grant_en), .test_expr({gnt3, gnt2, gnt1})); Ensures that the bits of {gnt3, gnt2, gnt1} are mutually exclusive when grant_en is TRUE at the rising edge of clk. clk reset_n grant_en gnt1 gnt2 gnt3 QVL_MUTEX The bits of test_expr are not mutually exclusive Questa Verification Library Checkers Data Book, 2010.1a 217 QVL Checker Data Sheets qvl_outstanding_id qvl_outstanding_id Ensures that all instances of IDs returned match the instances of IDs issued; that no more than a specified number of IDs are outstanding at any time; and that each ID must be outstanding for more than a specified minimum number of clock cycles and less than a specified maximum number of clock cycles. req req_id[width-1:0] req_count[count_width-1:0] ret ret_id[width-1:0] ret_count[count_width-1:0] flush qvl_outstanding_id flush_id[width-1:0] flush_count[count_width-1:0] pre_req_ids [pre_req_ids_count*width-1:0] pre_req_counts [pre_req_ids_count* pre_req_count_width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width count_width min max max_ids max_count_ per_id flush_enable flush_count_enable pre_req_ids_count pre_req_count_width allow_simultaneous_ req_ret allow_simultaneous_ flush_req allow_partial disallow_req_when_full known_ids_check known_flush_check Class: event-bounded assertion Application: control and interface Syntax qvl_outstanding_id [#(severity_level, property_type, msg, coverage_level, width, count_width, min, max, max_ids, max_count_per_id, flush_enable, flush_count_enable, pre_req_ids_count, pre_req_count_width, allow_simultaneous_req_ret, allow_simultaneous_flush_req, allow_partial, disallow_req_when_full, known_ids_check, known_flush_check)] instance_name (clk, reset_n, active, req, req_id, req_count, ret, ret_id, ret_count, flush, flush_id, flush_count, pre_req_ids, pre_req_counts); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL width Width of req_id, ret_id, flush_id and each item in pre_req_id. Default: 6. count_width Width of req_count, ret_count and flush_count. Default 2. 218 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_outstanding_id min Minimum number of clock cycles an ID instance must be outstanding. min = 0 (Default) Turns off the min check. min > 0 Turns on the min check. max Maximum number of clock cycles an ID instance can be outstanding. max = 0 (Default) Turns off the max check. max > 0 Turns on the max check. If min is also specified, max must be ≥ min. max_ids Value to use for the max_ids check. max_ids = 0 Turns off the max_ids check. (Default: max_ids = 16) Turns on the max_ids check. To minimize simulation overhead, set max_ids to the maximum expected value and no more (even if the maximum is less than 16). max_ids > 0 max_count_per_id Count to use for the max_count_per_id check. max_count_per_id = 0 Turns off the max_count_per_id check. max_count_per_id > 0 (Default: max_count_per_id = 8) Turns on the max_count_per_id check. To minimize simulation overhead, set max_count_per_id to the maximum expected value and no more (even if the maximum is less than 8). flush_enable Whether or not IDs can be flushed. flush_enable = 0 (Default) IDs cannot be flushed (flush, flush_id, flush_count, flush_count_enable and known_flush_check are ignored). flush_enable = 1 IDs can be flushed. flush_count_enable How to handle multiple instances of the same ID when the ID is flushed. flush_count_enable = 0 (Default) All instances of the ID are flushed (flush_count is ignored). flush_count_enable = 1 Only flush_count instances of the ID are flushed. pre_req_ids_count Number of unique IDs to assume are outstanding on reset. The pre_req_ids port is a concatenated list of IDs to add to the outstanding IDs list. Default: 0 (no IDs are outstanding). pre_req_count_width Width of each count in the pre_req_count port. Default 1. Questa Verification Library Checkers Data Book, 2010.1a 219 QVL Checker Data Sheets qvl_outstanding_id allow_simultaneous_ req_ret How the known_ids check handles request and return transactions with the same ID that occur in the same cycle. allow_simultaneous_req_ret = 0 (Default) Return ID is matched only with previously outstanding IDs. allow_simultaneous_req_ret = 1 Return ID is first matched with previously outstanding IDs, then is matched with the current request. allow_simultaneous_ flush_req How to handle request and flush transactions with the same ID that occur in the same cycle. allow_simultaneous_flush_req = 0 (Default) Instances of the request ID cannot be flushed. allow_simultaneous_flush_req = 1 Instances of the request ID can be flushed. allow_partial How to handle the current request when a max_count_per_id check violation occurs. allow_partial = 0 (Default) The current request is ignored. No instances of the current request ID are added to the outstanding IDs list. allow_partial = 1 The current request is partially fulfilled. Sufficient instances of the current request ID are added to the outstanding IDs list to make the outstanding count for the ID equal to max_count_per_id. disallow_req_when_full How the max_count_per_id check handles request and return transactions with the same ID that occur in the same cycle. disallow_req_when_full = 0 (Default) Return IDs are taken from the previously outstanding IDs, then the request IDs are made outstanding. disallow_req_when_full = 1 Request IDs are first considered outstanding, so, if the max_count_per_id is exceeded for the ID, a max_count_per_id check violation occurs. known_ids_check Whether or not to perform known_ids checks. known_ids_check = 0 Turns off the known_ids check. (Default) Turns on the known_ids check. known_ids_check = 1 known_flush_check Whether or not to perform known_flush checks. known_flush_check = 0 (Default) Turns off the known_flush check. known_flush_check = 1 Turns on the known_flush check. 220 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_outstanding_id Ports clk Clock event for the assertion. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. req Signal that indicates req_id is valid. req_id[width-1:0] Register or wire containing the request ID sent out on the bus. req_count [count_width-1:0] Register or wire containing the number of instances of req_id to make outstanding. ret Signal that indicates ret_id is valid. ret_id[width-1:0] Register or wire containing the ID returned from the bus. ret_count [count_width-1:0] Register or wire containing the number of instances of ret_id to remove from the outstanding IDs list. flush Signal that indicates flush_id is valid. flush_id [width-1:0] Register or wire containing the ID to flush. flush_count [count_width-1:0] Register or wire containing the number of instances of flush_id to flush (if flush_count_enable is 1). pre_req_ids [(pre_req_ids_count * width)-1:0] Concatenated list of IDs to assume are outstanding on reset. pre_req_ids_count = 0 No IDs are outstanding. The width of pre_req_ids should be width, however, no values from pre_req_ids are used. pre_req_ids_count > 0 The value of pre_req_ids is a concatenated list of unique IDs to assume are outstanding on reset (or simulation start). pre_req_counts [(pre_req_ids_count *pre_req_count_width) -1:0] Concatenated list of counts of the corresponding pre_req_ids IDs to assume are outstanding on reset. pre_req_ids_count = 0 No IDs are outstanding. The width of pre_req_counts should be 1, however, pre_req_counts is ignored. pre_req_ids_count > 0 Value of pre_req_counts is a concatenated list of pre_req_ids_count counts, each count being pre_req_count_width wide. The counts in pre_req_counts correspond to the IDs in pre_req_ids. Each count specifies the number of instances of its corresponding ID to assume are outstanding on reset. Questa Verification Library Checkers Data Book, 2010.1a 221 QVL Checker Data Sheets qvl_outstanding_id Description The qvl_outstanding_id assertion ensures bus IDs are issued and returned properly. The checker evaluates ret and req signals at each rising edge of clk whenever active is TRUE. By default, the following verification is performed: 1. If ret is TRUE, an ID return is assumed. a. Ret_id_count instances of ret_id are removed from the list of outstanding IDs. 2. If req is TRUE, an ID request is assumed. a. If 16 unique IDs are outstanding and req_id is not one of them, a max_ids check violation occurs. The request is ignored. b. If the number of outstanding instances of req_id plus req_id_count is larger than 8, a max_count_per_id check violation occurs. The request is ignored. c. Otherwise, req_id_count instances of req_id are added to the list of outstanding IDs. The default operation can be adjusted in the following ways: • If the max_ids parameter is specified, the maximum number of unique outstanding IDs is changed from 16. Setting this value to the smallest viable value is recommended • If the max_count_per_id parameter is specified, the maximum number of outstanding ID instances per unique ID is changed from 8. Setting this value to the smallest viable value is recommended • If the allow_partial parameter is 1, when a max_count_per_id violation occurs, instances of req_id are made outstanding (up to the max_count_per_id limit) • If the disallow_req_when_full parameter is 1, the max_count_per_id check is modified to ignore instances of the request ID that are returned in the current cycle. Here, a check violation occurs when max_count_per_id is exceeded even if the return transaction reduced the outstanding count for the ID to max_count_per_id or below. The following additional checker functionality is available: • Outstanding ID flushing. Set the flush_enable parameter to 1 to model outstanding ID flushing. When the flush signal is sampled TRUE, all instances of flush_id are removed from the outstanding IDs. If allow_simultaneous_flush_req is 1, this includes the current request ID if it equals flush_id. If flushing is enabled, set the flush_count_enable to 1 to allow partial flushing of IDs. Here, only flush_count instances of the flushed ID are removed from the outstanding IDs. 222 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_outstanding_id • Preload ID instances on reset. Setting pre_req_ids_count to non-zero causes the checker to preload pre_req_ids_count unique outstanding IDs on reset (read from pre_req_ids). The counts for the ID instances are taken from pre_req_counts. The following additional checks are available: • Known_ids check verifies that each returned ID instance was actually outstanding. • Known_flush check verifies that each flushed ID instance was actually outstanding. • Min check verifies that each ID instance is outstanding for at least min cycles. • Max check verifies that each ID instance is outstanding for at most max cycles. Uses: FIFO, queue, stack, LIFO, handshake, linked list, req_ack, request, acknowledge, ready, take, hold, wait, bridge, transactions, switch, packet, IDs, tokens, interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (IOs), pipeline, dataflow, datapath, memory, register array, temporal, time, window. Assertion Checks MAX_IDS New ID was requested when the maximum number of unique IDs were outstanding. = 0) The maximum number of unique IDs were outstanding and another ID was requested without a simultaneous return or flush that removed all instances of an ID from the outstanding IDs list. (max_ids > 0) and (disallow_req_when_full = 1) The maximum number of unique IDs were outstanding and a new ID was requested. (max_ids > 0) and (disallow_req_when_full When a max_ids violation occurs, the request ID is ignored (i.e., not added to the outstanding IDs list). If the ID subsequently is returned (or flushed), a known_ids (or known_flush) check violation might occur. Questa Verification Library Checkers Data Book, 2010.1a 223 QVL Checker Data Sheets qvl_outstanding_id MAX_COUNT_PER_ID ID was requested that would make the outstanding ID count for the ID exceed the maximum count per ID value. (max_count_per_id > 0) and (disallow_req_when_full = 0) For the request ID: the current outstanding count plus the request count minus the return count (if any) minus the flush count (if any) is greater than max_count_per_id. (max_count_per_id > 0) and (disallow_req_when_full = 1) For the request ID: the current outstanding count plus the request count is greater than max_count_per_id. How the checker handles a max_count_per_id violation depends on the allow_partial parameter. allow_partial = 0 The current request is ignored. No instances of the current request ID are added to the outstanding IDs list. allow_partial = 1 The current request is partially fulfilled. Sufficient instances of the current request ID are added to the outstanding IDs list to make the outstanding count for the ID equal to max_count_per_id. When an overflow error occurs, compare the outstanding requests (effective_req_count checker value) and the requested ids (req_count checker value). The effective_req_count is the number of requests outstanding for the active req_id. KNOWN_IDS The number of instances of the return ID exceeded the count of the ID’s outstanding instances. (known_ids_check = 1) and (allow_simultaneous_req_ret = 0) Return ID does not match any outstanding ID or the return ID count is > count of the current outstanding count for the ID. (known_ids_check = 1) and (allow_simultaneous_req_ret = 1) Return ID does not match an outstanding ID (or the request ID, if enabled) or the return ID count is > count of the current outstanding count for the ID (plus the request count, if enabled and the request ID is the same as the return ID). 224 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_outstanding_id KNOWN_FLUSH The number of instances of the flush ID exceeded the count of the ID’s outstanding instances. (known_flush_check = 1) and (allow_simultaneous_flush_req = 0) Flush ID does not match any outstanding ID or the flush ID count is > count of the current outstanding count for the ID. (known_flush_check = 1) and (allow_simultaneous_flush_req = 1) Flush ID does not match an outstanding ID (or the request ID, if enabled) or the flush ID count is > count of the current outstanding count for the ID (plus the request count, if enabled and the request ID is the same as the flush ID). MIN ID instance was returned before the minimum allowed number of cycles. min > 0 The returned ID instance was not outstanding for at least min cycles. MAX ID instance was outstanding longer than the maximum allowed number of cycles. max > 0 Max cycles have transpired from the cycle in which the ID instance was requested to the current cycle, but the ID instance was not returned or flushed. Cover Points Corner Cases IDs Requested Number of IDs requested. IDs Returned Number of IDs returned. Outstanding IDs Equal Maximum IDs Number of times the number of outstanding IDs equalled max_ids. Meaningful only if max_ids is not 0. Outstanding Count Per ID Equals Maximum Count Per ID Number of times an outstanding ID had max_count_per_id instances outstanding. Meaningful only if max_count_per_id is not 0. Minimum Cycles Outstanding Equals Minimum. Number of cycles in which an instance of the return ID was returned exactly min cycles after its request. Meaningful only if min is not 0. Maximum Cycles Outstanding Equals Maximum Number of cycles in which an instance of the return ID was returned exactly max cycles after its request. Meaningful only if max is not 0. Questa Verification Library Checkers Data Book, 2010.1a 225 QVL Checker Data Sheets qvl_outstanding_id All IDs Requested If non-zero, every value of req_id was requested. Statistics IDs Flushed Number of IDs flushed. Unique IDs Issued Number of unique IDs issued. Notes 1. The maximum number of unique IDs outstanding is max_ids (default: 16). The larger the max_ids value, the greater the simulation overhead. 2. This checker matches return IDs against pending IDs requested on previous clock cycles. If the same ID is requested and returned in the same cycle, the checker first matches the return instances against instances pending from instances requested in previous clock cycles. Then if more instances are returned than previously requested, the checker: • Fires the known_ids check (unless allow_simultaneous_req_ret is specified). • Matches the remaining return instances with the current request instances (if allow_simultaneous_req_ret is specified). If the number of IDs or counts per ID are nearing the maximums, the same ID simultaneously requested and returned can cause the max_ids or max_count_per_id checks to fire when the number of instances requested is greater than the number of instances returned. 3. The flush can be used to mimic a second ret option, provided the flush_count option is used. (If the flush_count option is not specified, all instances of the ID are flushed when flush asserts.) See also qvl_bus_id 226 qvl_scoreboard Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_outstanding_id Examples qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_OUTSTANDING_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .max_ids(1), .max_count_per_id(1) U1 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(send_sig), .req_id(send_id), .req_count(1’b1), .ret(back_sig), .ret_id(back_id), .ret_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_req_ids(4’b0), .pre_req_counts(1’b0)); Checks that outstanding IDs requested on send_id are not already outstanding and that only issued IDs are returned on back_id. Questa Verification Library Checkers Data Book, 2010.1a 227 QVL Checker Data Sheets qvl_outstanding_id qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_OUTSTANDING_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(8), .count_width(1), .max_ids(8), .max_count_per_id(2), .disallow_req_when_full(1)) U2 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(req), .req_id(out_id), .req_count(1’b1), .ret(ret), .ret_id(ret_sig), .ret_count(1’b1), .flush(1’b0), .flush_id(8’b0), .flush_count(1’b0), .pre_req_ids(8’b0), .pre_req_counts(1’b0)); Checks that at most eight unique IDs are outstanding, that at most two instances of a unique ID are outstanding and that no ID is requested if max_count_per_id instances of the ID are already outstanding even if instances of the ID are simultaneously returned. qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_OUTSTANDING_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .max_ids(12), .max_count_per_id(4)) U3 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(issue_sig), .req_id(issue_id), .req_count(1’b1), .ret(back_sig), .ret_id(back_id), .ret_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_req_ids(4’b0), .pre_req_counts(1’b0)); 228 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_outstanding_id Checks that IDs do not get issued more than 4 times and that no more than 12 total IDs are outstanding. qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_OUTSTANDING_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(3)) U4 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(issue_sig), .req_id(issue_id), .req_count(3’b1), .ret(back_sig), .ret_id(back_id), .ret_count(data_cycles), .flush(1’b0), .flush_id(4’b0), .flush_count(3’b0), .pre_req_ids(4’b0), .pre_req_counts(1’b0)); Checks that when an ID is returned that it asserts for each data cycle. This check can be used when a single read request gets multiple returns, each with some of the read data. qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_OUTSTANDING_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .min(2), .max(4)) U5 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(issue_sig), .req_id(issue_id), .req_count(1’b1), .ret(back_sig), .ret_id(back_id), .ret_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_req_ids(4’b0), .pre_req_counts(1’b0)); Checks that an ID is returned at least two cycles and at most four cycles after it is issued. Questa Verification Library Checkers Data Book, 2010.1a 229 QVL Checker Data Sheets qvl_outstanding_id qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_OUTSTANDING_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(1), .count_width(3), .max_count_per_id(13)) U6 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(send), .req_id(send), .req_count(3’d5), .ret(back), .ret_id(back), .ret_count(3’b1), .flush(1’b0), .flush_id(1’b0), .flush_count(3’b0), .pre_req_ids(1’b0), .pre_req_counts(1’b0)); If outstanding count per id is 10 and 3 new requests arrive, the max_count_per_id check fires and the outstanding count per id remains at 10. qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_OUTSTANDING_ID Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(1), .count_width(3), .max_count_per_id(13), .allow_partial(1)) U7 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(send), .req_id(send), .req_count(3’d5), .ret(back), .ret_id(back), .ret_count(3’b1), .flush(1’b0), .flush_id(1’b0), .flush_count(3’b0), .pre_req_ids(1’b0), .pre_req_counts(1’b0)); If outstanding count per id is 10 and 3 new requests arrive, the max_count_per_id check fires but the outstanding count per id increments to 13. 230 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_outstanding_id qvl_outstanding_id #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_OUTSTANDING_ID Violation: "), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .max_ids(0), .max_count_per_id(0), .pre_req_ids_count(6), .pre_req_count_width(4)) U8 ( .clk(system_clock), .reset_n(system_reset), .active(oid_active), .req(req), .req_id(req_id), .req_count(1’b1), .ret(ret), .ret_id(ret_id), .ret_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_req_ids({4’d15, 4’d14, 4’d13, 4’d12, 4’d11, 4’d10}), .pre_req_counts({4’d8, 4’d8, 4’d7, 4’d6, 4’d5, 4’d4})); Checks that only issued IDs are returned on ret_id. Here list of IDs to be considered outstanding prior to beginning simulation is specified along with count for each id. Questa Verification Library Checkers Data Book, 2010.1a 231 QVL Checker Data Sheets qvl_parallel_to_serial qvl_parallel_to_serial Ensures that a parallel-to-serial converter behaves properly. in_clk in_reset_n in_active active load hold qvl_parallel_to_serial msb in_data[width-1:0] out_data out_clk out_reset_n out_active Parameters: severity_level property_type msg coverage_level width latency sync_delay msb_convert_check hold_check reversal_check consecutive_load_check Class: n-cycle assertion Application: datapath Syntax qvl_parallel_to_serial [#(severity_level, property_type, msg, coverage_level, width, latency, sync_delay, msb_convert_check, hold_check, reversal_check, consecutive_load_check)] instance_name (in_clk, out_clk, in_reset_n, out_reset_n, active, in_active, out_active, load, hold, msb, in_data, out_data); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width Width of in_data. Default : 4. latency Latency for serial data in out_clk cycles. latency = 0 (Default) Out_data is valid at the current, or next, active edge of out_clk when a data item is loaded into the out_clk domain parallel data register. The value of out_data becomes stable when hold asserts and transitions to the value of the next serial bit when hold deasserts. latency > 0 Out_data is valid latency out_clk cycles after a data item is loaded into the out_clk domain parallel data register. The value of out_data becomes stable latency out_clk cycles after hold asserts and transitions to the value of the next serial bit latency out_clk cycles after hold deasserts. 232 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_parallel_to_serial sync_delay CDC synchronization delay for loading the out_clk domain parallel data register in out_clk cycles. sync_delay = 0 (Default) No delay is needed to synchronize the input parallel data with the internal parallel data register in the out_clk domain. sync_delay > 0 Parallel data items are delayed sync_delay out_clk cycles between the data_in port in the in_clk domain and the parallel data register in the out_clk domain. msb_convert_check Whether or not to perform MSB_convert checks. msb_convert_check = 0 (Default) Turns off the MSB_convert check. msb_convert_check = 1 Turns on the MSB_convert check. hold_check Whether or not to perform hold checks. hold_check = 0 (Default) Turns off the hold check. hold_check = 1 Turns on the hold check. reversal_check Whether or not to perform reversal checks. hold_check = 0 (Default) Turns off the reversal check. hold_check = 1 Turns on the reversal check. consecutive_load_check Whether or not to perform consecutive_load checks. consecutive_load_check = 0 (Default) Turns off the consecutive_load check. consecutive_load_check = 1 Turns on the consecutive_load check. Ports in_clk Clock event for the parallel data (input) domain. The checker samples the parallel data inputs on the rising edge of in_clk. out_clk Clock event for the serial data (output) domain. The checker samples the serial data inputs on the rising edge of out_clk. in_reset_n Active low synchronous reset signal indicating the parallel data domain logic is initialized. out_reset_n Active low synchronous reset signal indicating the serial data domain logic is initialized. active Expression that indicates whether or not to check the inputs. Questa Verification Library Checkers Data Book, 2010.1a 233 QVL Checker Data Sheets qvl_parallel_to_serial in_active Expression that indicates whether or not to activate checks of parallel data load operations (i.e., load and consecutive_load checks). out_active Expression that indicates whether or not to activate checks of serial data output operations (i.e., LSB_convert, MSB_convert. hold and reversal checks). load Load enable signal to the serializer. When load is sampled TRUE at the active edge of in_clk, the checker reads the value of data_in and propagates the value to its internal parallel data register. hold Hold signal from the serializer. When hold is sampled TRUE at the active edge of out_clk, the checker assumes the serial data output (data_out) is stalled for the same number of cycles that hold remains asserted. If latency is 0, this hold period aligns with the rising out_clk edges corresponding with the assertion and deassertion of the hold signal. If latency is > 0, this hold period is delayed by latency cycles of out_clk. During a hold period, the checker assumes the output bits of data_out represent the same bit in the data item. If hold_check is 1, a hold check violation occurs if the value of out_data changes during a hold period. msb Conversion direction signal to the serializer. If msb is FALSE, the serializer should perform LSB conversion (i.e., right-shift register after output least-significant bit). If msb is TRUE, the serializer should perform MSB conversion (i.e., left-shift register after output most-significant bit). If reversal_check is 1, a reversal check violation occurs if the value of msb changes in out_clk cycles where out_data contains new data for the same data item. in_data[width-1:0] Parallel data input to the serializer. out_data Serial data output from the serializer. Description The qvl_parallel_to_serial checker ensures a data serializer/synchronizer functions correctly. A data serializer takes multi-bit values and converts them to bit streams. In effect, a data serializer converts parallel data into serial data. The qvl_parallel_to_serial checker supports serializers that pass data from one clock domain (parallel data domain) to another (serial data domain). In particular, the checker is a dual-clock checker that has separate clock, reset and activation inputs for the data input logic (in_clk, in_reset_n and in_active) and for the data output logic (out_clk, 234 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_parallel_to_serial out_reset_n and out_active). The checker also has an asynchronous global activation input (active). The checker evaluates the load signal at each rising edge of in_clk whenever active and in_active are TRUE. If load is TRUE, the checker starts a data conversion cycle by reading the value of data_in. This is the parallel data item to be converted to a bit stream. In subsequent in_clk cycles, load should revert to FALSE and remain FALSE until the conversion is complete. Otherwise, a load check violation occurs. When a conversion cycles starts, the data_in value is propagated to an internal parallel data register in the out_clk domain. By default, if the two active clock edges are aligned when load asserts, data propagation is instantaneous; otherwise, the register is loaded at the next active edge of out_clk. If the internal register loads or contains a data value at the active edge of out_clk, the checker evaluates the hold and msb inputs. If hold is FALSE: • If msb is FALSE, the checker propagates the LSB bit of the parallel data register to a serial bit register and shifts the parallel data register 1 bit to the right (removing the LSB bit). • If msb is TRUE, the checker propagates the MSB bit of the parallel data register to a serial bit register and shifts the parallel data register 1 bit to the left (removing the MSB bit). By default, this propagation is instantaneous. Each out_clk cycle in which the serial bit register loads an LSB bit, the checker evaluates the data_out value. If both bits do not match, an LSB_convert check violation occurs. Most serializer implementations have delay and latency through their data paths. To accommodate these schemes, the qvl_parallel_to_serial checker can be configured as follows: • If the sync_delay parameter is > 0, the checker loads the internal parallel data register sync_delay out_clk cycles after the load input asserts. • If the latency parameter is > 0, the checker loads the serial data register latency out_clk cycles after the bit was shifted off the parallel data register. In addition to the load and LSB_convert checks, the qvl_parallel_to_serial checker can be configured to perform the following checks. • If msb_convert_check is 1, an MSB_convert check violation occurs whenever a serial data mismatch occurs on an MSB bit. • If hold_check is 1, a hold check violation occurs if latency cycles after hold asserts, the value of out_data is not the same as its previous value. • If reversal_check is 1, a reversal check violation occurs if msb changes value when the parallel data register contains a partially-converted value. Questa Verification Library Checkers Data Book, 2010.1a 235 QVL Checker Data Sheets qvl_parallel_to_serial • If consecutive_load_check is 1, a consecutive_load check violation occurs if the parallel data register does not load a new parallel data item in the same cycle a shift operation empties it. Uses: Interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (I/Os). Assertion Checks LOAD Parallel data item was loaded while the previous data item was being converted. sync_delay = 0 Load was TRUE at the active edge of in_clk. If this event coincided with the active edge of out_clk, then the parallel data register contained a pending data bit. Otherwise at the next active edge of out_clk, the parallel data register contained a pending data bit. sync_delay > 0 Load was TRUE at the active edge of in_clk. Then, sync_delay active out_clk edges later (including the current edge if coincident with the current in_clk edge), the parallel data register contained a pending data bit. LSB_CONVERT Serial data bit did not match the LSB of the parallel data. latency = 0 The internal parallel data register contained at least one bit of a pending data item at an active edge of out_clk when msb and hold were both FALSE. But, the register’s LSB bit did not match the value of out_data. latency > 0 The internal parallel data register contained at least one bit of a pending data item at an active edge of out_clk when msb and hold were both FALSE. But, the register’s LSB bit did not match the value of out_data, latency out_clk cycles later. 236 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_parallel_to_serial MSB_CONVERT Serial data bit did not match the MSB of the parallel data. msb_convert_check = 1 and latency = 0 The internal parallel data register contained at least one bit of a pending data item at an active edge of out_clk when msb was TRUE and hold was FALSE. But, the register’s MSB bit did not match the value of out_data. msb_convert_check = 1 and latency > 0 The internal parallel data register contained at least one bit of a pending data item at an active edge of out_clk when msb was TRUE and hold was FALSE. But, the register’s MSB bit did not match the value of out_data, latency out_clk cycles later. HOLD Hold was asserted but the corresponding serial bit changed value. hold_check = 1 and latency = 0 At an active edge of out_clk when hold was TRUE, the value of out_data changed from its value at the previous active edge of out_clk. hold_check = 1 and latency >0 At an active edge of out_clk latency cycles after hold was TRUE, the value of out_data changed from its value at the previous active edge of out_clk. REVERSAL Shift direction reversed while a parallel data item was being converted. reversal_check = 1 The internal parallel data register contained at least one bit of a pending data item (but fewer than width bits) at an active edge of out_clk when hold was FALSE. But, the value of msb had changed from its value at the last active edge of out_clk at which hold was FALSE. Questa Verification Library Checkers Data Book, 2010.1a 237 QVL Checker Data Sheets qvl_parallel_to_serial CONSECUTIVE_LOAD Parallel data item did not load right after a data item was converted. consecutive_load_check = 1 and sync_delay = 0 Load was FALSE at the active edge of in_clk. But, at the previous active edge of out_clk (or the current edge if the two clock edges are aligned), the last bit of a pending data item was shifted from the parallel data register. consecutive_load_check = 1 and sync_delay > 0 Load was FALSE at the active edge of in_clk. But, sync_delay active edges of out_clk later (including the current edge if the two clock edges are aligned), the last bit of a pending data item was shifted from the parallel data register. Cover Points Corner Cases LSB Conversions Number of parallel data items converted by right-shifting off the LSB bits. MSB Conversions Number of parallel data items converted by left-shifting off the MSB bits. Meaningful only if msb_convert_check is 1. Statistics Total Conversions Number of parallel data items converted by right-shifting off the LSB bits or left-shifting off the MSB bits. Right Shifts Number of out_clk cycles the parallel data register shifted right. Left Shifts Number of out_clk cycles the parallel data register shifted left. Load Cycles Number of in_clk cycles a parallel data item was loaded. Hold Cycles Number of out_clk cycles serial output was in a hold state. See also qvl_serial_to_parallel Examples qvl_parallel_to_serial #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("PtoS Violation"), .coverage_level(‘QVL_COVER_ALL), .width(4), .reversal_check(1)) QVL_PtoS1 ( .in_clk(pclk), 238 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_parallel_to_serial .out_clk(sclk), .in_reset_n(1’b1), .out_reset_n(1’b1), .active(1’b1), .in_active(1’b1), .out_active(1’b1), .load(load), .hold(1’b0), .msb(shift_mode), .in_data(p_data), .out_data(s_data)); ); Checks LSB first conversion. qvl_parallel_to_serial #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("PtoS Violation"), .coverage_level(‘QVL_COVER_ALL), .width(4), .reversal_check(1), .consecutive_load_check(1)) QVL_PtoS2 ( .in_clk(pclk), .out_clk(sclk), .in_reset_n(1’b1), .out_reset_n(1’b1), .active(1’b1), .in_active(1’b1), .out_active(1’b1), .load(load_sig), .hold(1’b0), .msb(1’b0), .in_data(p_data), .out_data(s_data)); Checks LSB first conversion and that the serializer is loaded with parallel data every time a conversion is complete. Questa Verification Library Checkers Data Book, 2010.1a 239 QVL Checker Data Sheets qvl_parallel_to_serial qvl_parallel_to_serial #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("PtoS Violation"), .coverage_level(‘QVL_COVER_ALL), .width(4), .sync_delay(1), .latency(2), .msb_conversion_check(1), .reversal_check(1)) QVL_PtoS3 ( .in_clk(pclk), .out_clk(sclk), .in_reset_n(1’b1), .out_reset_n(1’b1), .active(1’b1), .in_active(1’b1), .out_active(1’b1), .load(load), .hold(1’b0), .msb(shift_mode), .in_data(p_data), .out_data(s_data)); Checks LSB first and MSB first conversions with a load delay of 1 sclk cycle and an output latency of 2 sclk cycles. 240 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_req_ack qvl_req_ack Ensures that a request is correctly followed by an acknowledge, and that the req and ack signals conform to specified rules. req ack qvl_req_ack ack_assert_to_req_deassert_min ack_assert_to_req_deassert_max req_deassert_to_ack_deassert_min req_deassert_to_ack_deassert_max clk reset_n active Parameters: severity_level property_type msg coverage_level max max_check min no_simultaneous_req_ack new_req_after_ack req_until_ack min_max_port_width ack_assert_to_req_ deassert_max_check req_deassert_to_ack_ deassert_max_check ack_until_req_deassert ack_deassert_to_req_ deassert_max_check max_ack Class: event-bounded assertion Application: interface Syntax qvl_req_ack [#(severity_level, property_type, msg, coverage_level, max, max_check, min, no_simultaneous_req_ack, new_req_after_ack, req_until_ack, min_max_port_width, ack_assert_to_req_deassert_max_check, req_deassert_to_ack_deassert_max_check, ack_until_req_deassert, ack_deassert_to_req_deassert_max_check, max_ack )] instance_name (clk, reset_n, active, req, ack, ack_assert_to_req_deassert_min, ack_assert_to_req_deassert_max, req_deassert_to_ack_deassert_min, req_deassert_to_ack_deassert_max, ack_deassert_to_req_deassert_min, ack_deassert_to_req_deassert_max ); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. max Maximum number of clock cycles allowed from the cycle after a request is issued to the cycle the request is acknowledged (if the max check is on). Default: 0. Questa Verification Library Checkers Data Book, 2010.1a 241 QVL Checker Data Sheets qvl_req_ack max_check Whether or not to perform max checks. max_check = 0 (Default) Turns off the max check. max_check = 1 Turns on the max check. min Minimum number of clock cycles from the cycle after a request is issued to the cycle the request is acknowledged. Default: 0 (the acknowledge must be given in the cycle following the request). no_simultaneous_ req_ack Whether or not it is legal to acknowledgement a request in the same cycle the request is issued. no_simultaneous_req_ack = 0 (Default) Simultaneous acknowledgement of requests is legal. no_simultaneous_req_ack = 1 Simultaneous acknowledgement of requests is not legal. new_req_after_ack How to handle a req that remains asserted in the cycle ack asserts. new_req_after_ack = 0 (Default) When req remains asserted in the cycle ack asserts, a new request is not initiated. new_req_after_ack = 1 When req remains asserted in the cycle ack asserts, a new request is initiated. req_until_ack Whether or not to perform req_until_ack checks. req_until_ack = 0 (Default) Turns off the req_until_ack check. req_until_ack = 1 Turns on the req_until_ack check. min_max_port_width Width of the ports (default = 32): ack_assert_to_req_deassert_min ack_assert_to_req_deassert_max req_deassert_to_ack_deassert_min req_deassert_to_ack_deassert_max ack_deassert_to_req_deassert_min ack_deassert_to_req_deassert_max ack_assert_to_ req_deassert_max_check Whether or not to perform ack_assert_to_req_deassert_max checks. ack_assert_to_req_deassert_max_check = 0 (Default) Turns off the ack_assert_to_req_deassert_max check. ack_assert_to_req_deassert_max_check = 1 Turns on the ack_assert_to_req_deassert_max check. 242 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_req_ack req_deassert_to_ ack_deassert_max_check Whether or not to perform req_deassert_to_ack_deassert_max checks. req_deassert_to_ack_deassert_max_check = 0 (Default) Turns off the req_deassert_to_ack_deassert_max check. req_deassert_to_ack_deassert_max_check = 1 Turns on the req_deassert_to_ack_deassert_max check. ack_until_req_deassert Whether or not to perform ack_until_req_deassert checks. ack_until_req_deassert = 0 (Default) Turns off the ack_until_req_deassert check. ack_until_req_deassert = 1 Turns on the ack_until_req_deassert check. ack_deassert_to_ req_deassert_max_check Whether or not to perform ack_deassert_to_req_deassert_max checks. ack_deassert_to_req_deassert_max_check = 0 (Default) Turns off the ack_deassert_to_req_deassert_max check. ack_deassert_to_req_deassert_max_check = 1 Turns on the ack_deassert_to_req_deassert_max check. max_ack Maximum number of clock cycles that an ack signal should be held TRUE. max_ack = 0 (Default) Turns off the max_ack check. max_ack > 0 Turns on the max_ack check. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to monitor req and ack. req Request signal. ack Acknowledgment signal. ack_assert_to_ req_deassert_min Minimum number of cycles req should be held TRUE after ack asserts. ack_assert_to_ req_deassert_max Maximum number of cycles req should be held TRUE after ack asserts. req_deassert_to_ ack_deassert_min Minimum number of cycles ack should be held TRUE after req deasserts. req_deassert_to_ ack_deassert_max Maximum number of cycles ack should be held TRUE after req deasserts. Questa Verification Library Checkers Data Book, 2010.1a 243 QVL Checker Data Sheets qvl_req_ack ack_deassert_to_ req_deassert_min Minimum number of cycles req should be held TRUE after ack deasserts. ack_deassert_to_ req_deassert_max Maximum number of cycles req should be held TRUE after ack deasserts. Description The qvl_req_ack checker ensures two signals req and ack conform to a specified requestacknowledge handshake protocol. The checker checks the values of req and ack at the active edge of clk each cycle the checker is active. A req/ack transaction is initiated when req is sampled FALSE in one cycle and TRUE in the subsequent cycle. The transaction completes when ack is sampled FALSE in one cycle and TRUE in the subsequent cycle. The checker ensures each request is acknowledged before the next request is initiated (single_req check) and that no acknowledgment is given unless a request is pending (single_ack check). The checker can be configured to perform various checks of the req/ack pulses and their relative timing as it monitors each transaction. After asserting to acknowledge a request, ack must deassert before it can acknowledge the next request. In contrast, how the checker handles the case when req stays TRUE when ack asserts is determined by the new_req_after_ack parameter: new_req_after_ack = 0 (default) If req remains TRUE when ack asserts to acknowledge a request, then no new request is initiated. The request is considered part of the completed transaction as long as req remains TRUE. To initiate another request, req must be sampled FALSE and then TRUE. new_req_after_ack = 1 If req is TRUE when ack asserts to acknowledge a request, then a new request is initiated. The qvl_req_ack checker monitors pairs of 1-bit signals. To verify a multibit req/ack protocol, you must instantiate one qvl_req_ack checker for each pair of req/ack bits. Assertion Checks SINGLE_REQ More than one request occurred without an intervening acknowledgment. Req asserts to initiate a request, deasserts, and then reasserts to initiate a second request. However, an acknowledge is not issued for the first request. It is not a violation if the acknowledge is issued in the same cycle the second request is initiated. 244 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_req_ack SINGLE_ACK A non-requested acknowledge occurred. Ack asserts to acknowledge a request, but no request is outstanding from previous cycles and no request is initiated in the current cycle. MAX More than the specified maximum acknowledgment time of max cycles occurred between the request and the following acknowledgment. (max_check = 1) or (max > 0) Req asserts for more than max cycles without an acknowledgment. If max and min are specified, max must be > min or a compile error occurs and the checker is not compiled. MIN The number of cycles that occurred between a request and the following acknowledgment is less than the specified minimum acknowledgment time of min cycles. min > 0 Ack asserts to acknowledge a request that is pending less than min cycles. REQ_UNTIL_ACK A request deasserted before the acknowledgment was received. req_until_ack = 1 Req deasserts but the request is not acknowledged. ACK_ASSERT_TO_ REQ_DEASSERT_MAX The request continued to be asserted after the specified maximum of ack_assert_to_req_deassert_max cycles after ack asserted. ack_assert_to_req_deassert_max_check = 1 Ack asserts to acknowledge a request but then req remains asserted for longer than ack_assert_to_req_deassert_max cycles. ACK_ASSERT_TO_ REQ_DEASSERT_MIN The request deasserted earlier than the specified minimum of ack_assert_to_req_deassert_min cycles after ack asserted. (new_req_after_ack = 0) and (req_until_ack = 1) and (ack_assert_to_req_deassert_min > 0) Ack asserts to acknowledge a request but then req deasserts before ack_assert_to_req_deassert_min cycles. Questa Verification Library Checkers Data Book, 2010.1a 245 QVL Checker Data Sheets qvl_req_ack REQ_DEASSERT_TO_ ACK_DEASSERT_MAX The acknowledgment continued to be asserted after the specified maximum of req_deassert_to_ack_deassert_max cycles after req deasserted. req_deassert_to_ack_deassert_max_check = 1 Req deasserts when its request is acknowledged, but then ack remains asserted for longer than req_deassert_to_ack_deassert_max cycles. REQ_DEASSERT_TO_ ACK_DEASSERT_MIN The acknowledgement deasserted earlier than the specified minimum of req_deassert_to_ack_deassert_min cycles after req deasserted. (new_req_after_ack = 0) and (req_until_ack = 1) and (req_deassert_to_ack_deassert_min > 0) Req deasserts when its request is acknowledged, but then ack deasserts before req_deassert_to_ack_deassert_min cycles. ACK_UNTIL_REQ_DEASSERT An acknowledgement deasserted before the request deasserted. (ack_until_req_deassert = 1) and (req_until_ack = 1) Ack deasserts, but req is still asserted. ACK_DEASSERT_TO_ REQ_DEASSERT_MAX The request continued to be asserted after the specified maximum of ack_deassert_to_req_deassert_max cycles after ack deasserted. ack_deassert_to_req_deassert_max_check = 1 Ack deasserts but then req remains asserted for longer than ack_assert_to_req_deassert_max cycles. ACK_DEASSERT_TO_ REQ_DEASSERT_MIN The request deasserted earlier than the specified minimum of ack_deassert_to_req_deassert_min cycles after ack deasserted. (ack_deassert_to_req_deassert_min > 0) and (ack_assert_to_req_deassert_min = 0) and (req_deassert_to_ack_deassert = 0) and (ack_until_req_deassert = 0) Ack deasserts but then req deasserts before ack_assert_to_req_deassert_min cycles. 246 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_req_ack MAX_ACK The acknowledgement asserted for more than the specified maximum time of max_ack cycles. max_ack > 0 Ack is asserted continuously for more than max_ack cycles. Cover Points Corner Cases Requests Number of requests. Acknowledgments Number of acknowledgments. Request Asserted for Minimum Cycles Number of times ack asserted exactly min cycles after a request initiated. Request Asserted for Maximum Cycles Number of times ack asserted exactly max cycles after a request initiated. Reported only if max_check = 1. Acknowledgement Asserted for Maximum Cycles Number of times ack was asserted for max_ack cycles. Reported only if max_ack > 0. Statistics Number of Cycles Request and Acknowledgement Asserted Together Number of cycles req and ack asserted together. Number of Cycles Request and Acknowledgement Deasserted Together Number of cycles req and ack deasserted together. Reported only if ack_until_req_deassert = 1. See also qvl_arbiter Questa Verification Library Checkers Data Book, 2010.1a 247 QVL Checker Data Sheets qvl_resource_share qvl_resource_share Ensures that accesses to a resource do not conflict and that the accesses occur in specified time windows. Parameters: severity_level property_type msg coverage_level resource_enables [resource_count-1:0] min_idle[31:0] max_idle[31:0] qvl_resource_share Class: n-cycle assertion min_hold[31:0] max_hold[31:0] clk reset_n resource_count min_idle_check max_idle_check min_hold_check max_hold_check Application: control and interface active Syntax qvl_resource_share [#(severity_level, property_type, msg, coverage_level, resource_count, min_idle_check, max_idle_check, min_hold_check, max_hold_check)] instance_name (clk, reset_n, active, resource_enables, min_idle, max_idle, min_hold, max_hold); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. resource_count Number of bits in resource_enables. Default : 1. min_idle_check Whether or not to perform min_idle checks. min_idle_check = 0 (Default) Turns off the min_idle check. min_idle_check = 1 Turns on the min_idle check. max_idle_check Whether or not to perform max_idle checks. max_idle_check = 0 (Default) Turns off the max_idle check. min_idle_check = 1 Turns on the max_idle check. 248 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_resource_share min_hold_check Whether or not to perform min_hold checks. min_hold_check = 0 (Default) Turns off the min_hold check. min_hold_check = 1 Turns on the min_hold check. max_hold_check Whether or not to perform max_hold checks. max_hold_check = 0 (Default) Turns off the max_hold check. min_hold_check = 1 Turns on the max_hold check. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. resource_enables [resource_count-1:0] Concatenated list of resource enable signals. min_idle[31:0] Minimum number of consecutive clock cycles the resource must be idle (min_idle_check = 0). max_idle[31:0] Maximum number of consecutive clock cycles the resource can be idle (max_idle_check = 0). min_hold[31:0] Minimum number of consecutive clock cycles the resource must be held (min_hold_check = 0). max_hold[31:0] Maximum number of consecutive clock cycles the resource can be held (max_hold_check = 0). Description The qvl_resource_share assertion ensures a resource is accessed without conflict. The checker evaluates resource_enables at each rising edge of clk whenever active is TRUE. If resource_enables has 2 or more TRUE bits, a resource_conflict check violation occurs. The checker has two optional checks (min_hold and max_hold) that verify that the duration of each resource hold pulse is within the range from min_hold cycles to max_hold cycles. Similarly, the checker has two optional checks (min_idle and max_idle) that verify that the period between consecutive access pulses (i.e., when no bits of resource_enables are TRUE) is within the range from min_idle cycles to max_idle cycles. The min_hold, max_hold, min_idle and max_idle checks are dynamic: each check uses the current port value of the associated limit to determine whether or not the check violation occurred. Questa Verification Library Checkers Data Book, 2010.1a 249 QVL Checker Data Sheets qvl_resource_share Uses: Resource sharing, arbiter, memory interface. Assertion Checks RESOURCE_CONFLICT More than one requester accessed the resource in the same cycle. Two bits of resource_enables were TRUE in the current clock cycle. MIN_IDLE Resource was accessed before the minimum idle time expired. min_idle_check = 1 A resource_enables bit was TRUE in the current clock cycle, but a resource_enables bit was also TRUE in one of the min_idle previous cycles (or the checker was reset less than min_idle cycles before the current cycle). MAX_IDLE Resource was not accessed before the maximum idle time expired. max_idle_check = 1 All resource_enables bits were FALSE in the current clock cycle, but all resource_enables bits also were FALSE in all of the max_idle previous cycles. MIN_HOLD Resource was not held for the minimum hold time. min_hold_check = 1 A resource_enables bit was TRUE in the previous clock cycle and FALSE in the current cycle, but was also FALSE in one of the min_hold previous cycles (or the checker was reset less than min_hold cycles before the current cycle). MAX_HOLD Resource was held after the maximum hold time expired. max_hold_check = 1 A resource_enable bit was TRUE in the current clock cycle, but was also TRUE for the max_hold previous cycles. Cover Points Corner Cases All Resources Enabled If non-zero, every resource enable signal has asserted. Max Idle Count Number of times access to the resource was separated by exactly max_idle clock cycles. 250 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_resource_share Min Idle Count Number of times access to the resource was separated by exactly min_idle clock cycles. Max Hold Count Number of times the resource was held for exactly max_hold clock cycles. Min Hold Count Number of times the resource was held for exactly min_hold clock cycles. Statistics Resource Accessed Count Number of times the resource was accessed. See also qvl_arbiter qvl_bus_driver Examples qvl_resource_share #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("Resource Share Violation"), .coverage_level(‘QVL_COVER_ALL), .resource_count(2)) QVL_RESOURCE_SHARE ( .clk(clock), .reset_n(1’b1), .active(1’b1), .resource_enables({wr1,wr2}), .min_idle(1), .max_idle(1), .min_hold(1), .max_hold(1)); Checks that two writes do not assert at the same time. Questa Verification Library Checkers Data Book, 2010.1a 251 QVL Checker Data Sheets qvl_resource_share qvl_resource_share #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("Resource Share Violation"), .coverage_level(‘QVL_COVER_ALL), .resource_count(2), .min_idle_check(1)) QVL_RESOURCE_SHARE ( .clk(clock), .reset_n(1’b1), .active(1’b1), .resource_enables({wr1,wr2}), .min_idle(2), .max_idle(1), .min_hold(1), .max_hold(1)); Checks that any two consecutive write accesses are apart by at least two clocks. qvl_resource_share #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("Resource Share Violation"), .coverage_level(‘QVL_COVER_ALL), .resource_count(2), .min_idle_check(1), .max_idle_check(1)) QVL_RESOURCE_SHARE ( .clk(clock), .reset_n(1’b1), .active(1’b1), .resource_enables({wr1,wr2}), .min_idle(2), .max_idle(4), .min_hold(1), .max_hold(1)); Checks that the idle time between any two consecutive write accesses is not more that four clock cycles. 252 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_resource_share qvl_resource_share #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("Resource Share Violation"), .coverage_level(‘QVL_COVER_ALL), .resource_count(2), .min_hold_check(1)) QVL_RESOURCE_SHARE ( .clk(clock), .reset_n(1’b1), .active(1’b1), .resource_enables({wr1,wr2}), .min_idle(1), .max_idle(1), .min_hold(2), .max_hold(1)); Checks that the minimum pulse width for the write signal is two clock cycles. qvl_resource_share #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("Resource Share Violation"), .coverage_level(‘QVL_COVER_ALL), .resource_count(2), .max_hold_check(1)) QVL_RESOURCE_SHARE ( .clk(clock), .reset_n(1’b1), .active(1’b1), .resource_enables({wr1,wr2}), .min_idle(1), .max_idle(1), .min_hold(1), .max_hold(3)); Checks that the maximum pulse width for the write signal is three clock cycles. Questa Verification Library Checkers Data Book, 2010.1a 253 QVL Checker Data Sheets qvl_same qvl_same Ensures that all vectors in a list have the same value. test_expr[width*count-1:0] qvl_same clk reset_n active Parameters: severity_level property_type msg coverage_level width count match_xz Class: single-cycle assertion Application: user Syntax qvl_same [#(severity_level, property_type, msg, coverage_level, width, count, match_xz)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE width Width (number of bits) of each vector in test_expr. Default : 1. count Number of vectors in test_expr. The count must be > 1. Default: 2. match_xz How to handle X and Z bits in test_expr. (Default) Checker is inactive if test_expr has an X or Z bit. match_xz = 1 Checker is active when test_expr has X or Z bits. match_xz = 0 Ports clk Clock event for the assertion. The checker samples the test_expr on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. 254 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_same test_expr [width*count-1:0] Concatenated list of vectors to check. Vectors should be zeroextended so all vectors have the same width. Description The qvl_same checker ensures that all vectors in a list have the same values. The checker evaluates the expression test_expr at each rising edge of clk whenever active is TRUE. By default, if the value of test_expr has any bits that are X or Z, the checker treats the cycle as an inactive cycle. Otherwise, the value of test_expr is split into count vectors and if the vectors are not all equal, a same check violation occurs. Setting the match_xz parameter to 1 configures the checker to be active in cycles where test_expr has X or Z bits. A same violation occurs if all vectors of test_expr are not the same. Uses: Design partitioning, signal splitting, datapath, gate-to-layout linking. Assertion Checks SAME Not all vectors in the expression had the same value. =0 Value of test_expr contained no X or Z bits, but the vectors in test_expr were not all the same. match_xz = 1 The vectors in test_expr were not all the same. match_xz Cover Points Corner Cases Each Bit Set to Zero If non-zero, the low-order vectors of test_expr had a value of all 0 bits. Each Bit Set to One If non-zero, the low-order word of test_expr had a value of all 1 bits. Statistics Evaluations Number of cycles the checker was active. See also qvl_same_bit Questa Verification Library Checkers Data Book, 2010.1a qvl_same_word 255 QVL Checker Data Sheets qvl_same Examples reg [3:0] a[1:0], b[1:0]; qvl_same #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(8)) S1 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr({a[1],a[0],b[1],b[0]})); Checks that (a[1],a[0]) == (b[1],b[0]). To make the comparison, the elements of each vector are concatenated and the resulting words are compared. reg [3:0] a, b[1:0]; qvl_same #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(8)) S2 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr({4’b0,a,b[1],b[0]})); Checks that (4 b0,a) == (b[1],b[0]). The variable a is zero extended so the concatenated word matches the width of (b[1],b[0]). reg [2:0] a, b; qvl_same #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(3), .count(2), .match_xz(1)) S3 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr({a,b})); Checks that a === b, even if a and b have X and Z values. 256 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_same logic [2:0] [1:0] a, b, c; qvl_same #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(6), .count(3)) S4 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr({a,b,c})); Checks that the 6-bit values of a, b and c are the same (that is, a == b == c). logic [2:0] [1:0] a, b, c [1:0]; qvl_same #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(12), .count(3)) S5 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr({6’b0,a,6’b0,b,c[1],c[0]})); After zero-extending a and b from 6 to 12 bits to match the packed c[1:0], checks that (6’b0,a) == (6’b0,b) == (c[1],c[0]). logic [2:0] array1[1:0][1:0] array2[2:0][1:0] qvl_same #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width(16)) S6 ( .clk(clk), .reset_n(1’b1), .active(1’b1), .test_expr({3‘b000,3‘b000,array1[1][1],array1[1][0],array1[0][1], array1[0][0],array2[2][1],array2[2][0],array2[1][1], array2[1][0],array2[0][1],array2[0][0]})); Checks that : {3‘b000,3‘b000,array1[1][1],array1[1][0],array1[0][1],array1[0][0]} == {array2[2][1],array2[2][0],array2[1][1],array2[1][0], array2[0][1],array2[0][0]} Questa Verification Library Checkers Data Book, 2010.1a 257 QVL Checker Data Sheets qvl_same_bit qvl_same_bit Ensures that all bits of an expression have the same value. Parameters: severity_level property_type msg test_expr[width-1:0] qvl_same_bit clk reset_n active coverage_level width match_xz Class: single-cycle assertion Application: user Syntax qvl_same_bit [# (severity_level, property_type, msg, coverage_level, width, match_xz)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width Width of test_expr. The width must be > 1. Default: 2. match_xz How to handle X and Z bits in test_expr. (Default) Checker is inactive if test_expr has an X or Z bit. match_xz = 1 Checker is active when test_expr has X or Z bits. match_xz = 0 Ports clk Clock event for the assertion. The checker samples test_expr on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. test_expr[width-1:0] Expression or variable to check. 258 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_same_bit Description The qvl_same_bit checker ensures an expression has all bits the same. The checker evaluates the expression test_expr at each rising edge of clk whenever active is TRUE. By default, if the value of test_expr has any bits that are X or Z, the checker treats the cycle as an inactive cycle. Otherwise, if the bits are not all 0 or all 1, a same_bit check violation occurs. Setting the match_xz parameter to 1 configures the checker to be active in cycles where test_expr has X or Z bits. A same_bit violation occurs if all bits of test_expr are not the same. Uses: Design partitioning, signal splitting, datapath, gate-to-layout linking. Assertion Checks SAME_BIT Not all bits of the expression had the same value. =0 Value of test_expr contained no X or Z bits, but test_expr contained both a 0 bit and a 1 bit. match_xz = 1 Value of test_expr contained two bits with different values. match_xz Cover Points Corner Cases All Bits Zero Number of cycles all test_expr bits were 0. All Bits One Number of cycles all test_expr bits were 1. Statistics Evaluations Number of cycles the checker was active. See also qvl_same Questa Verification Library Checkers Data Book, 2010.1a qvl_same_word 259 QVL Checker Data Sheets qvl_same_bit Examples reg [3 : 0] a; qvl_same_bit #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_bit_violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4)) U0 ( .clk(clock), .active(active), .reset_n(reset), .test_expr(a)); Checks that all four bits of ‘a’ are the same. reg [3:0] b; qvl_same_bit #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_bit_violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .match_xz(1)) U1 ( .clk(clock), .active(active), .reset_n(reset), .test_expr(b)); Checks that all bits of ‘b’ are the same (even if ‘b’ has X or Z bits). reg [3:0]a; reg [3:0]b; wire [3:0] w; assign w = a & b; qvl_same_bit #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_bit_violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4)) U2 ( .clk(clock), .active(active), .reset_n(reset), .test_expr(w)); Checks that all four bits of ‘w’ are the same. 260 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_same_bit reg [3:0] a; reg [3:0]b; wire [3:0] w; assign w = a & b; qvl_same_bit #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_bit_violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .match_xz(1)) U3 ( .clk(clock), .active(active), .reset_n(reset), .test_expr(w)); Checks that all four bits of ‘w’ are the same (even if ‘w’ has X or Z bits). reg [3:0] a[2:0]; qvl_same_bit #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_bit_violation : "), .coverage_level(‘QVL_COVER_ALL), .width(12), .match_xz(1)) U4 ( .clk(clock), .active(active), .reset_n(reset), .test_expr({a[2], a[1], a[0]})); Checks that all bits of ‘a’ have the same value (even if ‘a’ has X or Z bits). logic [3:0] a [7:0]; qvl_same_bit #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_bit_violation : "), .coverage_level(‘QVL_COVER_ALL), .width(32)) U5 ( .clk(clock), .active(active), .reset_n(reset), .test_expr({a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]})); Checks that all bits of ‘a’ are the same. Questa Verification Library Checkers Data Book, 2010.1a 261 QVL Checker Data Sheets qvl_same_word qvl_same_word Ensures that all words in a list have the same value. test_expr[width*count-1:0] qvl_same_word clk reset_n active Parameters: severity_level property_type msg coverage_level width count match_xz Class: single-cycle assertion Application: user Syntax qvl_same_word [#(severity_level, property_type, msg, coverage_level, width, count, match_xz)] instance_name (clk, reset_n, active, test_expr); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE width Width of each word in test_expr. Default : 1. count Number of words in test_expr. The count must be > 1. Default: 2. match_xz How to handle X and Z bits in test_expr. (Default) Checker is inactive if test_expr has an X or Z bit. match_xz = 1 Checker is active when test_expr has X or Z bits. match_xz = 0 Ports clk Clock event for the assertion. The checker samples the test_expr on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. 262 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_same_word test_expr [width*count-1:0] Concatenated list of words to check. Description The qvl_same_word checker ensures that all words in a list have the same values. The checker evaluates the expression test_expr at each rising edge of clk whenever active is TRUE. By default, if the value of test_expr has any bits that are X or Z, the checker treats the cycle as an inactive cycle. Otherwise, the value of test_expr is split into count words and if the words are not all equal, a same_word check violation occurs. Setting the match_xz parameter to 1 configures the checker to be active in cycles where test_expr has X or Z bits. A same_word violation occurs if all words of test_expr are not the same. Uses: Design partitioning, signal splitting, datapath, gate-to-layout linking. Assertion Checks SAME_WORD Not all words in the expression had the same value. =0 Value of test_expr contained no X or Z bits, but the words in test_expr were not all the same. match_xz = 1 The words in test_expr were not all the same. match_xz Cover Points Corner Cases Each Bit Set to Zero If non-zero, the low-order word of test_expr had a value of all 0’s. Each Bit Set to One If non-zero, the low-order word of test_expr had a value of all 1’s. Statistics Evaluations Number of cycles the checker was active. See also qvl_same Questa Verification Library Checkers Data Book, 2010.1a qvl_same_bit 263 QVL Checker Data Sheets qvl_same_word Examples reg a, b, c; qvl_same_word #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_word Violation : "), .coverage_level(‘QVL_COVER_ALL), .count(3)) compare_bits ( .clk(clk), .active(active), .reset_n(reset), .test_expr({a, b, c})); Checks that the single bit signals a, b and c have the same values. reg [3:0] a, b, c; qvl_same_word #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_word Violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .count(3)) compare_words ( .clk(clk), .active(active), .reset_n(reset), .test_expr({a, b, c})); Checks that the 4 bit signals a, b and c have the same values. reg [3:0] a, b[1:0]; qvl_same_word #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_word Violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .count(3)) compare_words ( .clk(clk), .active(active), .reset_n(reset), .test_expr({a, b[1], b[0]})); Checks that 4-bit variables a, b[1] and b[0] have the same value. 264 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_same_word reg [3:0] a, b[1:0]; qvl_same_word #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_word Violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .count(3), .match_xz(1)) compare_words ( .clk(clk), .active(active), .reset_n(reset), .test_expr({a, b[1], b[0]})); Checks that 4-bit variables a, b[1] and b[0] have the same value (even if a or b has X or Z bits). reg [2:0] a; reg [3:0] b[1:0]; qvl_same_word #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_word Violation : "), .coverage_level(‘QVL_COVER_ALL), .width(4), .count(3)) compare_words ( .clk(clk), .active(active), .reset_n(reset), .test_expr({{1’b0,a}, b[1], b[0]})); Checks that {1 b0,a} == b[1] == b[0]. logic [3:0] [4:2] a, b, c; qvl_same_word #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_same_word Violation : "), .coverage_level(‘QVL_COVER_ALL), .width(12), .count(3)) compare_words ( .clk(clk), .active(active), .reset_n(reset), .test_expr({a, b, c})); Checks that the 12-bit values of a, b and c are the same (that is, a == b == c). Questa Verification Library Checkers Data Book, 2010.1a 265 QVL Checker Data Sheets qvl_scoreboard qvl_scoreboard Ensures that all instances of IDs transmitted match the instances of IDs received; that no more than a specified number of IDs are pending at any time; and that each ID must be pending for more than a specified minimum number of clock cycles and less than a specified maximum number of clock cycles. tx tx_id[width-1:0] tx_count[count_width-1:0] rx rx_id[width-1:0] rx_count[count_width-1:0] qvl_scoreboard flush flush_id[width-1:0] flush_count[count_width-1:0] pre_rx_ids [pre_rx_ids_count*width-1:0] pre_rx_counts [pre_rx_ids_count * pre_rx_count_width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width count_width min max max_ids max_count_ per_id flush_enable flush_count_enable pre_rx_ids_count pre_rx_count_width allow_simultaneous_rx_tx allow_simultaneous_ flush_rx allow_partial disallow_rx_when_full known_ids_check known_flush_check Class: event-bounded assertion Application: control and interface Syntax qvl_scoreboard [#(severity_level, property_type, msg, coverage_level, width, count_width, min, max, max_ids, max_count_per_id, flush_enable, flush_count_enable, pre_rx_ids_count, pre_rx_count_width, allow_simultaneous_rx_tx, allow_simultaneous_flush_rx, allow_partial, disallow_rx_when_full, known_ids_check, known_flush_check)] instance_name (clk, reset_n, active, rx, rx_id, rx_count, tx, tx_id, tx_count, flush, flush_id, flush_count, pre_rx_ids, pre_rx_counts); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL width Width of rx_id, tx_id, flush_id and each item in pre_rx_id. Default: 6. 266 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_scoreboard count_width Width of rx_count, tx_count and flush_count. Default 2. min Minimum number of clock cycles an ID instance must be pending. min = 0 (Default) Turns off the min check. min > 0 Turns on the min check. max Maximum number of clock cycles an ID instance can be pending. max = 0 (Default) Turns off the max check. max > 0 Turns on the max check. If min is also specified, max must be ≥ min. max_ids Value to use for the max_ids check. max_ids = 0 Turns off the max_ids check. (Default: max_ids = 16) Turns on the max_ids check. To minimize simulation overhead, set max_ids to the maximum expected value and no more (even if the maximum is less than 16). max_ids > 0 max_count_per_id Count to use for the max_count_per_id check. max_count_per_id = 0 Turns off the max_count_per_id check. (Default: max_count_per_id = 8) Turns on the max_count_per_id check. To minimize simulation overhead, set max_count_per_id to the maximum expected value and no more (even if the maximum is less than 8). max_count_per_id > 0 flush_enable Whether or not IDs can be flushed. flush_enable = 0 (Default) IDs cannot be flushed (flush, flush_id, flush_count, flush_count_enable and known_flush_check are ignored). flush_enable = 1 IDs can be flushed. flush_count_enable How to handle multiple instances of the same ID when the ID is flushed. flush_count_enable = 0 (Default) All instances of the ID are flushed (flush_count is ignored). flush_count_enable = 1 Only flush_count instances of the ID are flushed. pre_rx_ids_count Number of unique IDs to assume are pending on reset. The pre_rx_ids port is a concatenated list of IDs to add to the pending IDs list. Default: 0 (no IDs are pending). pre_rx_count_width Width of each count in the pre_rx_count port. Default 1. Questa Verification Library Checkers Data Book, 2010.1a 267 QVL Checker Data Sheets qvl_scoreboard allow_simultaneous_ rx_tx How the known_ids check handles receive and transmit transactions with the same ID that occur in the same cycle. allow_simultaneous_rx_tx = 0 (Default) Transmit ID is matched only with previously pending IDs. allow_simultaneous_rx_tx = 1 Transmit ID is first matched with previously pending IDs, then is matched with the current receive ID. allow_simultaneous_ flush_rx How to handle receive and flush transactions with the same ID that occur in the same cycle. allow_simultaneous_flush_rx = 0 (Default) Instances of the receive ID cannot be flushed. allow_simultaneous_flush_rx = 1 Instances of the receive ID can be flushed. allow_partial How to handle the current receive transaction when a max_count_per_id check violation occurs. allow_partial = 0 (Default) The current receive transaction is ignored. No instances of the current receive ID are added to the pending IDs list. allow_partial = 1 The current receive transaction is partially fulfilled. Sufficient instances of the current receive ID are added to the pending IDs list to make the pending count for the ID equal to max_count_per_id. disallow_rx_when_full How the max_count_per_id check handles receive and transmit transactions with the same ID that occur in the same cycle. disallow_rx_when_full = 0 (Default) Transmit IDs are taken from the previously pending IDs, then the receive IDs are made pending. disallow_rx_when_full = 1 Receive IDs are first considered pending, so, if the max_count_per_id is exceeded for the ID, a max_count_per_id check violation occurs. known_ids_check Whether or not to perform known_ids checks. known_ids_check = 0 Turns off the known_ids check. (Default) Turns on the known_ids check. known_ids_check = 1 known_flush_check Whether or not to perform known flush_ids checks. known_flush_check = 0 (Default) Turns off the known_flush check. known_flush_check = 1 Turns on the known_flush check. 268 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_scoreboard Ports clk Clock event for the assertion. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. rx Signal that indicates rx_id is valid. rx_id[width-1:0] Register or wire containing the receive ID. rx_count [count_width-1:0] Register or wire containing the number of instances of rx_id to make pending. tx Signal that indicates tx_id is valid. tx_id[width-1:0] Register or wire containing the transmit ID. tx_count [count_width-1:0] Register or wire containing the number of instances of tx_id to remove from the pending IDs list. flush Signal that indicates flush_id is valid. flush_id [width-1:0] Register or wire containing the ID to flush. flush_count [count_width-1:0] Register or wire containing the number of instances of flush_id to flush (if flush_count_enable is 1). pre_rx_ids [(pre_rx_ids_count * width)-1:0] Concatenated list of IDs to assume are pending on reset. pre_rx_ids_count = 0 No IDs are pending. The width of pre_rx_ids should be width, however, no values from pre_rx_ids are used. pre_rx_ids_count > 0 The value of pre_rx_ids is a concatenated list of unique IDs to assume are pending on reset (or simulation start). pre_rx_counts [(pre_rx_ids_count *pre_rx_count_width) -1:0] Concatenated list of counts of the corresponding pre_rx_ids IDs to assume are pending on reset. pre_rx_ids_count = 0 No IDs are pending. The width of pre_rx_counts should be 1, however, pre_rx_counts is ignored. pre_rx_ids_count > 0 Value of pre_rx_counts is a concatenated list of pre_rx_ids_count counts, each count being pre_rx_count_width wide. The counts in pre_rx_counts correspond to the IDs in pre_rx_ids. Each count specifies the number of instances of its corresponding ID to assume are pending on reset. Questa Verification Library Checkers Data Book, 2010.1a 269 QVL Checker Data Sheets qvl_scoreboard Description The qvl_scoreboard checker ensures IDs are received and transmitted properly. The checker evaluates tx and rx signals at each rising edge of clk whenever active is TRUE. By default, the following verification is performed: 1. If tx is TRUE, an ID transmit is assumed. a. Tx_id_count instances of tx_id are removed from the list of pending IDs. 2. If rx is TRUE, an ID receive is assumed. a. If 16 unique IDs are pending and rx_id is not one of them, a max_ids check violation occurs. The receive transaction is ignored. b. If the number of pending instances of rx_id plus rx_id_count is larger than 8, a max_count_per_id check violation occurs. The receive transaction is ignored. c. Otherwise, rx_id_count instances of rx_id are added to the list of pending IDs. The default operation can be adjusted in the following ways: • If the max_ids parameter is specified, the maximum number of unique pending IDs is changed from 16. Setting this value to the smallest viable value is recommended • If the max_count_per_id parameter is specified, the maximum number of pending ID instances per unique ID is changed from 8. Setting this value to the smallest viable value is recommended • If the allow_partial parameter is 1, when a max_count_per_id violation occurs, instances of rx_id are made pending (up to the max_count_per_id limit). • If the disallow_rx_when_full parameter is 1, the max_count_per_id check is modified to ignore instances of the receive ID that are transmitted in the current cycle. Here, a check violation occurs when max_count_per_id is exceeded even if the transmit transaction reduced the pending count for the ID to max_count_per_id or below. The following additional checker functionality is available: • Pending ID flushing. Set the flush_enable parameter to 1 to model pending ID flushing. When the flush signal is sampled TRUE, all instances of flush_id are removed from the pending IDs. If allow_simultaneous_flush_rx is 1, this includes the current receive ID if it equals flush_id. If flushing is enabled, set the flush_count_enable to 1 to allow partial flushing of IDs. Here, only flush_count instances of the flushed ID are removed from the pending IDs. 270 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_scoreboard • Preload ID instances on reset. Setting pre_rx_ids_count to non-zero causes the checker to preload pre_rx_ids_count unique pending IDs on reset (read from pre_rx_ids). The counts for the ID instances are taken from pre_rx_counts. The following additional checks are available: • Known_ids check verifies that each transmitted ID instance was actually pending. • Known_flush check verifies that each flushed ID instance was actually pending. • Min check verifies that each ID instance is pending for at least min cycles. • Max check verifies that each ID instance is pending for at most max cycles. Uses: FIFO, queue, stack, LIFO, handshake, linked list, req_ack, request, acknowledge, ready, take, hold, wait, bridge, transactions, switch, packet, IDs, tokens, interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (IOs), pipeline, dataflow, datapath, memory, register array, temporal, time, window. Assertion Checks MAX_IDS New ID was received when the maximum number of unique IDs were pending. = 0) The maximum number of unique IDs were pending and another ID was received without a simultaneous transmit or flush that removed all instances of an ID from the pending IDs list. (max_ids > 0) and (disallow_rx_when_full = 1) The maximum number of unique IDs were pending and a new ID was received. (max_ids > 0) and (disallow_rx_when_full When a max_ids violation occurs, the receive ID is ignored (i.e., not added to the pending IDs list). If the ID subsequently is transmitted (or flushed), a known_ids (or known_flush) check violation might occur. Questa Verification Library Checkers Data Book, 2010.1a 271 QVL Checker Data Sheets qvl_scoreboard MAX_COUNT_PER_ID ID was received that would make the pending ID count for the ID exceed the maximum count per ID value. (max_count_per_id > 0) and (disallow_rx_when_full = 0) For the receive ID: the current pending count plus the receive count minus the transmit count (if any) minus the flush count (if any) is greater than max_count_per_id. (max_count_per_id > 0) and (disallow_rx_when_full = 1) For the receive ID: the current pending count plus the receive count is greater than max_count_per_id. How the checker handles a max_count_per_id violation depends on the allow_partial parameter. allow_partial = 0 The current receive is ignored. No instances of the current receive ID are added to the pending IDs list. allow_partial = 1 The current receive is partially fulfilled. Sufficient instances of the current receive ID are added to the pending IDs list to make the pending count for the ID equal to max_count_per_id. KNOWN_IDS The number of instances of the transmit ID exceeded the count of the ID’s pending instances. (known_ids_check = 1) and (allow_simultaneous_rx_tx = 0) Transmit ID does not match a pending ID or the transmit ID count is > count of the current pending count for the ID. (known_ids_check = 1) and (allow_simultaneous_rx_tx = 1) Transmit ID does not match a pending ID (or the receive ID, if enabled) or the transmit ID count is > count of the current pending count for the ID (plus the receive count, if enabled and the receive ID is the same as the transmit ID). 272 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_scoreboard KNOWN_FLUSH The number of instances of the flush ID exceeded the count of the ID’s pending instances. (known_flush_check = 1) and (allow_simultaneous_flush_rx = 0) Flush ID does not match any pending ID or the flush ID count is > count of the current pending count for the ID. (known_flush_check = 1) and (allow_simultaneous_flush_rx = 1) Flush ID does not match an pending ID (or the receive ID, if enabled) or the flush ID count is > count of the current pending count for the ID (plus the receive count, if enabled and the receive ID is the same as the flush ID). MIN ID instance was transmitted before the minimum allowed number of cycles. min > 0 The transmitted ID instance was not pending for at least min cycles. MAX ID instance was pending longer than the maximum allowed number of cycles. max > 0 Max cycles have transpired from the cycle in which the ID instance was received to the current cycle, but the ID instance was not transmitted or flushed. Cover Points Corner Cases IDs Received Number of IDs received. IDs Transmitted Number of IDs transmitted. Pending IDs Equal Maximum IDs Number of times the number of pending IDs equalled max_ids. Meaningful only if max_ids is not 0. Pending Count Per ID Equals Maximum Count Per ID Number of times a pending ID had max_count_per_id instances pending. Meaningful only if max_count_per_id is not 0. Minimum Cycles Pending Equals Minimum. Number of cycles in which an instance of the transmit ID was transmitted exactly min cycles after it was received. Meaningful only if min is not 0. Maximum Cycles Pending Equals Maximum Number of cycles in which an instance of the transmit ID was transmitted exactly max cycles after it was received. Meaningful only if max is not 0. Questa Verification Library Checkers Data Book, 2010.1a 273 QVL Checker Data Sheets qvl_scoreboard All IDs Received If non-zero, every value of rx_id was received. Statistics IDs Flushed Number of IDs flushed. Unique IDs Received Number of unique IDs received. Notes 1. The maximum number of unique IDs pending is max_ids (default: 16). The larger the max_ids value, the greater the simulation overhead. 2. This checker matches transmit IDs against pending IDs received on previous clock cycles. If the same ID is received and transmitted in the same cycle, the checker first matches the transmit instances against instances pending from instances received in previous clock cycles. Then if more instances are transmitted than previously transmitted, the checker: • Fires the known_ids check (unless allow_simultaneous_req_ret is specified). • Matches the remaining transmit instances with the current receive instances (if allow_simultaneous_req_ret is specified). If the number of IDs or counts per ID are nearing the maximums, the same ID simultaneously received and transmitted can cause the max_ids or max_count_per_id checks to fire when the number of instances received is greater than the number of instances transmitted. 3. The flush can be used to mimic a second tx option, provided the flush_count option is used. (If the flush_count option is not specified, all instances of the ID are flushed when flush asserts.) See also qvl_bus_id 274 qvl_outstanding_id Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_scoreboard Examples qvl_scoreboard #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_SCOREBOARD Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .max_ids(1), .max_count_per_id(1)) U1 ( .clk(system_clock), .reset_n(system_reset), .active(score_active), .rx(rcv_sig), .rx_id(rcv_id), .rx_count(1’b1), .tx(xmt_sig), .tx_id(xmt_id), .tx_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_rx_ids(4’b0), .pre_rx_counts(1’b0)); Checks that pending IDs received on rcv_id are not already pending and that only received IDs are transmitted on xmt_id. qvl_scoreboard #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_SCOREBOARD Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .max_ids(12), .max_count_per_id(4)) U2 ( .clk(system_clock), .reset_n(system_reset), .active(score_active), .rx(issue_sig), .rx_id(issue_id), .rx_count(1’b1), .tx(back_sig), .tx_id(back_id), .tx_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_rx_ids(4’b0), .pre_rx_counts(1’b0)); Questa Verification Library Checkers Data Book, 2010.1a 275 QVL Checker Data Sheets qvl_scoreboard Checks that IDs are not received more than 4 times and that no more than 12 total IDs are pending. qvl_scoreboard #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_SCOREBOARD Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(3)) U3 ( .clk(system_clock), .reset_n(system_reset), .active(score_active), .rx(issue_sig), .rx_id(issue_id), .rx_count(3’b1), .tx(back_sig), .tx_id(back_id), .tx_count(data_cycles), .flush(1’b0), .flush_id(4’b0), .flush_count(3’b0), .pre_rx_ids(4’b0), .pre_rx_counts(1’b0)); Checks that when an ID is transmitted that it asserts for each data cycle. This check can be used when a single receive gets multiple transmits, each with some portion of the data. qvl_scoreboard #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_SCOREBOARD Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .min(2), .max(4)) U4 ( .clk(system_clock), .reset_n(system_reset), .active(score_active), .rx(issue_sig), .rx_id(issue_id), .rx_count(1’b1), .tx(back_sig), .tx_id(back_id), .tx_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_rx_ids(4’b0), .pre_rx_counts(1’b0)); Checks that an ID is transmitted at least two cycles and at most four cycles after it is received. 276 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_scoreboard qvl_scoreboard #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_SCOREBOARD Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(8), .count_width(1), .max_ids(8), .max_count_per_id(2), .disallow_rx_when_full(1)) U5 ( .clk(system_clock), .reset_n(system_reset), .active(score_active), .rx(rx), .rx_id(rx_id), .rx_count(1’b1), .tx(tx), .tx_id(tx_id), .tx_count(1’b1), .flush(1’b0), .flush_id(8’b0), .flush_count(1’b0), .pre_rx_ids(8’b0), .pre_rx_counts(1’b0)); Checks that at most eight unique IDs are pending, that at most two instances of a unique ID are pending and that no ID is received if max_count_per_id instances of the ID are already pending even if instances of the ID are simultaneously transmitted. qvl_scoreboard #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("QVL_SCOREBOARD Violation: "), .coverage_level(‘QVL_COVER_ALL), .width(4), .count_width(1), .max_ids(0), .max_count_per_id(0), .pre_rx_ids_count(6), .pre_rx_count_width(4)) U6 ( .clk(system_clock), .reset_n(system_reset), .active(score_active), .rx(rx), .rx_id(rx_id), .rx_count(1’b1), .tx(tx), .tx_id(tx_id), .tx_count(1’b1), .flush(1’b0), .flush_id(4’b0), .flush_count(1’b0), .pre_rx_ids({4’d15, 4’d14, 4’d13, 4’d12, 4’d11, 4’d10}), .pre_rx_counts({4’d8, 4’d8, 4’d7, 4’d6, 4’d5, 4’d4})); Questa Verification Library Checkers Data Book, 2010.1a 277 QVL Checker Data Sheets qvl_scoreboard Checks that only received IDs are transmitted on tx_id. Here list of IDs to be considered pending prior to beginning simulation is specified along with count for each id. 278 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_serial_to_parallel qvl_serial_to_parallel Ensures that a serial-to-parallel converter behaves properly. in_clk in_reset_n in_active active load read qvl_serial_to_parallel msb in_data[width-1:0] out_data out_clk out_reset_n out_active Parameters: severity_level property_type msg coverage_level width latency sync_delay msb_convert_check reversal_check read_check Class: n-cycle assertion Application: datapath Syntax qvl_serial_to_parallel [#(severity_level, property_type, msg, coverage_level, width, latency, sync_delay, msb_convert_check, reversal_check, read_check)] instance_name (in_clk, out_clk, in_reset_n, out_reset_n, active, in_active, out_active, load, read, msb, in_data, out_data); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width Width of out_data. Default : 2. latency Latency for parallel data in out_clk cycles. latency = 0 (Default) Out_data is valid at the current, or next, active edge of out_clk once a complete data item is loaded into the out_clk domain parallel data register. latency > 0 Out_data is valid latency out_clk cycles after a complete data item is loaded into the out_clk domain parallel data register. Questa Verification Library Checkers Data Book, 2010.1a 279 QVL Checker Data Sheets qvl_serial_to_parallel sync_delay CDC synchronization delay for loading the out_clk domain parallel data register in out_clk cycles. sync_delay = 0 (Default) No delay is needed to synchronize the serial data with the internal parallel data register. sync_delay > 0 Serial bits are delayed sync_delay out_clk cycles between the data_in port in the in_clk domain and the parallel data register in the out_clk domain. msb_convert_check Whether or not to perform MSB_convert checks. msb_convert_check = 0 (Default) Turns off the MSB_convert check. msb_convert_check = 1 Turns on the MSB_convert check. reversal_check Whether or not to perform reversal checks. hold_check = 0 (Default) Turns off the reversal check. hold_check = 1 Turns on the reversal check. read_check Whether or not to perform read checks. read_check = 0 (Default) Turns off the read check. read_check = 1 Turns on the read check. Ports in_clk Clock event for the serial data (input) domain. The checker samples the serial data inputs on the rising edge of in_clk. out_clk Clock event for the parallel data (output) domain. The checker samples the parallel data inputs on the rising edge of out_clk. in_reset_n Active low synchronous reset signal indicating the serial data domain logic is initialized. out_reset_n Active low synchronous reset signal indicating the parallel data domain logic is initialized. active Expression that indicates whether or not to check the inputs. in_active Expression that indicates whether or not to activate checks of serial data load operations (i.e., reversal and read checks). out_active Expression that indicates whether or not to activate checks of parallel data output operations (i.e., LSB_convert and MSB_convert checks). 280 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_serial_to_parallel load Load enable signal to the deserializer. When load is sampled TRUE at the active edge of in_clk, the checker reads the value of data_in and propagates the value to its internal parallel data register. msb Conversion direction signal to the deserializer. If msb is FALSE, the deserializer should perform LSB conversion (i.e., first input bit is the least-significant bit). If msb is TRUE, the deserializer should perform MSB conversion (i.e., first input bit is the mostsignificant bit). If reversal_check is 1, a reversal check violation occurs if the value of msb changes value in an in_clk cycle where load is TRUE and the parallel data item being converted is not complete. read Read signal from the deserializer indicating the value of out_data is the next parallel data item extracted from the serial data stream. in_data Serial data input to the deserializer. out_data[width-1:0] Parallel data output from the deserializer. Description The qvl_serial_to_parallel checker ensures a data deserializer/synchronizer functions correctly. A data deserializer extracts multi-bit values from bit streams. In effect, a data deserializer converts serial data into parallel data. The qvl_serial_to_parallel checker supports deserializers that pass data from one clock domain (serial data domain) to another (parallel data domain). In particular, the checker is a dual-clock checker that has separate clock, reset and activation inputs for the data input logic (in_clk, in_reset_n and in_active) and for the data output logic (out_clk, out_reset_n and out_active). The checker also has an asynchronous global activation input (active). The checker evaluates the load signal at each rising edge of in_clk whenever active and in_active are TRUE. If load is TRUE, the checker starts a data conversion cycle by reading the value of data_in. This is the first bit of a data item in the bit stream. In subsequent in_clk cycles, if load is TRUE, the checker reads the next bit of the data item from in_data (otherwise, the checker “holds” the conversion at the current bit for the cycle). For the first bit, the checker resets its parallel data register in the in_clk domain. Then as the bits of the data item are read, they are shifted onto the parallel data register: • If msb is FALSE, the first data_in bit represents the LSB bit of the parallel data register. So, bits are added to the register by right-shifting the register value and shifting new bits onto the MSB bit of the register. Questa Verification Library Checkers Data Book, 2010.1a 281 QVL Checker Data Sheets qvl_serial_to_parallel • If msb is TRUE, the first data_in bit represents the MSB bit of the parallel data register. So, bits are added to the register by right-shifting the register value and shifting new bits onto the LSB bit of the register. Once the last bit of a data item is read, the parallel register value propagates to an internal buffer representing the final collected data item. By default, if the two active clock edges are aligned when load asserts, data propagation is instantaneous; otherwise, the register value propagates to the buffer at the next active edge of out_clk. At this clock edge, if msb was FALSE when the last bit was read and the data items in the parallel data item buffer and data_out do not match, an LSB_convert violation occurs. Most deserializer implementations have delay and latency through their data paths. To accommodate these schemes, the qvl_serial_to_parallel checker can be configured as follows: • If the sync_delay parameter is > 0, the checker loads the internal parallel data buffer sync_delay out_clk cycles after the load input asserts. • If the latency parameter is > 0, the checker waits for latency out_clk cycles after a complete data is loaded into the parallel data buffer to perform the conversion checks. In addition to the LSB_convert checks, the qvl_parallel_to_serial checker can be configured to perform the following checks. • If msb_convert_check is 1, an MSB_convert check violation occurs whenever a parallel data mismatch occurs with a data item whose last collected bit was read when msb was TRUE. • If reversal_check is 1, a reversal check violation occurs if msb changes value when load is TRUE and data_in is not the first bit of a data item. • If read_check is 1, a read check violation occurs if read is FALSE (sync_delay + latency +1) out_clk cycles after the last bit of a data item is loaded. Uses: Interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (I/Os). Assertion Checks LSB_CONVERT Parallel data item did not match the serial input in LSB-first mode. At the active edge of in_clk, load was TRUE, msb was FALSE and in_data contained the last bit of a data item. But, (sync_delay + latency + 1) out_clk edges later (including the current edge, if the two clock edges align), out_data did not match the deserialized value of the input data item. 282 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_serial_to_parallel MSB_CONVERT Parallel data item did not match the serial input in MSB-first mode. msb_convert_check = 1 At the active edge of in_clk, load and msb were TRUE and in_data contained the last bit of a data item. But, (sync_delay + latency + 1) out_clk edges later (including the current edge, if the two clock edges align), out_data did not match the deserialized value of the input data item. REVERSAL Shift direction reversed while a parallel data item was being collected. reversal_check = 1 At the active edge of in_clk, load was TRUE and the value of msb had a value different from its value at the previous active in_clk edge in which load was TRUE. But, the value of in_data was not the first bit of a data item. READ Parallel data item was not read once it was converted. read_check = 1 At the active edge of out_clk, read was TRUE. But, less than sync_delay out_clk edges later (including the current edge, if the two edges of align), read was FALSE. At the active edge of in_clk, load was TRUE and in_data contained the last bit of a data item. But, (sync_delay + latency + 1) out_clk edges later (including the current edge, if the two clock edges align), read was FALSE. Uses: Interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (I/Os). Cover Points Corner Cases LSB Conversions Number of parallel data items collected by left-shifting in LSB bits. MSB Conversions Number of parallel data items collected by right-shifting in MSB bits. Meaningful only if msb_convert_check is 1. Statistics Total Conversions Number of parallel data items collected by left-shifting on the LSB bits or right-shifting on the MSB bits. Left Shifts Number of in_clk cycles load was TRUE and msb was FALSE. Right Shifts Number of in_clk cycles load and msb were TRUE. Questa Verification Library Checkers Data Book, 2010.1a 283 QVL Checker Data Sheets qvl_serial_to_parallel Hold Cycles Number of in_clk cycles load was FALSE. Read Cycles Number of out_clk cycles read asserted. See also qvl_parallel_to_serial Examples qvl_serial_to_parallel #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("StoP Violation"), .coverage_level(‘QVL_COVER_ALL), .width(3), .reversal_check(1)) QVL_StoP ( .in_clk(sclk), .out_clk(pclk), .in_reset_n(1’b1), .out_reset_n(1’b1), .active(1’b1), .in_active(1’b1), .out_active(1’b1), .load(data_valid), .msb(shift_mode), .in_data(bit_data), .out_data(word_data), .read(read_word)); Checks LSB first conversion. qvl_serial_to_parallel #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("StoP Violation"), .coverage_level(‘QVL_COVER_ALL), .width(3), .reversal_check(1), .read_check(1)) QVL_StoP ( .in_clk(sclk), .out_clk(pclk), .in_reset_n(1’b1), .out_reset_n(1’b1), .active(1’b1), .in_active(1’b1), .out_active(1’b1), .load(data_valid), .msb(shift_mode), .in_data(bit_data), .out_data(word_data), .read(read_word)); 284 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_serial_to_parallel Checks LSB first conversion and that the parallel data is read every time a complete conversion occurs. qvl_serial_to_parallel #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("StoP Violation"), .coverage_level(‘QVL_COVER_ALL), .width(3), .latency(1), .sync_delay(1), .reversal_check(1), .msb_convert_check(1), .read_check(1)) QVL_StoP ( .in_clk(sclk), .out_clk(pclk), .in_reset_n(1’b1), .out_reset_n(1’b1), .active(1’b1), .in_active(1’b1), .out_active(1’b1), .load(data_valid), .msb(shift_mode), .in_data(bit_data), .out_data(word_data), .read(read_word)); Checks LSB first and MSB first conversions with a load delay of 1 sclk cycle and an output latency of 2 sclk cycles. Questa Verification Library Checkers Data Book, 2010.1a 285 QVL Checker Data Sheets qvl_stack qvl_stack Ensures the data integrity of a stack and ensures that the stack does not overflow or underflow. push pop full empty qvl_stack push_data[width-1:0] pop_data[width-1:0] preload[preload_count*width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width depth high_water latency preload_count full_check empty_check value_check Class: event-bounded assertion Application: control Syntax qvl_stack [#(severity_level, property_type, msg, coverage_level, width, depth, high_water, latency, preload_count, full_check, empty_check, value_check)] instance_name (clk, reset_n, active, push, pop, full, empty, push_data, pop_data, preload); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL width Width of push_data and pop_data. Default: 32. depth Stack depth. The depth must be > 0 . Default : 1. latency Latency for popped data used for the value check. latency = 0 (Default) Pop_data is valid in the same cycle that pop asserts. latency > 0 Pop_data is valid latency cycles after pop asserts. preload_count Number of entries to preload onto the stack on reset. The preload port is a concatenated list of entries to be preloaded onto the stack. Default: 0 (stack empty on reset). high_water Stack high-water mark. Must be < depth. A value of 0 sets the high-water mark to depth - 1 (or 1 if depth is 1). Default: 0. 286 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_stack full_check Whether or not to perform full checks. full_check = 0 (Default) Turns off the full check. full_check = 1 Turns on the full check. empty_check Whether or not to perform empty checks. empty_check = 0 (Default) Turns off the empty check. empty_check = 1 Turns on the empty check. value_check Whether or not to perform value checks. value_check = 0 (Default) Turns off the value check. value_check = 1 Turns on the value check. Ports clk Clock event for the assertion. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. push Stack push input. When push asserts, the stack performs a push operation in that cycle. A data entry is pushed onto the stack and the stack counter increments by 1. pop Stack pop input. When pop asserts, the stack performs a pop operation. A data entry is popped from the stack (latency cycles later) and the stack counter decrements by 1. full Output status flag from the stack. full = 0 Stack not full. full = 1 Stack full. empty Output status flag from the stack. empty = 0 Stack not empty. empty = 1 Stack empty. push_data[width-1:0] Stack push data input. Contains the data entry to push when push is asserted. Questa Verification Library Checkers Data Book, 2010.1a 287 QVL Checker Data Sheets qvl_stack pop_data[width-1:0] Stack pop data output. Contains the popped data entry latency cycles after pop is asserted. preload [(preload_count * width)-1 : 0] Concatenated preload data to push onto the stack on reset. preload_count = 0 No preloading of the stack is assumed. The width of preload should be width, however, no values from preload are used. The stack is assumed to be empty on reset. preload_count > 0 Checker assumes the value of preload is a concatenated list of entries to push onto the stack on reset (or simulation start). The width of preload should be preload_count * width (preload entries are the same width). Preload values are pushed from the low order entry to the high order entry. Description The qvl_stack checker ensures a stack functions legally. A stack is a LIFO memory structure that stores and retrieves data entries based on a last-in first-out queueing protocol. The stack has configured properties specified as parameters to the qvl_fifo checker: width of the data entries (width), capacity of the stack (depth), and the high-water mark that identifies the point at which the stack is almost full (high_water). Control and data signals to and from the stack are connected to the qvl_stack checker. The checker checks push and pop at the active edge of clk each cycle the checker is active. If push is TRUE, the stack has enqueued a data entry onto the stack. If pop is TRUE, the stack is in the process of popping a data entry from the stack. The pop operation can take more than one cycle. The stack latency is the number of cycles it takes for the popped data entry to appear at the pop_data output from the stack after the cycle that pop is sampled TRUE. The checker ensures that an entry is not pushed onto the stack when it is full (push check), that an entry is not popped when the stack is empty (pop check) and that push and pop operations do not both occur in the same clock cycle. The checker can be configured to perform various additional checks such as verifying the data integrity of popped data (value check) and verifying that the stack’s full and empty status flags operate correctly (full and empty checks). The checker also can be configured to preloading entry on reset. Uses: Stack, LIFO. Assertion Checks PUSH A push operation occurred while the stack was full. Push was TRUE, but the stack contained depth entries. 288 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_stack POP A pop operation occurred while the stack was empty. Pop was TRUE, but the stack contained 0 entries. PUSH_POP Push and pop asserted together. Push and pop were both TRUE in the same cycle. FULL Stack was not full when the full signal was asserted. full_check = 1 Full was TRUE, but the stack contained fewer than depth entries. Full signal was not asserted when the stack was full. full_check = 1 Full was FALSE, but the stack contained depth entries. EMPTY Stack was not empty when the empty signal was asserted. empty_check = 1 Empty was TRUE, but the stack contained at least one entry. Empty signal was not asserted when the FIFO was empty. empty_check = 1 Empty was FALSE, but the stack contained no entries. VALUE Popped stack value did not equal the corresponding pushed value. value_check = 1 and latency = 0 Pop was TRUE, but pop_data did not equal the corresponding pushed entry. value_check = 1 and latency > 0 Pop was TRUE, but latency cycles later pop_data did not equal the corresponding pushed entry. Pop_data is compared to the top stack entry at the cycle pop was TRUE, so if push is TRUE in the latency period, the push operation is performed “after” the pop operation. This check automatically turns off if a push, pop or push_pop check violation occurs since it is no longer possible to correspond pushed with popped values. The check turns back on when the checker resets. Questa Verification Library Checkers Data Book, 2010.1a 289 QVL Checker Data Sheets qvl_stack Cover Points Corner Cases Stack Is Full Number of cycles the stack was full. Stack Is Empty Number of cycles the stack was empty. Stack Is Over High-water Mark Number of cycles the number of stack entries exceeded the highwater mark. Statistics Push Count Number of push operations. Pop Count Number of pop operations. See also qvl_fifo qvl_multi_clock_fifo qvl_multi_enq_deq_fifo Examples qvl_stack #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_stack Violation : "), .coverage_level(‘QVL_COVER_ALL), .depth(1024)) qvl_stack_instance ( .clk(clk), .active(active), .reset_n(1’b1), .push(push), .pop(pop), .full(1’b0), .empty(1’b0), .push_data(0), .pop_data(0), .preload(0)); In the above example only push, pop and push_pop checks are on (by default). 290 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_stack qvl_stack #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_stack Violation : "), .coverage_level(‘QVL_COVER_ALL), .width(3), .depth(8), .preload_count(3), .value_check(1)) qvl_stack_instance ( .clk(clk), .active(active), .reset_n(1’b1), .push(push), .pop(pop), .full(1’b0), .empty(1’b0), .push_data(push_data), .pop_data(pop_data), .preload({3’b110, 3’b101, 3’b100})); The assertion instance in the above example checks that the stack correctly pops the preloaded values pushed onto the stack after a reset. Also checks that the stack does not pop when empty and does not get a pushed value when full. qvl_stack #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg("qvl_stack Violation : "), .coverage_level(‘QVL_COVER_ALL), .width(16), .depth(2), .preload_count(1), .value_check(1)) qvl_stack_instance ( .clk(clk), .active(active), .reset_n(1’b1), .push(push), .pop(pop), .full(1’b0), .empty(1’b0), .push_data(push_data), .pop_data(pop_data), .preload(3’d4)); In the above example push, pop, push_pop and value checks are on. Questa Verification Library Checkers Data Book, 2010.1a 291 QVL Checker Data Sheets qvl_state_transition qvl_state_transition Ensures that an expression changes only to one of a specified set of values. test_expr[width-1:0] val[width-1:0] next_val[next_count*width-1:0] qvl_state_transition start condition[next_count-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width next_count start_enable condition_enable match_by_cycle is_not_check Class: event-bounded assertion Application: control Syntax qvl_state_transition [#(severity_level, property_type, msg, coverage_level, width, next_count, start_enable, condition_enable, match_by_cycle, is_not_check)] instance_name (clk, reset_n, active, test_expr, val, next_val, start, condition); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default: 1. next_count Number of next values. The next_val port is a concatenated list of next values. Default: 1. start_enable How to open an event window. start_enable = 0 (Default) Window opens when test_expr equals val (start is ignored). start_enable = 1 Window opens when test_expr equals val and start is TRUE. condition_enable Whether or not to condition the next values. condition_enable = 0 (Default) Disables the condition port. condition_enable = 1 Enables the condition port. 292 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_state_transition match_by_cycle How to close an event window. match_by_cycle = 0 (Default) Window closes in the cycle test_expr transitions to a different value. match_by_cycle = 1 Window closes 1 cycle after it opens. is_not_check Whether or not to perform is_not checks. is_not_check = 0 (Default) Turns off the is_not check and turns on the state_transition check. is_not_check = 1 Turns on the is_not check and turns off the state_transition check. Ports clk Clock event for the assertion. The assertion samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. test_expr[width-1:0] Variable or expression to check. val[width-1:0] Value to compare with test_expr. An event window is not opened unless val and test_expr have the same value. next_val [(next_count*width) -1:0] Concatenated list of next values. is_not_check = 0 Next values are valid values for test_expr when the current event window closes. is_not_check = 1 Next values are not valid values for test_expr when the current event window closes. start Signal to open an event window if test_expr matches val. start_enable = 0 Window opens for any value of start. start_enable = 1 Window opens if start is TRUE. Questa Verification Library Checkers Data Book, 2010.1a 293 QVL Checker Data Sheets qvl_state_transition condition [next_count-1:0] Concatenated list of condition signals for the corresponding next values. condition_enable = 0 Condition port is ignored. Every value in next_val is an active next value. condition_enable = 1 Only values in next_val that have corresponding condition bits that are TRUE are active next values. Description The qvl_state_transition checker ensures a state expression transitions to legal values. The checker evaluates the expressions test_expr and val at each rising edge of clk whenever active is TRUE. If the value of test_expr matches the value of val, an event window opens. The event window closes when test_expr transitions to a new value. In the cycle the event window closes, the value of next_val is sampled—the value of next_val is a concatenated list of “next” values for test_expr—and if the value of test_expr does not match one of the next values, a state_transition check violation occurs. The default operation can be adjusted in the following ways: • If the start_enable parameter is 1, event windows do not open unless start is TRUE. • If the condition_enable parameter is 1, condition is sampled along with next_val when the event window closes. Each bit of condition corresponds to a value in next_val. The value of test_expr is only matched against next_val values whose corresponding condition bits are TRUE. • If the match_by_cycle parameter is 1, event windows close 1 cycle after they open (even if the value of test_expr has not changed). • If the is_not_check parameter is 1, the sense of the matching of test_expr and next_val values is flipped: The state_transition check is turned off and the is_not check is turned on. When the event window closes, an is_not check violation occurs if the value of test_expr does match a next_val value (unless condition_enable is 1 and the condition signal for the matched value is FALSE). Uses: FSM, state machine, controller, coverage, line coverage, path coverage, branch coverage, state coverage, arc coverage. 294 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_state_transition Assertion Checks STATE_TRANSITION Value of the expression was not a specified next value. (is_not_check = 0) and (match_by_cycle = 0) Event window closed when test_expr changed value, but the new value was not a next value. (is_not_check = 0) and (match_by_cycle = 1) Event window closed 1 cycle after it opened, but the value of test_expr was not a next value. Value of the expression was a specified next value, but the corresponding condition signal was not asserted. (condition_enable = 1) Event window closed and the new value was a next value, but the condition bit for the next value was FALSE. (is_not_check = 0) and IS_NOT Value of the expression was a next value. (condition_enable = 0) Event window closed when the value of test_expr was a next value. (is_not_check = 1) and (is_not_check = 1) and (condition_enable = 1) Event window closed when the value of test_expr was a next value with a TRUE corresponding condition bit. Notes 1. This checker is difficult to use with a non-constant activation signal. Cover Points Corner Cases All Transitions Covered Non-zero if test_expr transitioned to every next value found in the sampled next_val values. Not meaningful if is_not_check is 1. Statistics Cycles Checked Number of clock cycles checked. Number of Transitions Covered Number of different values in next_val that test_expr transitioned to. Not meaningful if is_not_check is 1. Questa Verification Library Checkers Data Book, 2010.1a 295 QVL Checker Data Sheets qvl_state_transition See also none Examples ‘define IDLE 3’b000 ‘define ILLEGAL 3’b111 ‘define FETCH 3’b100 ‘define COMP 3’b010 case (state_reg) ‘IDLE: begin if (error) next_state <= #1 ‘ILLEGAL; else if (cond1) next_state <= #1 ‘FETCH; else if (cond2) next_state <= #1 ‘COMP; else next_state <= #1 ‘IDLE; end ‘FETCH: begin if (error) next_state <= #1 ‘ILLEGAL; else next_state <= #1 ‘COMP; end ‘COMP: begin if (error) next_state <= #1 ‘ILLEGAL; else next_state <= #1 ‘IDLE; end ‘ILLEGAL: begin next_state <= #1 ‘IDLE; end endcase qvl_state_transition #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_ALL), .width(3), .next_count(2)) U1 ( .clk(clock), .reset_n(~reset), .active(reset === 1’b0), .test_expr(state_reg), .val(‘IDLE), .next_val({‘COMP, ‘FETCH}), .start(1’b0), .condition(2’b00)); Checks that state_reg transitions from IDLE to either the FETCH or COMP states. The IDLE to IDLE transition is implicitly specified, since the match_by_cycle option is not explicitly specified. 296 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_state_transition qvl_state_transition #( .width(3), .next_count(2), .condition_enable(1)) U2 ( .clk(clock), .reset_n(~reset), .active(reset === 1’b0), .test_expr(state_reg), .val(‘IDLE), .next_val({‘COMP, ‘FETCH}), .start(1’b0), .condition({idle2comp, idle2fetch})); Checks that state_reg does not transition from IDLE to the FETCH state unless idle2fetch asserts and does not transition from IDLE to the COMP state unless idle2comp asserts. qvl_state_transition #( .width(3), .next_count(2), .match_by_cycle(1’b1)) U3 ( .clk(clock), .reset_n(~reset), .active(reset === 1’b0), .test_expr(state_reg), .val(‘FETCH), .next_val({‘ILLEGAL, ‘COMP}), .start(1’b0), .condition(2’b00)); Checks that state_reg transitions from FETCH to either the COMP or ILLEGAL states on consecutive clock cycles. qvl_state_transition #( .width(3), .next_count(1), .is_not_check(1)) U4( .clk(clock), .reset_n(~reset), .active(reset === 1’b0), .test_expr(state_reg), .val(‘IDLE), .next_val(‘ILLEGAL), .start(1’b0), .condition(1’b0)); Checks that state_reg does not transition from IDLE to the ILLEGAL state. Questa Verification Library Checkers Data Book, 2010.1a 297 QVL Checker Data Sheets qvl_state_transition qvl_state_transition #( .width(3), .next_count(1), .condition_enable(1), .is_not_check(1’b1)) U5 ( .clk(clock), .reset_n(~reset), .active(reset === 1’b0), .test_expr(state_reg), .val(‘IDLE), .next_val(‘ILLEGAL), .start(1’b0), .condition(illegal_not_OK)); Checks that state_reg does not transition from IDLE to the ILLEGAL state while illegal_not_OK is asserted. qvl_state_transition #( .width(3), .next_count(1), .start_enable(1)) U6 ( .clk(clock), .reset_n(~reset), .active(reset === 1’b0), .test_expr(state_reg), .val(‘IDLE), .next_val(‘COMP), .start(start), .condition(1’b0)); Checks that when state_reg is IDLE and start asserts, state_reg transitions to COMP on the following clock cycle. This example shows the state_transition checker behavior when start asserts for more than one clock cycle. The checker activates on the last assertion of start when state_reg is IDLE. 298 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_three_state qvl_three_state Ensures that a three-state buffer’s output matches its input when the buffer is enabled. enable qvl_three_state in_data[width-1:0] out_data[width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width Class: single-cycle assertion Application: control and interface Syntax qvl_three_state [#(severity_level, property_type, msg, coverage_level, width)] instance_name (clk, reset_n, active, enable, in_data, out_data); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL width Width of each in_data and out_data. Default: 1 Ports clk Clock event for the assertion. The checker samples inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. enable Signal that indicates the three-state buffer is enabled. in_data[width-1:0] Input bus. out_data[width-1:0] Output bus. Questa Verification Library Checkers Data Book, 2010.1a 299 QVL Checker Data Sheets qvl_three_state Description The qvl_three_state checker ensures a three-state buffer’s output matches its input when the buffer is enabled. The checker evaluates the expressions enable, in_data and out_data at each rising edge of clk whenever active is TRUE. If the value of enable is TRUE and in_data does not equal out_data, then a three_state check violation occurs. Uses: Interface, input ports (inputs), output ports (outputs), inout ports (inouts), I/O (IOs), tristate, trireg, buffer, floating. Assertion Checks THREE_STATE Three-state buffer enable asserted when the buffer’s output did not match its input. The enable signal was TRUE, but out_data did not equal in_data. Cover Points Statistics Cycles Checked Number of cycles enable was sampled asserted. Enable Transitions Number of cycles enable transitioned to TRUE. See also none Examples qvl_three_state #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“Three State Violation: ”), .coverage_level(‘QVL_COVER_ALL), .width(2)) questa_tristate( .clk(system_clock), .reset_n(system_reset), .active(active), .enable(en), .in_data(insig), .out_data(outsig)); Checks that (insig === outsig) when (enable === 1’b1). 300 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_timeout qvl_timeout Ensures that values of a specified expression do not remain the same for more than the specified number of cycles. Parameters: severity_level property_type msg test_expr[width-1:0] qvl_timeout val[val_width-1:0] clk reset_n active coverage_level width val_width max_possible_val Class: n-cycle assertion Application: user Syntax qvl_timeout [#(severity_level, property_type, msg, coverage_level, width, val_width, max_possible_val)] instance_name (clk, reset_n, active, test_expr, val); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default: 2. val_width Width of the val. Default: 1. max_possible_val Maximum value of val. Default: 32’hffff_ffff. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width -1:0] Variable or expression to check. val Value that specifies the maximum number of cycles for which test_expr can remain unchanged. The value must be > 0. Questa Verification Library Checkers Data Book, 2010.1a 301 QVL Checker Data Sheets qvl_timeout Description The qvl_timeout checker ensures values in test_expr do not remain the same for more than a specified timeout period (the current number of cycles specified by val) when the checker is active. This check occurs at the active clock edge, except for the first cycle after a checker reset. It fires each cycle that the number of cycles test_expr has remained unchanged is greater than the current timeout value (in val). The checker is useful for verifying FSMs, state machines, controllers, pipelines, dataflow elements, registers and latches. Assertion Checks TIMEOUT The value of test_expr remained the same for more than the specified maximum number of cycles. Test_expr did not change value within the timeout period specified by val. ILLEGAL The value of val is illegal (less than 1 or too large). Value of val is illegal. (val < 1 or val > max_possible_value). Cover Points Corner Cases Value Changed at Maximum Limit Number of times test_expr changed at val cycles. Statistics Values Checked Number of cycles test_expr or value changed. Fastest Value Change Time (in cycles) Fewest number of cycles it has taken test_expr to change. Slowest Value Change Time (in cycles) Most number of cycles it has taken test_expr to change. See also qvl_assert_timer 302 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_timeout Example qvl_timeout #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: state timeout”), .coverage_level(‘QVL_COVER_ALL), .width(3), .val_width(2), .max_possible_val(3)) qvl_valid_state_timeout( .clk(clk), .reset_n(reset_n), .active(state != IDLE), .test_expr(state), .val(timeout)); Ensures that each cycle state is not ‘IDLE, the value of state changes by the end of the timeout period specified by timeout and that the value of timeout is not > 5. clk reset_n state != ‘IDLE state timeout WRITE READ ECC STAT WRITE 1 2 1 3 1 QVL_TIMEOUT The value of test_expr remained the same for more than the specified maximum of val cycles. Questa Verification Library Checkers Data Book, 2010.1a QVL_TIMEOUT_ILLEGAL The value of val is illegal (less than 1 or too large). 303 QVL Checker Data Sheets qvl_value qvl_value Ensures that values of a specified expression are always (or never) equal to any of a set of specified values. test_expr[width-1:0] is_not qvl_value val[val_width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width val_width num_values value_xz Class: single-cycle assertion Application: control Syntax qvl_value [#(severity_level, property_type, msg, coverage_level, width, val_width, num_values, value_xz)] instance_name (clk, reset_n, active, test_expr, is_not, val); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default: 4. val_width Width of each value. This is the width of the largest value. The width of the val input is val_width * num_values. Default: 4. num_values Number of values. Default: 4. value_xz How to handle X and Z bits in val. value_xz = 0 (Default) X and Z bits in val cannot match any bit in test_expr. Any X or Z bit in test_expr or val causes a value check violation. value_xz = 1 X bits in val are considered don’t care bits in test_expr. An X bit matches any value in the corresponding bit in test_expr. Z bits in val cannot match bits in test_expr. Any Z bit in test_expr or val causes a value check violation. 304 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_value value_xz = 2 X and Z bits in val are considered don’t care bits in test_expr. An X or Z value bit matches any value in the corresponding bit in test_expr. Ports clk Clock event for the checker. The checker samples the inputs on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check test_expr. test_expr[width-1:0] Variable or expression to check. is_not Sense of values in val. is_not = 0 Values in val are the only legal values. Values of test_expr should match one of the values in val. If test_expr has a value not in val, a value check violation occurs. is_not = 1 Values in val are the illegal values. Values of test_expr should never match one of the values in val. If test_expr has a value matching one in val, an is_not check violation occurs. val Concatenated list of num_values variables containing values for testing test_expr. The width of val is val_width * num_values. Description The qvl_value checker ensures the value of test_expr is either in or not in a specified set of values, when the checker is active. The is_not flag input determines which check is performed. The value check is violated when is_not is 0 and test_expr does not match a value in val. The is_not check is violated when is_not is 1 and test_expr matches a value in val. The check occurs at the active clock edge, except for the first cycle after a checker reset. It fires each time a violation occurs. Assertion Checks VALUE The value does not equal any of the specified values. is_not = 0 The value of test_expr should match one of the values in val. This check is violated when the value of test_expr does not match any value in val. Questa Verification Library Checkers Data Book, 2010.1a 305 QVL Checker Data Sheets qvl_value IS_NOT The value equals one of the specified values. is_not = 1 The value of test_expr should not match one of the values in val. This check is violated when the value of test_expr matches a value in val. Cover Points Corner Cases All Values Covered If non-zero, then all possible values for test_expr are covered (in cycles is_not is 0). Statistics Values Checked Number of times test_expr loaded a new value. Values Covered Number of values covered. See also qvl_constant qvl_value_coverage Examples qvl_value #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_ERROR: incorrect state”), .coverage_level(‘QVL_COVER_ALL), .width(3), .val_width(3), .num_values(5)) qvl_valid_state( .clk(clk), .reset_n(reset_n), .active(sleep_n), .test_expr(state), .is_not(ack), .val({RIO, WIO, WDT, RM, WM})); Ensures that each cycle sleep_n is TRUE, the value of state is RIO, WIO, WDT, RM or WM if ack is FALSE and not one of those values if ack is TRUE. 306 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_value clk reset_n sleep_n ack state RIO RAK QVL_VALUE The value does not equal any of the specified values. Questa Verification Library Checkers Data Book, 2010.1a WIO WM QVL_VALUE_IS_NOT The value equals one of the specified values. 307 QVL Checker Data Sheets qvl_value_coverage qvl_value_coverage Ensures that values of a specified expression are covered during simulation. test_expr[width-1:0] qvl_value_coverage is_not[total_is_not_width-1:0] clk reset_n active Parameters: severity_level property_type msg coverage_level width is_not_width is_not_count value_coverage Class: two-cycle assertion Application: coverage total_is_not_width = (is_not_count*is_not_width) ? is_not_count*is_not_width : 1 Syntax qvl_value_coverage [#(severity_level, property_type, msg, coverage_level, width, is_not_width, is_not_count, value_coverage)] instance_name (clk, reset_n, active, test_expr, is_not); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_ALL. width Width of test_expr. Default: 1. is_not_width Maximum width of an is_not value. Default: 1. is_not_count Number of is_not values. Default: 0. value_coverage Whether or not to perform value_coverage checks. value_coverage = 0 (Default) Turns off the value_coverage check. value_coverage = 1 Turns on the value_coverage check. Ports clk 308 Clock event for the checker. The checker samples on the rising edge of the clock. Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_value_coverage reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. test_expr[width-1:0] Variable or expression to check. is_not [total_is_not_width - 1:0] Concatenated list of is_not_count variables containing ‘is-not’ values for test_expr. The variables’ values are latched at reset and are then used as values of test_expr to exclude from cover point data. If is_not = 1’b0 and both is_not_width and is_not_count are undefined, then is-not values are not used. The test_expr variable is covered when all possible values have been covered. Description The qvl_value_coverage checker ensures the value of test_expr does not change when the checker is active. The checker checks the multiple-bit expression test_expr at each rising edge of clk whenever active is TRUE. If test_expr has changed value, the assertion fails and msg is printed. This checker is used to determine coverage of test_expr and to gather coverpoint data. As such, the sense of the assertion is reversed. Unlike most other QVL checkers (which verify assertions that are not expected to fail), qvl_coverage checkers’ assertion is intended to fail, therefore the value_coverage check typically is turned off (value_coverage = 0). Assertion Checks VALUE_COVERAGE The value of the variable was covered. property_type = ‘QVL_ASSERT The value of test_expr should not change. This check occurs at every active clock edge and fires if the value of test_expr has changed from the value at the previous active clock edge. Cover Points Corner Cases All Values Covered Non-zero if all values of test_expr (except is_not values) have been covered. Otherwise it is set to 0. Statistics Values Checked Number of times test_expr changed value. Values Covered Number of values (including is-not values) that test_expr has covered Questa Verification Library Checkers Data Book, 2010.1a 309 QVL Checker Data Sheets qvl_value_coverage Values Uncovered Number of values (except is-not values) that test_expr has not covered. See also qvl_coverage qvl_value_coverage Examples qvl_value_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .coverage_level(‘QVL_COVER_ALL), .width(2)) qvl_coverage_mux_select( .clk(clk), .reset_n(reset_n), .active(1’b1), .test_expr(mux_sel), .is_not(1’b0)); All Values Covered corner case asserts when mux_sel has covered all encodings. Is_not_count by default is 0; is_not_width by default is 1 and the is_not port is tied to 1’b0, so no is-not values are included. clk reset_n mux_sel 2’b00 2’b10 2’b11 2’b10 2’b01 2’b00 Cornercases for Value Coverage Checker All Values Covered 310 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_xproduct_bit_coverage qvl_xproduct_bit_coverage Ensures functional cross product bit coverage of two vectors. test_expr1[width1-1:0] qvl_xproduct_bit_coverage test_expr2[width2-1:0] clk reset_n Parameters: severity_level property_type msg coverage_level width1 width2 test_expr2_enable coverage_check active Class: event-bounded assertion Application: coverage Syntax qvl_xproduct_bit_coverage [#(severity_level, property_type, msg, coverage_level, width1, width2, test_expr2_enable, coverage_check)] instance_name (clk, reset_n, active, test_expr1, test_expr2); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width1 Width of the test_expr1. Default: 1. width2 Width of the test_expr2. Default: 1. test_expr2_enable Whether or not to use test_expr2 as the second vector. test_expr2_enable = 0 (Default) Use test_expr1 as the second vector (test_expr2 is ignored). test_expr2_enable = 1 Use test_expr1 as the second vector. coverage_check Whether or not to perform coverage checks. coverage_check = 0 (Default) Turns off the coverage check. coverage_check = 1 Turns on the coverage check. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. Questa Verification Library Checkers Data Book, 2010.1a 311 QVL Checker Data Sheets qvl_xproduct_bit_coverage reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. test_expr1[width1-1:0] First vector, specified as a signal, vector or concatenation of signals. test_expr2[width2-1:0] Second vector (if test_expr2_enable is 1), specified as a signal, vector or concatenation of signals (or 1’b0). Description The qvl_xproduct_bit_coverage checker determines cross-product coverage of the bits of one or two variables and gathers coverpoint data. By default, the checker performs no assertion checks. If test_expr2_enable is 1, the checker checks the expressions test_expr1 and test_expr2 at each rising edge of clk whenever active is TRUE. If test_expr1or test_expr2 has changed value, the checker updates its cross-product coverage matrix based on the values of test_expr1 and test_expr2. The checker’s cross-product coverage matrix is a bit matrix whose rows correspond to the descending bits of test_expr1 and whose columns correspond to the descending bits of test_expr2. Elements in the matrix are the corresponding bits of test_expr1and test_expr2 ANDed together. For example, if: test_expr1 is a[9:6] and test_expr2 is b[5:3] then the cross-product coverage matrix is: a[9] & b[5] a[9] & b[4] a[9] & b[3] a[8] & b[5] a[8] & b[4] a[8] & b[3] a[7] & b[5] a[7] & b[4] a[7] & b[3] a[6] & b[5] a[6] & b[4] a[6] & b[3] At reset, the matrix is initialized to all 0’s. Each cycle test_expr1 or test_expr2 changes, the checker calculates a temporary matrix for the current values of test_expr1 and test_expr2. Then, the cross-coverage matrix is updated by setting all elements to 1 whose corresponding elements in the temporary matrix are 1. That is, the bits of the cross-product coverage matrix are “sticky”: once set to 1, they remain set to 1. The matrix is considered covered when all bits are 1. To help analyze partial coverage, the Coverage Matrix Bitmap statistic coverpoint is a concatenated list of the bits of the cross-product coverage matrix arranged by rows. 312 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_xproduct_bit_coverage By default, the value of test_expr2_enable is 0, which disables the test_expr2 port. This is the special case where the checker maintains a cross-product coverage matrix for a vector with itself. However, the Coverage Matrix Bitmap value reported is not the same as one for a matrix where test_expr2 = test_expr1. In this special case, diagonal elements are extraneous (for example, a[3]==1 && a[3]==1) and the elements of the lower-half matrix are redundant. So, the matrix reported by the Coverage Matrix Bitmap is formed by removing the diagonal elements and setting all lower-half matrix elements to 1. For example, if: test_expr2_enable is 0 test_expr1 is a[9:6] test_expr2 is 1’b0 then the cross-product coverage matrix reported by Coverage Matrix Bitmap is: a[9] & a[8] a[9] & a[7] a[9] & a[6] 1 a[8] & a[7] a[8] & a[6] 1 1 a[7] & a[6] Uses: Coverage, cross product coverage, functional coverage. Assertion Checks COVERAGE All bits of the coverage matrix were covered. Every bit of the cross product coverage matrix is 1. Cover Points Corner Cases Matrix Covered If non-zero, all bits of the cross product coverage matrix are covered. Statistics Values Checked Number of cycles in which test_expr1 or test_expr2 loaded a value. Coverage Matrix Bitmap Bitmap of the coverage matrix. The bitmap is arranged in rows. The high-order bit of the bitmap corresponds to the (0,0) element of the matrix. The low-order bit of the bitmap corresponds to the (val2_count -1, val1_count - 1) element of the matrix. Questa Verification Library Checkers Data Book, 2010.1a 313 QVL Checker Data Sheets qvl_xproduct_bit_coverage See also qvl_coverage qvl_xproduct_value_coverage qvl_value_coverage Examples qvl_xproduct_bit_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width1(5)) XPD1 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1(a[4:0]), .test_expr2(1’b0)); Maintains the following bit coverage matrix: a[4] & a[3] a[4] & a[2] a[4] & a[1] a[4] & a[0] 1 a[3] & a[2] a[3] & a[1] a[3] & a[0] 1 1 a[2] & a[1] a[2] & a[0] 1 1 1 a[1] & a[0] qvl_xproduct_bit_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width1(4), .coverage_check(1’b1)) XPD2 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1({sig3, sig2, sig1, sig0})); Maintains the following bit coverage matrix: sig3 & sig2 sig3 & sig0 1 sig2 & sig1 sig2 & sig0 1 314 sig3 & sig1 1 sig1 & sig0 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_xproduct_bit_coverage qvl_xproduct_bit_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width1(5), .width2(4), .test_expr2_enable(1), .coverage_check(1’b1)) XPD3 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1(a[4:0]), .test_expr2(b[3:0])); Maintains the following bit coverage matrix: a[4] & b[3] a[4] & b[2] a[4] & b[1] a[4] & b[0] a[3] & b[3] a[3] & b[2] a[3] & b[1] a[3] & b[0] a[2] & b[3] a[2] & b[2] a[2] & b[1] a[2] & b[0] a[1] & b[3] a[1] & b[2] a[1] & b[1] a[1] & b[0] a[0] & b[3] a[0] & b[2] a[0] & b[1] a[0] & b[0] qvl_xproduct_bit_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width1(4), .width2(1), .xbit(1’b1), .test_expr2_enable(1)) XPD4 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1(a[3:0]), .test_expr2(sig)); Maintains the following bit coverage matrix: a[3] & sig a[2] & sig a[1] & sig a[0] & sig Questa Verification Library Checkers Data Book, 2010.1a 315 QVL Checker Data Sheets qvl_xproduct_value_coverage qvl_xproduct_value_coverage Ensures functional cross product value coverage of two variables. test_expr1[width1-1:0] val1[val1_width-1:0]* qvl_xproduct_value_coverage test_expr2[width2-1:0] val2[val2_width-1:0]** clk reset_n active Parameters: severity_level property_type msg coverage_level width1 width2 val1_width val2_width val1_count val2_count min1 min2 max1 max2 coverage_check Class: event-bounded assertion Application: coverage *val1_width = val1_count > 0 ? val1_count * val1_width : 1 **val2_width = val2_count > 0 ? val2_count * val2_width : 1 Syntax qvl_xproduct_value_coverage [#(severity_level, property_type, msg, coverage_level, width1, width2, val1_width, val2_width, val1_count, val2_count, min1, min2, max1, max2, coverage_check)] instance_name (clk, reset_n, active, test_expr1, test_expr2, val1, val2); Parameters severity_level Severity of the failure. Default: ‘QVL_ERROR. property_type Property type. Default: ‘QVL_ASSERT. msg Error message printed when assertion fails. Default: "QVL_VIOLATION : ". coverage_level Coverage level. Default: ‘QVL_COVER_NONE. width1 Width of the test_expr1. Default: 1. width2 Width of the test_expr2. Default: 1. val1_width Width of each item in val1. Default: 1. val2_width Width of each item in val2. Default: 1. val1_count Number of items in val1. Default: 0. val2_count Number of items in val2. Default: 0. min1 Minimum value of the range of test_expr1. Ignored unless val1_count = 0. Default : 0 316 Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_xproduct_value_coverage min2 Minimum value of the range of test_expr2. Ignored unless val2_count = 0. Default : 0 max1 Maximum value of the range of test_expr1. Ignored unless val1_count = 0. max1 = 0 (Default) Maximum value is the largest possible value of test_expr1. max1 > 0 Maximum value is max1. max2 Maximum value of the range of test_expr2. Ignored unless val2_count = 0. max2 = 0 (Default) Maximum value is the largest possible value of test_expr2. max2 > 0 Maximum value is max2. coverage_check Whether or not to perform coverage checks. coverage_check = 0 (Default) Turns off the coverage check. coverage_check = 1 Turns on the coverage check. Ports clk Clock event for the checker. The checker samples on the rising edge of the clock. reset_n Active low synchronous reset signal indicating completed initialization. active Expression that indicates whether or not to check the inputs. test_expr1[width1-1:0] First variable or expression. test_expr2[width2-1:0] Second variable or expression. val1[val1_width-1:0] val1_count = 0 Connect to 1‘b0. val1_count > 0 Concatenated list of val1_count elements that define the range of test_expr1. Each element is a val1_width wide variable or expression. val2[val2_width-1:0] val2_count = 0 Connect to 1‘b0. val2_count > 0 Concatenated list of val2_count elements that define the range of test_expr2. Each element is a val2_width wide variable or expression. Questa Verification Library Checkers Data Book, 2010.1a 317 QVL Checker Data Sheets qvl_xproduct_value_coverage Description The qvl_xproduct_value_coverage checker determines cross-product coverage of the ranges of two variables and gathers coverpoint data. By default, the checker performs no assertion checks. The checker checks the expressions test_expr1 and test_expr2 at each rising edge of clk whenever active is TRUE. If test_expr1or test_expr2 has changed value, the checker updates its cross-product coverage matrix based on the values of test_expr1 and test_expr2. The checker’s cross-product coverage matrix is a bit matrix whose rows correspond to the range of values of test_expr1 and whose columns correspond to the range of values of test_expr2. At reset, the matrix is initialized to all 0’s. In a cycle in which both test_expr1 and test_expr2 have values in their respective ranges, the matrix element corresponding to that event is set to 1. The bits of the cross-product coverage matrix are “sticky”: once set to 1, they remain set to 1. The matrix is considered covered when all bits are 1. To help analyze partial coverage, the Coverage Matrix Bitmap statistic coverpoint is a concatenated list of the bits of the cross-product coverage matrix arranged by rows. The ranges of test_expr1 and test_expr2 can be specified in two ways: as contiguous value ranges and as discrete value ranges. Contiguous Value Range By default, the ranges of test_expr1 and test_expr2 are from 0 to their largest possible value. Setting min1 and max1 restricts the range of test_expr1 to min1, min1+1, ... , max1. Similarly, setting min2 and max2 restricts the range of test_expr2 to min2, min2+1, ... , max2. The default value of min1 and min2 is 0. The default value of max1 and max2 is 0, which sets the top range values to the maximum values of test_expr1 and test_expr2. For example, if: test_expr1 is a min1 = 6 and max1 = 9 and test_expr2 is b min2 = 3 and max2 = 5 then the cross-product coverage matrix is: (a==9)&&(b==5) (a==9)&&(b==3) (a==8)&&(b==5) (a==8)&&(b==4) (a==8)&&(b==3) (a==7)&&(b==5) (a==7)&&(b==4) (a==7)&&(b==3) (a==6)&&(b==5) 318 (a==9)&&(b==4) (a==6)&&(b==4) (a==6)&&(b==3) Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_xproduct_value_coverage Discrete Value Range Setting val1_count > 1 enables discrete values for the range of test_expr1. The val1 port contains these values as a concatenated list of val1_count values, each value having width val1_width. The values of min1 and max1 are ignored. Similarly, setting val2_count > 1 enables discrete values for the range of test_expr2. The val2 port contains these values as a concatenated list of val2_count values, each value having width val2_width. The values of min2 and max2 are ignored. For example, if: test_expr1 is a val1_count = 4, val1_width = 16 and val2 = {1h‘9, 1‘hB, 1h‘F, 1h‘4} and test_expr2 is b val1_count = 3, val1_width = 16 and val1 = {1h‘3, 1h‘8, 1h‘7} then the cross-product coverage matrix is: (a==4)&&(b==7) (a==4)&&(b==8) (a==4)&&(b==3) (a==F)&&(b==7) (a==F)&&(b==8) (a==F)&&(b==3) (a==B)&&(b==7) (a==B)&&(b==8) (a==B)&&(b==3) (a==9)&&(b==7) (a==9)&&(b==8) (a==9)&&(b==3) Discrete value ranges have the following characteristics: • One test expression can have a contiguous range while the other test expression has a discrete range. • Discrete ranges can be dynamic. Typically, the val1 and val2 ports should remain constant, so the coverage matrix makes sense. However, the checker does not check this restriction. If the value of val1 or val2 has changed, a new set of range values are used for the current cycle. The same cross-product coverage matrix is updated, but the updated elements correspond to the new ranges. • Discrete ranges can have duplicate values. Although this is not a typical usage, if a value with duplicates is covered, all corresponding matrix bits are set. Uses: Coverage, cross product coverage, functional coverage. Assertion Checks COVERAGE All bits of the coverage matrix were covered. Every bit of the cross-product coverage matrix is 1. Questa Verification Library Checkers Data Book, 2010.1a 319 QVL Checker Data Sheets qvl_xproduct_value_coverage Cover Points Corner Cases Matrix Covered If non-zero, all bits of the cross-product coverage matrix are covered. Statistics Values Checked Number of cycles in which test_expr1 or test_expr2 loaded a value. Coverage Matrix Bitmap Bitmap of the coverage matrix. The bitmap is arranged in rows. The high-order bit of the bitmap corresponds to the (0,0) element of the matrix. The low-order bit of the bitmap corresponds to the (val2_count -1, val1_count - 1) element of the matrix. See also qvl_coverage qvl_xproduct_bit_coverage qvl_value_coverage Examples qvl_xproduct_value_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width1(3), .width2(2), .coverage_check(1’b0)) XVC1 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1(a), .test_expr2(b), .val1(1’b0), .val2(1’b0)); Maintains the following cross-product coverage matrix: (a==7)&&(b==3) (a==6)&&(b==3) (a==5)&&(b==3) (a==4)&&(b==3) (a==3)&&(b==3) (a==2)&&(b==3) (a==1)&&(b==3) (a==0)&&(b==3) 320 (a==7)&&(b==2) (a==6)&&(b==2) (a==5)&&(b==2) (a==4)&&(b==2) (a==3)&&(b==2) (a==2)&&(b==2) (a==1)&&(b==2) (a==0)&&(b==2) (a==7)&&(b==1) (a==6)&&(b==1) (a==5)&&(b==1) (a==4)&&(b==1) (a==3)&&(b==1) (a==2)&&(b==1) (a==1)&&(b==1) (a==0)&&(b==1) (a==7)&&(b==0) (a==6)&&(b==0) (a==5)&&(b==0) (a==4)&&(b==0) (a==3)&&(b==0) (a==2)&&(b==0) (a==1)&&(b==0) (a==0)&&(b==0) Questa Verification Library Checkers Data Book, 2010.1a QVL Checker Data Sheets qvl_xproduct_value_coverage qvl_xproduct_value_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width1(3), .width2(2), .min1(3), .min2(1), .max1(4), .coverage_check(1’b1)) XVC2 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1(a), .test_expr2(b), .val1(1’b0), .val2(1’b0)); Maintains the following cross-product coverage matrix: (a==4)&&(b==3) (a==4)&&(b==2) (a==4)&&(b==1) (a==3)&&(b==3) (a==3)&&(b==2) (a==3)&&(b==1) If the Coverage Matrix Bitmap is 111100, the cross-product coverage matrix is: 1 1 1 1 0 0 Here, all combinations were covered except (a==3)&&(b==2) and (a==3)&&(b==1). Questa Verification Library Checkers Data Book, 2010.1a 321 QVL Checker Data Sheets qvl_xproduct_value_coverage qvl_xproduct_value_coverage #( .severity_level(‘QVL_ERROR), .property_type(‘QVL_ASSERT), .msg(“QVL_VIOLATION : "), .coverage_level(‘QVL_COVER_NONE), .width1(8), .width2(4), .val1_width(8), .val1_count(3), .val2_width(4), .val2_count(4), .coverage_check(1’b1)) XVC3 ( .clk(clock), .reset_n(1’b1), .active(1’b1), .test_expr1(a), .test_expr2(b), .val1(24’b111111110111111100000001), .val2(16’b0111000001010010)); Maintains the following coverage matrix: (a==225)&&(b==7) (a==127)&&(b==7) (a==1)&&(b==7) (a==225)&&(b==0) (a==127)&&(b==0) (a==1)&&(b==0) (a==225)&&(b==5) (a==127)&&(b==5) (a==1)&&(b==5) (a==225)&&(b==2) (a==127)&&(b==2) (a==1)&&(b==2) If the Coverage Matrix Bitmap is 101111111110, the cross-product coverage matrix is: 1 0 1 1 1 1 1 1 1 1 1 0 Here, all combinations were covered except (a==225)&&(b==0) and (a==1)&&(b==2). 322 Questa Verification Library Checkers Data Book, 2010.1a Appendix A QVL Macros Global Macros Type Macro Description Function QVL_ASSERT_ON Activates QVL assertion logic. Default: not defined. QVL_COVER_ON Activates QVL coverage logic. Default: not defined. QVL_SV_COVERGROUP_OFF Disables creation of SystemVerilog covergroup logic. Default: not defined. QVL_CW_FINAL_COVER Turns on the display of final coverage information for QVL checkers. Default: final coverage not displayed. QVL_MW_FINAL_COVER_OFF Turns off the display of final coverage information for QVL monitors. Default: final coverage is displayed. Synthesizable Logic QVL_SVA_INTERFACE Instantiates QVL assertion checkers in a SystemVerilog interface construct. Default: not defined. Race Conditions QVL_RACE_AVOID Adds one resolution unit of delay (i.e., Verilog #1) to all QVL input signals. Default: zero delay. Coverage Internal Global Macros The following global variables are for internal use and the user should not redefine them: qvlmodule qvlendmodule QVL_STD_DEFINES_H Questa Verification Library Checkers Data Book, 2010.1a 323 QVL Macros Macros Common to All Assertions Macros Common to All Assertions Parameter Macro Description severity_level QVL_FATAL Runtime fatal error. QVL_ERROR (default) Runtime error. QVL_WARNING Runtime Warning. QVL_INFO Assertion failure has no specific severity. QVL_ASSERT (default) All the assertion checker’s checks are asserts. QVL_ASSUME All the assertion checker’s checks are assumes. QVL_IGNORE All the assertion checker’s checks are ignored. QVL_COVER_ALL (default) Activates coverage logic for the checker if QVL_COVER_ON is defined. QVL_COVER_NONE, QVL_COVER_SANITY, QVL_COVER_BASIC, QVL_COVER_CORNER, QVL_COVER_STATISTIC Reserved for future use. property_type coverage_level 324 Questa Verification Library Checkers Data Book, 2010.1a ABCDE FGH I J KLMNOPQRS TUVWXY Z Index — Symbols — $finish, 19 +acc option, 18 —A— Activation port, 25 Adding checker/monitor instances, 13 Assertion check, 25 assertion fail command, 19 Assertion logic, 10 —B— bind module, 21 Bits mutually exclusive, 216 —C— Checker class, 22 Checker schematic, 22 Checkers qvl_assert_follower, 35 qvl_assert_leader, 39 qvl_assert_timer, 44 qvl_assert_together, 48 qvl_back_pressure, 50 qvl_bits_off, 53 qvl_bits_on, 55 qvl_bus_driver, 57 qvl_bus_id, 61 qvl_change_timer, 67 qvl_channel_data_integrity, 71 qvl_constant, 80 qvl_content_addressable_memory, 82 qvl_coverage, 92 qvl_crc, 95 qvl_data_loaded, 105 qvl_data_used, 108 qvl_decoder, 113 qvl_decoder_8b10b, 116 qvl_driven, 123 qvl_encoder, 125 Questa Verification Library Checkers Data Book, 2010.1a qvl_encoder_8b10b, 129 qvl_fifo, 138 qvl_gray_code, 147 qvl_hamming_distance, 150 qvl_known, 154 qvl_maximum, 156 qvl_memory_access, 159 qvl_minimum, 167 qvl_multi_clock_fifo, 170 qvl_multi_clock_multi_enq_deq_fifo, 179 qvl_multi_clock_multi_port_memory_acc ess, 188 qvl_multi_enq_deq_fifo, 199 qvl_multiplexor, 210 qvl_mutex, 215 qvl_outstanding_id, 218 qvl_parallel_to_serial, 232 qvl_req_ack, 241 qvl_resource_share, 248 qvl_same, 254 qvl_same_bit, 258 qvl_same_word, 262 qvl_scoreboard, 266 qvl_serial_to_parallel, 279 qvl_stack, 286 qvl_state_transition, 292 qvl_three_state, 299 qvl_timeout, 301 qvl_value, 304 qvl_value_coverage, 308 qvl_xproduct_bit_coverage, 311 qvl_xproduct_value_coverage, 316 Clock port, 24 compile_qvl_lib, 15 Compiling QVL libraries, 15 Corner cases, 26 Cover points, 25 Corner cases, 26 Statistics, 25 Coverage and statistics information, 20 325 ABCDE FGH I J KLMNOPQRS TUVWXY Z Coverage logic, 10 coverage on/coverage off pragmas, 14 Coverage report, 17 —D— Debugging violations, 18 defines QVL_ASSERT, 324 QVL_ASSERT_ON, 10, 23, 24, 323 QVL_ASSUME, 324 QVL_COVER_ALL, 24, 324 QVL_COVER_BASIC, 24, 324 QVL_COVER_CORNER, 24, 324 QVL_COVER_NONE, 24 QVL_COVER_ON, 10, 323 QVL_COVER_SANITY, 24, 324 QVL_COVER_STATISTIC, 24, 324 QVL_CW_FINAL_COVER, 11, 323 QVL_ERROR, 23, 324 QVL_FATAL, 23, 324 QVL_IGNORE, 324 QVL_INFO, 23, 324 QVL_MW_FINAL_COVER_OFF, 11, 323 QVL_RACE_AVOID, 11, 323 QVL_SV_COVERGROUP_OFF, 323 QVL_SVA_INTERFACE, 11, 323 QVL_WARNING, 23, 324 Disparity, 131 —F— Failure column, 18 fcover report command, 19 Formal verification, 21 —G— Global macros, 10 —H— Hierarchical references, 13 —I— Instance templates directory, 12 Instantiating QVL components, 12 interface construct, 11 326 —M— ModelSim library and package, 13 modelsim_lib, 13 Mutually exclusive bits, 216 —N— -novopt option, 18 —O— Optimization, 18 —P— PSL vunit, 13 —Q— QVL library and packages, 14 QVL_ASSERT, 324 qvl_assert_follower, 35 qvl_assert_leader, 39 QVL_ASSERT_ON, 10, 23, 24, 323 qvl_assert_timer, 44 qvl_assert_together, 48 QVL_ASSUME, 324 qvl_back_pressure, 50 qvl_bits_off, 53 qvl_bits_on, 55 qvl_bus_driver, 57 qvl_bus_id, 61 qvl_change_timer, 67 qvl_channel_data_integrity, 71 qvl_constant, 80 qvl_content_addressable_memory, 82 QVL_COVER_ALL, 24, 324 QVL_COVER_BASIC, 24, 324 QVL_COVER_CORNER, 24, 324 QVL_COVER_NONE, 24 QVL_COVER_ON, 10, 323 QVL_COVER_SANITY, 24, 324 QVL_COVER_STATISTIC, 24, 324 qvl_coverage, 92 qvl_crc, 95 QVL_CW_FINAL_COVER, 11, 323 qvl_data_loaded, 105 qvl_data_used, 108 qvl_decoder, 113 qvl_decoder_8b10b, 116 qvl_driven, 123 Questa Verification Library Checkers Data Book, 2010.1a ABCDE FGH I J KLMNOPQRS TUVWXY Z qvl_encoder, 125 qvl_encoder_8b10b, 129 QVL_ERROR, 23, 324 QVL_FATAL, 23, 324 qvl_fifo, 138 qvl_gray_code, 147 qvl_hamming_distance, 150 QVL_IGNORE, 324 QVL_INFO, 23, 324 qvl_known, 154 qvl_maximum, 156 qvl_memory_access, 159 qvl_minimum, 167 qvl_multi_clock_fifo, 170 qvl_multi_clock_multi_enq_deq_fifo, 179 qvl_multi_clock_multi_port_memory_access, 188 qvl_multi_enq_deq_fifo, 199 qvl_multiplexor, 210 qvl_mutex, 215 QVL_MW_FINAL_COVER_OFF, 11, 323 qvl_outstanding_id, 218 qvl_parallel_to_serial, 232 QVL_RACE_AVOID, 11, 323 qvl_req_ack, 241 qvl_resource_share, 248 qvl_same, 254 qvl_same_bit, 258 qvl_same_word, 262 qvl_scoreboard, 266 qvl_serial_to_parallel, 279 qvl_stack, 286 qvl_state_transition, 292 QVL_SV_COVERGROUP_OFF, 323 QVL_SVA_INTERFACE, 11, 323 qvl_three_state, 299 qvl_timeout, 301 qvl_value, 304 qvl_value_coverage, 308 QVL_WARNING, 23, 324 qvl_xproduct_bit_coverage, 311 qvl_xproduct_value_coverage, 316 Running disparity, 131 —S— Severity level, 23 Signal spy, 13 Simulator arguments file, 16 Statistics, 25 SVA bind, 13 SystemVerilog interface construct, 11 —T— Templates directory, 12 —U— UCDB, 19 —V— vcom-19 error, 18 —R— Race conditions, 11 Reset port, 25 Questa Verification Library Checkers Data Book, 2010.1a 327 ABCDE FGH I J KLMNOPQRS TUVWXY Z 328 Questa Verification Library Checkers Data Book, 2010.1a End-User License Agreement The latest version of the End-User License Agreement is available on-line at: www.mentor.com/eula IMPORTANT INFORMATION USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS. CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE. USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT. ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY. END-USER LICENSE AGREEMENT (“Agreement”) This is a legal agreement concerning the use of Software (as defined in Section 2) between the company acquiring the license (“Customer”), and the Mentor Graphics entity that issued the corresponding quotation or, if no quotation was issued, the applicable local Mentor Graphics entity (“Mentor Graphics”). Except for license agreements related to the subject matter of this license agreement which are physically signed by Customer and an authorized representative of Mentor Graphics, this Agreement and the applicable quotation contain the parties' entire understanding relating to the subject matter and supersede all prior or contemporaneous agreements. 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All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of Portland, Oregon when the laws of Oregon apply, or Dublin, Ireland when the laws of Ireland apply. Notwithstanding the foregoing, all disputes in Asia (except for Japan) arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a single arbitrator to be appointed by the Chairman of the Singapore International Arbitration Centre (“SIAC”) to be conducted in the English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be incorporated by reference in this section. This section shall not restrict Mentor Graphics’ right to bring an action against Customer in the jurisdiction where Customer’s place of business is located. The United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement. 18. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect. 19. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes all prior or contemporaneous agreements, including but not limited to any purchase order terms and conditions. Some Software may contain code distributed under a third party license agreement that may provide additional rights to Customer. Please see the applicable Software documentation for details. This Agreement may only be modified in writing by authorized representatives of the parties. All notices required or authorized under this Agreement must be in writing and shall be sent to the person who signs this Agreement, at the address specified below. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver or excuse. Rev. 090402, Part No. 239301 ...
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This note was uploaded on 02/01/2012 for the course ING 101 taught by Professor James during the Spring '11 term at Universidad del Cauca.

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