tt_ipusb20hr_hw_sim_2.4

tt_ipusb20hr_hw_sim_2.4 - Designing & Simulating...

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Unformatted text preview: Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions, Inc. (USA) 14100 Murphy Avenue San Martin, CA 95046 (408) 852 - 0067 IP Core Version: 2.4 Document Version: 2.4 http://www.slscorp.com Document Date: June 2009 IP Usage Note The Intellectual Property (IP) core is intended solely for our clients for physical integration into their own technical products after careful examination by experienced technical personnel for its suitability for the intended purpose. The IP was not developed for or intended for use in any specific customer application. The firmware/software of the device may have to be adapted to the specific intended modalities of use or even replaced by other firmware/software in order to ensure flawless function in the respective areas of application. Performance data may depend on the operating environment, the area of application, the configuration, and method of control, as well as on other conditions of use; these may deviate from the technical specifications, the Design Guide specifications, or other product documentation. The actual performance characteristics can be determined only by measurements subsequent to integration. The reference designs were tested in a reference environment for compliance with the legal requirements applicable to the reference environment. No representation is made regarding the compliance with legal, regulatory, or other requirements in other environments. No representation can be made and no warranty can be assumed regarding the suitability of the device for a specific purpose as defined by our customers. SLS reserves the right to make changes to the hardware or firmware or software or to the specifications without prior notice or to replace the IP with a successor model to improve performance or design of the IP. Of course, any changes to the hardware or firmware or software of any IP for which we have entered into an agreement with our customers will be made only if, and only to the extent that, such changes can reasonably be expected to be acceptable to our customers. Copyright©2005-2009, System Level Solutions, All rights reserved. SLS, An Embedded systems company, the stylized SLS logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of SLS in India and other countries. All other products or service names are the property of their respective holders. SLS products are protected under numerous U.S. and foreign patents and pending applications, mask working rights, and copyrights. SLS warrants performance of its semiconductor products to current specifications in accordance with SLS’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. SLS assumes no responsibility or liability arising out of the application or use of any information, products, or service described herein except as expressly agreed to in writing by SLS. SLS customers are advised to obtain the latest version of device specifications before relying on any published information and before orders for products or services. tt_ipusb20hr_hw_sim_2.4 ii Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 About this Tutorial Introduction This tutorial accompanies all the steps for creating and simulating USB20HR system from scratch. Also it shows how to create, compile, debug, run and simulate a C/C++ program using the Nios II IDE. Table below shows the revision history of the tutorial. Version Date Description 2.4 - Updated document for IP Core version 2.3. - Added support for Quartus, ver. 8.1 and CoreCommnader board, ver. r1b. 2.3 May 2008 - Added note for figure 5.2 - Minor modification in chapter 5 - Updated document as per the new directory structure 2.2 March 2008 Changed Table 5.1 2.1 February 2008 Combined hardware and simulating the USB20HR system in one tutorial 2.0 November 2007 Updated tutorial as per the USB2.0 IP core version 2.x (USB20HR) 1.2 December 2006 Second Publication of the Designing USB2.0 System from Scratch-Removal of Control Endpoint Registers and Modification of CSR Register of each endpoint. 1.1 How to find Information January 2009 May 2006 First Publication of the Tutorial The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Use Ctrl + F to open the Find dialog box. Use Shift + Ctrl + N to open to the Go To Page dialog box. • System Level Solutions June 2009 • Thumbnail icons, which provide miniature preview of each page, provide a link to the pages. Links allow you to jump to related information. iii Designing & Simulating the USB20HR System from Scratch Tutorial How to Contact SLS How to Contact SLS For the most up-to-date information about SLS products, go to the SLS worldwide website at http://www.slscorp.com. For additional information about SLS products, consult the source shown below. Information Type E-mail Product literature services, SLS literature services, Nontechnical customer services, Technical support. Typographic Conventions support@slscorp.com The tutorial uses the typographic conventions as shown below. Visual Cue Meaning Bold Type with Initial Capital letters All headings and Sub heading Titles in a document are displayed in bold type with initial capital letters; Example: Designing & Compiling, Creating a Quartus II Project etc. Bold Type with Italic Letters All Definitions, Figure and Table Headings are displayed in Italics. Examples: Figure 1-1. Create a new System Dialog box. 1. 2. Numbered steps are used in a list of items, when the sequence of items is important. Such as steps listed in procedure. • Bullets are used in a list of items when the sequence of items is not important. The hand points to special information that requires special attention The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. The warning indicates information that should be read prior to starting or continuing the procedure or processes. The feet direct you to more information on a particular topic. iv Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Contents About this Tutorial ............................................................................................................. iii Introduction ..............................................................................................................................................iii How to find Information ..........................................................................................................................iii How to Contact SLS ................................................................................................................................ iv Typographic Conventions ........................................................................................................................ iv 1. Introduction ............................................................................................................................... 1 Hardware & Software Requirements ........................................................................................................ 2 2. Designing & Compiling............................................................................................................. 3 Creating a Quartus II Project .................................................................................................................... 3 Start SOPC Builder ................................................................................................................................... 3 Define the System in SOPC Builder ......................................................................................................... 5 Specify Target Hardware Settings ..................................................................................................... 5 Adding CPU & Peripherals................................................................................................................ 6 Generating the System ............................................................................................................................ 31 Integrate the SOPC Builder System into Quartus II ............................................................................... 32 Adding the Quartus II Symbol to the BDF ...................................................................................... 33 Device Settings ................................................................................................................................ 35 Compiling the Design ...................................................................................................................... 40 3. Programming........................................................................................................................... 42 Configure an FPGA ................................................................................................................................ 42 4. Running the Project in Nios II System .................................................................................. 44 Creating the Project................................................................................................................................. 44 System Library Settings .......................................................................................................................... 45 Project Settings ....................................................................................................................................... 46 Building and Managing the Project ........................................................................................................ 50 Compile C Application .................................................................................................................... 50 Running the Program on Nios II System ................................................................................................ 50 Device Detection.............................................................................................................................. 52 System Level Solutions v 5. Simulating the System in Modelsim Using Nios II IDE ........................................................ 54 Creating the Project................................................................................................................................. 54 System Library Settings .......................................................................................................................... 54 Building and Managing the Project ........................................................................................................ 54 Running the Program on Nios II System ......................................................................................... 56 Appendix A: Pin Assignments for CoreCommander Board (3C25) ................................. 61 vi Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 1. Introduction This tutorial walks you through the hardware & software development flow. It shows you how to use SOPC Builder and the Quartus II software to create, process and simulate your own USB20HR Device IP core & Nios II system This tutorial is basically for users who are new to the Nios II processor as well as users who are new to the concept of using embedded systems in FPGA’s. This tutorial guides you through the steps necessary to create, compile and simulate a USB20HR IP system design. This simple, single-master Nios II system consist of a Nios II embedded processor and associated system peripherals and interconnections for use with the input & output hardware available on cyclone board. This tutorial is divided into the following four sections: ‘Designing & Compiling’ - Teaches you how to use SOPC builder to create the Nios II & USB20HR system module in block design file (.bdf) and how to compile the Nios II design using the Quartus II Compiler. ‘Programming’ - Teaches you how to use the Quartus II Programmer and the Byte Blaster / USB Blaster cable to configure the FPGA on the cyclone board, so that the FPGA can be configured with your design whenever power is applied to the board. ‘Running the Software on Your Nios II System’ - Provides the instructions for running software on your Nios II system using the Nios II integrated development environment (IDE). Simulating the USB20HR Application on Nios II System - Provides the steps, which will guide you how to build a system for the Nios II processor and simulate it with ModelSim-Altera 6.3g_p1 simulation tool. System Level Solutions June 2009 1 Designing & Simulating the USB20HR System from Scratch Tutorial Hardware & Software Requirements Hardware & Software Requirements The user will require following hardware & software A PC running with Win 2000/XP OS Nios II embedded processor version 8.1 or higher The Quartus II software version 8.1 or higher CoreCommander Board (3C25) Altera/SLS USB-Blaster/Byte Blaster download cable ModelSim -Altera 6.3g_p1 2 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 2. Designing & Compiling To use the instructions in this section, you need to be familiar with the Quartus II software interface, specifically toolbars. Refer to Quartus II help for more information about using the Quartus II software. Creating a Quartus II Project Here are the steps to create a new Quartus II project: 1. Open the Quartus II. 2. Choose File>New Project Wizard. 3. Click Next. 4. Select Working Directory of the Project, Name of the project as ‘usb20hr_pi_n2_cc_3c25’ & top-level entity as “usb20hr_pi_n2_cc_3c25”. 5. Click Next. 6. Click Next. 7. Select the family as ‘Cyclone III’. Select Specify device selected in ‘Available device list’ radio button in Target Device option. 8. This design from scratch is given for CoreCommander Board (3C25), so you have to select the FPGA for cyclone board (which is Cyclone III EP3C25F256C8), so under Filters / Speed Grade select 8 Then under Available devices: highlight ‘EP3C25F256C8’. Click Next. If you want to design a system for the board other then CoreCommander (3C25) then you will have to select device whichever is there on your board. 9. Click Next. 10. Click Finish. After creating a new project in Quartus II, its now time to generate a system into SOPC builder. Start SOPC Builder System Level Solutions June 2009 SOPC builder is a software tool that allows you to create a fully functioning, custom-embedded micro controller called the Nios II system module. A complete Nios II system module contains a Nios II embedded processor and its associated peripherals. 3 Designing & Simulating the USB20HR System from Scratch Tutorial Start SOPC Builder To start SOPC builder, perform the following steps: 1. Choose SOPC Builder from the Tools menu. SOPC Builder displays the Create New System dialog box. 2. Type ‘usb20hr_refdes’ in the System Name box. See Figure 2-1. 3. Under HDL Language field specify Verilog. SOPC Builder generates plain text Verilog HDL or VHDL for all of its native components depending on the language you choose. Figure 2-1. Create New System 4. Click OK. 5. The Altera SOPC Builder - usb20hr_refdes system window appears and the System Contents tab is displayed. You are now ready to set the speed and add the Nios II CPU and peripherals to your system. The components you will be adding are located in the module pool on the left hand side of the System Content tab. See Figure 2-2. 4 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-2. SOPC Builder -System Contents Tab Define the System in SOPC Builder After creating project in SOPC builder, now to define the system in SOPC Builder follow the procedure mentioned below: Specify Target Hardware Settings The functionality of the SOPC Builder system depends on the hardware on which it will run. Thus, specifying the target board is the first step in creating a system according to your requirement. 1. 2. System Level Solutions June 2009 Select the System Clock Frequency as 48 Mhz. Select the usb_out_clk as a 60Mhz. 5 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-3. SOPC Builder Clock Adding CPU & Peripherals This section describes adding following modules to the SOPC Builder. Nios II 32-bit CPU JTAG UART Avalon-MM Clock Crossing Bridge USB20HR Avalon-MM Tristate Bridge FLASH Memory (CFI) SDRAM On-chip Memory DMA PLL PIO Add the Nios II 32-bit CPU To add the Nios II 32-bit CPU, named CPU, perform the following steps: 1. Under Avalon Modules, select Nios II Processor - Altera Corporation. 2. Double click to Add. The Nios II configuration wizard titled Nios II Processor - cpu displays. 3. Specify the following options under the Nios II Core tab. 6 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 • Select the processor core: Nios II/s. • Keep Hardware multiply: None see Figure 2-4. You can also select Nios II/f processor for better performance. Figure 2-4. Nios II Processor - CPU Configuration Wizard 4. System Level Solutions June 2009 Select settings for Nios II core as shown in Figure 2-5. 7 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-5. Nios II Core Options - Caches & Tightly Coupled Memories Configuration Wizard 5. Click the JTAG Debug Module tab and choose the highlighted tab as shown in Figure 2-6. 8 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-6. Nios II Options - JTAG Debug Module 6. Click Finish & you are returned to the main SOPC Builder window. You will see errors in the SOPC Builder message display. However, the issue causing the errors are resolved when the rest of the elements are added to the design. At this stage error messages can be safely ignored. Add the JTAG UART This Nios II design includes one JTAG UART interface component, which is added to reduce the number of connections necessary to ‘talk’ to the Nios II. To add this peripheral perform the following steps: System Level Solutions June 2009 9 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder 1. Select Interface Protocol>Serial> JTAG UART and click Add. The JTAG UART - jtag_uart wizard displays as shown in Figure 2-7. Figure 2-7. JTAG UART Configuration Wizard 2. Accept the default options by clicking Finish. Add the Avalon-MM Clock Crossing Bridge To add Avalon-MM Clock Crossing bridge follow the steps below: 1. Select Bridges and Adapters>Memory Mapped > Avalon-MM Clock Crossing Bridge and click Add. The Avalon-MM Clock Crossing Bridge - Clock Crossing_bridge wizard displays as shown in Figure 2-8. 10 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-8. Avalon-MM Clock Crossing Bridge 2. Click Finish. Add the USB20HR To add USB20HR, double click on SLS>Communication>USB>USB 2.0 HS Device Controller (RAM based). IP Mega wizard opens. See Figure 2-9. System Level Solutions June 2009 11 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-9. USB20HR IP Tool-bench 1. IN Buffer Depth(X32 bits) and OUT Buffer Depth(X32 bits) specifies onchip memory used by USB Core for all IN and Out Endpoints respectively through their buffer registers pointer and size. You can select buffer depth from 2 Kbytes to 64 Kbytes.depending upon onchip memory availble inside the selected device. Use larger buffer depth if more then two endpoints are used for USB IP Core. 2. Under Enable Simulation Option: • Type 0 while you are designing the USB20HR System from Scratch. • Type 1 while simulating the USB20HR System. 3. Under Hex File Path, type the Hex file path. The Hex file is located at <USB20HR IP installation path>\hardware\component\hdl. 4. Click Finish. You will return to SOPC Builder System content tab window. After the IP is added, please note that this IP is encrypted one. To use this IP follow the steps below: • Open the Quartus II > Tool > License Setup… • Then under License Setup/ License file edit combo box. Add semicolon & type the license file path of USB20HR IP. Make sure that you have given the license file extension “. dat”. 5. Then click OK. & reopen the Quartus II > Tool > License Setup… You will see as displayed in Figure 2-10. 12 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-10. License Setup Add the Avalon-MM Tristate Bridge For the Nios II system to communicate with memory external to the FPGA on the CoreCommander Board (3C25), you must add a bridge between the Avalon bus. To add this: 1. System Level Solutions June 2009 Select Bridges and Adapters>Memory Mapped > Avalon-MM Tristate Bridge and click Add. The Avalon-MM Tristate Bridge - tri_state_bridge wizard displays. See Figure 2-11. 13 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-11.Avalon Tristate Bridge Configuration Wizard- Incoming Signals Tab 2. Click Finish. Adding CFI Flash Memory To add the CFI Flash Memory, follow the steps below: 1. Select Memory and Memory Controller->Flash->Flash Memory (CFI) and click Add. 2. CFI Flash Memory Wizard opens. 3. Make the settings as shown in Figure 2-12. 14 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-12. CFI Flash Memory Wizard 4. 5. System Level Solutions June 2009 Click Next. Make the settings as shown in Figure 2-13. 15 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-13. Flash Memory (CFI) Wizard 6. Click on Finish. Add the SDRAM Depending on which hardware you are using, user has to select the external SRAM or any memory. To add SDRAM perform the following steps: 1. Select Memories and Memory controller > SDRAM>SDRAM Controller. You will see SRAM Configuration wizard as shown in Figure 2-9. Configure it for the settings as shown in the figure. 16 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-14. SDRAM Configuration Wizard 2. System Level Solutions June 2009 Click Next and configure the second page as shown in Figure 2-15. 17 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-15. SDRAM Configuration Page 2 Add the On-chip Memory On-Chip RAM is used as a data storage memory into SOPC builder system. To add on chip memory into SOPC builder system perform following steps. 1. Select Memories and Memory Controllers -> On -Chip> On -Chip Memory (RAM or ROM) and then click on Add. 2. Change settings as shown in Figure 2-16. 18 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-16. On-Chip Memory Configuration Wizard 3. Click on Finish. Add the PIO To provide an interface for the LEDs, add the PIO. 1. Select PIO(Parallel I/O) under Peripherals>Micro Controller Peripheral>PIO and click Add. The PIO-pio wizard displays as shown in Figure 2-17. System Level Solutions June 2009 19 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-17. PIO Configuration Wizard 2. Under Basic Settings tab, specify the following options: See • • 3. Width: 2 bits Direction: Output ports only Click Finish. You are returned to the Altera SOPC Builder-nios32 window. Add the DMA To access FIFO directly in the core, add DMA. To add DMA follow the steps below: 1. Select DMA under Memories and Memory Controller>DMA> DMA Controller and click Add. The DMA Controller - dma wizard displays as shown in Figure 2-18. 20 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 2. Under DMA parameter tab, specify following settings: • Under Transfer Size, type “13bit” in the width of DMA length register box. • Under FIFO Implementation, select “Construct FIFO from embedded memory blocks”. Figure 2-18. Avalon DMA Controller Configuration Wizard 3. 4. System Level Solutions June 2009 Click Finish. You will return to SOPC builder system content tab. Connect DMA read and write master with USB20HR and SRAM. 21 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Add the PLL To provide the direct clk to the SDRAM, PLL is used. Select PLL under PLL and click Add. You will see the PLL Configuration Wizard as shown in Figure 2-19. Figure 2-19. PLL Configuration Wizard 1. Click on the Launch Altera’s ALTPLL MegaWizard. You will see the MegaWizard Plug-In Manager[Page 1] as shown in Figure 2-20. 22 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-20.MegaWizard Plug-In Manager [Page 1 of 12] 2. 3. Keep the default settings as shown in Figure 2-20. 4. System Level Solutions June 2009 Type 48 under What is the frequency of the inclock0 input?. Press Enter. See Figure 2-22. 23 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-21.MegaWizard Plug-In Manager [Page 2 of 12] 5. Check Create “locked” output under Lock output. 6. Press Enter. 7. Press Enter. You will go on to the 6th page of the wizard Figure 2-22. 24 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-22.MegaWizard Plug-In Manager [Page 6 of 12] 8. Select Enter output clock parameters: under Clock Tap Settings. Set the following options: • Clock phase shift: 0.00 ps • System Level Solutions June 2009 Clock division factor: 5 • 9. Clock multiplication factor: 2 • Clock duty cycle: 50 Press Enter. You will go on to the 7th page of the wizard. See Figure 2-23. 25 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-23.MegaWizard Plug-In Manager [Page 7 of 12] 10. Select Enter output clock parameters: under Clock Tap Settings. Set the following options: • Clock multiplication factor: 62 • Clock division factor: 35 • Clock phase shift: 0.00 ps • Clock duty cycle: 50 11. Press Enter. You will go on to the 8th page of the wizard. See Figure 2-24. 26 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-24.MegaWizard Plug-In Manager [Page 8 of 12] 12. Select Enter output clock parameters: under Clock Tap Settings. Set the following options: • Clock multiplication factor: 62 • Clock division factor: 35 • Clock phase shift: -2.00 ns • Clock duty cycle: 50 13. Click on the Summary tab, and you will see the window as per Figure 2-25. System Level Solutions June 2009 27 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-25.MegaWizard Plug-In Manager [Page 12 of 12] 14. Press Enter. You will return to PLL Configuration Wizard. See Figure 2-19. 15. Click Next and set the configuration as shown in Figure 2-26. 28 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-26. Final PLL configuration 16. Click on Finish. After adding all components, the SOPC builder system will look like as shown in Figure 2-27. System Level Solutions June 2009 29 Designing & Simulating the USB20HR System from Scratch Tutorial Define the System in SOPC Builder Figure 2-27.SOPC Builder System After Adding all Components Now, arrange all components and provide the clock to each component as shown in Figure 2-28. Also rename the clocks under clock settings as shown in Figure 2-28. 30 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-28.Final View of the SOPC Builder System Click on the Module name CPU. You will return to the Nios II Processor CPU Configuration Wizard. Specify following options: • • Generating the System Reset Vector Memory: cfi_flash Exception Vector Memory: onchip_memory To generate the design logic, perform the following steps. 1. Click the System Generation tab. 2. Make the following settings under Options in System Generation tab. See Figure 2-29. • System Level Solutions June 2009 Simulation: – If you are designing the USB20HR system from scratch, uncheck this box. – If you are simulating the USB20HR system, check this box. 31 Designing & Simulating the USB20HR System from Scratch Tutorial Integrate the SOPC Builder System into Quartus II Figure 2-29.Generating the System 3. 4. When generation is complete, the SYSTEM GENERATION COMPLETED message displays. 5. Integrate the SOPC Builder System into Quartus II Click Generate. Click Exit. You have now created your SOPC builder system to evaluate USB20HR IP. Now compile this system with other necessary logic in quartus II software for generating programming file. 32 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Adding the Quartus II Symbol to the BDF During generation, SOPC Builder creates a symbol of the System Top, for use in Quartus II. You can add this symbol to your BDF. To add the symbol perform the following steps: 1. Select File (menu) > New. 2. Under Device Design Files, highlight Block Diagram/Schematic File. See Figure 2-30. Figure 2-30. New Block Design File 3. 4. Return to the Quartus II software and double click anywhere inside the BDF window. The Symbol dialog box appears. 5. In the Symbol dialog box, Click on Project to expand Project directory. 6. System Level Solutions June 2009 Click OK Click on the project usb20hr_refdes. A large symbol will appear representing the Nios II system module you just created. See Figure 2-31. 33 Designing & Simulating the USB20HR System from Scratch Tutorial Integrate the SOPC Builder System into Quartus II Figure 2-31. BDF Dialogbox 7. Click OK. The Symbol dialog box closes and an outline of the System Top symbol is attached to the pointer. 8. Place the symbol in the block design schematic files. 9. Choose Save. 10. Similarly add input, output pins into design schematic file and make a connection of those pins as shown in Figure 2-32. 11. Now assign input output pins for ULPI as shown in Figure 2-32. If you are designing a system for another board then you will have to do pin assignment according to FPGA IO pins assignment of that board. For pin assignments refer Appendix A. 34 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-32.Final BDF for ULPI Interface Device Settings Device settings will depend on board used for reference design. Device setting for this design for CoreCommander Board (3C25) is given below. To do device settings follow the steps below: 1. 2. System Level Solutions June 2009 Choose Assignment>Settings. Select Library under Category and add the path of the USB20HR component from <USB20HR Installation path>usb20hr\ hardware\ component\hdl. See Figure 2-33. 35 Designing & Simulating the USB20HR System from Scratch Tutorial Integrate the SOPC Builder System into Quartus II Figure 2-33.Library Settings 3. Under Category select Device. 4. Under Device tab select Cyclone III family. See Figure 2-34. 5. Specify following options in the Available Devices list see Figure 2-34. • Package: Any • Pin Count: 256 • Speed grade: 8 • Available Devices: EP3C25F256C8 36 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-34. Device Settings 6. Click on Device & Pin Options. 7. Specify following options under Configuration tab see Figure 2-35. • • Configuration device: EPCS64 • System Level Solutions June 2009 Configuration scheme: Active Serial (can use Configuration Device) Check on Generate Compressed Bitstream. 37 Designing & Simulating the USB20HR System from Scratch Tutorial Integrate the SOPC Builder System into Quartus II Figure 2-35. Configuration Tab Settings 8. Click on Unused Pins Tab. 9. Click on As inputs, tristated under Unused pins tab. See Figure 2-36. 38 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 2-36. Unused Pins Tab Settings 10. Remain Default settings for all other tabs. 11. Click on OK. 12. Click on Analysis and Synthesis settings and do settings according to Figure 2-37. System Level Solutions June 2009 39 Designing & Simulating the USB20HR System from Scratch Tutorial Integrate the SOPC Builder System into Quartus II Figure 2-37.Analysis and Synthesis Settings 13. Click OK. Compiling the Design During compilation, the Compiler locates & processes all design and project files, generates messages & reports related to the current compilation, creates the SRAM object file (.sof) as well as any optional programming files. To compile the usb20hr_pi_n2_cc_3c25 design, follow these steps: 1. Choose Start Compilation (Processing menu), or click the Start Compilation toolbar button. If you get a message asking if you want to save the changes you made the BDF file, choose Yes. 40 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 2. When compilation completes, you can view the results in the Status window. See Figure 2-38. Figure 2-38.Compilation Report Window System Level Solutions June 2009 41 Designing & Simulating the USB20HR System from Scratch Tutorial 3. Programming After successful compilation, the Quartus II Compiler generates one or more programming files that the Programmer uses to program or configure a device. Configure an FPGA To program your design, follow these steps: 1. Choose Programmer (Tool menu). The Programmer window opens. 2. In the Mode list select JTAG. If user selects active serial mode, .pof appears else if jtag is selected .sof appears. 3. Click Hardware Setup to configure the programming hardware, see Figure 3-1. 4. Under Hardware Settings tab select USB Blaster or Byte BlasterII (LPT1) in the Currently selected hardware Figure 3-1. Hardware Setup System Level Solutions June 2009 42 Designing & Simulating the USB20HR System from Scratch Tutorial 5. Click Close to exit the Hardware Setup window. 6. In the Programmer window, turn on Program/Configure. See Figure 3-2. Figure 3-2. Programmer Window 7. 8. System Level Solutions June 2009 Click Start. User can see the progress as shown in Figure 3-2. 43 Designing & Simulating the USB20HR System from Scratch Tutorial 4. Running the Project in Nios II System The design that we have created is for the CoreCommander board ver. r1b. We will run a simple test application of port interface on the CoreCommander board using USB Interface. We will be using Nios II Integrated Development Environment (IDE) to run our software on top of Nios II System. Start Nios II IDE by following one of the two options Start>programs>altera>Nios II EDS<Version>Nios II IDE or Click System Generation tab of the SOPC Builder window then click the Run Nios II IDE button. Creating the Project To create a new project in Nios II IDE follow the steps below: Select New (File Menu)>Nios C/C++ Application. 2. Select Project Template “slsusb2.0 PortInterface”. 3. System Level Solutions June 2009 1. In SOPC Builder System option, under Select Target Hardware browse your system.ptf (usb20hr_refdes.ptf) file. See Figure 4-1. 44 Designing & Simulating the USB20HR System from Scratch Tutorial Figure 4-1. Creating USB Project Sample Application 4. Write PortInterface_0 in the Name. 5. This template loads the required source (.c) file into the project. 6. After making above settings click Next and then Finish. It will create the project. 7. Copy all required header files and library file from the following path: <USB20 HR Installation Path>\ embedded\ lib and paste in to your NIOS II IDE project. If you are using full version of IP Core setup then skip the PROJECT SETTING steps and directly go to Building and Managing the Project. System Library Settings System Level Solutions June 2009 1. Right click on the project portinterface_0 under System Library Property. Select sdram as Program memory, Read-only data memory, Read/write memory, Heap memory, Stack memory. see Figure 4-2. 45 Designing & Simulating the USB20HR System from Scratch Tutorial Project Settings Figure 4-2. System Library Settings 2. 3. Project Settings Select jtag_uart in stdin, stderr, stdin toolbar. This is a cable through which program will run in Nios II IDE. Click OK. Follow the steps below to do project settings: 1. Right click on the Project and select Properties. 2. Select C/C++ Build from the left pane to set the project property settings. 3. Click on Tool Setting tab under Configuration Settings. • Select General under Linker. 46 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 4-3. Project Property Settings 4. Click on Add Library icon under Libraries to add library file. You will see the dialog box as shown in Figure 4-8. 5. Type usb20hr. Figure 4-4. Add Library 6. 7. System Level Solutions June 2009 Click OK. Click on Add Library path icon under Library path. You will see Add Directory path dialog box as shown in Figure 4-5. 47 Designing & Simulating the USB20HR System from Scratch Tutorial Project Settings Figure 4-5. Add Library Path 8. Click on Workspace. 9. The folder selection dialog box opens. See Figure 4-6. 10. Select the folder PortInterface_0. Figure 4-6. Selecting the Folder PortInterface_0 11. Click OK. See Figure 4-7. 48 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 4-7. Add Library Path 12. Click OK. 13. You will return to the Project Property dialog box. See Figure 4-8. Figure 4-8. Project Property after adding Library and Library Path 14. Click Apply & then click OK. System Level Solutions June 2009 49 Designing & Simulating the USB20HR System from Scratch Tutorial Building and Managing the Project Building and Managing the Project Compile C Application To compile C Application, perform the following steps: 1. To build your project, right click on your project in the navigator pane and select Build Project. See Figure 4-9. Figure 4-9. Building the Project 2. Running the Program on Nios II System When the build process successfully completes, you can run the project. After Successful running the project on hardware. To run your program on the development board, perform the following steps: 1. Choose Run>Run in the main Nios II IDE window. 2. Double Click on Nios II Hardware (RAM) in the Configurations browser on the left-hand side. The Run window displays. 3. If you have more than one JTAG cable connection, then you will need to select the Target Connection tab and choose the cable that is connected to your board from the JTAG Cable pull down menu. 50 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 4-10.Run Dialog box 4. 5. System Level Solutions June 2009 Click Apply and click Run. You can also run the Nios II project by right clicking on Project and selecting Run As> Nios II Hardware. See Figure 4-11. 51 Designing & Simulating the USB20HR System from Scratch Tutorial Running the Program on Nios II System Figure 4-11. Running Project 6. On successful download, you should see as shown in Figure 4-12.below. Figure 4-12. Program Downloaded Successfully Device Detection 1. Now connect the USB cable, one end at the back of the PC and other to USB B-type connector. 2. If you are using this IP for the first time then you will see “New Hardware found” Wizard. Browse for the driver files located at <USB20HR Installation Path>\usb20hr\software\driver\ windows. 3. Click on usbview_winxp from <USB20HR Installation Path>\ usb20hr\software\utilities\usbview. You will see the device connected on port where you connect your USB cable. For Bulk transfer you will see “Device Connected: slsusb2.0 device”. See Figure 4-13. 52 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Figure 4-13.SLSUSBView 4. Now open the PortInterface application from the following path. <USB20HR Installation Path>\usb20hr\software\ utilities\portinterface. In order to use the Port Interface software application, .NET framework version 2.0 must be installed in the machine. If not installed, then please visit the microsoft website and download the framework. 5. For use of portinterface application, refer readme.html file located at <USB20HR Installation Path>. <USB20HR Installation Path> is the installation directory. The default installation directory is c:\altera\<version #>\ip\sls. This is the hardware tutorial you learned for the CoreCommander Board (3C25), ver. r1b. By this way, you can make the USB 2.0 system for any board by adding or removing the components as per your requirement. System Level Solutions June 2009 53 Designing & Simulating the USB20HR System from Scratch Tutorial 5. Simulating the System in Modelsim Using Nios II IDE We will run a simple test application of port interface on the modelsim to perform simulation of the design. We will be using Nios II Integrated Development Environment (IDE) to run our software on top of Nios II System. Start NIOS II IDE by following one of the two options Start>programs>altera>Nios II EDS<Version>NiosII IDE or Click System Generation tab of the SOPC Builder window then click the Run NiosII IDE button. Creating the Project For creating the project, follow the steps mentioned in “Creating the Project” on page 44 of chapter 4. System Library Settings For system library settings, follow the steps mentioned in “System Library Settings” on page 45 of chapter 4. Building and Managing the Project For building and managing the project, follow the steps mentioned in “Building and Managing the Project” on page 50 of chapter 4. After successfully building the system and before running the program, do the following modifications in usb20hr_refdes.v file: 1. 2. System Level Solutions June 2009 The USB20HR component uses Mega wizard RAM for enumeration data and for endpoint buffer memory, so simulation within ModelSimAltera 6.3g_p1 add “define USE_convert_hex2ver” in User comment area of usb20hr_refdes.v file. See Figure 5-1. Now to perform a simulation of the design you will need “.VO” file for USB20HR component. Select usb20hr_0.vo file from the following path: <USB20HR IP installation path>\usb20hr\hardware\ 54 Designing & Simulating the USB20HR System from Scratch Tutorial simulation\sim_lib and copy and add this file into current project directory. Also include this file into usb20hr_refdes.v file. See Figure 5-1. Figure 5-1. usb20hr_refdes.v file (Part 1) 3. System Level Solutions June 2009 Create an instance of usb20hr_0_test_component into the test bench area of usb20hr_refdes.v file. See Figure 5-2. 55 Designing & Simulating the USB20HR System from Scratch Tutorial Building and Managing the Project Figure 5-2. usb20hr_refdes.v (Part 2) 1. If you are using name of the component different then the usb20hr_0 inside the SOPC builder then accordingly you will have to modify the name inside the port mapping area. 2. Also make sure that the .vo file and its module name have the same name as the USB component name used in the SOPC builder. Running the Program on Nios II System To run your program on Nios II Model Sim, perform the following steps: 1. To run the program Right click on the project. Click on the Run As Nios II Model Sim 2. You will see that the ModelSim Altera 6.3g_p1 will be opened automatically. 56 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 3. Right click in Workspace select Add to Project --> Exiting File. 4. Browse the Enum_ram.hex file from this path <USB20HR IP Installation Directory>\usb20hr \hardware\component. 5. Click on Copy to project directory. See Figure 5-3. Figure 5-3. Adding Enum_ram.hex file 6. Type ‘s’ command in the command prompt of the ModelSim-Altera 6.3g_p1. The design gets compiled but will not be loaded into the simulation workspace. USB20HR IP uses precompiled library so in order to use precompile part, user need to create a simulation configuration and the precompile library as explained in following two steps. 7. On the left hand side of the ModelSim-Altera 6.3g_p1, in the “workspace” part, right click and select add to “project / simulation configuration”. 8. Select test_bench to simulate from “design /work/” • Under library browse to the path where precompiled parts are placed. <USB20HR IP installation path>\usb20hr\ hardware\simulation\sim_lib\usb20hr_lib_6.3g_p1. (precompile library version should be same as ModelSim-Altera 6.3g_p1 version) • 9. System Level Solutions June 2009 Under library browse to the path where altera_mf is placed. <ALTERA Installation Path>\ModelTech_ae\altera\Verilog Click OK. Now you are ready to start simulation. Double click on the new generated simulation configuration, the design gets loaded. 57 Designing & Simulating the USB20HR System from Scratch Tutorial Building and Managing the Project 10. Right click on the instances you want to simulate and add to the wave window as shown in the Figure 5-4. Figure 5-4. Adding Instance to Wave Window 11. Now type Run-all to run the test component.This will take few minutes. 12. You will see different Waveform generated as shown in simulation waveform window. See Figure 5-5. , Figure 5-6., Figure 5-7. • This behavioral model is for the host. Host resets the device and waits for Chirp K from the device to start speed negotiation. You will see a message on the ModelSim-Altera 6.3g_p1 console. • After that host sends the chirp sequence(KJKJKJ) for the speed negotiation with the device in the reset mode. See Figure 5-5. • Later then, word enumeration process will start. In enumeration process host grabes the necessary information about the descriptors from the device for further communication.See Figure 5-6.(host reads 1st descriptor.) 58 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 • In data Transfer mode(Bulk Out) host transfers 4 byte address (00220000) and 4byte data(11223344) with write operation opcode for port interface application to the device See Figure 5-7. Figure 5-5. Simulation Waveform Window-showing Sending of Chirp Sequence Figure 5-6. Simulation Waveform Window-Showing reading of 1st descriptor System Level Solutions June 2009 59 Designing & Simulating the USB20HR System from Scratch Tutorial Building and Managing the Project Figure 5-7. Simulation Waveform Window-Data Transfer Mode You have learned here the steps for simulating the system with USB20HR IP, acting as an avalon slave, and Nios II processor acting as an avalon master. Similarly, you can simulate and verify your own system. 60 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Appendix A: Pin Assignments for CoreCommander Board (3C25) Table 5-1 shows the pin assignments for the CoreCommander Board (3C25). Table 5-1. Pin Assignments for the CoreCommander Board (3C25) FPGA Pin No. Pin Name PIN_E1 PIN_B14 sdr_clk PIN_E2 reset_n PIN_D6 tri_addr[0] PIN_J15 tri_addr[1] PIN_D1 tri_addr[2] PIN_F2 tri_addr[3] PIN_F1 tri_addr[4] PIN_C2 tri_addr[5] PIN_B1 tri_addr[6] PIN_A2 tri_addr[7] PIN_B3 tri_addr[8] PIN_A3 tri_addr[9] PIN_D5 tri_addr[10] PIN_B4 tri_addr[11] PIN_A4 tri_addr[12] PIN_A12 tri_addr[13] PIN_A5 tri_addr[14] PIN_B5 tri_addr[15] PIN_T4 tri_addr[16] PIN_N9 tri_addr[17] PIN_A14 System Level Solutions June 2009 osc_clk tri_addr[18] 61 Designing & Simulating the USB20HR System from Scratch Tutorial Table 5-1. Pin Assignments for the CoreCommander Board (3C25) FPGA Pin No. Pin Name PIN_P8 tri_addr[19] PIN_T12 tri_addr[20] PIN_J1 tri_addr[21] PIN_T13 tri_addr[22] PIN_G2 tri_be_n[0] PIN_F3 tri_be_n[1] PIN_J2 sdr_ba[0] PIN_A10 sdr_ba[1] PIN_P16 tri_data[0] PIN_D16 tri_data[1] PIN_C16 tri_data[2] PIN_F15 tri_data[3] PIN_D15 tri_data[4] PIN_D14 tri_data[5] PIN_C14 tri_data[6] PIN_B13 tri_data[7] PIN_B6 tri_data[8] PIN_A6 tri_data[9] PIN_B7 tri_data[10] PIN_A7 tri_data[11] PIN_D9 tri_data[12] PIN_C9 tri_data[13] PIN_B11 tri_data[14] PIN_A11 tri_data[15] PIN_G1 fl_ce_n PIN_K1 fl_we_n PIN_D8 fl_oe_n PIN_B10 sdr_cs_n 62 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 Table 5-1. Pin Assignments for the CoreCommander Board (3C25) FPGA Pin No. Pin Name PIN_B12 sdr_we_n PIN_C6 sdr_cas_n PIN_C8 sdr_ras_n PIN_P15 user_led[1] PIN_F16 user_led[0] USB Interface PIN_P14 PIN_T10 u20_clk_out PIN_R16 u20_reset_n PIN_T9 u20_dir PIN_R9 u20_nxt PIN_R14 u20_cs_n PIN_R12 u20_stp PIN_N12 u20_d[7] PIN_N11 u20_d[6] PIN_P11 u20_d[5] PIN_R13 u20_d[4] PIN_R10 u20_d[3] PIN_T11 u20_d[2] PIN_R11 u20_d[1] PIN_P9 System Level Solutions June 2009 u20_clk_in u20_d[0] 63 Designing & Simulating the USB20HR System from Scratch Tutorial 64 Designing & Simulating the USB20HR System from Scratch Tutorial System Level Solutions June 2009 ...
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This note was uploaded on 02/01/2012 for the course ING 101 taught by Professor James during the Spring '11 term at Universidad del Cauca.

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