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ug_rldram_ii - RLDRAM II Controller MegaCore Function User...

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101 Innovation Drive San Jose, CA 95134 www.altera.com RLDRAM II Controller MegaCore Function User Guide MegaCore Version: 9.1 Document Date: November 2009
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Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des- ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap- plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in- formation and before placing orders for products or services . ii MegaCore Version 9.1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide UG-RLDRAM-8.1
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Altera Corporation MegaCore Version 9.1 iii Contents Chapter 1. About This MegaCore Function Release Information ............................................................................................................................... 1–1 Device Family Support ......................................................................................................................... 1–1 Features ................................................................................................................................................... 1–2 General Description ............................................................................................................................... 1–2 OpenCore Plus Evaluation .............................................................................................................. 1–4 Performance and Resource Utilization ............................................................................................... 1–4 Chapter 2. Functional Description Block Description ................................................................................................................................... 2–1 Control Logic .................................................................................................................................... 2–2 Datapath ............................................................................................................................................ 2–3 Timing Assignments ...................................................................................................................... 2–12 OpenCore Plus Time-Out Behavior ............................................................................................. 2–13 Device-Level Configuration ............................................................................................................... 2–13 PLL Configuration ......................................................................................................................... 2–13 Example Design .............................................................................................................................. 2–15 Constraints ...................................................................................................................................... 2–17 Interfaces ............................................................................................................................................... 2–17 Initialization .................................................................................................................................... 2–17 Writes ............................................................................................................................................... 2–18 Reads ................................................................................................................................................ 2–20 Refreshes .......................................................................................................................................... 2–22 Signals ................................................................................................................................................... 2–23 Parameters ............................................................................................................................................ 2–28 Memory ............................................................................................................................................ 2–29 Timing .............................................................................................................................................. 2–31 Project Settings ................................................................................................................................ 2–32 MegaCore Verification ........................................................................................................................ 2–33 Simulation Environment ............................................................................................................... 2–33 Hardware Testing ........................................................................................................................... 2–33 Chapter 3. Getting Started Design Flow ............................................................................................................................................ 3–1 RLDRAM II Controller Walkthrough ................................................................................................. 3–2 Create a New Quartus II Project .................................................................................................... 3–3 Launch IP Toolbench ....................................................................................................................... 3–4 Step 1: Parameterize ......................................................................................................................... 3–5 Step 2: Constraints ............................................................................................................................ 3–7 Step 3: Set Up Simulation ................................................................................................................ 3–8 Step 4: Generate ................................................................................................................................ 3–8
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iv MegaCore Version 9.1 Altera Corporation RLDRAM II Controller MegaCore Function User Guide Contents Simulate the Example Design ............................................................................................................ 3–11 Simulate with IP Functional Simulation Models ....................................................................... 3–11 Simulating in Third-Party Simulation Tools Using NativeLink ............................................. 3–12 Edit the PLL .......................................................................................................................................... 3–13 Compile the Example Design ............................................................................................................ 3–14 Program a Device ................................................................................................................................ 3–15 Implement Your Design ..................................................................................................................... 3–15 Set Up Licensing .................................................................................................................................. 3–15 Additional Information Revision History ......................................................................................................................................... i How to Contact Altera ............................................................................................................................... i Typographic Conventions ....................................................................................................................... ii
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Altera Corporation MegaCore Version 9.1 1–1 November 2009 1. About This MegaCore Function Release Information Table 1–1
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