wp_ddr_sdram_efficiency

wp_ddr_sdram_efficiency - White Paper The Efficiency of the...

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® White Paper The Efficiency of the DDR & DDR2 SDRAM Controller Compiler December 2004, ver. 1.1 1 WP-IPDDR-1.1 Introduction This white paper on the efficiency of the Altera ® DDR & DDR2 SDRAM Controller Compiler discusses the follow- ing topics: “Bandwidth” on page 1 “Efficiency—Worst-Case Scenario” on page 1 “Efficiency—Best-Case Scenario” on page 1 “The Effect of Refresh” on page 2 “Read Latency” on page 2 “An Application Example” on page 2 “Increase the Efficiency” on page 3 Bandwidth Improving the efficiency of either the DDR or DDR2 SDRAM controller improves the bandwidth. The maximum bandwidth for a desired situation is given by: Bandwidth = DDR SDRAM bus width × 2 × frequency of operation × efficiency For example, running a 16-bit DDR SDRAM interface at a frequency of 100 MHz: Bandwidth = 16 bits × 2 clock edges × 100 MHz × efficiency The Altera DDR or DDR2 SDRAM controller can be up to 90% efficient depending on the conditions—it can be as low as 10%. Therefore the maximum bandwidth is given by: bandwidth = 3.2 Gbps × 0.9 = 2.88 Gbps Efficiency—Worst-Case Scenario The worst-case scenario arises when the DDR or DDR2 SDRAM controller is swapping between writes and reads and simultaneously addressing is forcing a row to be opened and closed on every transaction. Assuming that the address bus is in the default order—chip select, bank, row, column—so 4,096 is above bit 10, the column boundary, write to address 0, read from address 4,096, then write to address 1, and read from address 4,097 etc.
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This note was uploaded on 02/01/2012 for the course ING 101 taught by Professor James during the Spring '11 term at Universidad del Cauca.

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wp_ddr_sdram_efficiency - White Paper The Efficiency of the...

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