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fs10_mt - pci_mt64 MegaCore Function Reference Design...

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Altera Corporation 1 pci_mt64 MegaCore Function Reference Design September 2003, ver. 1.2 Functional Specification 10 FS-10-1.2 Features Provides an interface between the Altera pci_mt64 MegaCore ® function and a 64-bit, 32-MByte SDRAM module Supports 32- and 64-bit PCI master and target transactions Supports chaining and non-chaining mode DMA Uses the dual-port FIFO buffer function from the library of parameterized modules (LPM) Uses the SDR SDRAM controller MegaCore function General Description This reference design shows how to connect the local-side signals of the Altera ® pci_mt64 MegaCore function to local-side applications when the MegaCore function is used as a master or target on the PCI bus. Figure 1 shows a high-level block diagram of the reference design. The reference design consists of the following elements: Master control logic Target control logic DMA engine Data path FIFO buffer functions SDRAM interface
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2 Altera Corporation Functional Specification 10: pci_mt64 MegaCore Function Reference Design Figure 1. Block Diagram Master Control Logic When the pci_mt64 function is acts as a master, the master control logic interacts with the DMA engine to control the PCI master transactions. During a PCI master write, the data flows from the local master to the PCI bus. The master control logic: Provides status of the PCI bus to the DMA engine Interacts with the pci_mt64 function to execute a PCI master write cycle Transfers the data from the SDRAM-to-PCI FIFO buffer to the pci_mt64 function During a PCI master read, the data flows from the PCI bus to the local master. The master control logic: Provides the status of the PCI bus to the DMA engine Interacts with the PCI function to execute the PCI master read cycle Buffers the data read by the pci_mt64 function into the PCI-to- SDRAM FIFO buffer Parameterized Configuration Registers Local Master Control Local Address/ Data/ Command/ Byte Enable Local Target Control Master Control Logic Target Control Logic PCI to SDRAM FIFO Data Mask FIFO SDRAM Controller SDRAM Module pci_mt64 Reference Design PCI Bus Interface PCI Bus Data Path FIFOs SDRAM to PCI FIFO DMA Control Logic DMA Registers DMA Descriptor FIFO DMA Engine
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Altera Corporation 3 Functional Specification 10: pci_mt64 MegaCore Function Reference Design Target Control Logic When the PCI function acts as a target, the pci_mt64 function prompts the target control logic to execute target transactions. During a PCI target write, the data flows from PCI bus to the local target. The target control logic: Interacts with the pci_mt64 function to execute a PCI target write Buffers the data—written by the host or the master on the PCI bus— into the PCI-to-SDRAM FIFO buffer Interacts with the SDRAM controller to read data from the PCI-to- SDRAM FIFO buffer and write into the SDRAM During a PCI target read, the data flows from local target to the PCI bus.
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