PLL-5ManeatisClockGeneratorLowJitter

PLL-5ManeatisClockGeneratorLowJitter - Self-Biased,...

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Self-Biased, High-Bandwidth, Low- Jitter 1-to-4096 Multiplier Clock Generator PLL Based on a presentation by: John G. Maneatis 1 , Jaeha Kim 1 , Iain McClatchie 1 , Jay Maxey 2 , Manjusha Shankaradas 2 True Circuits, Los Altos, CA 1 Texas Instruments, Dallas, TX 2 PDF file of JSSC paper linked at class web page.
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2 Clock Generator PLLs for ASICs Most ASICs PLLs for clock generation, but … Use different frequencies and multiplication Graphics Processor Network Processor I/O Controller Your ASIC ÷ N F REF F OUT PLL
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3 Optimal PLL Design For each F OUT and N, one must adjust loop parameters for both minimum jitter and stability For clock generators (track input clocks) ( ϖ REF = 2 π ·F OUT /N) Loop bandwidth : ϖ N ~ ϖ REF /20 Damping ratio : ζ ~ 1 Third-order pole : ϖ C ~ ϖ REF /2 Circuit parameters (e.g. I CH , R) must vary with F OUT and N!
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4 Addressing Diverse Specifications Designing a different PLL for each ASIC Easier to meet the specification, but … Verifying all designs is difficult and costly Our Goal: One PLL design for all ASICs Only one design needs verification, but … Loop parameters must adjust automatically to satisfy wide range of F OUT and N
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5 Challenges Self-biased PLLs [Maneatis ‘96] adjust for F OUT Achieve fixed ϖ N / ϖ REF and ζ indep. of PVT But, Self-Biased PLLs do NOT adjust for N ϖ N / ϖ REF and ζ vary with N (want fixed) ϖ C / ϖ REF varies with N (want fixed) This talk extends Self-Biased PLLs for wide ranges of N with a new loop filter network
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6 Outline Introduction Review of Self-Biased PLLs Pattern Jitter Issues Loop Filter Architecture Implementation of Key Circuits Measured Results Conclusions
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7 Second-Order PLLs PFD CP I CH V CTL ÷ N CK OUT CK REF CK FB UP DN C 1 R VCO K V 2 N N N I O ) / s ( ) / s ( 2 1 ) / s ( 2 1 N ) s ( P ) s ( P ϖ ϖ ζ ϖ ζ + + + = 1 C R 2 1 N = ϖ ζ 1 V CH C 1 K I N 1 N = ϖ
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8 Second-Order PLLs PFD CP I CH V CTL ÷ N CK OUT CK REF CK FB UP DN C 1 R VCO K V ) 1 ( R CS I V CH CTL + = Oscillation frequency is supposed to be controlled by V CTL , that is by I CH /CS + I CH *R. In Ring Oscillators, frequency is more easily controlled by
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PLL-5ManeatisClockGeneratorLowJitter - Self-Biased,...

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