EE2730 Syllabus

EE2730 Syllabus - 50 Final(Wednesday 12/14 10:00AM 30...

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EE 2730 Digital Logic II Fall 2005 Instructor: Gabriel A. de Souza Room 313 EE Building, Ph: 578-4831, email: [email protected] Office hours: 9:00 – 10:30 MTWTh TA: Tong Wang Desk 22 Room 146 EE Building, Ph: 578-5486, email: [email protected] Office hours: 11:30-2:00 T TH Course Description: This course introduces the student to the analysis and design of sequential logic circuits. Prerequisites: EE2720. Text: John F. Wakerly, rd Ed.) 2000. Grading Policy: 2 Tests (Wednesday, 10/05, and Wednesday, 11/23.):
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Unformatted text preview: 50% Final (Wednesday, 12/14 @ 10:00AM): 30% Homework/Quizzes: 20% Policy on Exams: Make-ups on Exams are allowed under extenuating circumstances. Policy on Quizzes and Homework: There will be no make-up quizzes or homework due to the fact that one or more of the lowest grades will be dropped. The student will be given the opportunity to submit late homework until the first class after the homework’s due date. Late homework will be penalized 10% of the original maximum grade for each day it is late....
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