ADSP_B52x Blackfin Processor Hardware Reference

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Unformatted text preview: ADSP-BF52x Blackfin® Processor Hardware Reference Revision 1.0, March 2010 Part Number 82-000525 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a C opyright Information © 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. C ONTENTS PREFACE Purpose of This Manual ................................................................ lix Intended Audience ........................................................................ lix What’s New in This Manual ........................................................... lx Technical or Customer Support ....................................................... lx Product Information ...................................................................... lxi Analog Devices Web Site .......................................................... lxi VisualDSP++ Online Documentation ..................................... lxi Technical Library CD ............................................................. lxii Social Networking Web Sites ................................................. lxiii Notation Conventions ................................................................. lxiii INTRODUCTION Manual Contents .......................................................................... 1-1 Peripherals .................................................................................... 1-5 Memory Architecture .................................................................... 1-7 Internal Memory ..................................................................... 1-9 External Memory .................................................................... 1-9 I/O Memory Space .................................................................. 1-9 ADSP-BF52x Blackfin Processor Hardware Reference iii Contents One-Time-Programmable (OTP) Memory ............................. 1-10 DMA Support ............................................................................ 1-11 External Bus Interface Unit ......................................................... 1-12 SDRAM Controller ............................................................... 1-12 Asynchronous Controller ...................................................... 1-13 Ports .......................................................................................... 1-13 General-Purpose I/O (GPIO) ................................................ 1-13 Two-Wire Interface ..................................................................... 1-15 Ethernet MAC ............................................................................ 1-16 Parallel Peripheral Interface ......................................................... 1-16 SPORT Controllers .................................................................... 1-18 Serial Peripheral Interface (SPI) Port ........................................... 1-20 Timers ....................................................................................... 1-20 UART Ports ............................................................................... 1-21 Security ...................................................................................... 1-22 Real-Time Clock ........................................................................ 1-23 Watchdog Timer ......................................................................... 1-24 Clock Signals .............................................................................. 1-25 Dynamic Power Management ..................................................... 1-26 Full-On Mode (Maximum Performance) ................................ 1-26 Active Mode (Moderate Power Savings) ................................. 1-26 Sleep Mode (High Power Savings) ......................................... 1-26 Deep Sleep Mode (Maximum Power Savings) ........................ 1-27 Hibernate State .................................................................... 1-27 iv ADSP-BF52x Blackfin Processor Hardware Reference Contents Voltage Regulation ...................................................................... 1-27 Instruction Set Description ......................................................... 1-28 Development Tools ..................................................................... 1-29 CHIP BUS HIERARCHY Overview ...................................................................................... 2-1 Interface Overview ........................................................................ 2-3 Internal Clocks ........................................................................ 2-3 Core Bus Overview .................................................................. 2-4 Peripheral Access Bus (PAB) ..................................................... 2-6 PAB Arbitration .................................................................. 2-6 PAB Agents (Masters, Slaves) ............................................... 2-6 PAB Performance ................................................................ 2-7 DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB) .................................................... 2-8 DAB, DCB, DEB Arbitration ............................................. 2-8 DCB Sharing ...................................................................... 2-9 Using the CDPRIO Bit to Change Priorities .................. 2-13 DAB Bus Agents (Masters) ................................................ 2-13 DAB, DCB, and DEB Performance ................................... 2-14 External Access Bus (EAB) ..................................................... 2-14 Arbitration of the External Bus .............................................. 2-15 DEB/EAB Performance ......................................................... 2-15 MEMORY Memory Architecture .................................................................... 3-1 ADSP-BF52x Blackfin Processor Hardware Reference v Contents L1 Instruction SRAM ................................................................... 3-3 L1 Data SRAM ............................................................................ 3-4 L1 Data Cache ............................................................................. 3-4 Boot ROM ................................................................................... 3-5 External Memory .......................................................................... 3-5 Processor-Specific MMRs .............................................................. 3-5 DMEM_CONTROL Register ................................................. 3-6 DTEST_COMMAND Register .............................................. 3-6 ONE-TIME PROGRAMMABLE MEMORY OTP Memory Overview ............................................................... 4-1 OTP Memory Map ...................................................................... 4-2 Error Correction ........................................................................... 4-7 Error Correction Policy ........................................................... 4-8 OTP Access ................................................................................ 4-10 OTP Timing Parameters ....................................................... 4-12 Timing for the ADSP-BF523/525/527 Processors .............. 4-13 Timing for the ADSP-BF522/524/526 Processors .............. 4-14 OTP_TIMING Register ................................................... 4-17 Callable ROM Functions for OTP ACCESS .......................... 4-17 Initializing OTP ............................................................... 4-17 bfrom_OtpCommand ................................................... 4-17 Programming and Reading OTP ....................................... 4-19 bfrom_OtpRead ........................................................... 4-20 bfrom_OtpWrite .......................................................... 4-21 vi ADSP-BF52x Blackfin Processor Hardware Reference Contents Error Codes .................................................................. 4-24 Write-protecting OTP Memory ......................................... 4-25 Accessing Private OTP Memory ........................................ 4-28 OTP Programming Examples ...................................................... 4-28 SYSTEM INTERRUPTS Specific Information for the ADSP-BF52x ..................................... 5-1 Overview ...................................................................................... 5-1 Features ................................................................................... 5-2 Description of Operation .............................................................. 5-2 Events and Sequencing ............................................................ 5-2 System Peripheral Interrupts .................................................... 5-4 Programming Model ..................................................................... 5-7 System Interrupt Initialization ................................................. 5-8 System Interrupt Processing Summary ...................................... 5-8 System Interrupt Controller Registers .......................................... 5-10 System Interrupt Assignment (SIC_IAR) Register ................... 5-11 System Interrupt Mask (SIC_IMASK) Register ...................... 5-12 System Interrupt Status (SIC_ISR) Register ........................... 5-12 System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 5-12 Programming Examples ............................................................... 5-13 Clearing Interrupt Requests ................................................... 5-13 Unique Behavior for the ADSP-BF52x Processor ......................... 5-15 Interfaces .............................................................................. 5-15 System Peripheral Interrupts .................................................. 5-18 ADSP-BF52x Blackfin Processor Hardware Reference vii Contents DIRECT MEMORY ACCESS Specific Information for the ADSP-BF52x .................................... 6-1 Overview and Features .................................................................. 6-2 DMA Controller Overview ........................................................... 6-4 External Interfaces .................................................................. 6-4 Internal Interfaces ................................................................... 6-5 Peripheral DMA ...................................................................... 6-6 Memory DMA ........................................................................ 6-7 Handshaked Memory DMA (HMDMA) Mode ................... 6-9 Modes of Operation ................................................................... 6-10 Register-Based DMA Operation ............................................ 6-10 Stop Mode ....................................................................... 6-11 Autobuffer Mode .............................................................. 6-12 Two-Dimensional DMA Operation ....................................... 6-12 Examples of Two-Dimensional DMA ................................ 6-13 Descriptor-based DMA Operation ......................................... 6-14 Descriptor List Mode ........................................................ 6-15 Descriptor Array Mode ..................................................... 6-16 Variable Descriptor Size .................................................... 6-16 Mixing Flow Modes .......................................................... 6-17 Functional Description ............................................................... 6-18 DMA Operation Flow ........................................................... 6-18 DMA Startup ................................................................... 6-18 DMA Refresh ................................................................... 6-23 viii ADSP-BF52x Blackfin Processor Hardware Reference Contents Work Unit Transitions ...................................................... 6-25 DMA Transmit and MDMA Source .............................. 6-26 DMA Receive ............................................................... 6-27 Stopping DMA Transfers ................................................... 6-29 DMA Errors (Aborts) ............................................................ 6-29 DMA Control Commands ..................................................... 6-32 Restrictions ....................................................................... 6-35 Transmit Restart or Finish ............................................. 6-35 Receive Restart or Finish ............................................... 6-36 Handshaked Memory DMA Operation .................................. 6-37 Pipelining DMA Requests ................................................. 6-38 HMDMA Interrupts ......................................................... 6-41 DMA Performance ................................................................ 6-42 DMA Throughput ............................................................ 6-43 Memory DMA Timing Details .......................................... 6-45 Static Channel Prioritization ............................................ 6-46 Temporary DMA Urgency ................................................. 6-46 Memory DMA Priority and Scheduling ............................. 6-48 Traffic Control .................................................................. 6-49 Programming Model .................................................................. 6-51 Synchronization of Software and DMA .................................. 6-52 Single-Buffer DMA Transfers ............................................ 6-54 Continuous Transfers Using Autobuffering ........................ 6-54 Descriptor Structures ........................................................ 6-57 ADSP-BF52x Blackfin Processor Hardware Reference ix Contents Descriptor Queue Management ........................................ 6-58 Descriptor Queue Using Interrupts on Every Descriptor 6-58 Descriptor Queue Using Minimal Interrupts ................. 6-60 Software Triggered Descriptor Fetches ............................... 6-62 DMA Registers ........................................................................... 6-64 DMA Channel Registers ........................................................ 6-64 DMA Peripheral Map Registers(DMAx_PERIPHERAL_MAP/ MDMA_yy_PERIPHERAL_MAP) ............................... 6-68 DMA Configuration Registers (DMAx_CONFIG/MDMA_yy_CONFIG) ................... 6-68 DMA Interrupt Status Registers (DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ..... 6-73 DMA Start Address Registers (DMAx_START_ADDR/MDMA_yy_START_ADDR) . 6-76 DMA Current Address Registers (DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) ... 6-76 DMA Inner Loop Count Registers (DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 6-77 DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT /MDMA_yy_CURR_X_COUNT) ................................ 6-78 DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 6-79 DMA Outer Loop Count Registers (DMAx_Y_COUNT/MDMA_yy_Y_COUNT) ............. 6-80 DMA Current Outer Loop Count Registers (DMAx_CURR_Y_COUNT/ MDMA_yy_CURR_Y_COUNT) .................................. 6-81 x ADSP-BF52x Blackfin Processor Hardware Reference Contents DMA Outer Loop Address Increment Registers (DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ............ 6-81 DMA Next Descriptor Pointer Registers (DMAx_NEXT_DESC_PTR/ MDMA_yy_NEXT_DESC_PTR) .................................. 6-82 DMA Current Descriptor Pointer Registers (DMAx_CURR_DESC_PTR/ MDMA_yy_CURR_DESC_PTR) .................................. 6-83 HMDMA Registers ............................................................... 6-84 Handshake MDMA Control Registers (HMDMAx_CONTROL) 6-84 Handshake MDMA Initial Block Count Registers (HMDMAx_BCINIT) ................................................... 6-87 Handshake MDMA Current Block Count Registers (HMDMAx_BCOUNT) ................................................ 6-87 Handshake MDMA Current Edge Count Registers (HMDMAx_ECOUNT) ................................................ 6-88 Handshake MDMA Initial Edge Count Registers (HMDMAx_ECINIT) ................................................... 6-89 Handshake MDMA Edge Count Urgent Registers (HMDMAx_ECURGENT) ............................................ 6-89 Handshake MDMA Edge Count Overflow Interrupt Registers (HMDMAx_ECOVERFLOW) ........................ 6-90 DMA Traffic Control Registers (DMA_TC_PER and DMA_TC_CNT) .............................. 6-90 DMA_TC_PER Register ................................................... 6-91 DMA_TC_CNT Register ................................................. 6-92 Programming Examples ............................................................... 6-93 ADSP-BF52x Blackfin Processor Hardware Reference xi Contents Register-Based 2-D Memory DMA ........................................ 6-94 Initializing Descriptors in Memory ........................................ 6-97 Software-Triggered Descriptor Fetch Example ...................... 6-100 Handshaked Memory DMA Example .................................. 6-102 Unique Behavior for the ADSP-BF52x Processor ....................... 6-105 Static Channel Prioritization ............................................... 6-106 DMA Control Commands .................................................. 6-107 Handshaked Memory DMA Operation ................................ 6-107 HMDMA Interrupts ....................................................... 6-107 EXTERNAL BUS INTERFACE UNIT EBIU Overview ............................................................................ 7-1 Block Diagram ........................................................................ 7-4 Internal Memory Interfaces ..................................................... 7-5 Registers ................................................................................. 7-6 Shared Pins ............................................................................. 7-6 System Clock .......................................................................... 7-7 Error Detection ....................................................................... 7-7 AMC Overview and Features ........................................................ 7-7 Features .................................................................................. 7-8 Asynchronous Memory Interface ............................................. 7-8 Asynchronous Memory Address Decode .............................. 7-9 AMC Pin Description ................................................................... 7-9 AMC Description of Operation .................................................. 7-10 Avoiding Bus Contention ...................................................... 7-10 xii ADSP-BF52x Blackfin Processor Hardware Reference Contents External Access Extension .................................................. 7-11 AMC Functional Description ...................................................... 7-11 Programmable Timing Characteristics .................................... 7-11 Asynchronous Reads ......................................................... 7-11 Asynchronous Writes ......................................................... 7-13 Adding External Access Extension ..................................... 7-15 Byte Enables .......................................................................... 7-17 AMC Programming Model .......................................................... 7-17 AMC Registers ............................................................................ 7-19 EBIU_AMGCTL Register ..................................................... 7-20 EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ............... 7-20 AMC Programming Examples ..................................................... 7-23 SDC Overview and Features ........................................................ 7-24 Features ................................................................................. 7-24 SDRAM Configurations Supported ....................................... 7-25 SDRAM External Bank Size ................................................... 7-26 SDC Address Mapping .......................................................... 7-26 Internal SDRAM Bank Select ................................................ 7-27 Parallel Connection of SDRAMs ............................................ 7-28 SDC Interface Overview ............................................................. 7-28 SDC Pin Description ............................................................. 7-29 SDRAM Performance ............................................................ 7-30 SDC Description of Operation .................................................... 7-31 Definition of SDRAM Architecture Terms ............................. 7-31 ADSP-BF52x Blackfin Processor Hardware Reference xiii Contents Refresh ............................................................................. 7-31 Row Activation ................................................................. 7-31 Column Read/Write ......................................................... 7-31 Row Precharge .................................................................. 7-31 Internal Bank ................................................................... 7-32 External Bank ................................................................... 7-32 Memory Size .................................................................... 7-32 Burst Length .................................................................... 7-32 Burst Type ........................................................................ 7-32 CAS Latency .................................................................... 7-33 Data I/O Mask Function .................................................. 7-33 SDRAM Commands ........................................................ 7-33 Mode Register Set (MRS) command ................................. 7-33 Extended Mode Register Set (EMRS) command ................ 7-33 Bank Activate command ................................................... 7-33 Read/Write command ....................................................... 7-34 Precharge/Precharge All Command ................................... 7-34 Auto-refresh command ..................................................... 7-34 Enter Self-Refresh Mode ................................................... 7-34 Exit Self-Refresh Mode ..................................................... 7-34 SDC Timing Specifications ................................................... 7-35 tMRD ................................................................................ 7-35 tRAS ................................................................................. 7-35 tCL ................................................................................... 7-35 xiv ADSP-BF52x Blackfin Processor Hardware Reference Contents tRCD ................................................................................. 7-36 tRRD ................................................................................. 7-36 tWR .................................................................................. 7-36 tRP .................................................................................... 7-36 tRC ................................................................................... 7-37 tRFC ................................................................................. 7-37 tXSR .................................................................................. 7-37 tREF .................................................................................. 7-37 tREFI ................................................................................. 7-38 SDC Functional Description ....................................................... 7-38 SDC Operation .................................................................... 7-38 SDC Address Muxing ........................................................ 7-41 Multibank Operation ........................................................ 7-42 Core and DMA Arbitration ............................................... 7-43 Changing System Clock During Runtime .......................... 7-44 Changing Power Management During Runtime ................. 7-45 Deep Sleep Mode .......................................................... 7-45 Hibernate State ............................................................. 7-45 SDC Commands ................................................................... 7-46 Mode Register Set Command ............................................ 7-47 Extended Mode Register Set Command (Mobile SDRAM) 7-48 Bank Activation Command ............................................... 7-49 Read/Write Command ...................................................... 7-49 ADSP-BF52x Blackfin Processor Hardware Reference xv Contents Write Command With Data Mask .................................... 7-50 Single Precharge Command .............................................. 7-51 Precharge All Command ................................................... 7-51 Auto-Refresh Command ................................................... 7-51 Self-Refresh Mode ............................................................ 7-52 Self-Refresh Entry Command ................................... 7-52 Self-Refresh Exit Command ..................................... 7-52 No Operation Command .................................................. 7-53 SDC SA10 Pin ...................................................................... 7-54 SDC Programming Model .......................................................... 7-54 SDC Configuration .............................................................. 7-54 Example SDRAM System Block Diagrams ............................. 7-56 SDC Register Definitions ........................................................... 7-59 EBIU_SDRRC Register ........................................................ 7-59 EBIU_SDBCTL Register ...................................................... 7-61 Using SDRAMs With Systems Smaller than 16M byte ....... 7-63 EBIU_SDGCTL Register ...................................................... 7-65 SDRAM clock enable (SCTLE) ....................................... 7-65 CAS latency (CL) ............................................................ 7-67 Partial array self refresh (PASR) ........................................ 7-67 Bank activate command delay (TRAS) ............................. 7-68 Bank precharge delay (TRP) ............................................ 7-68 RAS to CAS delay (TRCD) ............................................. 7-68 Write to precharge delay (TWR) ....................................... 7-69 xvi ADSP-BF52x Blackfin Processor Hardware Reference Contents Power-Up Start Delay (PUPSD) ........................................ 7-69 Power-Up Sequence Mode (PSM) ...................................... 7-70 Power-Up Sequence Start Enable (PSSE) .......................... 7-70 Self-Refresh Setting (SRFS) .............................................. 7-71 Enter Self-Refresh Mode ................................................ 7-71 Exit Self-Refresh Mode .................................................. 7-72 External buffering enabled (EBUFE) ................................ 7-72 Fast Back-to-Back Read to Write (FBBRW) ....................... 7-73 Extended Mode Register Enabled (EMREN) ..................... 7-73 Temperature Compensated Self-Refresh (TCSR) ................ 7-74 EBIU_SDSTAT Register ........................................................ 7-74 SDC Programming Examples ...................................................... 7-76 HOST DMA PORT Overview ...................................................................................... 8-1 Features ........................................................................................ 8-2 Interface Overview ........................................................................ 8-3 Description of Operation .............................................................. 8-3 Architecture ............................................................................ 8-4 Functional Description ............................................................ 8-5 HOSTDP Configuration .................................................... 8-5 HOSTDP Transactions ....................................................... 8-7 Host Read Status ............................................................. 8-8 Host Read Data and Host Write Data Operations ............ 8-9 HOSTDP Modes of Operation ......................................... 8-10 ADSP-BF52x Blackfin Processor Hardware Reference xvii Contents Acknowledge Mode ...................................................... 8-11 Acknowledge Mode Timing Diagrams ...................... 8-11 Host Bus Timeout .................................................... 8-13 Interrupt Mode ............................................................. 8-14 DMA STOP Mode and AUTOBUFFER Mode ................. 8-16 Bus Widths and Endian Order .......................................... 8-16 Access Control .................................................................. 8-17 Improving HOSTDP DMA Bus Bandwidth ...................... 8-18 Control Commands Between the External Host and HOSTDP ......................................... 8-19 Programming Model ................................................................... 8-21 Host DMA Port Registers ........................................................... 8-26 HOSTDP Control (HOST_CONTROL) Register ................ 8-26 HOSTDP Status (HOST_STATUS) Register ........................ 8-28 HOSTDP Timeout (HOST_TIMEOUT) Register ................ 8-31 Programming Examples .............................................................. 8-32 GENERAL-PURPOSE PORTS Overview ...................................................................................... 9-1 Features ........................................................................................ 9-2 Interface Overview ....................................................................... 9-3 External Interface .................................................................... 9-4 Port F Structure .................................................................. 9-4 Port G Structure ................................................................. 9-5 Port H Structure ................................................................. 9-7 xviii ADSP-BF52x Blackfin Processor Hardware Reference Contents Port J Structure ................................................................... 9-9 Input Tap Considerations .................................................... 9-9 Internal Interfaces ................................................................. 9-10 Internal Signals ................................................................. 9-10 Performance/Throughput ...................................................... 9-11 Description of Operation ............................................................ 9-12 Operation ............................................................................. 9-12 General-Purpose I/O Modules ............................................... 9-13 GPIO Interrupt Processing .................................................... 9-16 Programming Model ................................................................... 9-22 GPIO Drive Hysteresis Control ................................................... 9-24 Portx Control (PORTx_HYSTERESIS) Register .................... 9-24 Hysteresis Control Register .................................................... 9-26 TWI Drive Strength Control Register .......................................... 9-27 Memory-Mapped GPIO Registers ............................................... 9-27 Port Multiplexer Control Register (PORTx_MUX) ................ 9-28 Function Enable Registers (PORTx_FER) .............................. 9-30 GPIO Direction Registers (PORTxIO_DIR) .......................... 9-31 GPIO Input Enable Registers (PORTxIO_INEN) .................. 9-32 GPIO Data Registers (PORTxIO) .......................................... 9-32 GPIO Set Registers (PORTxIO_SET) .................................... 9-33 GPIO Clear Registers (PORTxIO_CLEAR) ........................... 9-33 GPIO Toggle Registers (PORTxIO_TOGGLE) ...................... 9-34 GPIO Polarity Registers (PORTxIO_POLAR) ....................... 9-34 ADSP-BF52x Blackfin Processor Hardware Reference xix Contents Interrupt Sensitivity Registers (PORTxIO_EDGE) ................ 9-35 GPIO Set on Both Edges Registers (PORTxIO_BOTH) ........ 9-35 GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 9-36 GPIO Mask Interrupt Set Registers (PORTxIO_MASKA/B_SET) ............................................ 9-37 GPIO Mask Interrupt Clear Registers (PORTxIO_MASKA/B_CLEAR) ....................................... 9-39 GPIO Mask Interrupt Toggle Registers (PORTxIO_MASKA/B_TOGGLE) .................................... 9-41 Programming Examples .............................................................. 9-42 GENERAL-PURPOSE TIMERS Specific Information for the ADSP-BF52x .................................. 10-1 Overview .................................................................................... 10-2 External Interface .................................................................. 10-3 Internal Interface .................................................................. 10-4 Description of Operation ............................................................ 10-4 Interrupt Processing .............................................................. 10-5 Illegal States .......................................................................... 10-7 Modes of Operation ................................................................. 10-10 Pulse Width Modulation (PWM_OUT) Mode .................... 10-10 Output Pad Disable ........................................................ 10-12 Single Pulse Generation .................................................. 10-12 Pulse Width Modulation Waveform Generation .............. 10-13 PULSE_HI Toggle Mode ................................................ 10-15 Externally Clocked PWM_OUT ..................................... 10-20 xx ADSP-BF52x Blackfin Processor Hardware Reference Contents Using PWM_OUT Mode With the PPI .......................... 10-21 Stopping the Timer in PWM_OUT Mode ....................... 10-21 Pulse Width Count and Capture (WDTH_CAP) Mode ....... 10-23 Autobaud Mode .............................................................. 10-31 External Event (EXT_CLK) Mode ....................................... 10-31 Programming Model ................................................................. 10-33 Timer Registers ......................................................................... 10-34 Timer Enable Register (TIMER_ENABLE) .......................... 10-35 Timer Disable Register (TIMER_DISABLE) ........................ 10-36 Timer Status Register (TIMER_STATUS) ............................ 10-37 Timer Configuration Register (TIMER_CONFIG) .............. 10-40 Timer Counter Register (TIMER_COUNTER) ................... 10-41 Timer Period (TIMER_PERIOD) and Timer Width (TIMER_WIDTH) Registers ................................. 10-43 Summary ............................................................................ 10-46 Programming Examples ............................................................. 10-48 Unique Behavior for the ADSP-BF52x Processor ....................... 10-57 Interface Overview .............................................................. 10-58 External Interface ............................................................ 10-58 CORE TIMER Specific Information for the ADSP-BF52x ................................... 11-1 Overview and Features ................................................................ 11-1 Timer Overview .......................................................................... 11-2 External Interfaces ................................................................. 11-2 ADSP-BF52x Blackfin Processor Hardware Reference xxi Contents Internal Interfaces ................................................................. 11-3 Description of Operation ............................................................ 11-3 Interrupt Processing .............................................................. 11-3 Core Timer Registers .................................................................. 11-4 Core Timer Control Register (TCNTL) ................................. 11-5 Core Timer Count Register (TCOUNT) ............................... 11-5 Core Timer Period Register (TPERIOD) ............................... 11-6 Core Timer Scale Register (TSCALE) .................................... 11-7 Programming Examples .............................................................. 11-7 Unique Behavior for the ADSP-BF52x Processor ......................... 11-9 WATCHDOG TIMER Specific Information for the ADSP-BF52x .................................. 12-1 Overview and Features ................................................................ 12-1 Interface Overview ..................................................................... 12-3 External Interface .................................................................. 12-3 Internal Interface .................................................................. 12-3 Description of Operation ............................................................ 12-4 Register Definitions .................................................................... 12-5 Watchdog Count (WDOG_CNT) Register ........................... 12-5 Watchdog Status (WDOG_STAT) Register ........................... 12-6 Watchdog Control (WDOG_CTL) Register .......................... 12-7 Programming Examples .............................................................. 12-8 Unique Information for the ADSP-BF52x Processor .................. 12-11 xxii ADSP-BF52x Blackfin Processor Hardware Reference Contents GENERAL-PURPOSE COUNTER Specific Information for the ADSP-BF52x ................................... 13-1 Overview .................................................................................... 13-2 Features ...................................................................................... 13-2 Interface Overview ...................................................................... 13-3 Description of Operation ............................................................ 13-4 Quadrature Encoder Mode .................................................... 13-4 Binary Encoder Mode ............................................................ 13-5 Up/Down Counter Mode ...................................................... 13-6 Direction Counter Mode ....................................................... 13-7 Timed Direction Mode .......................................................... 13-7 Functional Description ............................................................... 13-7 Input Noise Filtering (Debouncing) ....................................... 13-8 Zero Marker (Push Button) Operation ................................... 13-9 Boundary Comparison Modes .............................................. 13-10 Control and Signaling Events ............................................... 13-12 Illegal Gray/Binary Code Events ...................................... 13-12 Up/Down Count Events .................................................. 13-12 Zero-Count Events ......................................................... 13-13 Overflow Events .............................................................. 13-13 Boundary Match Events .................................................. 13-13 Zero Marker Events ......................................................... 13-14 Capturing Timing Information ............................................ 13-14 ADSP-BF52x Blackfin Processor Hardware Reference xxiii Contents Capturing Time Interval Between Successive Counter Events ............................................ 13-15 Capturing Counter Interval and CNT_COUNTER Read Timing .................................. 13-16 Programming Model ................................................................. 13-18 Registers ................................................................................... 13-19 Counter Module Register Overview ..................................... 13-19 Counter Configuration Register (CNT_CONFIG) .............. 13-20 Counter Interrupt Mask Register (CNT_IMASK) ................ 13-20 Counter Status Register (CNT_STATUS) ............................ 13-21 Counter Command Register (CNT_COMMAND) ............. 13-22 Counter Debounce Register (CNT_DEBOUNCE) .............. 13-24 Counter Count Value Register (CNT_COUNTER) ............ 13-25 Counter Boundary Registers (CNT_MIN and CNT_MAX) . 13-26 Programming Examples ............................................................ 13-27 Unique Behavior for the ADSP-BF52x Processor ....................... 13-38 REAL-TIME CLOCK Specific Information for the ADSP-BF52x .................................. 14-1 Overview .................................................................................... 14-1 Interface Overview ..................................................................... 14-3 Description of Operation ............................................................ 14-4 RTC Clock Requirements ..................................................... 14-5 Prescaler Enable .................................................................... 14-5 RTC Programming Model .......................................................... 14-7 xxiv ADSP-BF52x Blackfin Processor Hardware Reference Contents Register Writes ...................................................................... 14-8 Write Latency ........................................................................ 14-9 Register Reads ..................................................................... 14-10 Deep Sleep .......................................................................... 14-10 Event Flags .......................................................................... 14-11 Setting Time of Day ............................................................ 14-13 Using the Stopwatch ............................................................ 14-13 Interrupts ............................................................................ 14-14 State Transitions Summary ................................................... 14-16 Register Definitions .................................................................. 14-19 RTC Status (RTC_STAT) Register ....................................... 14-20 RTC Interrupt Control (RTC_ICTL) Register ..................... 14-20 RTC Interrupt Status (RTC_ISTAT) Register ....................... 14-21 RTC Stopwatch Count (RTC_SWCNT) Register ................. 14-21 RTC Alarm (RTC_ALARM) Register ................................... 14-22 RTC Prescaler Enable (RTC_PREN) Register ....................... 14-22 Programming Examples ............................................................. 14-22 Enable RTC Prescaler .......................................................... 14-23 RTC Stopwatch For Exiting Deep Sleep Mode ..................... 14-23 RTC Alarm to Come Out of Hibernate State ....................... 14-25 Unique Information for the ADSP-BF52x Processor .................. 14-27 PARALLEL PERIPHERAL INTERFACE Specific Information for the ADSP-BF52x ................................... 15-1 Overview .................................................................................... 15-2 ADSP-BF52x Blackfin Processor Hardware Reference xxv Contents Features ...................................................................................... 15-2 Interface Overview ..................................................................... 15-3 Description of Operation ............................................................ 15-4 Functional Description ............................................................... 15-5 ITU-R 656 Modes ................................................................ 15-5 ITU-R 656 Background .................................................... 15-5 ITU-R 656 Input Modes .................................................. 15-9 Entire Field .................................................................. 15-9 Active Video Only ...................................................... 15-10 Vertical Blanking Interval (VBI) only .......................... 15-10 ITU-R 656 Output Mode ............................................... 15-11 Frame Synchronization in ITU-R 656 Modes .................. 15-11 General-Purpose PPI Modes ................................................ 15-12 Data Input (RX) Modes .................................................. 15-14 No Frame Syncs .......................................................... 15-15 1, 2, or 3 External Frame Syncs ................................... 15-16 2 or 3 Internal Frame Syncs ........................................ 15-16 Data Output (TX) Modes ............................................... 15-17 No Frame Syncs .......................................................... 15-17 1 or 2 External Frame Syncs ........................................ 15-18 1, 2, or 3 Internal Frame Syncs ................................... 15-19 Frame Synchronization in GP Modes .............................. 15-20 Modes With Internal Frame Syncs ............................... 15-20 Modes With External Frame Syncs .............................. 15-21 xxvi ADSP-BF52x Blackfin Processor Hardware Reference Contents Programming Model ................................................................. 15-22 DMA Operation .................................................................. 15-23 PPI Registers ............................................................................. 15-26 PPI Control Register (PPI_CONTROL) ............................. 15-26 PPI Status Register (PPI_STATUS) ...................................... 15-31 PPI Delay Count Register (PPI_DELAY) ............................. 15-34 PPI Transfer Count Register (PPI_COUNT) ....................... 15-34 PPI Lines Per Frame Register (PPI_FRAME) ........................ 15-35 Programming Examples ............................................................. 15-37 Unique Behavior for the ADSP-BF52x Processor ....................... 15-39 SECURITY Overview .................................................................................... 16-1 Features ...................................................................................... 16-4 Description of Operation ............................................................ 16-6 Secure State Machine ............................................................. 16-7 Open Mode ...................................................................... 16-8 Secure Entry Mode ........................................................... 16-8 Secure Mode ..................................................................... 16-9 SecureMode Control ....................................................... 16-11 Security Features ................................................................. 16-13 Digital Signature Authentication ..................................... 16-13 Digital Signature Authentication Performance Measurement ............................................ 16-16 Protection Features .............................................................. 16-16 ADSP-BF52x Blackfin Processor Hardware Reference xxvii Contents Operating in Secure Mode ................................................... 16-20 Entering Secure Mode .................................................... 16-20 Exiting Secure Mode ....................................................... 16-21 Reset Handling in Secure Mode ........................................... 16-21 Hardware Reset .............................................................. 16-21 Clearing Private Data ...................................................... 16-22 Public Key Requirements .................................................... 16-24 Storing Public Cipher Key in Public OTP ....................... 16-26 Cryptographic Ciphers ........................................................ 16-27 Keys ................................................................................... 16-27 Debug Functionality .......................................................... 16-27 Programming Examples .................................................. 16-31 Programming Model ................................................................. 16-32 Secure Entry Service Routine (SESR) API ............................ 16-32 Starting Authentication ....................................................... 16-33 Memory Configuration ....................................................... 16-34 Message Placement ......................................................... 16-35 Digital Signature ............................................................ 16-35 Message Size Constraints ................................................ 16-35 Memory Usage ............................................................... 16-36 Memory Protection ......................................................... 16-36 Secure Function and Secure Entry Service Routine Arguments 16-36 Secure Function Arguments ............................................ 16-37 Secure Entry Service Routine Arguments ......................... 16-38 xxviii ADSP-BF52x Blackfin Processor Hardware Reference Contents usFlags ............................................................................ 16-38 uslRQMask ..................................................................... 16-39 ulMessageSize ................................................................. 16-40 ulSFEntryPoint ............................................................... 16-40 ulMessagePtr ................................................................... 16-40 Secure Message Execution ............................................... 16-40 Return Codes .................................................................. 16-41 Secure Hash Algorithm (SHA-1) API ............................... 16-43 ADI_SHA1 Data Type ................................................ 16-43 bfrom_Sha1Init ROM Routine .................................... 16-44 bfrom_Sha1Hash ROM Routine ................................. 16-44 Security Registers ...................................................................... 16-45 Secure System Switch (SECURE_SYSSWT) Register ............ 16-46 Secure Control (SECURE_CONTROL) Register ................. 16-52 Secure Status (SECURE_STATUS) Register ......................... 16-55 SYSTEM RESET AND BOOTING Overview .................................................................................... 17-1 Reset and Power-up .................................................................... 17-4 Hardware Reset ..................................................................... 17-6 Software Resets ...................................................................... 17-7 Reset Vector .......................................................................... 17-8 Servicing Reset Interrupts .................................................... 17-10 Preboot ..................................................................................... 17-11 Factory Page Settings (FPS) ................................................. 17-14 ADSP-BF52x Blackfin Processor Hardware Reference xxix Contents Preboot Page Settings (PBS) ................................................ 17-14 Alternative PBS Pages ..................................................... 17-16 Programming PBS Pages ................................................. 17-16 Recovering From Misprogrammed PBS Pages .................. 17-17 Customizing Power Management .................................... 17-17 Customizing Booting Options ........................................ 17-18 Customizing the Asynchronous Port ................................ 17-19 Customizing the Synchronous Port ................................. 17-20 Basic Booting Process ............................................................... 17-21 Block Headers ..................................................................... 17-23 Block Code .................................................................... 17-25 DMA Code Field ........................................................ 17-25 Block Flags Field ......................................................... 17-27 Header Checksum Field .............................................. 17-28 Header Sign Field ....................................................... 17-29 Target Address ................................................................ 17-29 Byte Count ..................................................................... 17-30 Argument ....................................................................... 17-31 Boot Host Wait (HWAIT) Feedback Strobe ......................... 17-31 Using HWAIT as Reset Indicator .................................... 17-32 Boot Termination ............................................................... 17-33 Single Block Boot Streams ................................................... 17-34 Direct Code Execution ................................................... 17-34 Advanced Boot Techniques ....................................................... 17-37 xxx ADSP-BF52x Blackfin Processor Hardware Reference Contents Initialization Code ............................................................... 17-37 Quick Boot ......................................................................... 17-41 Indirect Booting .................................................................. 17-42 Callback Routines ............................................................... 17-43 Error Handler ..................................................................... 17-46 CRC Checksum Calculation ................................................ 17-46 Load Functions ................................................................... 17-47 Calling the Boot Kernel at Runtime ..................................... 17-48 Debugging the Boot Process ................................................ 17-49 Boot Management ..................................................................... 17-51 Booting a Different Application ........................................... 17-52 Multi-DXE Boot Streams ................................................ 17-53 Determining Boot Stream Start Addresses ........................ 17-57 Initialization Hook Routine ............................................ 17-57 Specific Boot Modes .................................................................. 17-58 No Boot Mode .................................................................... 17-59 Flash Boot Modes ................................................................ 17-59 SDRAM Boot Mode ............................................................ 17-63 FIFO Boot Mode ................................................................ 17-63 SPI Master Boot Modes ....................................................... 17-65 SPI Device Detection Routine ......................................... 17-67 SPI Slave Boot Mode ........................................................... 17-69 TWI Master Boot Mode ...................................................... 17-72 TWI Slave Boot Mode ......................................................... 17-75 ADSP-BF52x Blackfin Processor Hardware Reference xxxi Contents UART Slave Mode Boot ...................................................... 17-78 OTP Boot Mode ................................................................. 17-80 Host DMA Boot Modes ...................................................... 17-81 NAND Flash Boot Mode .................................................... 17-86 Supported Devices .......................................................... 17-86 NAND Flash Page Structure ........................................... 17-89 Auto Detection ............................................................... 17-91 Boot Stream Processing ................................................... 17-91 Software Configurable NAND Flash Boot Modes ............ 17-93 Sequential Block Mode ............................................... 17-94 Block Skip Mode ........................................................ 17-95 Multiple Image Mode ................................................. 17-96 Reset and Booting Registers ...................................................... 17-98 Software Reset (SWRST) Register ....................................... 17-99 System Reset Configuration (SYSCR) Register ................... 17-100 Boot Code Revision Control (BK_REVISION) ................. 17-103 Boot Code Date Code (BK_DATECODE) ........................ 17-104 Zero Word (BK_ZEROS) .................................................. 17-105 Ones Word (BK_ONES) ................................................... 17-106 OTP Memory Pages for Booting ............................................. 17-106 Lower PBS00 Half Page .................................................... 17-106 Upper PBS00 Half Page .................................................... 17-110 Lower PBS01 Half Page .................................................... 17-111 Upper PBS01 Half Page .................................................... 17-111 xxxii ADSP-BF52x Blackfin Processor Hardware Reference Contents Lower PBS02 Half Page ..................................................... 17-114 Upper PBS02 Half Page ..................................................... 17-115 Reserved Half Pages ........................................................... 17-115 Data Structures ....................................................................... 17-115 ADI_BOOT_HEADER .................................................... 17-115 ADI_BOOT_BUFFER ...................................................... 17-116 ADI_BOOT_DATA .......................................................... 17-116 dFlags Word ................................................................. 17-120 ADI_BOOT_NAND ........................................................ 17-121 ADI_BOOT_NAND_DEVICE ........................................ 17-122 ADI_BOOT_NAND_BUFFER ........................................ 17-124 ADI_BOOT_NAND_ACCESS ......................................... 17-125 ADI_BOOT_NAND_ADDRESS ...................................... 17-125 ADI_BOOT_NAND_ECC ............................................... 17-127 Callable ROM Functions for Booting ...................................... 17-129 BFROM_FINALINIT ....................................................... 17-129 BFROM_PDMA ............................................................... 17-129 BFROM_MDMA ............................................................ 17-130 BFROM_MEMBOOT ...................................................... 17-130 BFROM_TWIBOOT ....................................................... 17-132 BFROM_SPIBOOT .......................................................... 17-132 BFROM_OTPBOOT ....................................................... 17-133 BFROM_NANDBOOT .................................................... 17-134 BFROM_BOOTKERNEL ................................................ 17-135 ADSP-BF52x Blackfin Processor Hardware Reference xxxiii Contents BFROM_CRC32 .............................................................. 17-136 BFROM_CRC32POLY ..................................................... 17-136 BFROM_CRC32CALLBACK ........................................... 17-137 BFROM_CRC32INITCODE ........................................... 17-137 Programming Examples .......................................................... 17-138 System Reset ..................................................................... 17-138 Exiting Reset to User Mode ............................................... 17-139 Exiting Reset to Supervisor Mode ...................................... 17-139 Initcode (SDRAM Controller Setup) ................................. 17-140 Initcode (Power Management Control) .............................. 17-142 Initcode (NAND Flash Boot Mode Configuration) ............ 17-144 Quickboot With Restore From SDRAM ............................ 17-145 XOR Checksum ................................................................ 17-146 Direct Code Execution ...................................................... 17-148 Managing PBS Pages in OTP Memory ............................... 17-149 DYNAMIC POWER MANAGEMENT Phase Locked Loop and Clock Control ....................................... 18-1 PLL Overview ....................................................................... 18-2 PLL Clock Multiplier Ratios ................................................. 18-3 Core Clock/System Clock Ratio Control ........................... 18-5 Dynamic Power Management Controller ..................................... 18-7 Operating Modes .................................................................. 18-8 Dynamic Power Management Controller States ...................... 18-8 Full-On Mode ................................................................. 18-8 xxxiv ADSP-BF52x Blackfin Processor Hardware Reference Contents Active Mode .................................................................... 18-9 Sleep Mode ...................................................................... 18-9 Deep Sleep Mode ........................................................... 18-10 Hibernate State .............................................................. 18-11 Operating Mode Transitions ................................................ 18-11 Programming Operating Mode Transitions ........................... 18-14 Dynamic Supply Voltage Control ......................................... 18-16 Power Supply Management .................................................. 18-17 Controlling the Internal Voltage Regulator ...................... 18-19 Changing Voltage on ADSP-BF523/ADSP-BF525/ADSP-BF527 ................... 18-19 Changing Voltage on ADSP-BF522/ADSP-BF524/ADSP-BF526 ................... 18-21 Powering Down the Core (Hibernate State) ..................... 18-22 PLL and VR Registers ............................................................... 18-25 PLL_DIV Register ............................................................... 18-26 PLL_CTL Register .............................................................. 18-26 PLL_STAT Register ............................................................. 18-28 PLL_LOCKCNT Register ................................................... 18-28 VR_CTL Register ................................................................ 18-28 System Control ROM Function ................................................. 18-30 Programming Model ............................................................ 18-32 Accessing the System Control ROM Function in C/C++ ...... 18-32 Accessing the System Control ROM Function in Assembly ... 18-33 Programming Examples ............................................................. 18-36 ADSP-BF52x Blackfin Processor Hardware Reference xxxv Contents Full-on Mode to Active Mode and Back ............................... 18-37 Transition to Sleep Mode or Deep Sleep Mode ..................... 18-39 Set Wakeups and Entering Hibernate State .......................... 18-40 Perform a System Reset or Soft-Reset ................................... 18-42 In Full-on Mode, Change VCO Frequency, Core Clock Frequency, and System Clock Frequency .............................................................. 18-43 Changing Voltage Levels ..................................................... 18-45 SYSTEM DESIGN Pin Descriptions ......................................................................... 19-1 Managing Clocks ........................................................................ 19-1 Managing Core and System Clocks ........................................ 19-2 Configuring and Servicing Interrupts .......................................... 19-2 Semaphores ................................................................................ 19-2 Example Code for Query Semaphore ..................................... 19-3 Data Delays, Latencies and Throughput ...................................... 19-4 Bus Priorities .............................................................................. 19-4 External Memory Design Issues ................................................... 19-4 Example Asynchronous Memory Interfaces ............................ 19-5 Avoiding Bus Contention ..................................................... 19-7 High-Frequency Design Considerations ...................................... 19-7 Signal Integrity ..................................................................... 19-8 Decoupling Capacitors and Ground Planes ............................ 19-9 5 Volt Tolerance .................................................................. 19-11 xxxvi ADSP-BF52x Blackfin Processor Hardware Reference Contents Test Point Access ................................................................. 19-11 Oscilloscope Probes ............................................................. 19-11 Recommended Reading ....................................................... 19-11 Resetting the Processor .............................................................. 19-13 Recommendations for Unused Pins ........................................... 19-13 Programmable Outputs ............................................................. 19-13 USB System Hardware Design ................................................... 19-14 Voltage Regulator System Hardware Design ............................... 19-15 For VRSEL = Logic 0, Internal Regulator, SS Mode ............. 19-16 For VRSEL = Logic 1, External Regulator, PG Mode ............ 19-16 NAND FLASH CONTROLLER Overview .................................................................................... 20-1 Features ...................................................................................... 20-2 Interface Overview ...................................................................... 20-3 Description of Operation ............................................................ 20-3 Internal Bus Interfaces ........................................................... 20-3 Bus Access Types ................................................................... 20-4 Access Timing ....................................................................... 20-5 Functional Description ............................................................... 20-6 Page Write ............................................................................. 20-6 Page Read ............................................................................. 20-7 Additional Operations ........................................................... 20-8 Write Protection .................................................................... 20-9 Chip Enable Don’t Care ........................................................ 20-9 ADSP-BF52x Blackfin Processor Hardware Reference xxxvii Contents NFC Error Detection ............................................................ 20-9 Error Analysis ................................................................. 20-10 Large Page Size Support .................................................. 20-12 NFC SmartMedia Support .................................................. 20-12 Programming Model ................................................................. 20-13 NFC Registers .......................................................................... 20-14 NFC Control (NFC_CTL) Register .................................... 20-16 NFC Status (NFC_STAT) Register ...................................... 20-16 NFC Interrupt Status (NFC_IRQSTAT) Register ................ 20-17 NFC Interrupt Mask (NFC_IRQMASK) Register ................ 20-19 NFC ECC (NFC_ECCx) Registers ..................................... 20-19 NFC Count (NFC_COUNT) Register ................................ 20-20 NFC Reset (NFC_RST) Register ......................................... 20-21 NFC Page Control (NFC_PGCTL) Register ........................ 20-21 NFC Read Data (NFC_READ) Register .............................. 20-22 NFC Address (NFC_ADDR) Register ................................. 20-23 NFC Command (NFC_CMD) Register .............................. 20-23 NFC Data Write (NFC_DATA_WR) Register ..................... 20-24 NFC Data Read (NFC_DATA_RD) Register ....................... 20-25 NFC Programming Examples ................................................... 20-25 ETHERNET MAC Specific Information for the ADSP-BF52x .................................. 21-1 Overview .................................................................................... 21-2 Features ................................................................................ 21-2 xxxviii ADSP-BF52x Blackfin Processor Hardware Reference Contents Interface Overview ...................................................................... 21-3 External Interface .................................................................. 21-4 Clocking ........................................................................... 21-4 Pins .................................................................................. 21-5 Internal Interface ................................................................... 21-7 Power Management ........................................................... 21-7 Description of Operation ............................................................ 21-7 Protocol ................................................................................ 21-8 MII Management Interface ................................................ 21-8 Operation ........................................................................... 21-10 MII Management Interface Operation ............................. 21-10 Receive DMA Operation ................................................. 21-11 Frame Reception and Filtering ..................................... 21-13 Discarded Frames ................................................... 21-15 Aborted Frames ...................................................... 21-16 Control Frames ....................................................... 21-16 Examples ................................................................ 21-16 RX Automatic Pad Stripping ....................................... 21-17 RX DMA Data Alignment ........................................... 21-17 RX DMA Buffer Structure ........................................... 21-18 RX Frame Status Buffer ............................................... 21-19 RX Frame Status Classification .................................... 21-19 RX IP Frame Checksum Calculation ............................ 21-21 RX DMA Direction Errors .......................................... 21-22 ADSP-BF52x Blackfin Processor Hardware Reference xxxix Contents Transmit DMA Operation .............................................. 21-23 Flexible Descriptor Structure ....................................... 21-26 TX DMA Data Alignment .......................................... 21-27 Late Collisions ............................................................ 21-28 TX Frame Status Classification ................................... 21-28 TX DMA Direction Errors .......................................... 21-29 Power Management ........................................................ 21-30 Ethernet Operation in the Sleep State .......................... 21-32 Magic Packet Detection .............................................. 21-34 Remote Wake-up Filters .............................................. 21-34 Ethernet Event Interrupts ............................................... 21-39 RX/TX Frame Status Interrupt Operation ................... 21-42 RX Frame Status Register Operation at Startup and Shutdown ............................................. 21-42 TX Frame Status Register Operation at Startup and Shutdown ............................................. 21-43 MAC Management Counters .......................................... 21-43 Programming Model ................................................................. 21-46 Configure MAC Pins .......................................................... 21-46 Multiplexing Scheme ...................................................... 21-46 CLKBUF ....................................................................... 21-47 Configure Interrupts .......................................................... 21-47 Configure MAC Registers ................................................... 21-48 MAC Address ................................................................. 21-48 MII Station Management ................................................ 21-48 xl ADSP-BF52x Blackfin Processor Hardware Reference Contents Configure PHY ................................................................... 21-49 Receive and Transmit Data .................................................. 21-50 Receiving Data ................................................................ 21-50 Transmitting Data ........................................................... 21-51 Ethernet MAC Register Definitions ........................................... 21-51 Control-Status Register Group ............................................. 21-60 MAC Operating Mode (EMAC_OPMODE) Register ...... 21-61 MAC Address Low (EMAC_ADDRLO) Register ............. 21-67 MAC Address High Register (EMAC_ADDRHI) Register 21-68 MAC Multicast Hash Table High (EMAC_HASHHI) and Low (EMAC_HASHLO) Registers ......................... 21-69 MAC Station Management Address (EMAC_STAADD) Register ......................................... 21-72 MAC Station Management Data (EMAC_STADAT) Register ......................................... 21-74 MAC Flow Control (EMAC_FLC) Register ..................... 21-75 MAC VLAN1 Tag (EMAC_VLAN1) and MAC VLAN2 Tag (EMAC_VLAN2)Registers ........ 21-77 MAC Wakeup Frame Control and Status (EMAC_WKUP_CTL) Register ................................... 21-78 MAC Wakeup Frame0 Byte Mask (EMAC_WKUP_FFMSK0) MAC Wakeup Frame1 Byte Mask (EMAC_WKUP_FFMSK1) MAC Wakeup Frame2 Byte Mask (EMAC_WKUP_FFMSK2) MAC Wakeup Frame3 Byte Mask (EMAC_WKUP_FFMSK3) Registers ...................................................................... 21-81 MAC Wakeup Frame Filter Commands (EMAC_WKUP_FFCMD) Register ............................. 21-86 ADSP-BF52x Blackfin Processor Hardware Reference xli Contents Ethernet MAC Wakeup Frame Filter Offsets (EMAC_WKUP_FFOFF) Register ............................... 21-88 MAC Wakeup Frame Filter CRC0/1 (EMAC_WKUP_FFCRC0) and CRC2/3 (EMAC_WKUP_FFCRC1) Registers ....... 21-88 System Interface Register Group .......................................... 21-89 MAC System Control (EMAC_SYSCTL) Register ........... 21-90 MAC System Status (EMAC_SYSTAT) Register .............. 21-91 Ethernet MAC Frame Status Registers ................................. 21-94 Ethernet MAC RX Current Frame Status (EMAC_RX_STAT) Register ....................................... 21-94 Ethernet MAC RX Sticky Frame Status (EMAC_RX_STKY) Register ..................................... 21-100 Ethernet MAC RX Frame Status Interrupt Enable (EMAC_RX_IRQE) Register ..................................... 21-104 Ethernet MAC TX Current Frame Status (EMAC_TX_STAT) Register ..................................................................... 21-105 Ethernet MAC TX Sticky Frame Status (EMAC_TX_STKY) Register ..................................... 21-109 Ethernet MAC TX Frame Status Interrupt Enable (EMAC_TX_IRQE) Register ..................................... 21-112 Ethernet MAC MMC RX Interrupt Status (EMAC_MMC_RIRQS) Register ............................... 21-112 Ethernet MAC MMC RX Interrupt Enable (EMAC_MMC_RIRQE) Register .............................. 21-114 Ethernet MAC MMC TX Interrupt Status (EMAC_MMC_TIRQS) Register .............................. 21-116 Ethernet MAC MMC TX Interrupt Enable (EMAC_MMC_TIRQE) Register .............................. 21-118 xlii ADSP-BF52x Blackfin Processor Hardware Reference Contents MAC Management Counter Registers ................................ 21-120 MAC Management Counters Control (EMAC_MMC_CTL) Register ................................... 21-121 Programming Examples ........................................................... 21-122 Ethernet Structures ............................................................ 21-123 MAC Address Setup .......................................................... 21-126 PHY Control Routines ...................................................... 21-126 Unique Behavior for the ADSP-BF52x Processor ..................... 21-128 SPI-COMPATIBLE PORT CONTROLLER Specific Information for the ADSP-BF52x ................................... 22-1 Overview .................................................................................... 22-2 Features ...................................................................................... 22-2 Interface Overview ...................................................................... 22-3 External Interface .................................................................. 22-4 SPI Clock Signal (SCK) ................................................... 22-4 Master-Out, Slave-In (MOSI) Signal ................................. 22-5 Master-In, Slave-Out (MISO) Signal ................................. 22-5 SPI Slave Select Input Signal (SPISS) ................................. 22-6 SPI Slave Select Enable Output Signals .............................. 22-7 Slave Select Inputs ............................................................ 22-8 Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems 22-8 Internal Interfaces ............................................................... 22-11 DMA Functionality ........................................................ 22-11 Description of Operation .......................................................... 22-12 ADSP-BF52x Blackfin Processor Hardware Reference xliii Contents SPI Transfer Protocols ......................................................... 22-12 SPI General Operation ........................................................ 22-15 Clock Signals ...................................................................... 22-16 Interrupt Output ................................................................ 22-17 Functional Description ............................................................. 22-17 Master Mode Operation (Non-DMA) .................................. 22-18 Transfer Initiation From Master (Transfer Modes) ................ 22-19 Slave Mode Operation (Non-DMA) .................................... 22-20 Slave Ready for a Transfer .................................................... 22-22 Programming Model ................................................................. 22-22 Beginning and Ending an SPI Transfer ................................ 22-22 Master Mode DMA Operation ............................................ 22-24 Slave Mode DMA Operation ............................................... 22-27 SPI Registers ............................................................................ 22-34 SPI Baud Rate (SPI_BAUD) Register .................................. 22-34 SPI Control (SPI_CTL) Register ......................................... 22-35 SPI Flag (SPI_FLG) Register ............................................... 22-38 SPI Status (SPI_STAT) Register ........................................... 22-40 Mode Fault Error (MODF) ............................................. 22-41 Transmission Error (TXE) .............................................. 22-42 Reception Error (RBSY) ................................................. 22-42 Transmit Collision Error (TXCOL) ................................. 22-42 SPI Transmit Data Buffer (SPI_TDBR) Register .................. 22-42 SPI Receive Data Buffer (SPI_RDBR) Register .................... 22-43 xliv ADSP-BF52x Blackfin Processor Hardware Reference Contents SPI RDBR Shadow (SPI_SHADOW) Register ..................... 22-44 Programming Examples ............................................................. 22-45 Core-Generated Transfer ...................................................... 22-45 Initialization Sequence .................................................... 22-45 Starting a Transfer ........................................................... 22-46 Post Transfer and Next Transfer ....................................... 22-47 Stopping ......................................................................... 22-48 DMA-Based Transfer ........................................................... 22-48 DMA Initialization Sequence .......................................... 22-48 SPI Initialization Sequence .............................................. 22-49 Starting a Transfer ........................................................... 22-51 Stopping a Transfer ......................................................... 22-51 Unique Behavior for the ADSP-BF52x Processor ....................... 22-53 TWO WIRE INTERFACE CONTROLLER Specific Information for the ADSP-BF52x ................................... 23-1 Overview .................................................................................... 23-2 Interface Overview ...................................................................... 23-3 External Interface .................................................................. 23-4 Serial Clock Signal (SCL) .................................................. 23-4 Serial Data Signal (SDA) ................................................... 23-4 TWI Pins .......................................................................... 23-5 Internal Interfaces ................................................................. 23-5 Description of Operation ............................................................ 23-6 TWI Transfer Protocols ......................................................... 23-6 ADSP-BF52x Blackfin Processor Hardware Reference xlv Contents Clock Generation and Synchronization ............................. 23-7 Bus Arbitration ................................................................. 23-8 Start and Stop Conditions ................................................. 23-9 General Call Support ...................................................... 23-10 Fast Mode ...................................................................... 23-10 Functional Description ............................................................. 23-10 General Setup ..................................................................... 23-11 Slave Mode ......................................................................... 23-11 Master Mode Clock Setup ................................................... 23-12 Master Mode Transmit ........................................................ 23-13 Master Mode Receive .......................................................... 23-14 Repeated Start Condition ............................................... 23-15 Transmit/Receive Repeated Start Sequence .................. 23-15 Receive/Transmit Repeated Start Sequence .................. 23-17 Clock Stretching ............................................................. 23-18 Clock Stretching During FIFO Underflow ...................... 23-18 Clock Stretching During FIFO Overflow ........................ 23-20 Clock Stretching During Repeated Start Condition ......... 23-21 Programming Model ................................................................. 23-24 Register Descriptions ................................................................ 23-26 TWI CONTROL Register (TWI_CONTROL) ................... 23-26 SCL Clock Divider Register (TWI_CLKDIV) ..................... 23-27 TWI Slave Mode Control Register (TWI_SLAVE_CTL) ..... 23-28 TWI Slave Mode Address Register (TWI_SLAVE_ADDR) .. 23-30 xlvi ADSP-BF52x Blackfin Processor Hardware Reference Contents TWI Slave Mode Status Register (TWI_SLAVE_STAT) ....... 23-30 TWI Master Mode Control Register (TWI_MASTER_CTL) 23-32 TWI Master Mode Address Register (TWI_MASTER_ADDR) 23-34 TWI Master Mode Status Register (TWI_MASTER_STAT) . 23-35 TWI FIFO Control Register (TWI_FIFO_CTL) ................. 23-38 TWI FIFO Status Register (TWI_FIFO_STAT) ................... 23-40 TWI FIFO Status ........................................................... 23-40 TWI Interrupt Mask Register (TWI_INT_MASK) .............. 23-41 TWI Interrupt Status Register (TWI_INT_STAT) ............... 23-42 TWI FIFO Transmit Data Single Byte Register (TWI_XMT_DATA8) ......................................... 23-45 TWI FIFO Transmit Data Double Byte Register (TWI_XMT_DATA16) ....................................... 23-45 TWI FIFO Receive Data Single Byte Register (TWI_RCV_DATA8) .......................................... 23-46 TWI FIFO Receive Data Double Byte Register (TWI_RCV_DATA16) ........................................ 23-47 Programming Examples ............................................................. 23-48 Master Mode Setup ............................................................. 23-48 Slave Mode Setup ................................................................ 23-53 Electrical Specifications ............................................................. 23-60 Unique Information for the ADSP-BF52x Processor .................. 23-60 SPORT CONTROLLER Specific Information for the ADSP-BF52x ................................... 24-1 Overview .................................................................................... 24-2 ADSP-BF52x Blackfin Processor Hardware Reference xlvii Contents Features ................................................................................ 24-2 Interface Overview ..................................................................... 24-4 SPORT Pin/Line Terminations .............................................. 24-9 Description of Operation .......................................................... 24-10 SPORT Disable .................................................................. 24-10 Setting SPORT Modes ........................................................ 24-11 Stereo Serial Operation ....................................................... 24-11 Multichannel Operation ...................................................... 24-15 Multichannel Enable ....................................................... 24-18 Frame Syncs in Multichannel Mode ................................ 24-19 The Multichannel Frame ................................................ 24-20 Multichannel Frame Delay .............................................. 24-21 Window Size .................................................................. 24-21 Window Offset ............................................................... 24-22 Other Multichannel Fields in SPORT_MCMC2 ............. 24-22 Channel Selection Register .............................................. 24-23 Multichannel DMA Data Packing ................................... 24-24 Support for H.100 Standard Protocol .................................. 24-25 2× Clock Recovery Control ............................................. 24-25 Functional Description ............................................................. 24-26 Clock and Frame Sync Frequencies ...................................... 24-26 Maximum Clock Rate Restrictions .................................. 24-27 Word Length ...................................................................... 24-28 Bit Order ............................................................................ 24-28 xlviii ADSP-BF52x Blackfin Processor Hardware Reference Contents Data Type ........................................................................... 24-29 Companding ....................................................................... 24-29 Clock Signal Options .......................................................... 24-30 Frame Sync Options ............................................................ 24-31 Framed Versus Unframed ................................................ 24-31 Internal Versus External Frame Syncs ............................... 24-33 Active Low Versus Active High Frame Syncs .................... 24-34 Sampling Edge for Data and Frame Syncs ........................ 24-34 Early Versus Late Frame Syncs (Normal Versus Alternate Timing) ........................................................ 24-36 Data Independent Transmit Frame Sync .......................... 24-38 Moving Data Between SPORTs and Memory ....................... 24-39 SPORT RX, TX, and Error Interrupts ................................. 24-39 Peripheral Bus Errors ........................................................... 24-40 Timing Examples ................................................................ 24-40 SPORT Registers ...................................................................... 24-46 Register Writes and Effective Latency ................................... 24-47 SPORT Transmit Configuration (SPORT_TCR1 and SPORT_TCR2) Registers ................. 24-48 SPORT Receive Configuration (SPORT_RCR1 and SPORT_RCR2) Registers ................. 24-54 Data Word Formats ............................................................. 24-58 SPORT Transmit Data (SPORT_TX) Register ..................... 24-59 SPORT Receive Data (SPORT_RX) Register ....................... 24-61 SPORT Status (SPORT_STAT) Register .............................. 24-64 ADSP-BF52x Blackfin Processor Hardware Reference xlix Contents SPORT Transmit and Receive Serial Clock Divider (SPORT_TCLKDIV and SPORT_RCLKDIV) Registers ... 24-65 SPORT Transmit and Receive Frame Sync Divider (SPORT_TFSDIV and SPORT_RFSDIV) Registers ......... 24-66 SPORT Multichannel Configuration (SPORT_MCMC1 and SPORT_MCMC2) Registers ....... 24-67 SPORT Current Channel (SPORT_CHNL) Register ........... 24-68 SPORT Multichannel Receive Selection (SPORT_MRCSn) Registers ............................................. 24-69 SPORT Multichannel Transmit Selection (SPORT_MTCSn) Registers ............................................. 24-70 Programming Examples ............................................................ 24-71 SPORT Initialization Sequence ........................................... 24-72 DMA Initialization Sequence .............................................. 24-74 Interrupt Servicing .............................................................. 24-76 Starting a Transfer ............................................................... 24-77 Unique Information for the ADSP-BF52x Processor .................. 24-78 UART PORT CONTROLLERS Specific Information for the ADSP-BF52x .................................. 25-1 Overview .................................................................................... 25-2 Features ...................................................................................... 25-2 Interface Overview ..................................................................... 25-3 External Interface .................................................................. 25-3 Internal Interface .................................................................. 25-4 Description of Operation ............................................................ 25-5 l ADSP-BF52x Blackfin Processor Hardware Reference Contents UART Transfer Protocol ........................................................ 25-5 UART Transmit Operation .................................................... 25-6 UART Receive Operation ...................................................... 25-7 IrDA Transmit Operation ...................................................... 25-9 IrDA Receive Operation ........................................................ 25-9 Interrupt Processing ............................................................ 25-11 Bit Rate Generation ............................................................. 25-13 Autobaud Detection ............................................................ 25-14 Programming Model ................................................................. 25-16 Non-DMA Mode ................................................................ 25-16 DMA Mode ........................................................................ 25-18 Mixing Modes ..................................................................... 25-19 UART Registers ........................................................................ 25-20 UART Line Control (UART_LCR) Register ......................... 25-22 UART Modem Control (UART_MCR) Register .................. 25-24 UART Line Status (UART_LSR) Register ............................ 25-25 UART Transmit Holding (UART_THR) Register ................ 25-26 UART Receive Buffer (UART_RBR) Register ...................... 25-27 UART Interrupt Enable (UART_IER) Register .................... 25-27 UART Interrupt Identification (UART_IIR) Register ........... 25-29 UART Divisor Latch (UART_DLL and UART_DLH) Registers ......................... 25-30 UART Scratch (UART_SCR) Register ................................. 25-32 UART Global Control (UART_GCTL) Register .................. 25-32 Programming Examples ............................................................. 25-33 ADSP-BF52x Blackfin Processor Hardware Reference li Contents Unique Information for the ADSP-BF52x Processor .................. 25-43 USB OTG CONTROLLER Overview .................................................................................... 26-1 Features ................................................................................ 26-2 Interface Overview ..................................................................... 26-3 FIFO Configuration ............................................................. 26-7 Interrupts ............................................................................. 26-8 Resets ................................................................................. 26-11 Description of Operation .......................................................... 26-12 Peripheral Mode Operation ................................................. 26-12 Endpoint Setup .............................................................. 26-12 IN Transactions as a Peripheral ...................................... 26-14 OUT Transactions as a Peripheral ................................... 26-15 Peripheral Transfer Workflows ........................................ 26-16 Control Transactions as a Peripheral ............................ 26-18 Write Requests ............................................................ 26-18 Read Requests ............................................................ 26-20 Zero Data Requests ..................................................... 26-21 ENDPOINT 0 States ................................................. 26-22 Endpoint 0 Service Routine as Peripheral .................... 26-24 Idle Mode .............................................................. 26-27 TX Mode ............................................................... 26-27 RX Mode ............................................................... 26-29 Peripheral Mode, Bulk IN, Transfer Size Known .......... 26-32 lii ADSP-BF52x Blackfin Processor Hardware Reference Contents Peripheral Mode, Bulk IN, Transfer Size Unknown ...... 26-32 Peripheral Mode, ISO IN, Small MaxPktSize ............... 26-33 Peripheral Mode, ISO IN, Large MaxPktSize ............... 26-34 Peripheral Mode, Bulk OUT, Transfer Size Known ....... 26-35 Peripheral Mode, Bulk OUT, Transfer Size Unknown ... 26-35 Peripheral Mode, ISO OUT, Small MaxPktSize ............ 26-36 Peripheral Mode, ISO OUT, Large MaxPktSize ............ 26-37 Peripheral Mode Suspend ................................................ 26-37 Start-of-frame (SOF) Packets ........................................... 26-38 Soft Connect/Soft Disconnect ......................................... 26-38 Error Handling As a Peripheral ........................................ 26-39 Stalls Issued to Control Transfers ..................................... 26-40 Zero Length OUT Data Packets in Control Transfers ....... 26-41 Host Mode Operation ......................................................... 26-41 Endpoint Setup and Data Transfer ................................... 26-41 Control Transaction as a Host ......................................... 26-42 Setup Phase as a Host ...................................................... 26-43 IN Data Phase as a Host .................................................. 26-44 OUT Data as a Host (Control) ........................................ 26-45 IN Status Phase as a Host (Following SETUP Phase or OUT Data Phase) ............. 26-46 OUT Status Phase as a Host (following IN Data Phase) ... 26-47 Host IN Transactions ...................................................... 26-48 Host OUT Transactions .................................................. 26-49 Transaction Scheduling ................................................... 26-49 ADSP-BF52x Blackfin Processor Hardware Reference liii Contents Babble ............................................................................ 26-50 Host Mode Reset ............................................................ 26-51 Host Mode Suspend ....................................................... 26-51 Functional Description ............................................................. 26-51 On-Chip Bus Interfaces ...................................................... 26-51 Interface Pins ...................................................................... 26-53 Power and Clocking ............................................................ 26-53 UTMI Interface .................................................................. 26-54 Programming Model ................................................................. 26-54 Peripheral Mode Flow Charts .............................................. 26-55 Host Mode Flow Charts ...................................................... 26-64 DMA Mode Flow Charts ..................................................... 26-73 OTG Session Request ......................................................... 26-78 Starting a Session ............................................................ 26-78 Detecting Activity .......................................................... 26-79 Host Negotiation/Configuration ......................................... 26-80 Software Clock Control ....................................................... 26-81 Wakeup from Hibernate State ............................................. 26-81 Wakeup Without Re-Enumeration ...................................... 26-83 Data Transfer ...................................................................... 26-85 Loading/Unloading Packets from Endpoints ........................ 26-86 DMA Master Channels ....................................................... 26-87 DMA Bus Cycles ................................................................ 26-89 Transferring Packets Using DMA ......................................... 26-90 liv ADSP-BF52x Blackfin Processor Hardware Reference Contents Individual Packet: RX Endpoint ..................................... 26-91 Individual Packet: TX Endpoint ...................................... 26-92 Multiple Packets: RX Endpoint ....................................... 26-92 Multiple Packets: TX Endpoints ...................................... 26-94 USB OTG Registers .................................................................. 26-95 USB Global Control (USB_GLOBAL_CTL) Register .......... 26-95 USB Power Management (USB_POWER) Register .............. 26-98 USB Function Address (USB_FADDR) Register ................ 26-100 USB Test Mode (USB_TESTMODE) Register ................... 26-101 USB Global Interrupt (USB_GLOBINTR) Register ........... 26-102 USB Transmit Interrupt (USB_INTRTX) Register ............ 26-103 USB Receive Interrupt (USB_INTRRX) Register ............... 26-103 USB Transmit Interrupt Enable (USB_INTRTXE) Register 26-105 USB Receive Interrupt Enable (USB_INTRRXE) Register .. 26-106 USB Common Interrupts (USB_INTRUSB) Register ......... 26-107 USB Common Interrupt Enable (USB_INTRUSBE) Register 26-107 USB Frame Number (USB_FRAME) Register .................... 26-109 USB Index (USB_INDEX) Register ................................... 26-109 USB TX Max Packet (USB_TX_MAX_PACKET) Register 26-110 USB Control/Status EP0 (USB_CSR0) Register ................. 26-110 USB TX Control/Status EPx (USB_TXCSR) Register ........ 26-115 USB RX Max Packet (USB_RX_MAX_PACKET) Register . 26-120 USB RX Control/Status (USB_RXCSR) Register ............... 26-121 USB Count 0 (USB_COUNT0) Register ........................... 26-126 ADSP-BF52x Blackfin Processor Hardware Reference lv Contents USB RX Byte Count EPx (USB_RXCOUNT) Register ...... 26-126 USB TX Type (USB_TXTYPE) Register ........................... 26-127 USB NAK Limit 0 (USB_NAKLIMIT0) Register .............. 26-128 USB TX Interval (USB_TXINTERVAL) Register .............. 26-128 USB RX Type (USB_RXTYPE) Register ............................ 26-129 USB RX Interval (USB_RXINTERVAL) Register .............. 26-130 USB TX Byte Count EPx (USB_TXCOUNT) Register ..... 26-131 USB Endpoint FIFO (USB_EPx_FIFO) Registers ............. 26-132 USB OTG Device Control (USB_OTG_DEV_CTL) Register 26-132 USB OTG VBUS Interrupt (USB_OTG_VBUS_IRQ) Register 26-134 USB OTG VBUS Mask (USB_OTG_VBUS_MASK) Register 26-136 USB Link Info (USB_LINKINFO) Register ...................... 26-137 USB VBUS Pulse Length (USB_VPLEN) Register ............. 26-137 USB High-Speed EOF 1 (USB_HS_EOF1) Register .......... 26-138 USB Full-Speed EOF 1 (USB_FS_EOF1) Register ............. 26-138 USB Low-Speed EOF 1 (USB_LS_EOF1) Register ............ 26-139 USB APHY Control 2 (USB_APHY_CNTRL2) Register ... 26-140 USB PLL OSC Control (USB_PLLOSC_CTRL) Registers 26-140 USB SRP Clock Divider (USB_SRP_CLKDIV) Register ... 26-142 USB DMA Interrupt (USB_DMA_INTERRUPT) Register 26-143 USB DMAx Control (USB_DMA_CONTROL) Registers . 26-143 USB DMAx Address Low (USB_DMAxADDRLOW) Registers 26-146 USB DMAx Address High (USB_DMAxADDRHIGH) Registers .. 26-146 lvi ADSP-BF52x Blackfin Processor Hardware Reference Contents USB DMAx Count Low (USB_DMAxCOUNTLOW) Registers .... 26-147 USB DMAx Count High (USB_DMAxCOUNTHIGH) Registers . 26-147 References .............................................................................. 26-148 Glossary of USB Terms .......................................................... 26-148 SYSTEM MMR ASSIGNMENTS Dynamic Power Management Registers ......................................... A-3 System Reset and Interrupt Control Registers ................................................................................... A-4 OTP Memory Registers ................................................................ A-5 Watchdog Timer Registers ............................................................ A-5 Real-Time Clock Registers ........................................................... A-6 UART0 Controller Registers ........................................................ A-6 SPI Controller Registers ............................................................... A-7 Timer Registers ............................................................................ A-8 Ports Registers .............................................................................. A-9 SPORT0 Controller Registers ..................................................... A-12 SPORT1 Controller Registers ..................................................... A-13 External Bus Interface Unit Registers .......................................... A-14 DMA/Memory DMA Control Registers ..................................... A-15 PPI Registers .............................................................................. A-17 Security Registers ....................................................................... A-18 Reset and Booting Registers ........................................................ A-18 TWI Registers ............................................................................ A-19 ADSP-BF52x Blackfin Processor Hardware Reference lvii Contents UART1 Controller Registers ....................................................... A-20 Ethernet MAC Registers ............................................................. A-20 Handshake MDMA Control Registers ......................................... A-24 HOST DMA Port Registers ........................................................ A-25 GP Counter Registers ................................................................. A-25 NFC Registers ............................................................................ A-26 USB Registers ............................................................................. A-27 Processor-Specific Memory Registers ........................................... A-35 Core Timer Registers .................................................................. A-35 TEST FEATURES JTAG Standard ............................................................................. B-1 Boundary-Scan Architecture ......................................................... B-2 Instruction Register ................................................................. B-4 Public Instructions .................................................................. B-5 EXTEST – Binary Code 00000 ........................................... B-6 SAMPLE/PRELOAD – Binary Code 10000 ....................... B-6 BYPASS – Binary Code 11111 ............................................ B-6 Boundary-Scan Register .......................................................... B-7 GLOSSARY INDEX lviii ADSP-BF52x Blackfin Processor Hardware Reference P REFACE Thank you for purchasing and developing systems using an enhanced Blackfin® processor from Analog Devices. Purpose of This Manual The ADSP-BF52x Blackfin Processor Hardware Reference provides architectural information about the ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, and ADSP-BF527 processors. This hardware reference provides architectural information about these processors and the peripherals contained within the ADSP-BF52x Blackfin packages. The architectural descriptions cover functional blocks, buses, and ports, including all features and processes that they support. For programming information, see the Blackfin Processor Programming Reference. For timing, electrical, and package specifications, see the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate instruction set reference manuals and data sheets) that describe your target architecture. ADSP-BF52x Blackfin Processor Hardware Reference lix W hat’s New in This Manual This is Revision 1.0 of the ADSP-BF52x Blackfin Processor Hardware Reference. Peripheral chapters have been expanded and reorganized, and modifications and corrections based on errata reports against this manual have been made. Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/technical_support • E-mail tools questions to processor.tools.support@analog.com • E-mail processor questions to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support) • Phone questions to 1-800-ANALOGD • Contact your Analog Devices, Inc. local sales office or authorized distributor • Send questions by mail to: Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA lx ADSP-BF52x Blackfin Processor Hardware Reference P roduct Information Product information can be obtained from the Analog Devices Web site, VisualDSP++ online Help system, and a technical library CD. Analog Devices Web Site The Analog Devices Web site, www.analog.com, provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. To access a complete technical library for each processor family, go to http://www.analog.com/processors/technical_library. The manuals selection opens a list of current manuals related to the product as well as a link to the previous revisions of the manuals. When locating your manual title, note a possible errata check mark next to the title that leads to the current correction report against the manual. Also note, MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information about products you are interested in. You can choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. Visit MyAnalog.com to sign up. If you are a registered user, just log on. Your user name is your e-mail address. VisualDSP++ Online Documentation Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, Dinkum Abridged C++ library, and FLEXnet License Tools software documenta- ADSP-BF52x Blackfin Processor Hardware Reference lxi tion. You can search easily across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary Portable Documentation Format (.pdf) files for all manuals are provided on the VisualDSP++ installation CD. Each documentation file type is described as follows. File Description .chm Help system files and manuals in Microsoft help format .htm or .html Dinkum Abridged C++ library and FLEXnet License Tools software documentation. Viewing and printing the .html files requires a browser, such as Internet Explorer 6.0 (or higher). .pdf VisualDSP++ and processor manuals in PDF format. Viewing and printing the .pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher). Technical Library CD The technical library CD contains seminar materials, product highlights, a selection guide, and documentation files of processor manuals, VisualDSP++ software manuals, and hardware tools manuals for the following processor families: Blackfin, SHARC, TigerSHARC, ADSP-218x, and ADSP-219x. To order the technical library CD, go to http://www.analog.com/procesnavigate to the manuals page for your processor, click the request CD check mark, and fill out the order form. sors/technical_library, Data sheets, which can be downloaded from the Analog Devices Web site, change rapidly, and therefore are not included on the technical library CD. Technical manuals change periodically. Check the Web site for the latest manual revisions and associated documentation errata. EngineerZone lxii ADSP-BF52x Blackfin Processor Hardware Reference EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions. Use EngineerZone to connect with other DSP developers who face similar design challenges. You can also use this open forum to share knowledge and collaborate with the ADI support team and your peers. Visit http://ez.analog.com to sign up. S ocial Networking Web Sites You can now follow Analog Devices processor development on Twitter and LinkedIn. To access: • Twitter: http://twitter.com/ADISHARC and http://twitter.com/blackfin • LinkedIn: Network with the LinkedIn group, Analog Devices SHARC or Analog Devices Blackfin: http://www.linkedin.com Notation Conventions Text conventions used in this manual are identified and described as follows. Additional conventions, which apply only to specific chapters, may appear throughout this document. Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu). {this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required. ADSP-BF52x Blackfin Processor Hardware Reference lxiii Example Description [this | that] Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. [this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this. .SECTION Commands, directives, keywords, and feature names are in text with letter gothic font. filename Non-keyword placeholders appear in text with italic style format. lxiv Note: For correct operation, ... A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. Caution: Incorrect device operation may result if ... Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol. Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol. ADSP-BF52x Blackfin Processor Hardware Reference ADSP-BF52x Blackfin Processor Hardware Reference lxv lxvi ADSP-BF52x Blackfin Processor Hardware Reference 1 INTRODUCTION The ADSP-BF52x processors are members of the Blackfin processor family that offer significant high performance and low power while retaining their ease-of-use benefits. All parts within the family are pin-compatible, but only the ADSP-BF526 and ADSP-BF527 include an embedded Ethernet MAC module. Manual Contents This manual consists of one volume. • Chapter 1, “Introduction” Provides a high level overview of the processor, including peripherals, power management, and development tools. • Chapter 2, “Chip Bus Hierarchy” Describes on-chip buses, including how data moves through the system. • Chapter 3, “Memory” Describes processor-specific memory topics, including L1 memories and processor-specific memory MMRs. • Chapter 4, “One-Time Programmable Memory” Describes the on-chip, one-time-programmable memory array which provides 64k-bits of non-volatile memory for developers to store both public and private data on-chip. ADSP-BF52x Blackfin Processor Hardware Reference 1-1 • Chapter 5, “System Interrupts” Describes the system peripheral interrupts, including setup and clearing of interrupt requests. • Chapter 6, “Direct Memory Access” Describes the peripheral DMA and Memory DMA controllers. Includes performance, software management of DMA, and DMA errors. • Chapter 7, “External Bus Interface Unit” Describes the external bus interface unit of the processor. The chapter also discusses the asynchronous memory interface, the SDRAM controller (SDC), related registers, and SDC configuration and commands. • Chapter 8, “Host DMA Port” Describes the Host DMA port of the processor. The Host DMA Port (HOSTDP) allows an external host device to be the DMA master to transfer data to and from the Blackfin device. The host device masters the transactions and the Blackfin is a DMA slave device. • Chapter 9, “General-Purpose Ports” Describes the general-purpose I/O ports, including the structure of each port, multiplexing, configuring the pins, and generating interrupts. • Chapter 10, “General-Purpose Timers” Describes the general-purpose timers. • Chapter 11, “Core Timer” Describes the core timer. • Chapter 12, “Watchdog Timer” Describes the watchdog timer. 1-2 ADSP-BF52x Blackfin Processor Hardware Reference • Chapter 13, “General-Purpose Counter” Describes the general purpose up/down counter which provides support for manually controlled rotary controllers, such as the volume wheel on a radio device. This unit also supports industrial or motor-control type of wheels. • Chapter 14, “Real-Time Clock” The RTC provides a set of digital watch features to the processor, including time of day, alarm, and stopwatch countdown. It is typically used to implement either a real-time watch or a life counter, which counts the elapsed time since the last system reset. • Chapter 16, “Security” Describes the LockboxTM Secure Technology for Analog Devices Blackfin processors. This comprises a mix of hardware and software mechanisms designed to prevent unauthorized accesses and allow trusted code to execute on the processor. • Chapter 17, “System Reset and Booting” Describes the booting methods, booting process and specific boot modes for the processor. • Chapter 18, “Dynamic Power Management” Describes the clocking, including the PLL, and the dynamic power management controller. • Chapter 19, “System Design” Describes how to use the processor as part of an overall system. It includes information about bus timing and latency numbers, semaphores, and a discussion of the treatment of unused pins. • Chapter 21, “Ethernet MAC” Describes the Ethernet Media Access Controller (MAC) peripheral which provides a 10/100M bit/s Ethernet interface, compliant to IEEE Std. 802.3-2002, between an MII (Media Independent Interface) and the Blackfin peripheral subsystem. ADSP-BF52x Blackfin Processor Hardware Reference 1-3 • Chapter 20, “NAND Flash Controller” Describes the NAND Flash Controller (NFC)—which is part of the External Bus Interface—of the processor. NAND Flash devices provide high-density, low-cost memory. • Chapter 15, “Parallel Peripheral Interface” Describes the Parallel Peripheral Interface (PPI) of the processor. The PPI is a half-duplex, bidirectional port accommodating up to 16 bits of data and is used for digital video and data converter applications. • Chapter 22, “SPI-Compatible Port Controller” Describes the Serial Peripheral Interface (SPI) port that provides an I/O interface to a variety of SPI compatible peripheral devices. • Chapter 23, “Two Wire Interface Controller” Describes the Two Wire Interface (TWI) controller, which allows a device to interface to an Inter IC bus as specified by the Philips I2C Bus Specification version 2.1 dated January 2000. • Chapter 24, “SPORT Controller” Describes the independent, synchronous Serial Port Controller which provides an I/O interface to a variety of serial peripheral devices. • Chapter 25, “UART Port Controllers” Describes the Universal Asynchronous Receiver/Transmitter port that converts data between serial and parallel formats. The UART supports the half-duplex IrDA® SIR protocol as a mode-enabled feature. • Chapter 26, “USB OTG Controller” Describes the USB OTG interface of the processor. This interface provides a low-cost connectivity solution for consumer mobile devices such as cell phones, digital still cameras and MP3 players, allowing these devices to transfer data via a point-to-point USB connection without the need for a PC host. 1-4 ADSP-BF52x Blackfin Processor Hardware Reference • Appendix A, “System MMR Assignments” Lists the memory-mapped registers included in this manual, their addresses, and cross-references to text. • Appendix B, “Test Features” Describes test features for the processor, discusses the JTAG standard, boundary-scan architecture, instruction and boundary registers, and public instructions. • Appendix G, “Glossary” Contains definitions of terms used in this book, including acronyms. is a companion This hardware reference Reference. document to the Blackfin Processor Programming Peripherals The processor system peripherals include: • Two memory-to-memory DMAs with handshake DMA • Event handler with 54 interrupt inputs • 12 peripheral DMAs (2 mastered by the Ethernet MAC on ADSP-BF527 processors) • Host DMA port (HOSTDP) • 48 General-Purpose I/Os (GPIOs) • Eight 32-bit timer/counters with PWM support • 32-bit core timer • Real-Time Clock (RTC) and watchdog timer • Rotary counter ADSP-BF52x Blackfin Processor Hardware Reference 1-5 • Lockbox™ Secure Technology • OTP Memory • On-chip PLL capable of 0.5× to 64× frequency multiplication • Debug/JTAG interface • IEEE 802.3-compliant 10/100 Ethernet MAC (only on the ADSP-BF527) • NAND flash controller • Parallel Peripheral Interface (PPI), supporting ITU-R 656 video data formats • Serial Peripheral Interface (SPI)-compatible port • Two-Wire Interface (TWI) controller • Two dual-channel, full-duplex synchronous Serial Ports (SPORTs), supporting eight stereo I2S channels • Two UARTs with IrDA® support • USB 2.0 high-speed on-the-go (OTG) interface with integrated PHY These peripherals are connected to the core via several high bandwidth buses, as shown in Figure 1-1. All of the peripherals, except for general-purpose I/O, TWI, RTC, and timers, are supported by a flexible DMA structure. There are also two separate memory DMA channels dedicated to data transfers between the processor’s memory spaces, which include external SDRAM and asynchronous memory. Multiple on-chip buses provide enough bandwidth to keep 1-6 ADSP-BF52x Blackfin Processor Hardware Reference the processor core running even when there is also activity on all of the on-chip and external peripherals. VOLTAGE REGULATOR JTAG TEST AND EMULATION OTP PERIPHERAL ACCESS BUS WATCHDOG TIMER RTC B L1 INSTRUCTION MEMORY USB INTERRUPT CONTROLLER SPORT1-0 L1 DATA MEMORY 16 TWI NFC DMA CONTROLLER DMA CORE BUS EXTERNAL ACCESS BUS PPI DMA EXTERNAL BUS EXTERNAL PORT FLASH, SDRAM CONTROL PORTS UART1-0 SPI TIMERS7-0 BOOT ROM EMAC/HOST DMA Figure 1-1. ADSP-BF52x Processor Block Diagram Memory Architecture The Blackfin processor architecture structures memory as a single, unified 4G byte address space using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and lower performance off-chip ADSP-BF52x Blackfin Processor Hardware Reference 1-7 memory systems. Table 1-1 shows the memory for the ADSP-BF52x processors. Table 1-1. Memory Configurations Type of Memory ADSP-BF52x Instruction SRAM/cache, lockable by way or line 16K byte Instruction SRAM 48K byte Data SRAM/cache 32K byte Data SRAM 32K byte Data scratchpad SRAM 4K byte L3 Boot ROM 32K byte Total 164K byte The L1 memory system is the primary highest performance memory available to the core. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controller provides high bandwidth data movement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces. 1-8 ADSP-BF52x Blackfin Processor Hardware Reference I nternal Memory The processor has three blocks of on-chip memory that provide high bandwidth access to the core: • L1 instruction memory, consisting of SRAM and a 4-way set-associative cache. This memory is accessed at full processor speed. • L1 data memory, consisting of SRAM and/or a 2-way set-associative cache. This memory block is accessed at full processor speed. • L1 scratchpad RAM, which runs at the same speed as the L1 memories but is only accessible as data SRAM and cannot be configured as cache memory. E xternal Memory External (off-chip) memory is accessed via the external bus interface unit (EBIU). This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) and as many as four banks of asynchronous memory devices including flash memory, EPROM, ROM, SRAM, and memory-mapped I/O devices. The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The asynchronous memory controller can be programmed to control up to four banks of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory. I/O Memory Space Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Control registers for on-chip I/O devices are mapped into memory-mapped registers (MMRs) ADSP-BF52x Blackfin Processor Hardware Reference 1-9 at addresses near the top of the 4G byte address space. These are separated into two smaller blocks: one contains the control MMRs for all core functions and the other contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode. They appear as reserved space to on-chip peripherals. One-Time-Programmable (OTP) Memory ADSP-BF52x processors also include an on-chip OTP memory array which provides 64K bits of non-volatile memory that can be programmed by the developer one time only. It includes the array and logic to support read access and programming. A mechanism for error correction is provided. Additionally, its pages can be write protected. The OTP is not part of the Blackfin linear memory map. OTP memory is not accessed directly using the Blackfin memory map; rather, it is accessed via four 32-bit-wide registers (OTP_DATA3–0) that act as the OTP memory read/write buffer. This memory is organized into 512 pages, each comprised of 128 bits and equally separated into two distinct areas with privileged access dependant upon modes of operation when security features are utilized. Approximately 400 pages are available for developer use. The remaining 100 pages are utilized for page protection bits, error correction, and Analog Devices factory-reserved areas. One area is read/write accessible at all time (Public OTP Memory). The second area maintains privileged access and can only be accessed (read/write) upon entry to Secure Mode when security features are utilized (Private OTP Memory). All together, OTP memory provides a means to store Public Keys in Public OTP Memory or secrets such as Private Keys or Symmetric Keys in Private OTP Memory. One page of the Public OTP Memory is initialized in the Analog Devices factory with a Unique Chip ID. This OTP memory provides a means to store public and private cipher keys as well as chip, customer, and factory identification data. 1-10 ADSP-BF52x Blackfin Processor Hardware Reference D MA Support The processor has a DMA controller which supports automated data transfers with minimal overhead for the core. DMA transfers can occur between the internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI ports, UARTs, and PPI. For the ADSP-BF527 processor, Ethernet is also a DMA-capable peripheral. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The DMA controller supports both one-dimensional (1D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to +/- 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved datastreams. This feature is especially useful in video applications where data can be de-interleaved on the fly. Examples of DMA types supported include: • A single, linear buffer that stops upon completion • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer • 1-D or 2-D DMA using a linked list of descriptors • 2-D DMA using an array of descriptors specifying only the base DMA address within a common page ADSP-BF52x Blackfin Processor Hardware Reference 1-11 In addition to the dedicated peripheral DMA channels, there are two separate pairs of memory DMA channels provided for transfers between the various memories of the system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. The ADSP-BF52x processors also include a handshake DMA capability via dual external DMA request pins when used in conjunction with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for MDMA. The number of transfers per edge is programmable. This feature can be programmed to allow MDMA to have an increased priority on the external bus relative to the core. External Bus Interface Unit The external bus interface unit (EBIU) on the processor interfaces with a wide variety of industry-standard memory devices. The controller consists of an SDRAM controller and an asynchronous memory controller. SDRAM Controller The SDRAM controller provides an interface to a single bank of industry-standard SDRAM devices or DIMMs. The bank can be configured to contain between 16M and 128M bytes of memory. A set of programmable timing parameters is available to configure the SDRAM bank to support slower memory devices. The memory bank is 16 bits wide for minimum device count and lower system cost. 1-12 ADSP-BF52x Blackfin Processor Hardware Reference A synchronous Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters. This allows connection to a wide variety of memory devices, including SRAM, ROM, and flash EPROM, as well as I/O devices that interface with standard memory control lines. Each bank occupies a 1M byte window in the processor address space, but if not fully populated, these are not made contiguous by the memory controller. The banks are 16 bits wide, for interfacing to a range of memories and I/O devices. Ports Because of the rich set of peripherals, the ADSP-BF52x processor groups the many peripheral signals to four ports—port F, port G, port H, and port J. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls. The ports have programmable hysteresis. General-Purpose I/O (GPIO) The ADSP-BF52x processors have 48 bi-directional, general-purpose I/O (GPIO) pins allocated across three separate GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associated with port F, port G, and port H, respectively. Port J does not provide GPIO functionality. Each GPIO-capable pin shares functionality with other ADSP-BF52x processor peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon powerup. Neither GPIO output or input drivers are active by default. Each general-purpose port pin can be ADSP-BF52x Blackfin Processor Hardware Reference 1-13 individually controlled by manipulation of the port control, status, and interrupt registers: • GPIO direction control register – Specifies the direction of each individual GPIO pin as input or output. • GPIO control and status registers – The ADSP-BF52x processors employ a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows software to interrogate the sense of the pins. • GPIO interrupt mask registers – The two GPIO interrupt mask registers allow each individual GPIO pin to function as an interrupt to the processor. Similar to the two GPIO control registers that are used to set and clear individual pin values, one GPIO interrupt mask register sets bits to enable interrupt function, and the other GPIO interrupt mask register clears bits to disable interrupt function. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. • GPIO interrupt sensitivity registers – The two GPIO interrupt sensitivity registers specify whether individual pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. 1-14 ADSP-BF52x Blackfin Processor Hardware Reference T wo-Wire Interface The Two-Wire Interface (TWI) is fully compatible with the widely used I2C bus standard. It was designed with a high level of functionality and is compatible with multi-master, multi-slave bus configurations. To preserve processor bandwidth, the TWI controller can be set up and a transfer initiated with interrupts only to service FIFO buffer data reads and writes. Protocol related interrupts are optional. The TWI externally moves 8-bit data while maintaining compliance with the I2C bus protocol. The Philips I2C Bus Specification version 2.1 covers many variants of I2C. The TWI controller includes these features: • Simultaneous master and slave operation on multiple device systems • Support for multi-master data arbitration • 7-bit addressing • 100K bits/second and 400K bit/second data rates • General call address support • Master clock synchronization and support for clock low extension • Separate multiple-byte receive and transmit FIFOs • Low interrupt rate • Individual override control of data and clock lines in the event of bus lock-up • Input filter for spike suppression • Serial camera control bus support as specified in the OmniVision Serial Camera Control Bus (SCCB) Functional Specification version 2.1 ADSP-BF52x Blackfin Processor Hardware Reference 1-15 E thernet MAC The Ethernet Media Access Controller (MAC) peripheral for the ADSP-BF527 processors provides a 10/100M bit/second Ethernet interface, compliant with IEEE Std. 802.3-2002, between a Media Independent Interface (MII) and the Blackfin peripheral subsystem. The MAC operates in both half-duplex and full-duplex modes. It provides programmable enhanced features designed to minimize bus utilization and pre- or post-message processing. The connection to the external physical layer device (PHY) is achieved via the MII or a Reduced Media Independent Interface (RMII). The RMII provides data buses half as wide (2 bit vs. 4 bit) as those of an MII, operating at double the frequency. The MAC is clocked internally from the CLKIN pin on the processor. A buffered version of this clock can also be used to drive the external PHY via the CLKBUF pin. A 25 MHz source should be used with an MII PHY. A 50 MHz clock source is required to drive an RMII PHY. Parallel Peripheral Interface The processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin and three multiplexed frame sync pins. The input clock supports parallel data rates up to half the system clock rate. In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported. 1-16 ADSP-BF52x Blackfin Processor Hardware Reference Three distinct ITU-R 656 modes are supported: • Active video only - The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. • Vertical blanking only - The PPI only transfers Vertical Blanking Interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines. • Entire field - The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Though not explicitly supported, ITU-R 656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor’s 2-D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle: • Data receive with internally generated frame syncs • Data receive with externally generated frame syncs • Data transmit with internally generated frame syncs • Data transmit with externally generated frame syncs ADSP-BF52x Blackfin Processor Hardware Reference 1-17 These modes support ADC/DAC connections, as well as video communication with hardware signalling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data. SPORT Controllers The processor incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support these features: • Bidirectional, I2S capable operation Each SPORT has two sets of independent transmit and receive pins, which enable eight channels of I2S stereo audio. • Buffered (eight-deep) transmit and receive ports Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. • Clocking Each transmit and receive port can either use an external serial clock or can generate its own in a wide range of frequencies. • Word length Each SPORT supports serial data words from 3 to 32 bits in length, transferred in most significant bit first or least significant bit first format. 1-18 ADSP-BF52x Blackfin Processor Hardware Reference • Framing Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. • Companding in hardware Each SPORT can perform A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. • DMA operations with single cycle overhead Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. • Interrupts Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. • Multichannel capability Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. ADSP-BF52x Blackfin Processor Hardware Reference 1-19 S erial Peripheral Interface (SPI) Port The processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins and a clock pin. An SPI chip select input pin lets other SPI devices select the processor, and seven SPI chip select output pins let the processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master and slave modes and multimaster environments. The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support either transmit or receive datastreams. The SPI’s DMA controller can only service unidirectional accesses at any given time. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out of its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. Timers There are nine general-purpose programmable timer units in the processor. Eight timers have an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths of external events. These timer units can be synchronized to an external clock input connected to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK. 1-20 ADSP-BF52x Blackfin Processor Hardware Reference The timer units can be used in conjunction with the UARTs to measure the width of the pulses in the datastream to provide an autobaud detect function for a serial channel. The timers can generate interrupts to the processor core to provide periodic events for synchronization, either to the processor clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a 9th timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. UART Ports The processor provides two half-duplex Universal Asynchronous Receiver/Transmitter (UART) ports, which are fully compatible with PC-standard UARTs. The UART ports provide a simplified UART interface to other peripherals or hosts, providing half-duplex, DMA-supported, asynchronous transfers of serial data. The UART ports include support for 5 to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The UART ports support two modes of operation: • Programmed I/O The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double buffered on both transmit and receive. • Direct Memory Access (DMA) The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. Each of the two UARTs have two ADSP-BF52x Blackfin Processor Hardware Reference 1-21 dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower priority than most DMA channels because of their relatively low service rates. The UARTs’ baud rate, serial data format, error code generation and status, and interrupts can be programmed to support: • Wide range of bit rates • Data formats from 7 to 12 bits per frame • Generation of maskable interrupts to the processor by both transmit and receive operations In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UART ports are further extended with support for the Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol. Security ADSP-BF52x processors provides security features (Blackfin Lockbox™ Secure Technology) that enable customer applications to use secure protocols, consisting of code authentication and execution of code within a secure environment. Implementing secure protocols on Blackfin processors involves a combination of hardware and software components. 1-22 ADSP-BF52x Blackfin Processor Hardware Reference Together these components protect secure memory spaces and restrict control of security features to authenticated developer code. • Blackfin Lockbox Secure Technology incorporates a secure hardware platform for confidentiality and integrity protection of secure code and data with authenticity maintained by secure software. • This secure platform provides: • A secure execution mode • Secure storage for on-chip keys • On-chip secure ROM • Secure RAM • Access to code and data in the secure domain is monitored by the hardware and any unauthorized access to the secure domain is prevented. • The secure ROM code establishes the root of trust for the secure software in the system. • The secure RAM provides integrity protection and confidentiality for authenticated code and data. • User-defined cipher key(s) and ID(s) can be securely stored in the on-chip OTP memory. • Every processor ships from the ADI factory with a unique chip ID value stored in publicly accessible OTP memory area. Real-Time Clock The processor’s Real-Time Clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is ADSP-BF52x Blackfin Processor Hardware Reference 1-23 clocked by a 32.768 kHz crystal external to the processor. The RTC peripheral has dedicated power supply pins, so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60 second counter, a 60 minute counter, a 24 hours counter, and a 32768 day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms. The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one minute resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the processor from sleep mode or deep sleep mode upon generation of any RTC wakeup event. An RTC wakeup event can also wake up the on-chip internal voltage regulator from a powered down state. Watchdog Timer The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate 1-24 ADSP-BF52x Blackfin Processor Hardware Reference interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software that would normally reset the timer has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the CPU and the peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK. C lock Signals The processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. This external clock connects to the processor CLKIN pin. The CLKIN input cannot be halted, changed, or operated below the specified frequency during normal operation. This clock signal should be a TTL-compatible signal. The core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip Phase Locked Loop (PLL) is capable of multiplying the CLKIN signal by a user-programmable (0.5× to 64×) multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10×, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be made by simply writing to the PLL_DIV register. All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL[3:0] bits of the PLL_DIV register. ADSP-BF52x Blackfin Processor Hardware Reference 1-25 D ynamic Power Management The processor provides four operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage to further reduce power dissipation. Control of clocking to each of the peripherals also reduces power consumption. F ull-On Mode (Maximum Performance) In the full-on mode, the PLL is enabled, not bypassed, providing the maximum operational frequency. This is the normal execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed. Active Mode (Moderate Power Savings) In the active mode, the PLL is enabled, but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to VCO multiplier ratio can be changed, although the changes are not realized until the full on mode is entered. DMA access is available to appropriately configured L1 memories. In the active mode, it is possible to disable the PLL through the PLL control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the full on or sleep modes. Sleep Mode (High Power Savings) The sleep mode reduces power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the sleep mode, assertion of any 1-26 ADSP-BF52x Blackfin Processor Hardware Reference interrupt causes the processor to sense the value of the bypass bit (BYPASS) in the PLL control register (PLL_CTL). If bypass is disabled, the processor transitions to the full on mode. If bypass is enabled, the processor transitions to the active mode. When in the sleep mode, system DMA access to L1 memory is not supported. Deep Sleep Mode (Maximum Power Savings) The deep sleep mode maximizes dynamic power savings by disabling the processor core and synchronous system clocks (CCLK and SCLK). Asynchronous systems, such as the RTC, may still be running, but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode. Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode. Hibernate State For lowest possible power dissipation, this state allows the internal supply (VDDINT) to be powered down, while keeping the I/O supply (VDDEXT) running. Although not strictly an operating mode like the four modes detailed above, it is illustrative to view it as such. Voltage Regulation The ADSP-BF523, ADSP-BF525, ADSP-BF527 processors provide an on-chip voltage regulator that can generate VDDINT from an external supply. Figure 18-3 on page 18-18 shows the typical external components required to complete the power management system. The regulator con- ADSP-BF52x Blackfin Processor Hardware Reference 1-27 trols the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in this state, VDDEXT can still be applied, eliminating the need for external buffers. The regulator can also be disabled and bypassed at the user’s discretion. Instruction Set Description The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. Refer to the Blackfin Processor Programming Reference for detailed information. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core resources. The assembly language, which takes advantage of the processor’s unique architecture, offers these advantages: • Embedded 16/32-bit microcontroller features, such as arbitrary bit and bit field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and supervisor stack pointers • Seamlessly integrated DSP/CPU features optimized for both 8-bit and 16-bit operations 1-28 ADSP-BF52x Blackfin Processor Hardware Reference • A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle • All registers, I/O, and memory mapped into a unified 4G byte memory space, providing a simplified programming model Code density enhancements include intermixing of 16- and 32-bit instructions with no mode switching or code segregation. Frequently used instructions are encoded in 16 bits. Development Tools The processor is supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and the VisualDSP++® development environment. The same emulator hardware that supports other Analog Devices products also fully emulates the Blackfin processor family. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax, an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to Blackfin processor assembly. The Blackfin processor has architectural features that improve the efficiency of compiled C/C++ code. ADSP-BF52x Blackfin Processor Hardware Reference 1-29 Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C/C++ and assembly code (interleaved source and object information) • Insert breakpoints • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution • Perform linear or statistical profiling of program execution • Fill, dump, and graphically plot the contents of memory • Perform source level debugging • Create custom debugger windows The VisualDSP++ Integrated Development and Debugging Environment (IDDE) lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all development tools, including color syntax highlighting in the VisualDSP++ editor. These capabilities permit programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s command-line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, coopera- 1-30 ADSP-BF52x Blackfin Processor Hardware Reference tive and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment but can also be used with standard command-line tools. The VDK development environment assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state during application debug. Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Hardware tools include the ADSP-BF52x EZ-KIT Lite standalone evaluation/development cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. ADSP-BF52x Blackfin Processor Hardware Reference 1-31 1-32 ADSP-BF52x Blackfin Processor Hardware Reference 2 CHIP BUS HIERARCHY This chapter discusses on-chip buses, how data moves through the system, and other factors that determine the system organization. Following an overview and a list of key features is a block diagram of the chip bus hierarchy and a description of its operation. The chapter concludes with details about the system interconnects and associated system buses. Overview The ADSP-BF52x Blackfin processors feature a powerful chip bus hierarchy on which all data movement between the processor core, internal memory, external memory, and its rich set of peripherals occurs. The chip bus hierarchy includes the controllers for system interrupts, test/emulation, and clock and power management. Synchronous clock domain conversion is provided to support clock domain transactions between the core and the system. The processor system includes: • The peripheral set (timers, real-time clock, TWI, Ethernet MAC (ADSP-BF527), USB 2.0, GPIOs, UARTs, SPORTs, PPI, watchdog timer, and SPI) • The external bus interface unit (EBIU) • The host DMA port (HOSTDP) ADSP-BF52x Blackfin Processor Hardware Reference 2-1 • The Direct Memory Access (DMA) controller • The interfaces between these, the system, and the optional external (off-chip) resources The following sections describe the on-chip interfaces between the system and the peripherals via the: • Peripheral Access Bus (PAB) • DMA Access Bus (DAB) • DMA Core Bus (DCB) • DMA External Bus (DEB) • External Access Bus (EAB) The external bus interface unit (EBIU) is the primary chip pin bus and is discussed in Chapter 7, “External Bus Interface Unit”. 2-2 ADSP-BF52x Blackfin Processor Hardware Reference I nterface Overview Figure 2-1 shows the core processor and system boundaries as well as the interfaces between them. 64 INSTRUCTION 32 LOAD DATA 32 LOAD DATA 32 CORE STORE DATA L1 MEMORY 16 EXTERNAL ACCESS BUS (EAB) CORE CLOCK (CCLK) DOMAIN SYSTEM CLOCK (SCLK) DOMAIN 16 C-XBAR DMA CORE BUS (DCB) DCB2 16 DCB1 USB 2.0 LOGIC 16 DMA CONTROLLER 32KB ROM DEB2 16 DEB1 16 EBIU 16 PAB 16 NFC HOSTDP EMAC PPI SPORTS UARTS GPIOS TIMERS ROTARY COUNTER TWI DAB PLL VOLTAGE CONTROL UNIT EXTERNAL MEMORY DEVICES 16 DEB E-XBAR Figure 2-1. Processor Bus Hierarchy Internal Clocks The core processor clock (CCLK) rate is highly programmable with respect to CLKIN. The CCLK rate is divided down from the Phase Locked Loop ADSP-BF52x Blackfin Processor Hardware Reference 2-3 (PLL) output rate. This divider ratio is set using the CSEL parameter of the PLL divide register. The PAB, the DAB, the EAB, the DCB, the DEB, the EPB, and the EBIU run at system clock frequency (SCLK domain). This divider ratio is set using the SSEL parameter of the PLL divide register and must be set so that these buses run as specified in the processor data sheet, and slower than or equal to the core clock frequency. These buses can also be cycled at a programmable frequency to reduce power consumption, or to allow the core processor to run at an optimal frequency. Note all synchronous peripherals derive their timing from the SCLK. For example, the UART clock rate is determined by further dividing this clock frequency. Core Bus Overview For the purposes of this discussion, level 1 memories (L1) are included in the description of the core; they have full bandwidth access from the processor core with a 64-bit instruction bus and two 32-bit data buses. 2-4 ADSP-BF52x Blackfin Processor Hardware Reference Figure 2-2 shows the core processor and its interfaces to the peripherals and external memory resources. DEBUG AND JTAG INTERFACE INT ACK SYSTEM CLOCK AND POWER MANAGEMENT DSP ID (8 BITS) JTAG CORE EVENT CONTROLLER POWER AND CLOCK CONTROLLER RESET VECTOR PROCESSOR PERFORMANCE MONITOR DA0 DA1 IAB IDB 32 LD1 32 LD0 32 SD CORE TIMER 32 32 32 64 L1 DATA DMA CORE BUS (DCB) MEMORY MANAGEMENT UNIT EAB CORE L1 INSTRUCTION PAB Figure 2-2. Core Block Diagram The core can generate up to three simultaneous off-core accesses per cycle. The core bus structure between the processor and L1 memory runs at the full core frequency and has data paths up to 64 bits. ADSP-BF52x Blackfin Processor Hardware Reference 2-5 When the instruction request is filled, the 64-bit read can contain a single 64-bit instruction or any combination of 16-, 32-, or 64-bit (partial) instructions. When cache is enabled, four 64-bit read requests are issued to support 32-byte line fill burst operations. These requests are pipelined so that each transfer after the first is filled in a single, consecutive cycle. Peripheral Access Bus (PAB) The processor has a dedicated low latency peripheral bus that keeps core stalls to a minimum and allows for manageable interrupt latencies to time-critical peripherals. All peripheral resources accessed through the PAB are mapped into the system MMR space of the processor memory map. The core accesses system MMR space through the PAB bus. The core processor has byte addressability, but the programming model is restricted to only 32-bit (aligned) access to the system MMRs. Byte accesses to this region are not supported. PAB Arbitration The core is the only master on this bus. No arbitration is necessary. PAB Agents (Masters, Slaves) The processor core can master bus operations on the PAB. All peripherals have a peripheral bus slave interface which allows the core to access control and status state. These registers are mapped into the system MMR space of the memory map. Appendix B lists system MMR addresses. The slaves on the PAB bus are: • System event controller • Clock and power management controller 2-6 ADSP-BF52x Blackfin Processor Hardware Reference • Watchdog timer • Real-time clock (RTC) • Timer 0–7 • SPORT0–1 • SPI • Ports • UART0–1 • PPI • TWI • NAND flash controller (NFC) • Ethernet MAC • USB 2.0 • Asynchronous memory controller (AMC) • SDRAM controller (SDC) • DMA controller PAB Performance For the PAB, the primary performance criteria is latency, not throughput. Transfer latencies for both read and write transfers on the PAB are two SCLK cycles. For example, the core can transfer up to 32 bits per access to the PAB slaves. With the core clock running at 2× the frequency of the system clock, the first and subsequent system MMR read or write accesses take four core clocks (CCLK) of latency. ADSP-BF52x Blackfin Processor Hardware Reference 2-7 The PAB has a maximum frequency of SCLK. DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB) The DAB, DCB, and DEB buses provide a means for DMA-capable peripherals to gain access to on-chip and off-chip memory with little or no degradation in core bandwidth to memory. DAB, DCB, DEB Arbitration Sixteen DMA channels and bus masters support the DMA-capable peripherals in the processor system. The twelve peripheral DMA channel controllers can transfer data between peripherals and internal or external memory. Both the read and write channels of the dual-stream memory DMA controller access their descriptor lists through the DAB. The DCB has priority over the core processor on arbitration into L1 configured as SRAM. The following priority applies to external bus accesses, between core and DMA: 1. Core Locked Access (Testset) 2. Urgent DMA Access 3. Core Access 4. Normal (Regular) DMA Access 2-8 ADSP-BF52x Blackfin Processor Hardware Reference The processor has a programmable priority arbitration policy on the DAB. Table 2-1 shows the default arbitration priority. Table 2-1. DAB, DCB, and DEB Arbitration Priority DAB, DCB, DEB Master Default Arbitration Priority PPI receive/transmit or NFC 0 - highest Ethernet receive 1 Ethernet transmit or NFC 2 SPORT0 receive 3 SPORT0 transmit 4 SPORT1 receive 5 SPORT1 transmit 6 SPI receive/transmit 7 UART0 receive 8 UART0 transmit 9 UART1 receive 10 UART1 transmit 11 MDMA stream 0 destination 12 MDMA stream 0 source 13 MDMA stream 1 destination 14 MDMA stream 1 source 15 - lowest D CB Sharing USB has a separate DMA Controller and supports eight channels. The Peripheral DMA bus (DCB1) and USB DMA bus (DCB2) have to share the same L1 memory bus (DCB). This sharing happens in the C-XBAR. Arbitration logic determines who gets the bus when requests from DCB1 and DCB2 arrive in the same cycle. There are control bits which deter- ADSP-BF52x Blackfin Processor Hardware Reference 2-9 mine how the arbitration is to be performed. Table 2-2 on page 2-10 describes the arbitration scheme. In Table 2-2 on page 2-10 the DCBx Urgency columns denote that one or more peripherals on the specified DCBx bus is making an urgent request. For more information, see “Temporary DMA Urgency” on page 6-46. Table 2-2. Arbitration Scheme for DCB DCB_ROT_PRIO DCB1_PRIO_HI DCB1 Urgency DCB2 Urgency Access to DCB (L1 bus) 0 0 0 0 DCB2 0 0 X 1 DCB2 0 0 1 0 DCB1 0 1 0 0 DCB1 0 1 1 X DCB1 0 1 0 1 DCB2 1 X 0 0 Ping-Pong 1 X 0 1 DCB2 1 X 1 0 DCB1 1 X 1 1 Ping –Pong 1. DCB_ROT_PRIO is configured in the SYSCR register. When this bit is set to “1”, a rotating priority scheme is selected between DCB1 and DCB2, and the DCB_PRIO_HI setting is ignored. Note that the rotating priority scheme switches the access between DCB1 and DCB2 at every access to the internal L1 memory. This limits bursty transfers to/from L1 memory to the DMA channel, which could limit efficient utilization of the bus bandwidth. 2. 2-10 is also be configured in the SYSCR register. When this bit is set to “1”, DCB1 has a higher priority than DCB2. If this bit is set to “0”, DCB2 has a higher priority than DCB1. DCB1_PRIO_HI ADSP-BF52x Blackfin Processor Hardware Reference For more information on the SYSCR register, see “System Reset Configuration (SYSCR) Register” on page 17-100. For L3 access, the L3 memory bus (DEB) is shared between the USB bus (DEB2) and the DEB1 bus which is used for all other accesses (peripheral DMA, core accesses, MDMA). This sharing happens in the E-XBAR. The arbitration logic and the scheme is identical to the C-XBAR. Table 2-3 on page 2-12 indicates the arbitration scheme. In Table 2-3, the DEBx Urgency columns denote that one or more peripherals on the specified ADSP-BF52x Blackfin Processor Hardware Reference 2-11 DEBx bus is making an urgent request. For more information, see “Temporary DMA Urgency” on page 6-46. Table 2-3. Arbitration Scheme for DEB DEB_ROT_PRIO DEB1_PRIO_HI DEB1 Urgency DEB2 Urgency Access to DEB (L3 bus) 0 0 0 0 DEB2 0 0 X 1 DEB2 0 0 1 0 DEB1 0 1 0 0 DEB1 0 1 1 X DEB1 0 1 0 1 DEB2 1 X 0 0 Ping-pong 1 X 0 1 DEB2 1 X 1 0 DEB1 1 X 1 1 Ping-pong 1. is configured in the SYSCR register. When this bit is set to “1”, a rotating priority scheme is selected between DEB1 and DEB2, and the DEB1_PRIO_HI setting is ignored. DEB_ROT_PRIO_En Note that the rotating priority scheme switches the access between DEB1 and DEB2 at every access to the external memory. This limits bursty transfers to/from the external memory to the DMA channel, which could limit efficient utilization of the bus bandwidth. 2. can also configured in the SYSCR register, When this bit is set to “1”, DEB1 has higher priority than DEB2. If this bit is set to “0”, DEB2 has higher priority than DEB1. DEB1_PRIO_HI For more information on the SYSCR register, see “System Reset Configuration (SYSCR) Register” on page 17-100. 2-12 ADSP-BF52x Blackfin Processor Hardware Reference Using the CDPRIO Bit to Change Priorities The core and DMA prioritization over the external bus can also be programmed statically by using the CDPRIO bit in the EBIU_AMGCTL register. By setting the CDPRIO bit in the EBIU_AMGCTL register, all DEB (DEB1 and DEB2) transactions to the external bus have priority over core accesses to external memory. Use of this bit is application dependent. For example, if you are polling a peripheral mapped to asynchronous memory with long access times, by default the core will “win” over DMA requests. By setting the CDPRIO bit, the core would be held off until DMA requests were serviced. Use this bit only if "Temporary Urgent DMA" functionality of DEB1 as controlled automatically by the hardware is insufficient to meet system bandwidth requirements. The "Temporary Urgent DMA" functionality of DEB2 is not controlled automatically by the hardware. DEB2 requests never go urgent automatically and thus can never beat the core for external memory accesses under temporary urgent conditions. The DEB2_URGENT bit in the USB_PLLOSC_CTRL register can be used to statically assign DEB2 requests higher priority than the core. See “USB PLL OSC Control (USB_PLLOSC_CTRL) Registers” on page 26-140. DAB Bus Agents (Masters) All peripherals capable of sourcing a DMA access are masters on this bus, as shown in Table 2-1. A single arbiter supports a programmable priority arbitration policy for access to the DAB. When two or more DMA master channels are actively requesting the DAB, bus utilization is considerably higher due to the DAB’s pipelined design. Bus arbitration cycles are concurrent with the previous DMA access’s data cycles. ADSP-BF52x Blackfin Processor Hardware Reference 2-13 D AB, DCB, and DEB Performance The processor DAB supports data transfers of 16 bits or 32 bits. The data bus has a 16-bit width with a maximum frequency as specified in the processor data sheet. The DAB has a dedicated port into L1 memory. No stalls occur as long as the core access and the DMA access are not to the same memory bank (4K byte size for L1). If there is a conflict, DMA is the highest priority requester, followed by the core. Note that a locked transfer by the core processor (for example, execution of a TESTSET instruction) effectively disables arbitration for the addressed memory bank or resource until the memory lock is deasserted. DMA controllers cannot perform locked transfers. DMA access to L1 memory can only be stalled by an access already in progress from another DMA channel. Latencies caused by these stalls are in addition to any arbitration latencies. core processor must arbitrate for access exter Thememory throughand the DABThis additional arbitrationtolatency nal the EBIU. added to the latency required to read off-chip memory devices can significantly degrade DAB throughput, potentially causing peripheral data buffers to underflow or overflow. If you use DMA peripherals other than the memory DMA controller, and you target external memory for DMA accesses, you need to carefully analyze your specific traffic patterns. Make sure that isochronous peripherals targeting internal memory have enough allocated bandwidth and the appropriate maximum arbitration latencies. External Access Bus (EAB) The EAB provides a way for the processor core to directly access off-chip memory. 2-14 ADSP-BF52x Blackfin Processor Hardware Reference A rbitration of the External Bus Arbitration for use of external port bus interface resources is required because of possible contention between the potential masters of this bus. A fixed-priority arbitration scheme is used. That is, core accesses via the EAB will be of higher priority than those from the DMA external bus (DEB). DEB/EAB Performance The DEB and the EAB support single word accesses of either 8-bit or 16-bit data types. The DEB and the EAB operate at the same frequency as the PAB and the DAB, up to the maximum SCLK frequency specified in the processor data sheet. Memory DMA transfers can result in repeated accesses to the same memory location. Because the memory DMA controller has the potential of simultaneously accessing on-chip and off-chip memory, considerable throughput can be achieved. The throughput rate for an on-chip/off-chip memory access is limited by the slower of the two accesses. In the case where the transfer is from on-chip to on-chip memory or from off-chip to off-chip memory, the burst accesses cannot occur simultaneously. The transfer rate is then determined by adding each transfer plus an additional cycle between each transfer. Table 2-4 shows many types of 16-bit memory DMA transfers. In the table, it is assumed that no other DMA activity is conflicting with ongoing operations. The numbers in the table are theoretical values. These values may be higher when they are measured on actual hardware due to a variety of reasons relating to the device that is connected to the EBIU. For non-DMA accesses (for example, a core access via the EAB), a 32-bit access to SDRAM (of the form R0 = [P0]; where P0 points to an address in SDRAM) is always more efficient than executing two 16-bit accesses (of the form R0 = W[P0++]; where P0 points to an address in SDRAM). In ADSP-BF52x Blackfin Processor Hardware Reference 2-15 this example, a 32-bit SDRAM read takes 10 SCLK cycles while two 16-bit reads take 9 SCLK cycles each. Table 2-4. Performance of DMA Access to External Memory Source Destination Approximate SCLKs For n Words (from start of DMA to interrupt at end) 16-bit SDRAM L1 data memory n + 14 L1 data memory 16-bit SDRAM n + 11 16-bit async memory L1 data memory xn + 12, where x is the number of wait states + setup/hold SCLK cycles (minimum x = 2) L1 data memory 16-bit async memory xn + 9, where x is the number of wait states + setup/hold SCLK cycles (minimum x = 2) 16-bit SDRAM 16-bit SDRAM 10 + (17n/7) 16-bit async memory 16-bit async memory 10 + 2xn, where x is the number of wait states + setup/hold SCLK cycles (minimum x = 2) L1 data memory L1 data memory 2n + 12 2-16 ADSP-BF52x Blackfin Processor Hardware Reference 3 MEMORY This chapter discusses memory population specific to the ADSP-BF52x processors. Functional memory architecture is described in the Blackfin Processor Programming Reference. Memory Architecture Table 3-1 on page 3-1 provides an overview of the ADSP-BF52x processor system memory map. For a detailed discussion of how to use them, see the Blackfin Processor Programming Reference. Note the architecture does not define a separate I/O space. All resources are mapped through the flat 32-bit address space. The memory is byte-addressable. The upper portion of internal memory space is allocated to the core and system MMRs. Accesses to this area are allowed only when the processor is in supervisor or emulation mode (see the Operating Modes and States chapter of the Blackfin Processor Programming Reference). Within the external memory map, four banks of asynchronous memory space and one bank of SDRAM memory are available. Each of the asynchronous banks is 1M byte and the SDRAM bank is up to 128M byte. Table 3-1. ADSP-BF52x Memory Map Starting Address Ending Address Description 0xFFE0 0000 0xFFFF FFFF Core MMR 0xFFC0 0000 0xFFDF FFFF System MMR 0xFFB0 1000 0xFFBF FFFF reserved ADSP-BF52x Blackfin Processor Hardware Reference 3-1 Table 3-1. ADSP-BF52x Memory Map Starting Address Ending Address Description 0xFFB0 0000 Scratchpad SRAM 0xFFA1 4000 0xFFAF FFFF reserved 0xFFA1 0000 0xFFA1 3FFF Instruction Bank C SRAM/Cache 0xFFA0 C000 0xFFA0 FFFF reserved 0xFFA0 8000 0xFFA0 BFFF Instruction Bank B SRAM 0xFFA0 0000 0xFFA0 7FFF Instruction Bank A SRAM 0xFF90 8000 0xFF9F FFFF reserved 0xFF90 4000 0xFF90 7FFF Data Bank B SRAM/Cache 0xFF90 0000 0xFF90 3FFF Data Bank B SRAM 0xFF80 8000 0xFF8F FFFF reserved 0xFF80 4000 0xFF80 7FFF Data Bank A SRAM/Cache 0xFF80 0000 0xFF80 3FFF Data Bank A SRAM 0xEF00 4000 0xFF7F FFFF reserved 0xEF00 0000 0xEF00 7FFF BOOT ROM (32K Byte) 0x2080 0000 0xEEFF FFFF reserved 0x2040 0000 0x207F FFFF reserved 0x2030 0000 0x203F FFFF Async Bank 3 0x2020 0000 0x202F FFFF Async Bank 2 0x2010 0000 0x201F FFFF Async Bank 1 0x2000 0000 0x200F FFFF Async Bank 0 0x0800 0000 0x1FFF FFFF reserved 0x0000 0000 3-2 0xFFB0 0FFF 0x07FF FFFF SDRAM ADSP-BF52x Blackfin Processor Hardware Reference L 1 Instruction SRAM The processor core reads the instruction memory through the 64-bit wide instruction fetch bus. All addresses from this bus are 64-bit aligned. Each instruction fetch can return any combination of 16-, 32- or 64-bit instructions (for example, four 16-bit instructions, two 16-bit instructions and one 32-bit instruction, or one 64-bit instruction). Table 3-2 lists the memory start locations of the L1 instruction memory subbanks. Table 3-2. L1 Instruction Memory Subbanks Memory Subbank Memory Start Location for ADSP-BF52x Processors 0 0xFFA0 0000 1 0xFFA0 1000 2 0xFFA0 2000 3 0xFFA0 3000 4 0xFFA0 4000 5 0xFFA0 5000 6 0xFFA0 6000 7 0xFFA0 7000 8 0xFFA0 8000 9 0xFFA0 9000 10 0xFFA0 A000 11 0xFFA0 B000 12 0xFFA1 0000 13 0xFFA1 1000 14 0xFFA1 2000 15 0xFFA1 3000 ADSP-BF52x Blackfin Processor Hardware Reference 3-3 L 1 Data SRAM Table 3-3 shows how the subbank organization is mapped into memory. Table 3-3. L1 Data Memory SRAM Subbank Start Addresses Memory Bank and Subbank ADSP-BF52x Processors Data Bank A, Subbank 0 0xFF80 0000 Data Bank A, Subbank 1 0xFF80 1000 Data Bank A, Subbank 2 0xFF80 2000 Data Bank A, Subbank 3 0xFF80 3000 Data Bank A, Subbank 4 0xFF80 4000 Data Bank A, Subbank 5 0xFF80 5000 Data Bank A, Subbank 6 0xFF80 6000 Data Bank A, Subbank 7 0xFF80 7000 Data Bank B, Subbank 0 0xFF90 0000 Data Bank B, Subbank 1 0xFF90 1000 Data Bank B, Subbank 2 0xFF90 2000 Data Bank B, Subbank 3 0xFF90 3000 Data Bank B, Subbank 4 0xFF90 4000 Data Bank B, Subbank 5 0xFF90 5000 Data Bank B, Subbank 6 0xFF90 6000 Data Bank B, Subbank 7 0xFF90 7000 L 1 Data Cache When data cache is enabled (controlled by bits DMC[1:0] in the DMEM_CONTROL register), either 16K byte of data bank A or 16K byte of both data bank A and data bank B can be set to serve as cache. 3-4 ADSP-BF52x Blackfin Processor Hardware Reference B oot ROM The lowest 32K byte of internal memory space is occupied by the boot ROM starting from address 0xEF00 0000. This 16-bit boot ROM is not part of the L1 memory module. Read accesses take one SCLK cycle and no wait states are required. The read-only memory can be read by the core as well as by DMA. It can be cached and protected by CPLD blocks like external memory. The boot ROM not only contains boot-strap loader code, it also provides some subfunctions that are user-callable at runtime. For more information, see “System Reset and Booting” on page 17-1. External Memory The external memory space is shown in Figure 3-1 on page 3-1. One of the memory regions is dedicated to SDRAM support. The size of the SDRAM bank is programmable and can range in size from 16M byte to 128M byte. The start address of the bank is 0x0000 0000. Each of the next four banks contains 1M byte and is dedicated to support asynchronous memories. The start address of the asynchronous memory bank is 0x2000 0000. Processor-Specific MMRs The complete set of memory-related MMRs is described in the Blackfin Processor Programming Reference. Several MMRs have bit definitions specific to the processors described in this manual. These registers are described in the following sections. ADSP-BF52x Blackfin Processor Hardware Reference 3-5 D MEM_CONTROL Register The data memory control register (DMEM_CONTROL), shown in Figure 3-1, contains control bits for the L1 data memory. Data Memory Control Register (DMEM_CONTROL) 31 30 29 28 0xFFE0 0004 27 26 25 24 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 1 0 0 23 22 0 0 0 0 21 20 19 18 17 16 0 0 0 0 7 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 0 0 Reset = 0x0000 1001 1 PORT_PREF1 (DAG1 Port Preference) 0 - DAG1 non-cacheable fetches use port A 1 - DAG1 non-cacheable fetches use port B PORT_PREF0 (DAG0 Port Preference) 0 - DAG0 non-cacheable fetches use port A 1 - DAG0 non-cacheable fetches use port B DCBS (L1 Data Cache Bank Select) Valid only when DMC[1:0] = 11. Determines whether Address bit A[14] or A[23] is used to select the L1 data cache bank. 0 - Address bit 14 is used to select Bank A or B for cache access. If bit 14 of address is 1, select L1 Data Memory Data Bank A; if bit 14 of address is 0, select L1 Data Memory Data Bank B. 1 - Address bit 23 is used to select Bank A or B for cache access. If bit 23 of address is 1, select L1 Data Memory Data Bank A; if bit 23 of address is 0, select L1 Data Memory Data Bank B. ENDCPLB (Data Cacheability Protection Lookaside Buffer Enable) 0 - CPLBs disabled. Minimal address checking only 1 - CPLBs enabled DMC[1:0] (L1 Data Memory Configure) For ADSP-BF52x: 00 - Both data banks are SRAM, also invalidates all cache lines if previously configured as cache 01 - Reserved 10 - Data Bank A is lower 16K byte SRAM, upper 16K byte cache Data Bank B is SRAM 11 - Both data banks are lower 16K byte SRAM, upper 16K byte cache Figure 3-1. L1 Data Memory Control Register DTEST_COMMAND Register When the data test command register (DTEST_COMMAND) is written to, the L1 cache data or tag arrays are accessed, and the data is transferred 3-6 ADSP-BF52x Blackfin Processor Hardware Reference through the data test data registers (DTEST shown in Figure 3-2. DATA[1:0]). This register is The data/instruction access bit allows direct access via the MMR to L1 instruction SRAM. DTEST_COMMAND Data Test Command Register (DTEST_COMMAND) 31 30 29 28 0xFFE0 0300 27 26 25 24 23 22 21 20 X X X X X X X X X X X X 19 18 17 16 X X X X Access Way/Instruction Address Bit 11 0 - Access Way0/Instruction bit 11 = 0 1 - Access Way1/Instruction bit 11 = 1 Data/Instruction Access 0 - Access Data 1 - Access Instruction Reset = Undefined Subbank Access[1:0] (SRAM ADDR[13:12]) 00 - Access subbank 0 01 - Access subbank 1 10 - Access subbank 2 11 - Access subbank 3 Data Bank Access 0 - Access Data Bank A/Instr Memory 0xFFA0 0000 1 - Access Data Bank B/Instr Memory 0xFFA0 8000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Data Cache Select/ Address Bit 14 0 - Reserved/Instruction bit 14 = 0 1 - Select Data Cache Bank/Instruction bit 14 = 1 Set Index[5:0] Selects one of 64 sets Read/Write Access 0 - Read access 1 - Write access Array Access 0 - Access tag array 1 - Access data array Double Word Index[1:0] Selects one of four 64-bit double words in a 256-bit line Figure 3-2. Data Test Command Register ADSP-BF52x Blackfin Processor Hardware Reference 3-7 3-8 ADSP-BF52x Blackfin Processor Hardware Reference 4 ONE-TIME PROGRAMMABLE MEMORY This chapter describes One-Time-Programmable (OTP) memory features of the ADSP-BF52x Blackfin processor. The chapter includes the following sections: • “OTP Memory Map” on page 4-2 • “Error Correction” on page 4-7 • “OTP Access” on page 4-10 • “Error Correction Policy” on page 4-8 • “OTP Timing Parameters” on page 4-12 • “Callable ROM Functions for OTP ACCESS” on page 4-17 • “Programming and Reading OTP” on page 4-19 • “Write-protecting OTP Memory” on page 4-25 • “Accessing Private OTP Memory” on page 4-28 • “OTP Programming Examples” on page 4-28 OTP Memory Overview The ADSP-BF52x processors include an on-chip, one-time-programmable memory array which provides 64k-bits of non-volatile memory. This includes the array and logic to support read access and programming. A ADSP-BF52x Blackfin Processor Hardware Reference 4-1 mechanism for error correction is also provided. Additionally, pages can be write protected. OTP memory can be programmed through various methods, including software running on the Blackfin processor. The ADSP-BF52x processors provide C and assembly callable functions in the on-chip ROM to help the developer access the OTP memory. The one-time-programmable memory (OTP) is divided into two main regions. A 32K bit “public” unsecured region, which has no access restrictions, and a 32K bit “private” secured region with access restricted to authenticated code when operating in Secure Mode (For information about these modes, see Chapter 16, “Security” of the ADSP-BF52x Blackfin Processor Hardware Reference.) OTP enables developers to store both public and private data on-chip. A 64K x 1 bit array is available as shown in Figure 4-2 on page 4-4 and Figure 4-3 on page 4-5. In addition to storing public and private data, it allows developers to store completely user-definable data, such as customer ID, product ID, MAC address, etc. of The public portion areOTP memory contains many “factory setto only” values. Users urged to exercise caution when writing OTP memory and to consult the OTP memory map for details of Customer Programmable Settings (CPS) and factory reserved areas of this memory. See also Factory Page Settings (FPS) and Preboot Page Settings (PBS) in “System Reset and Booting” on page 17-1 in this volume of the ADSP-BF52x Blackfin Processor Hardware Reference. OTP Memory Map The OTP is not part of the Blackfin linear memory map. It has a separate memory map that is shown in Figure 4-2 on page 4-4 and Figure 4-3 on page 4-5. OTP memory is not accessed directly using the Blackfin mem- 4-2 ADSP-BF52x Blackfin Processor Hardware Reference ory map; rather, it is accessed via four 32-bit wide registers (OTP_DATA3—0) which act as the OTP memory read/write buffer. In the case of an OTP memory read, the OTP_DATAx registers will contain the 16-byte result of the OTP memory access. In the case of an OTP memory write, the OTP_DATAx registers will contain 16 bytes of data to be written to the OTP memory. OTP_DATA3—0 registers are organized into a 128 bit page as shown in Figure 4-1. 127 BIT 31 96 95 64 63 32 31 BIT 0 BIT 31 BIT 0 BIT 31 BIT 0 BIT 31 OTP_DATA3 OTP_DATA2 OTP_DATA1 0 BIT 0 OTP_DATA0 Figure 4-1. OTP_DATAx Registers ADSP-BF52x Blackfin Processor Hardware Reference 4-3 128 BIT PAGE 64 BIT LOWER HALF PAGE 64 BIT UPPER HALF PAGE PAGE PAGE ADDRESS NAME1 15 14 13 12 11 10 9 8 7 6 5 4 3 BIT 127 2 1 0 BYTE BIT 0 PROTECTION BITS FOR PAGES 0x000 (LSB) THROUGH 0x07F (MSB) 0x000 0x001 PROTECTION BITS FOR PAGES 0x080 (LSB) THROUGH 0x0FF (MSB) 0x002 PROTECTION BITS FOR PAGES 0x100 (LSB) THROUGH 0x17F (MSB) 0x003 PROTECTION BITS FOR PAGES 0x180 (LSB) THROUGH 0x1FF (MSB) 0x004 FPS00 UNIQUE CHIP ID [127:0] 0x005 FPS01 FACTORY RESERVED 0x006 FPS02 FACTORY RESERVED 0x007 FPS03 Bytes 15:14, Part Number Integer 0x008 FPS04 FACTORY RESERVED 0x009 FPS05 FACTORY RESERVED 0x00A FPS06 FACTORY RESERVED 0x00B FPS07 FACTORY RESERVED 0x00C FPS08 FACTORY RESERVED 0x00D FPS09 FACTORY RESERVED 0x00E FPS10 FACTORY RESERVED 0x00F FPS11 FACTORY RESERVED 0x10 CPS00 CUSTOMER KEY [127:0] 0x11 CPS01 CUSTOMER KEY [255:128] 0x12 CPS02 CUSTOMER KEY [383:256] 0x13 CPS03 RESERVED 0x14 CPS04 RESERVED 0x15 CPS05 RESERVED 0x16 CPS06 RESERVED 0x17 CPS07 RESERVED 0x18 PBS00 Bytes[15:8], PBS00H Bytes[7:0], PBS00L 0x19 PSS01 Bytes[15:8], PBS01H Bytes[7:0], RESERVED PBS001U 0x1A PBS02 Bytes[15:8], PBS002H Bytes[7:0], PBS002L 0x1B PBS03 Bytes[15:8], RESERVED PBS003H Bytes[7:0], RESERVED PBS003L PUBLIC OTP (256 PAGES) Bytes 12:0, Part Number String3 0x1C to 0x0DF UNSECURED GENERAL PURPOSE SPACE 0xE0 to 0x00F UNSECURED ERROR CORRECTION CODE (ECC) SPACE2 Figure 4-2. Public OTP Memory Map1, 2, 3 1 Factory Programmable Settings (FPS) are programmed at the factory. Customer Programmable Settings (CPS) are programmed by the customer. 2 This space should NOT be written by the customer. 8-bit error correction codes are automatically generated by firmware and stored in this region. 3 Part Number Field Definition. 4-4 ADSP-BF52x Blackfin Processor Hardware Reference 128 BIT PAGE 64 BIT UPPER HALF PAGE 0x100 to 0x10F 0x110 to 0x1DF 0x1E0 to 0x1FF 14 13 12 11 10 9 64 BIT LOWER HALF PAGE 8 7 6 5 4 BIT 127 3 2 1 0 BYTE BIT 0 SECURED FACTORY RESERVED SPACE SECURED GENERAL PURPOSE SPACE PRIVATE OTP (256 PAGES) PAGE ADDRESS 15 SECURED ERROR CORRECTION CODE (ECC) SPACE1 Footnotes 1. This space should NOT be written by the customer. 8-bit error correction codes are automatically generated by firmware an stored in this region. Figure 4-3. Private OTP Memory Map Part Number Field Definition. A string indicating the model number of the product is programmed into FPS03 (see Figure 4-2 on page 4-4. Each character is represented by standard 8-bit ASCII code. A termination character of 0x0000 0000 terminates the string. The field supports up to ADSP-BF52x Blackfin Processor Hardware Reference 4-5 12 alphanumeric characters plus one termination character. The first string character resides in bits[7:0] and the string grows to the left with the left most character being the termination character. Integer representation of the part number is shown in Table 4-1. Byte 13 in FPS03 is reserved. Table 4-1. Part Number Field Definition Part Number CODEC Code ADSP-BF522 N/A 0x020A ADSP-BF523 N/A 0x020B ADSP-BF524 N/A 0x020C ADSP-BF525 N/A 0x020D ADSP-BF526 N/A 0x020E ADSP-BF527 N/A 0x020F ADSP-BF522 C1 0x820A ADSP-BF523 C1 0x820B ADSP-BF524 C1 0x820C ADSP-BF525 C1 0x820D ADSP-BF526 C1 0x820E ADSP-BF527 C1 0x820F ADSP-BF522 C2 0x420A ADSP-BF523 C2 0x420B ADSP-BF524 C2 0x420C ADSP-BF525 C2 0x420D ADSP-BF526 C2 0x420E ADSP-BF527 C2 0x420F OTP memory ranges marked as Factory Reserved, Reserved and Error Correction Code Space (see Figure 4-2 on page 4-4) must not be pro- 4-6 ADSP-BF52x Blackfin Processor Hardware Reference grammed by the user. Customer Programmable Settings are optionally programmed by the developer. Page-Protection bits provide protection for each 128-bit page within the OTP. By default, the OTP array bits are not set and will read back as zero values if left unprogrammed. Programmed data values consist of zeroes and ones; therefore, after programming OTP memory, some bits will intentionally remain as zero values. The write-protect bits provide protection for the zero value bits to remain as zeroes and prevent future programming (inadvertent or malicious) from changing bit values from zero to one. Pages 0x10, 0x11, and 0x12 hold the customer public key, which is used for Lockbox digital signature authentication. Please refer to Chapter 16, “Security” for more information on Lockbox and how the public key is used. OTP memory is logically arranged in a sequential set of 128-bit pages. Each OTP memory address refers to a 128-bit page. The ADSP-BF52x processor thus provides 512 pages of OTP memory. In order to read or program the OTP memory, a set of functions are provided in the on-chip ROM. These functions include bfrom_OtpRead(), bfrom_OtpWrite() and bfrom_OtpCommand(). Error Correction To meet strict quality goals, error correction is used to ensure data integrity. bfrom_OtpRead() and bfrom_OtpWrite(), provided in the on-chip ROM, support error correction. Error correction works by calculating an 8-bit Error Correction Code (ECC) for each 64-bit data word (half page) when it is programmed into the OTP. When this word is later read from OTP, its corresponding ECC is also read, and a data integrity check is performed. If the check fails, ADSP-BF52x Blackfin Processor Hardware Reference 4-7 error correction on the data word can be attempted using the ECC. Depending on the type of error, the error correction algorithm will perform as shown in Table 4-2. Table 4-2. Hamming Code Single Error Corrections, Double Error Detection Number of bad bits in data word Error(s) detected? Error(s) corrected? 0 N/A N/A 1 Yes Yes 2 Yes No 3 or more No No Error Correction Policy 1. Error correction requires that OTP space is written and read in 64-bit widths. Firmware will only support writing or reading half of an OTP page. 2. Error correction is used to correct data in all pages of OTP space, except the protection pages (0x0 to 0x3) and ECC pages themselves. See “OTP Access” on page 4-10 for more information. 3. Firmware will generate and program the 8-bit ECC fields as mapped in Table 4-3 and Table 4-4. 4. The developer is responsible for locking both the data page(s) and the ECC page(s) after all programming is complete. 5. Pages 0x04 to 0x0F are reserved for ADI factory use. Therefore, pages 0x004 to 0x00F, 0x0E0, and 0x0E1 will be locked coming out of the Analog Devices factory. 4-8 ADSP-BF52x Blackfin Processor Hardware Reference Table 4-3. Mapping for Storage of Error Correction Codes for Unsecured OTP Space Page Byte 15 14 13 12 11 10 9 8 0x0E0 0x007U 0x007L 0x006U 0x006L 0x005U 0x005L 0x004U 0x004L 0x0E1 0x00FU 0x00FL 0x00EU 0x00EL 0x00DU 0x00DL 0x00CU 0x00CL 0x0E2 0x017U 0x017L 0x016U 0x016L 0x015U 0x015L 0x014U 0x014L 0x0FB 0x0DFU 0x0DFL 0x0DEU 0x0DEL 0x0DDU 0x0DDL 0x0DCU 0x0DCL Page 7 6 5 4 3 2 1 0 0x0E0 Unused Unused Unused Unused Unused Unused Unused Unused 0x0E1 0x00BU 0x00BL 0x00AU 0x00AL 0x009U 0x009L 0x008U 0x008L 0x0E2 0x013U 0x013L 0x012U 0x012L 0x011U 0x011L 0x010U 0x010L 0x0FB 0x0DBU 0x0DBL 0x0DAU 0x0DAL 0x0D9U 0x0D9L 0x0D8U 0x0D8L .... .... ADSP-BF52x Blackfin Processor Hardware Reference 4-9 Table 4-4. Mapping for Storage of Error Correction Codes for Secured OTP Space Page Byte 15 14 13 12 11 10 9 8 0x1E0 0x107U 0x107L 0x106U 0x106L 0x105U 0x105L 0x104U 0x104L 0x1E1 0x10FU 0x10FL 0x10EU 0x10EL 0x10DU 0x10DL 0x10CU 0x10CL 0x1E2 0x117U 0x117L 0x116U 0x116L 0x115U 0x115L 0x114U 0x114L 0x1FB 0x1DFU 0x1DFL 0x1DEU 0x1DEL 0x1DDU 0x1DDL 0x1DCU 0x1DCL Page 7 6 5 4 3 2 1 0 0x1E0 0x103U 0x103L 0x102U 0x102L 0x101U 0x101L 0x100U 0x100L 0x1E1 0x10BU 0x10BL 0x10AU 0x10AL 0x109U 0x109L 0x108U 0x108L 0x1E2 0x113U 0x113L 0x112U 0x112L 0x111U 0x111L 0x110U 0x110L 0x1DBL 0x1DAU 0x1DAL 0x1D9U 0x1D9L 0x1D8U 0x1D8L .... .... 0x1FB 0x1DBU O TP Access The ADSP-BF52x on-chip ROM contains functions for initializing OTP timing parameters, and for reading and programming the OTP memory. These functions include bfrom_OtpRead(), bfrom_OtpWrite() and bfrom_OtpCommand(). These functions are callable from C or assembly application code. Use only these functions for accessing OTP memory. Directly accessing memory locations within OTP memory by other means is not supported. 4-10 ADSP-BF52x Blackfin Processor Hardware Reference The existing ECC in ROM is known as “Hamming [72,64]”. This is specifically a 64-bit data, +8-bit ECC field, for 1-bit correction and 2-bit error detection scheme. OTP read/write API must e used for all OTP The ROM-based limited exceptions below). bADI does not support data accesses (see any ECC other than the ECC provided by ADI within the ROM API. This is the only ECC method supported by Analog Devices. Analog Devices does not support direct access of OTP data without using error correction. All attempts to implement other schemes are not guaranteed or supported by Analog Devices. Exceptions: The only bits that do not use ECC are page lock bits (first 4 pages) and the preboot invalidate bits. See the Preboot section in “System Reset and Booting” on page 17-1. OTP memory programming is done serially under software control. Since the unprogrammed OTP memory value defaults to zero—only bits whose value is intended to be “1” have to be programmed. In order to protect areas of OTP memory that have been programmed, or areas which have intentionally been left unprogrammed which end users wish to remain unchanged, write-protect bits can be set for each 128-bit page within OTP memory. Each write-protect bit, when set, will prevent further programming attempts to OTP memory on a per page basis. Refer to the OTP memory map (Figure 4-2 on page 4-4) for details. The ADSP-BF52x Blackfin processor can program OTP through software code executing directly on the Blackfin processor. For the ADSP-BF523/525/527 processor, a charge pump residing on-chip is used to apply the voltage levels appropriate for programming OTP memory. For the ADSP-BF522/524/526 processor, no on-chip charge pump exists, and an externally applied voltage is required to apply the voltage levels appropriate for programming OTP memory. Refer to the processor data sheet for VPPOTP specifications. OTP programming code can be loaded into the processor via JTAG emulation, DMA, and all supported boot methods. ADSP-BF52x Blackfin Processor Hardware Reference 4-11 OTP memory can only be written once (changing a bit from 0 to 1). Once a bit has been changed from a 0 to a 1, it cannot be changed back to 0. The write-protect bits prevent OTP memory that has already been programmed from having any bits that are meant to remain as 0 value later programmed to a value of 1. Prior to accessing OTP memory, refer to the product data sheet for specifications on VDDOTP and VPPOTP voltage levels to ensure reliable OTP programming. OTP timing parameter settings must be set prior to attempting any write accesses to OTP. OTP Timing Parameters In order to read and program the OTP memory reliably, set the OTP timing parameters prior to accessing OTP memory. All of the timing parameters are fields within the OTP_TIMING register (see “OTP_TIMING Register” on page 4-17). The bfrom_OtpCommand() function (detailed in the following sections) is provided in the on-chip ROM to program the timing parameters. The OTP timing parameters must be set using the . bfrom_OtpCommand() OTP read accesses can use the OTP timing default reset value (OTP_TIMING = 0x0000 1485). Using the OTP timing default reset value for writes will result in write errors as this timing value is not appropriate for performing write accesses. Insufficient voltage/current provided to OTP during write access or incorrect OTP timing parameters may return error code 0x11 (multiple bad bits in 64-bit data) during OTP writes. Subsequent reads from this page return 0. 4-12 ADSP-BF52x Blackfin Processor Hardware Reference T iming for the ADSP-BF523/525/527 Processors The OTP timing parameters consist of several concatenated fields that form one value, which is passed as an argument to the bfrom_OtpCommand() function. The developer must calculate a value based upon the desired SCLK frequency at which the OTP access will be performed. This calculated value is combined with a constant value provided by ADI to arrive at the appropriate access setting. The OTP timing parameters are comprised of two values: OTP_TIMING[7:0] = OTP_TP1 = 1000/sclk_period (in nanoseconds) OTP_TIMING[31:8] = OTP_TP2 = 0x0A5488 To ensure reliable OTP write accesses, the user-calculated field must be combined with the OTP_TP2 field specified by Analog Devices as shown in Listing 4-1 and Listing 4-2. Example calculations shown in Listing 4-1 and Listing 4-2 are based upon the VDDOTP and VPPOTP voltages specified in the ADSP-BF522/523/524/525/526/527 Blackfin Embedded Processor Data Sheet. The OTP timing parameter calculations are dependent upon the user-defined SCLK frequency. Do not rely on the specifications in the examples—refer to the processor data sheet for actual VDDOTP voltage, VPPOTP voltage, and SCLK specifications. For SCLK = 12.5ns (80 MHz), the following calculations determine the OTP timing argument for the bfrom_OtpCommand() call. OTP_TP1 = 1000/sclk_period = 1000/12.5 = 0x50 0x0000 0050 OTP_TP2 = (constant) 0x0A54 88xx Calculated OTP timing parameter value 0x0A54 8850 The code for the API call (in C) is: ADSP-BF52x Blackfin Processor Hardware Reference 4-13 Listing 4-1. OTP Timing Calculations for SCLK = 80 MHz // Initialize OTP access settings // Proper access settings for SCLK = 80 MHz const u32 OTP_init_value = 0x0A548850; return_code = bfrom_OtpCommand( OTP_INIT, OTP_init_value); For SCLK = 20.0ns (50 MHz), the following calculations determine the OTP timing argument for the bfrom_OtpCommand() call. OTP_TP1 = 1000/sclk_period = 1000/20.0 = 0x32 0x0000 0032 OTP_TP2 = (constant) 0x0A54 88xx Calculated OTP timing parameter value 0x0A54 8832 The code for the API call (in C) is: Listing 4-2. OTP Timing Calculations for SCLK = 50 MHz // Initialize OTP access settings // Proper access settings for SCLK = 50 MHz const u32 OTP_init_value = 0x0A548832; return_code = bfrom_OtpCommand( OTP_INIT, OTP_init_value); Timing for the ADSP-BF522/524/526 Processors The OTP timing parameters consist of several concatenated fields that form one value, which is passed as an argument to the bfrom_OtpCommand() function. The developer must calculate a value based upon the desired SCLK frequency at which the OTP access will be performed. This calculated value is combined with a constant value provided by ADI to arrive at the appropriate access setting. The OTP timing parameters are comprised of two values: 4-14 ADSP-BF52x Blackfin Processor Hardware Reference OTP_TIMING[7:0] = OTP_TP1 = 1000/sclk_period (in nanoseconds) OTP_TIMING[31:8] = OTP_TP2 = 0x145487 To ensure reliable OTP write accesses, the user-calculated field must be combined as shown in Listing 4-3 and Listing 4-4 with the OTP_TP2 field specified by Analog Devices. Example calculations in Listing 4-3 and Listing 4-4 are based upon the VDDOTP and VPPOTP voltages specified in the ADSP-BF522/523/524/525/526/527 Blackfin Embedded Processor Data Sheet. The OTP timing parameter calculations are dependent upon the user-defined SCLK frequency. Do not rely on the specifications in the examples—refer to the processor data sheet for actual VDDOTP voltage, VPPOTP voltage, and SCLK specifications. For SCLK = 12.5ns (80 MHz), the following field calculations determine the OTP timing argument for the bfrom_OtpCommand() call. OTP_TP1 = 1000 / sclk_period = 1000 / 12.5 = 0x50 0x00000050 OTP_TP2 = (constant) 0x145487xx Calculated OTP timing parameter value 0x14548750 The code for the API call (in C) is: Listing 4-3. OTP Timing Calculations for SCLK = 80 MHz // Initialize OTP access settings // Proper access settings for SCLK = 80 MHz const u32 OTP_init_value = 0x14548750; return_code = bfrom_OtpCommand( OTP_INIT, OTP_init_value); For SCLK = 20.0ns (50 MHz), the following field calculations determine the OTP timing argument for the bfrom_OtpCommand() call. ADSP-BF52x Blackfin Processor Hardware Reference 4-15 OTP_TP1 = 1000 / sclk_period = 1000 / 20.0 = 0x32 0x00000032 OTP_TP2 = (constant) 0x145487xx Calculated OTP timing parameter value 0x14548732 The code for the API call (in C) is: Listing 4-4. OTP Timing Calculations for SCLK = 50 MHz // Initialize OTP access settings // Proper access settings for SCLK = 50 MHz const u32 OTP_init_value = 0x14548732; return_code = bfrom_OtpCommand( OTP_INIT, OTP_init_value); 4-16 ADSP-BF52x Blackfin Processor Hardware Reference O TP_TIMING Register OTP_TIMING Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 15 14 13 12 11 10 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 1 0 1 Reset = 0x0000 1485 Valid for OTP Read Access OTP_TP1 [7:0] OTP_TP2 [31:8] OTP_TP1 = 1000/SCLK Period For ADSP-BF523/525/527 Processors: OTP_TP2 = 0x0A5488 For ADSP-BF522/524/526 Processors: OTP_TP2 = 0x145487 Figure 4-4. OTP_TIMING Register Callable ROM Functions for OTP ACCESS The following functions support OTP access. Initializing OTP This section describes the bfrom_OtpCommand() function for OTP memory controller setup. The prototype and macros to decode the function’s return codes are supplied in the bfrom.h header file located in the VisualDSP++ installation directory. The meaning of the error code is described in “Error Codes” on page 4-24. bfrom_OtpCommand This function implements various commands to setup the OTP controller. The first parameter is a mnemonic label specifying the command. The ADSP-BF52x Blackfin Processor Hardware Reference 4-17 second parameter is a generic value passed as the argument for the requested command. The second parameter is optional and can be an integer value or (via opportune casting) a pointer to an extension structure. There are two commands: • OTP_INIT sets the required timing value (register OTP_TIMING) to “value” • OTP_CLOSE reinitializes the OTP controller. This can be called by the user before exiting Secure Mode if desired. The value parameter may be specified as 0 or NULL. Entry address: 0xEF00 0018 Arguments: R0: command (dCommand) OTP_INIT OTP_CLOSE R1: timing value to be programmed (dValue), not used for OTP_CLOSE C Prototype: u32 bfrom_OtpCommand(u32 dCommand, u32 dValue); Return code: bfrom_OtpCommand() currently always returns with “0”. In the previous examples, the OTP timing parameter was calculated to be 0x0A54 8850 for the ADSP-BF527 processor with SCLK = 80 MHz. See Listing 4-1 on page 4-14. Listing 4-5 on page 4-18 shows a sample of C code that uses the bfrom_OtpCommand() function to program this timing parameter. Listing 4-5. Example Use of bfrom_OtpCommand() #include <bfrom.h> 4-18 ADSP-BF52x Blackfin Processor Hardware Reference #define OTP_TIMING_PARAM (0x0A548850) u32 Otp_Timing_Param_Init() { u32 otp_timing_parameter; u32 RetVal; otp_timing_parameter = OTP_TIMING_PARAM; RetVal = bfrom_OtpCommand(OTP_INIT, otp_timing_parameter); // (equivalently, with a variable): RetVal = bfrom_OtpCommand(OTP_INIT, OTP_TIMING_PARAM); return RetVal; } More examples: Listing 4-6. Another Example Use of bfrom_OtpCommand() //timing parameter const u32 init_value = 0x0A548850; // call sets OTP_TIMING register RetVal = bfrom_OtpCommand(OTP_INIT, init_value); // call sets OTP_TIMING register RetVal = bfrom_OtpCommand(OTP_INIT, 0x0A548850); // call clears OTP controller and data registers RetVal = bfrom_OtpCommand(OTP_CLOSE, NULL); The prototype of bfrom_OtpCommand() is also included in the bfrom.h header file installed with VisualDSP++ 5.0 and later releases. The OTP_INIT macro is defined in bfrom.h as well. Programming and Reading OTP This section describes the bfrom_OtpRead() and bfrom_OtpWrite() functions provided in the ADSP-BF52x processor’s on-chip ROM. The prototypes and macros to decode the return codes are supplied in the ADSP-BF52x Blackfin Processor Hardware Reference 4-19 header file located in the VisualDSP++ installation directory. The meaning of the error code is described in “Error Codes” on page 4-24. bfrom.h bfrom_OtpRead This function reads 64-bit OTP half-pages using error correction. Entry address: 0xEF00 001A Arguments: R0: R1: OTP page address (dPage) Flags (dFlags) OTP_LOWER_HALF OTP_UPPER_HALF OTP_NO_ECC R2: Pointer to 64-bit memory struct (long long) to put read data (*pPageContent) C prototype: u32 bfrom_OtpRead (u32 dPage, u32 dFlags, u64 *pPageContent); Return code: R0: error or warning code, see Table 4-5. This function reads a half-page and stores the content in the 64-bit variable pointed to by its last parameter. The page parameter defines the address. The flags parameter defines whether the upper or the lower half page is to be read. The default reset OTP_TIMING value may be used for all read accesses without requiring that a new value be programmed prior to read accesses. Programming a value valid for write accesses will also allow read accesses. Flag parameter OTP_NO_ECC should not be used with any OTP read access as it bypasses error correction code support. It is only for diagnostic use. 4-20 ADSP-BF52x Blackfin Processor Hardware Reference bfrom_OtpWrite This function writes a half-page with the content in the 64-bit variable pointed to by its last parameter. The page parameter defines the address. Entry address: 0xEF00 001C Arguments: R0: R1: OTP page address (dFlag) Flags (dFlags) OTP_LOWER_HALF OTP_UPPER_HALF OTP_NO_ECC OTP_LOCK OTP_CHECK_FOR_PREV_WRITE R2: Pointer to 64-bit memory struct (long long) that contains the data to be written to OTP memory (*pPageContent) C Prototype: u32 bfrom_OtpWrite (u32 dPage, u32 dFlags, u64 *pPageContent); Return code: R0: error or warning code, see Table 4-5. The dFlags parameter defines whether the upper or the lower half page is to be written and whether the target half page should be checked for a previously written value before any write attempt is made. Additionally, a page can optionally be locked (permanently protected against further writes). When performing pure lock operations (only locking a page without writing any data values to it), the half-page parameter is not required and it makes no difference which half-page is specified if this parameter is included in the function call. ADSP-BF52x Blackfin Processor Hardware Reference 4-21 To reduce the probability of inadvertent writes to OTP pages, this function checks for a valid OTP write timing setting in the OTP_TIMING register. Specifically, bits [31:15] must not be equal to zero. When this field is equal to zero, calls to the write routine cause an access violation error and the requested action is not performed. By calling the bfrom_OtpCommand (OTP_INIT, …) function with appropriate values for reads only and for read/write accesses—the user can protect against inadvertent writes. Users are free to ignore this mechanism by calling bfrom_OtpCommand (OTP_INIT, …) only once for read/write access. When the flag OTP_CHECK_FOR_PREV_WRITE is not specified, a previously written value will be overwritten, both in the ECC and in the data fields, for any unlocked page where a write access is performed. Of course, once a bit was set to “1” it cannot be reset to “0” by the new write operation. This means that, in all likelihood, if the new value is different from the previous one, the result will have multiple bit errors, in either or both the ECC and data fields. the ROM function, a Since the ECC field is written first bywithout writing the newmultiple bit error will abort the operation data value to the OTP data page. Since multiple bit errors have a statistical chance of not being detected as such, this default mode of operation should not be used. Or used with appropriate caution. The flag OTP_CHECK_FOR_PREV_WRITE should always be used when performing write accesses to OTP with the bfrom_OtpWrite() function. If the flag OTP_CHECK_FOR_PREV_WRITE is specified in the call, a write to a previously programmed page causes dedicated error messages and will not be performed. Errors are generated as follows. The 64-bit data and the 8-bit ECC field are read and the total number of “1”s is counted. If this number is equal to or greater than two, the error flag OTP_PREV_WR_ERROR is returned and the write operation is not performed. If the number is 0, the page is certainly blank and the write is performed. If the number is 4-22 ADSP-BF52x Blackfin Processor Hardware Reference one, a more thorough check is performed. If the “1” is in the ECC field, an error flag OTP_SB_DEFECT_ERROR is returned and the write is not performed. If the “1” is in the data field, it is determined whether the value to be written contains a “1” in the same position. If so, the write is performed. If not, the error flag OTP_SB_DEFECT_ERROR is returned and the write is not performed. This error code warns the user that a single-bit defect could be in the page. The user can then decide whether to use this page regardless (by repeating the call without the OTP_CHECK_FOR_PREV_WRITE flag) or skip this page. The OTP_CHECK_FOR_PREV_WRITE flag is ignored when a pure lock operation is requested (for example, a OTP_LOCK flag is set and *pPageContent = NULL). It is therefore unnecessary and harmless to specify this flag. The OTP_CHECK_FOR_PREV_WRITE flag is not ignored when doing a lock operation after a write (for example, OTP_LOCK + write in the same call and *pPageContent = NULL). If the flag parameter for the write operation is OR’d with the OTP_LOCK flag; the write operation, if successful, will be immediately followed by setting the protection bit for the requested full 128-bit page. A special case for using (OTP_LOCK) is the following. If the third parameter is NULL, this call will lock a page without writing any data value to it (pure lock function). Note that in this case, “page” can span all pages from 0x000 to 0x1FF. This is the only way to lock the ECC pages themselves. The use of flag parameter OTP_NO_ECC is only supported in write operations when used to implement write-protection/page-locking. Bypassing error correction in OTP writes may result in loss of OTP data integrity and is not supported for any other OTP access. The preferred method of locking pages is to use the OTP_LOCK parameter in the bfrom_Otp_Write ADSP-BF52x Blackfin Processor Hardware Reference 4-23 function (see “Write-protecting OTP Memory” on page 4-25. Or the preboot invalidate bits can be set (see “Preboot” on page 17-11). The use ofisECC in all OTP accesses other than in this limited exception mandatory. Error Codes This section describes the returned error codes from the API functions. Returned Error Codes from API Functions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 OTP_SUCCESS = 0 x0000 0 Reserved 0 0 0 0 Reserved OTP_ECC_SB_WARN Single bad bit on write of ECC OTP_DATA_SB_WARN Single bad bit on write of 64-bit data OTP_SB_DEFECT_ERROR Single bit defect in the page OTP_PREV_WR_ERROR Attempt to write previously written space OTP_ECC_MULT_ERROR Multple bad bits on write of ECC 0 0 OTP_MASTER_ERROR Master Error Bit = OP[OR(bits 1,2,3,4,5,6,7), AND(bits 8,9)] OTP_WRITE_ERROR OTP Write Error OTP_READ_ERROR OTP Read Error OTP_ACC_VIO_ERROR Attempt to access invalid OTP space OTP_DATA_MULT_ERROR Multiple bad bits on write of 64-bit data Figure 4-5. Returned Error Codes from API Functions 4-24 ADSP-BF52x Blackfin Processor Hardware Reference Table 4-5. Returned Error Codes from API Functions Bit Name Position Example Definition Return Value N/A OTP_SUCCESS 0x0 No Error 0 OTP_MASTER_ERROR 0x1 Master Error Bit = OR [OR (bits 1,2,3,4,5,6,7), AND (bits 8,9)] 1 OTP_WRITE_ERROR 0x3 (E) OTP Write Error 2 OTP_READ_ERROR 0x5 (E) OTP Read Error 3 OTP_ACC_VIO_ERROR 0x9 (E) Attempt to access invalid OTP space 4 OTP_DATA_MULT_ERROR 0x11 (E) Multiple bad bits on write of 64 bit data 5 OTP_ECC_MULT_ERROR 0x21 (E) Multiple bad bits on write of ECC 6 OTP_PREV_WR_ERROR 0x41 (E) Attempt to write previously written space 7 OTP_SB_DEFECT_ERROR 0x81 (E) Single-bit defect in the page 8 OTP_DATA_SB_WARN 0x100 (W) Single bad bit on write of 64 bit data 9 OTP_ECC_SB_WARN 0x200 (W) Single bad bit on write of ECC returns with an error when any of the bits [6:2] are set or both bits [9:8] are set. In this case, the OTP_MASTER_ERROR bit is also set. It returns with a warning if only one of the bits [9:8] is set. bfrom_OtpRead() returns with an error when any of the bits [7:1] are set or both bits [9:8] are set. In this case, the OTP_MASTER_ERROR bit is also set. It returns with a warning if only one of the bits [9:8] is set. bfrom_OtpWrite() bfrom_OtpCommand() currently always returns with “0”. Write-protecting OTP Memory As shown in Figure 4-2 on page 4-4, a small portion of OTP memory is reserved for write-protect bits (“write-protect” is synonymous with ADSP-BF52x Blackfin Processor Hardware Reference 4-25 “page-protect” in the context of this discussion). After programming OTP memory, the programmer can use these protection bits to “lock” the page that was just programmed by setting the write-protect bit corresponding to the OTP data page. Once the write-protect bit is set and the lock is in place, further attempts to write to that page are not allowed, resulting in an error. Page protect bits also can be set to prevent programming of unwritten OTP pages. Once an OTP page is page-protected, the write protection can not be reversed and no further write accesses can be made to the protected page(s). There are four pages reserved for the write-protection bits. Page 0x0 through page 0x3 contain the 512 write-protect bits, one bit for each of the 512 data pages within OTP memory. The first two write-protect bit pages (page 0x0 and page 0x1) correspond to the public (non-secure) regions of the OTP map. The other two write-protect bit pages (page 0x2 and page 0x3) correspond to the protection of private (secure) regions of the OTP map. The processor does not need to be operating in Secure Mode in order to program protection pages associated with secure OTP regions. All protection bits can be written in any security state including Open Mode. access a half-page a protec While readsaand writes effectively lock an at a time, settingfuture tion bit for page will entire page for write accesses (lower and upper half page). The programmer must ensure that all required programming is completed on a full 128-bit OTP data page before setting the write-protect bit for that page. Before locking the page, the programmer must make sure that the full 128-bit OTP page is programmed, or that no future programming will be required for the unprogrammed portion of the page. If P is the OTP page that is to be write-protected, the write-protect bit and its page can be calculated as follows. Let WPP be the write-protect page where the write-protect bit resides. Let WPB be the write-protect bit that needs to be set to lock page P. 4-26 ADSP-BF52x Blackfin Processor Hardware Reference The write-protect page can be calculated by: WPP = P >> 7; and the write-protect bit can be calculated by: WPB = P & 0x7f; Manual calculation generally unnecessary since the bfrom_OtpWrite() function can be used to lock pages (see “OTP Programming Examples” on page 4-28). // lock page (note third parameter equals NULL) return_code = bfrom_OtpWrite( 0x01C, OTP_LOCK, NULL); Locking a single ECC (error correction code) page results in locking the correction codes, which correspond to eight OTP data pages (16 half pages). This is because a 64-bit half-page access must be performed when write protecting the ECC page and every 8-bits within an ECC page is a parity correction code which corresponds to a 64-bit half-page of data in OTP. Therefore, a full 128-bit ECC page holds the correction codes for eight full 128-bit pages of data in OTP, or 16 half-pages. Pages can only be locked as full 128-bit pages even though read/write accesses may occur at 64-bit half-page granularity. Locking a single ECC page will prevent further write access to the corresponding eight OTP data pages. ECC (error correction code) space is not permitted to be written to directly. For example, locking ECC page 0xFB will result in locking the error correction parity data associated with the 16 data pages in the range 0x0D8– 0x0DF. // Only Lock ECC code page ADSP-BF52x Blackfin Processor Hardware Reference 4-27 return_code = bfrom_OtpWrite(0xFB, OTP_LOCK, NULL); write accesses the ECC page 0xFB or No further0x0D8–0x0DFtowill be allowed after writecorresponding data pages protection of the ECC page in this example. OTP the write-protect bits the four Bits [3:0] of whichpage 0 arethe write-protect bits. Ifforthese first are OTP pages, contain bits set, it will prevent the other write-protect bits from being set, thus disabling the write protection mechanism. But this does not prevent the user from programming the other user-programmable OTP pages. Accessing Private OTP Memory In order to read or write to the private area of OTP memory, the processor must be operating in Secure Mode and the OTPSEN bit within the SECURE_SYSSWT register must be set to a value of 1 to enable secured OTP access. For information about Security, Secure Mode and the Secure State Machine, see “Secure State Machine” on page 16-7. OTP Programming Examples The following steps are recommended for accessing OTP memory. 1. Initialize OTP array by calling bfrom_OtpCommand(). 2. Perform OTP read or write access by calling bfrom_OtpRead() or bfrom_OtpWrite(). 3. Call bfrom_OtpCommand() with OTP_CLOSE parameter to re-initialize the OTP controller when OTP read/write access is complete. 4-28 ADSP-BF52x Blackfin Processor Hardware Reference 4. Initialize OTP array by calling bfrom_OtpCommand() for next OTP access. 5. Repeat steps 1–3 for subsequent OTP accesses. In general, it is recommended that OTP_CLOSE be used if sensitive data has been written/read in a secure mode, and the processor is subsequently returned to Open Mode operation. For information about these modes, see Chapter 16, “Security”. To enable access to private OTP memory space while operating in Secure Mode, use the code shown in Listing 4-7. Listing 4-7. Enable Access to Private OTP /* This code enables access to private OTP via OTPSEN bit */ *pSECURE_SYSSWT = (*pSECURE_SYSSWT) | OTPSEN; SSYNC(); ... To enable JTAG emulation and access to private OTP memory space via OTPSEN while operating in Secure Mode, use the code shown in Listing 4-8. Listing 4-8. Enable Access to Private OTP and Enable JTAG Emulation /* This code enables JTAG and enables access to private OTP via OTPSEN bit */ *pSECURE_SYSSWT = (*pSECURE_SYSSWT & (~EMUDABL)) | OTPSEN; SSYNC(); ... To read pages 0x4 through 0xDF in public OTP memory space and print results to the VisualDSP++ console, use the code shown in Listing 4-9. ADSP-BF52x Blackfin Processor Hardware Reference 4-29 Listing 4-9. Read Pages 0x4 Through 0xDF and Print Results #include <blackfin.h> #include <bfrom.h> u32 return_code, i; u64 value; // Initialize OTP timing parameter // Proper timing for OTP read access const u32 OTP_init_value = 0x00001485; return_code = bfrom_OtpCommand( OTP_INIT, OTP_init_value); ... for (i= 0x004; <0x0xE0; i++) { return_code = bfrom_OtpRead(i, OTP_LOWER_HALF, &value); printf(“page: 0x%03xL, Content ECC: 0x%01611x, returncode: 0x%03x \n”, i, value, return_code); return_code = bfrom_OtpRead(i, OTP_UPPER_HALF, &value); printf(“page: 0x%03xH, Content ECC: 0x%01611x, returncode: 0x%03x \n”, i, value, return_code); } To write and lock a single OTP page and return the results to the VisualDSP++ console via printf, use the code shown in Listing 4-10. Listing 4-10. Perform OTP Write to a Single Page #include <blackfin.h> #include <bfrom.h> u64 value; u32 return_code; // Initialize OTP timing parameter // Proper timing for SCLK = 80 MHz const u32 OTP_init_value = 0x0A548850; return_code = bfrom_OtpCommand( OTP_INIT, OTP_init_value); return_code = bfrom_OtpWrite(0x01C, OTP_LOWER_HALF | 4-30 ADSP-BF52x Blackfin Processor Hardware Reference OTP_CHECK_FOR_PREV_WRITE, &testdata); printf(“WRITE page: 0x%03xL, Content ECC: 0x%01611x, returncode: 0x%03x \n”, 0x1C, testdata, return_code); return_code = bfrom_OtpWrite(0x01C, OTP_UPPER_HALF | OTP_CHECK_FOR_PREV_WRITE | OTP_LOCK, &testdata); printf(“WRITE page: 0x%03xH, Content ECC: 0x%01611x, returncode: 0x%03x \n”, 0x1C, testdata, return_code); Note that locking a page will lock the full 128-bit page, while the previous examples perform OTP access on a 64-bit half-page granularity. This is the finest level of granularity that is allowed due to the OTP error correction implementation. The page lock should occur only after both the lower and upper portion of the page have been written. Note that the page lock operation is performed on the second and final access to the page in the code in Listing 4-10. The programmer may wish to lock specific OTP pages in a separate access after writing data values is already complete. OTP pages are typically locked to protect them from being overwritten or to prevent inadvertent or malicious tampering. This can be done using the code shown in Listing 4-11. Listing 4-11. Perform Pure Page Lock without Writing Data #include <blackfin.h> #include <bfrom.h> u64 value; u32 return_code; // Initialize OTP timing parameter // Proper timing for SCLK = 80 MHz const u32 OTP_init_value = 0x0A548850; return_code = bfrom_OtpCommand( OTP_INIT, OTP_init_value); return_code = bfrom_OtpWrite(0x01C, OTP_LOCK, NULL); The code shown in Listing 4-12 can be used to read the chip ID code. ADSP-BF52x Blackfin Processor Hardware Reference 4-31 Listing 4-12. Read Unique Chip ID #include <bfrom.h> #include <stdio.h> #include <cdefBF526.h> #include <ccblkfn.h> // contains intrinsics for Blackfin // assembler commands void main() { u32 return_code; // 32-bit element to hold return code u64 idupper, idlower; // Two 64-bit elements to hold the // upper & lower halves of the unique chip id // Code to read the unique chip ID return_code = bfrom_OtpRead(0x4, OTP_LOWER_HALF, &idlower); printf("page: 0x%03xL, Content ECC: 0x%016llx, returncode: 0x%03x\n", 0x4, idlower, return_code); return_code = bfrom_OtpRead(0x4, OTP_UPPER_HALF, &idupper); printf("page: 0x%03xH, Content ECC: 0x%016llx, returncode: 0x%03x\n", 0x4, idupper, return_code); return; } 4-32 ADSP-BF52x Blackfin Processor Hardware Reference 5 SYSTEM INTERRUPTS This chapter discusses the system interrupt controller (SIC). While this chapter does refer to features of the core event controller (CEC), it does not cover all aspects of it. Please refer to the Blackfin Processor Programming Reference for more information on the CEC. Specific Information for the ADSP-BF52x For details regarding the number of system interrupts for the ADSP-BF52x product, please refer to the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. To determine how each of the system interrupts is multiplexed with other functional pins, refer to Table 9-2 on page 9-5 through Table 9-5 on page 9-9 in Chapter 9, “General-Purpose Ports”. For a list of MMR addresses for each DMA, refer to Appendix A, “System MMR Assignments”. System interrupt behavior for the ADSP-BF52x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Behavior for the ADSP-BF52x Processor” on page 5-15. Overview The processor system has numerous peripherals, which therefore require many supporting interrupts. ADSP-BF52x Blackfin Processor Hardware Reference 5-1 F eatures The Blackfin architecture provides a two-level interrupt processing scheme: • The core event controller (CEC) runs in the CCLK clock domain. It interacts closely with the program sequencer and manages the event vector table (EVT). The CEC processes not only core-related interrupts such as exceptions, core errors, and emulation events; it also supports software interrupts. • The system interrupt controller (SIC) runs in the SCLK clock domain. It masks, groups, and prioritizes interrupt requests signalled by on-chip or off-chip peripherals and forwards them to the CEC. Description of Operation The following sections describe the operation of the system interrupts. Events and Sequencing The processor employs a two-level event control mechanism. The processor SIC works with the CEC to prioritize and control all system interrupts. The SIC provides mapping between the many peripheral interrupt sources and the prioritized general-purpose interrupt inputs of the core. This mapping is programmable, and individual interrupt sources can be masked in the SIC. The CEC of the processor manages five types of activities or events: • Emulation • Reset • Nonmaskable interrupts (NMI) 5-2 ADSP-BF52x Blackfin Processor Hardware Reference • Exceptions • Interrupts Note the word event describes all five types of activities. The CEC manages fifteen different events in all: emulation, reset, NMI, exception, and eleven interrupts. An interrupt is an event that changes the normal processor instruction flow and is asynchronous to program flow. In contrast, an exception is a software initiated event whose effects are synchronous to program flow. The event system is nested and prioritized. Consequently, several service routines may be active at any time, and a low priority event may be pre-empted by one of higher priority. The CEC supports nine general-purpose interrupts (IVG7 – IVG15) in addition to the dedicated interrupt and exception events that are described in Table 5-1. It is common for applications to reserve the lowest or the two lowest priority interrupts (IVG14 and IVG15) for software interrupts, leaving eight or seven prioritized interrupt inputs (IVG7 – IVG13) for peripheral purposes. Refer to Table 5-1. Table 5-1. System and Core Event Mapping Event Source Core Event Name Core events Emulation (highest priority) EMU Reset RST NMI NMI Exception EVX Reserved – Hardware error IVHW Core timer IVTMR ADSP-BF52x Blackfin Processor Hardware Reference 5-3 Table 5-1. System and Core Event Mapping (Continued) Event Source Core Event Name System interrupts IVG7–IVG13 Software interrupt 1 IVG14 Software interrupt 2 (lowest priority) IVG15 S ystem Peripheral Interrupts To service the rich set of peripherals, the SIC has multiple interrupt request inputs and outputs that go to the CEC. The primary function of the SIC is to mask, group, and prioritize interrupt requests and to forward them to the nine general-purpose interrupt inputs of the CEC (IVG7– IVG15). Additionally, the SIC controller can enable individual peripheral interrupts to wake up the processor from Idle or power-down state. The nine general-purpose interrupt inputs (IVG7–IVG15) of the core event controller have fixed priority. Of this group, the IVG7 channel has the highest priority and IVG15 has the lowest priority. Therefore, the interrupt assignment in the SIC_IAR registers not only groups peripheral interrupts; it also programs their priority by assigning them to individual IVG channels. However, the relative priority of peripheral interrupts can be set by mapping the peripheral interrupt to the appropriate general-purpose interrupt level in the core. The mapping is controlled by the SIC_IAR register settings shown in Figure 5-2 on page 5-11 and the tables in Appendix A, “System MMR Assignments”. If more than one interrupt source is mapped to the same interrupt, they are logically OR’ed, with no hardware prioritization. Software can prioritize the interrupt processing as required for a particular system application. with peripheral For general-purpose interruptscare tomultiplethat softwareinterrupts assigned to them, take special ensure correctly processes all pending interrupts sharing that input. Software is responsible for prioritizing the shared interrupts. 5-4 ADSP-BF52x Blackfin Processor Hardware Reference The core timer has a dedicated input to the CEC controller. Its interrupt is not routed through the SIC controller and always has higher priority than requests from all peripherals. The SIC_IMASK register allows software to mask any peripheral interrupt source at the SIC level. This functionality is independent of whether the particular interrupt is enabled at the peripheral itself. At reset, the contents of the SIC_IMASK register are all 0s to mask off all peripheral interrupts. Turning off a system interrupt mask and enabling the particular interrupt is performed by writing a 1 to a bit location in the SIC_IMASK register. The SIC includes one or more read-only SIC_ISR registers with individual bits which correspond to the interrupt status of one of the peripheral interrupt sources. When the SIC detects the interrupt, the bit is asserted. When the SIC detects that the peripheral interrupt input has been deasserted, the respective bit in the system interrupt status register is cleared. Note for some peripherals, such as general-purpose I/O asynchronous input interrupts, many cycles of latency may pass from the time an interrupt service routine initiates the clearing of the interrupt (usually by writing a system MMR) to the time the SIC senses that the interrupt has been deasserted. Depending on how interrupt sources map to the general-purpose interrupt inputs of the core, the interrupt service routine may have to interrogate multiple interrupt status bits to determine the source of the interrupt. One of the first instructions executed in an interrupt service routine should read the SIC_ISR register to determine whether more than one of the peripherals sharing the input has asserted its interrupt output. The service routine should fully process all pending, shared interrupts before ADSP-BF52x Blackfin Processor Hardware Reference 5-5 executing the RTI, which enables further interrupt generation on that interrupt input. an Whenthe interrupt’s service routine is finished, the RTI instruction clears appropriate bit in the register. However, the releIPEND vant SIC_ISR bit is not cleared unless the service routine clears the mechanism that generated the interrupt. Many systems need relatively few interrupt-enabled peripherals, allowing each peripheral to map to a unique core priority level. In these designs, the SIC_ISR register will seldom, if ever, need to be interrogated. The SIC_ISR register is not affected by the state of the SIC_IMASK register and can be read at any time. Writes to the SIC_ISR register have no effect on its contents. Peripheral DMA channels are mapped in a fixed manner to the peripheral interrupt IDs. However, the assignment between peripherals and DMA channels is freely programmable with the DMA_PERIPHERAL_MAP registers. Table 5-1 on page 5-3 and Table 5-2 on page 5-11 show the default DMA assignment. Once a peripheral has been assigned to any other DMA channel it uses the new DMA channel’s interrupt ID regardless of whether DMA is enabled or not. Therefore, clean DMA_PERIPHERAL_MAP management is required even if the DMA is not used. The default setup should be the best choice for all non-DMA applications. For dynamic power management, any of the peripherals can be configured to wake up the core from its idled state to process the interrupt, simply by enabling the appropriate bit in the SIC_IWR register (refer to Table 5-1 on page 5-3 and Table 5-2 on page 5-11). If a peripheral interrupt source is enabled in SIC_IWR and the core is idled, the interrupt causes the DPMC to initiate the core wakeup sequence in order to process the interrupt. Note this mode of operation may add latency to interrupt processing, depending on the power control state. For further discussion of power modes and the idled state of the core, see the Dynamic Power Management chapter. 5-6 ADSP-BF52x Blackfin Processor Hardware Reference The SIC_IWR register has no effect unless the core is idled. By default, all interrupts generate a wakeup request to the core. However, for some applications it may be desirable to disable this function for some peripherals, such as for a SPORT transmit interrupt. The SIC_IWR register can be read from or written to at any time. To prevent spurious or lost interrupt activity, this register should be written to only when all peripheral interrupts are disabled. is independent The wakeup functionsource is enabled of the interrupt bmask function. If an interrupt in the ut masked SIC_IWR off in the SIC_IMASK register, the core wakes up if it is idled, but it does not generate an interrupt. The peripheral interrupt structure of the processor is flexible. Upon reset, multiple peripheral interrupts share a single, general-purpose interrupt in the core by default, as shown in Table 5-2 on page 5-11. An interrupt service routine that supports multiple interrupt sources must interrogate the appropriate system memory mapped registers (MMRs) to determine which peripheral generated the interrupt. Programming Model The programming model for the system interrupts is described in the following sections. ADSP-BF52x Blackfin Processor Hardware Reference 5-7 S ystem Interrupt Initialization If the default peripheral-to-IVG assignments shown in Table 5-1 on page 5-3 and Table 5-2 on page 5-11 are acceptable, then interrupt initialization involves only: • Initialization of the core event vector table (EVT) vector address entries • Initialization of the IMASK register • Unmasking the specific peripheral interrupts that the system requires in the SIC_IMASK register System Interrupt Processing Summary Referring to Figure 5-1 on page 5-10, note when an interrupt (interrupt A) is generated by an interrupt-enabled peripheral: 1. SIC_ISR 2. SIC_IWR 3. SIC_IMASK logs the request and keeps track of system interrupts that are asserted but not yet serviced (that is, an interrupt service routine hasn’t yet cleared the interrupt). checks to see if it should wake up the core from an idled state based on this interrupt request. masks off or enables interrupts from peripherals at the system level. If interrupt A is not masked, the request proceeds to Step 4. 4. The SIC_IAR registers, which map the peripheral interrupts to a smaller set of general-purpose core interrupts (IVG7 – IVG15), determine the core priority of interrupt A. 5. 5-8 adds interrupt A to its log of interrupts latched by the core but not yet actively being serviced. ILAT ADSP-BF52x Blackfin Processor Hardware Reference 6. masks off or enables events of different core priorities. If the IVGx event corresponding to interrupt A is not masked, the process proceeds to Step 7. IMASK 7. The event vector table (EVT) is accessed to look up the appropriate vector for interrupt A’s interrupt service routine (ISR). 8. When the event vector for interrupt A has entered the core pipeline, the appropriate IPEND bit is set, which clears the respective ILAT bit. Thus, IPEND tracks all pending interrupts, as well as those being presently serviced. 9. When the interrupt service routine (ISR) for interrupt A has been executed, the RTI instruction clears the appropriate IPEND bit. However, the relevant SIC_ISR bit is not cleared unless the interrupt service routine clears the mechanism that generated interrupt A, or if the process of servicing the interrupt clears this bit. It should be noted that emulation, reset, NMI, and exception events, as well as hardware error (IVHW) and core timer (IVTMR) interrupt requests, enter the interrupt processing chain at the ILAT level and are not affected by the system-level interrupt registers (SIC_IWR, SIC_ISR, SIC_IMASK, SIC_IAR). If multiple interrupt sources share a single core interrupt, then the interrupt service routine (ISR) must identify the peripheral that generated the ADSP-BF52x Blackfin Processor Hardware Reference 5-9 interrupt. The ISR may then need to interrogate the peripheral to determine the appropriate action to take. EMU RESET NMI EVX IVTMR IVHW "INTERRUPT A" PERIPHERAL INTERRUPT REQUESTS SYSTEM WAKEUP (SIC_IWR) SYSTEM INTERRUPT MASK (SIC_IMASK) ASSIGN SYSTEM PRIORITY (SIC_IAR) CORE STATUS (ILAT) CORE INTERRUPT MASK (IMASK) SYSTEM STATUS (SIC_ISR) CORE EVENT VECTOR TABLE (EVT[15:0]) CORE PENDING (IPEND) TO DYNAMIC POWER MANAGEMENT CONTROLLER SYSTEM INTERRUPT CONTROLLER CORE EVENT CONTROLLER NOTE: NAMES IN PARENTHESES ARE MEMORY-MAPPED REGISTERS. Figure 5-1. Interrupt Processing Block Diagram System Interrupt Controller Registers The SIC registers are described in the following sections. These registers can be read from or written to at any time in supervisor mode. It is advisable, however, to configure them in the reset interrupt service routine before enabling interrupts. To prevent spurious or lost interrupt activity, these registers should be written to only when all peripheral interrupts are disabled. 5-10 ADSP-BF52x Blackfin Processor Hardware Reference S ystem Interrupt Assignment (SIC_IAR) Register The SIC_IAR register maps each peripheral interrupt ID to a corresponding IVG priority level. This is accomplished with 4-bit groupings that translate to IVG levels as shown in Table 5-2 and Figure 5-2 on page 5-11. In other words, Table 5-2 defines the value to write in a 4-bit field within SIC_IAR in order to configure a peripheral interrupt ID for a particular IVG priority. Refer to Table 5-1 on page 5-3 for information on SIC_IAR mappings for this specific processor. System Interrupt Assignment Register (SIC_IAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Grouping 4 ID Grouping 7 ID Grouping 5 ID Grouping 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Grouping 0 ID Grouping 3 ID Grouping 1 ID Grouping 2 Figure 5-2. System Interrupt Assignment Register Table 5-2. IVG Select Definitions General-purpose Interrupt Value in SIC_IAR IVG7 0 IVG8 1 IVG9 2 IVG10 3 IVG11 4 IVG12 5 ADSP-BF52x Blackfin Processor Hardware Reference 5-11 Table 5-2. IVG Select Definitions (Continued) General-purpose Interrupt Value in SIC_IAR IVG13 6 IVG14 7 IVG15 8 S ystem Interrupt Mask (SIC_IMASK) Register The SIC_IMASK register masks or enables peripheral interrupts at the system level. A "0" in a bit position masks off (disables) interrupts for that particular peripheral interrupt ID. A "1" enables interrupts for that interrupt ID. Refer to Table 5-1 on page 5-3 and Table 5-2 on page 5-11 for information on how peripheral interrupt IDs are mapped to the SIC_IMASK register(s) for this particular processor. System Interrupt Status (SIC_ISR) Register The SIC_ISR register keeps track of system interrupts that are asserted but not yet serviced. A "0" in a bit position indicates that a particular interrupt is deasserted. A "1" indicates that it is asserted. Refer to Table 5-1 on page 5-3 and Table 5-2 on page 5-11 for information on how peripheral interrupt IDs are mapped to the SIC_ISR register(s) for this particular processor. System Interrupt Wakeup-Enable (SIC_IWR) Register The SIC_IWR register allows an interrupt request to wake up the processor core from an idled state. A "0" in a bit position indicates that a particular peripheral interrupt ID is not configured to wake the core (upon assertion of the interrupt request). A "1" indicates that it is configured to do so. Refer to Table 5-1 on page 5-3 and Table 5-2 on page 5-11 for informa- 5-12 ADSP-BF52x Blackfin Processor Hardware Reference tion on how peripheral interrupt IDs are mapped to the SIC_IWR register(s) for this particular processor. Programming Examples The following section provides an example for servicing interrupt requests. Clearing Interrupt Requests When the processor services a core event it automatically clears the requesting bit in the ILAT register and no further action is required by the interrupt service routine. It is important to understand that the SIC controller does not provide any interrupt acknowledgment feedback mechanism from the CEC controller back to the peripherals. Although the ILAT bits clear in the same way when a peripheral interrupt is serviced, the signalling peripheral does not release its level-sensitive request until it is explicitly instructed by software. If however, the peripheral keeps requesting, the respective ILAT bit is set again immediately and the service routine is invoked again as soon as its first run terminates by an RTI instruction. Every software routine that services peripheral interrupts must clear the signalling interrupt request in the respective peripheral. The individual peripherals provide customized mechanisms for how to clear interrupt requests. Receive interrupts, for example, are cleared when received data is read from the respective buffers. Transmit requests typically clear when software (or DMA) writes new data into the transmit buffers. These implicit acknowledge mechanisms avoid the need for cycle-consuming software handshakes in streaming interfaces. Other peripherals such as timers, GPIOs, and error requests require explicit acknowledge instructions, which are typically performed by efficient W1C (write-1-to-clear) operations. ADSP-BF52x Blackfin Processor Hardware Reference 5-13 Listing 5-1 shows a representative example of how a GPIO interrupt request might be serviced. Listing 5-1. Servicing GPIO Interrupt Request #include <defBF527.h> /*ADSP-BF527 product is used as an example*/ .section program; _portg_a_isr: /* push used registers */ [--sp] = (r7:7, p5:5); /* clear interrupt request on GPIO pin PG2 */ /* no matter whether used A or B channel */ p5.l = lo(PORTGIO_CLEAR); p5.h = hi(PORTGIO_CLEAR); r7 = PG2; w[p5] = r7; /* place user code here */ /* sync system, pop registers and exit */ ssync; (r7:7, p5:5) = [sp++]; rti; _portg_a_isr.end: The W1C instruction shown in this example may require several SCLK cycles to complete, depending on system load and instruction history. The program sequencer does not wait until the instruction completes and continues program execution immediately. The SSYNC instruction ensures that the W1C command indeed cleared the request in the GPIO peripheral before the RTI instruction executes. However, the SSYNC instruction does not guarantee that the release of interrupt request has also been recognized by the CEC controller, which may require a few more CCLK cycles depending on the CCLK-to-SCLK ratio. In service routines consisting of a few 5-14 ADSP-BF52x Blackfin Processor Hardware Reference instructions only, two SSYNC instructions are recommended between the clear command and the RTI instruction. However, one SSYNC instruction is typically sufficient if the clear command performs in the very beginning of the service routine, or the SSYNC instruction is followed by another set of instructions before the service routine returns. Commonly, a pop-multiple instruction is used for this purpose as shown in Listing 5-1. The level-sensitive nature of peripheral interrupts enables more than one of them to share the same IVG channel and therefore the same interrupt priority. This is programmable using the assignment registers. Then a common service routine typically interrogates the SIC_ISR register to determine the signalling interrupt source. If multiple peripherals are requesting interrupts at the same time, it is up to the service routine to either service all requests in a single pass or to service them one by one. If only one request is serviced and the respective request is cleared by software before the RTI instruction executes, the same service routine is invoked another time because the second request is still pending. While the first approach may require fewer cycles to service both requests, the second approach enables higher priority requests to be serviced more quickly in a non-nested interrupt system setup. Unique Behavior for the ADSP-BF52x Processor Interfaces Figure 5-3 on page 5-16 and Figure 5-4 on page 5-17 provide an overview of how the individual peripheral interrupt request lines connect to the ADSP-BF52x Blackfin Processor Hardware Reference 5-15 SIC. These figures show how the eight SIC_IAR registers control the assignment to the nine available peripheral request inputs of the CEC. IVG6 IVG5 IVG3 IVG2 IVG1 IVG0 CORE TIMER EXCEPTIONS NMI RESET EMULATION IVG7 IVG8 IVG9 IVG10 IVG11 and IPEND registers are part of IVG12 IVG14 IVG13 ILAT, IMASK, IVG15 memory-mapped TheCEC controller. the WAKE UP IPEND IMASK SIC_IAR0 SIC_IAR1 SIC_IMASK0 16 17 18 19 20 21 22 23 SIC_IAR2 DMA10 (UART1 RX) DMA11 (UART1 TX) OTP GP COUNTER DMA1 (MAC RX/HOSTDP) PORT H INTERRUPT A DMA2 (MAC TX/NFC) PORT H INTERRUPT B 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31 SIC_IAR3 DMA3 (SPORT0 RX) DMA4 (SPORT0 TX) DMA5 (SPORT1 RX) DMA6 (SPORT1 TX) TWI INTERRUPT DMA7 (SPI) DMA8 (UART0 RX) DMA9 (UART0 TX) 1 2 3 4 5 6 7 SIC_IWR0 SPORT0 STATUS SPORT1 STATUS RESERVED RESERVED UART0 STATUS UART1 STATUS REAL TIME CLOCK DMA0 (PPI/NFC) 0 SIC_ISR0 PLL WAKEUP INTERRUPT DMA ERROR (GENERIC) DMAR0 BLOCK INTERRUPT DMAR1 BLOCK INTERRUPT DMAR0 OVERFLOW ERROR DMAR1 OVERFLOW ERROR PPI STATUS MAC STATUS HARDWARE ERROR ILAT Figure 5-3. Interrupt Routing Overview (Part 1) 5-16 ADSP-BF52x Blackfin Processor Hardware Reference IVG3 IVG2 IVG1 EXCEPTIONS NMI RESET IVG0 IVG6 IVG5 CORE TIMER IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG14 IVG13 IVG15 WAKE UP IPEND IMASK EMULATION 24 25 26 27 28 29 30 31 SIC_IAR5 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SIC_IAR6 16 17 18 19 20 21 22 23 SIC_IAR7 NFC STATUS HOSTDP STATUS HOST READ DONE INTERRUPT RESERVED USB_INT0 INTERRUPT USB_INT1 INTERRUPT USB_INT2 INTERRUPT USB DMAINT SIC_IMASK1 8 9 10 11 12 13 14 15 SIC_IWR1 PORT G INTERRUPT A PORT G INTERRUPT B MDMA0 STREAM 0 INTERRUPT MDMA1 STREAM 0 INTERRUPT SOFTWARE WATCHDOG INTERRUPT PORT F INTERRUPT A PORT F INTERRUPT B SPI STATUS SIC_IAR4 0 1 2 3 4 5 6 7 SIC_ISR1 TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 HARDWARE ERROR ILAT Figure 5-4. Interrupt Routing Overview (Part 2) ADSP-BF52x Blackfin Processor Hardware Reference 5-17 S ystem Peripheral Interrupts The MAC interrupt requests shown in Figure 5-3 on page 5-16 are available only on ADSP-BF527 parts. However, for code compatibility, all of the default assignments for the ADSP-BF52x processors are the same. Table 5-3 and Table 5-4 on page 5-20 show the peripheral interrupt events, the default mapping of each event, the peripheral interrupt ID used in the system interrupt assignment registers (SIC_IAR), and the core interrupt ID. Note that the system interrupt to core event mappings shown are the default values at reset and can be changed by software. Where there is more than one DMA interrupt source for a given interrupt ID number, the default DMA source mapping is listed first in parentheses. The peripheral interrupt structure of the processor is flexible. Upon reset, multiple peripheral interrupts share a single, general-purpose interrupt in the core by default, as shown in Table 5-3 on page 5-18 and Table 5-4 on page 5-20. An interrupt service routine that supports multiple interrupt sources must interrogate the appropriate system memory mapped registers (MMRs) to determine which peripheral generated the interrupt. Table 5-3. Peripheral Interrupt Events (Part 1) Peripheral ID# Bit Position SIC_ISR0, SIC_IMASK0, SIC_IWR0 SIC_IAR3–0 31 Bit 31 Port H interrupt B SIC_IAR3[31:28] IVG11 30 Bit 30 DMA2 (Ethernet MAC TX/NFC) SIC_IAR3[27:24] IVG11 29 Bit 29 Port H interrupt A SIC_IAR3[23:20] IVG11 28 Bit 28 DMA1 (Ethernet MAC RX/HOSTDP) SIC_IAR3[19:16] IVG11 27 Bit 27 GP Counter SIC_IAR3[15:12] IVG11 26 Bit 26 OTP Memory SIC_IAR3[11:8] 5-18 Default Mapping IVG11 ADSP-BF52x Blackfin Processor Hardware Reference Table 5-3. Peripheral Interrupt Events (Part 1) (Continued) Peripheral ID# Bit Position SIC_ISR0, SIC_IMASK0, SIC_IWR0 SIC_IAR3–0 Default Mapping 25 Bit 25 DMA11 (UART1 TX) SIC_IAR3[7:4] IVG10 24 Bit 24 DMA10 (UART1 RX) SIC_IAR3[3:0] IVG10 23 Bit 23 DMA9 (UART0 TX) SIC_IAR2[31:28] IVG10 22 Bit 22 DMA8 (UART0 RX) SIC_IAR2[27:24] IVG10 21 Bit 21 DMA7 (SPI RX/TX) SIC_IAR2[23:20] IVG10 20 Bit 20 TWI SIC_IAR2[19:16] IVG10 19 Bit 19 DMA6 (SPORT1 TX) SIC_IAR2[15:12] IVG9 18 Bit 18 DMA5 (SPORT1 RX) SIC_IAR2[11:8] IVG9 17 Bit 17 DMA4 (SPORT0 TX) SIC_IAR2[7:4] IVG9 16 Bit 16 DMA3 (SPORT0 RX) SIC_IAR2[3:0] IVG9 15 Bit 15 DMA0 (PPI/NFC) SIC_IAR1[31:28] IVG8 14 Bit 14 Real-time clock SIC_IAR1[27:24] IVG8 13 Bit 13 UART1 status SIC_IAR1[23:20] IVG7 12 Bit 12 UART0 status SIC_IAR1[19:16] IVG7 11 Bit 11 Reserved SIC_IAR1[15:12] IVG7 10 Bit 10 Reserved SIC_IAR1[11:8] IVG7 9 Bit 9 SPORT1 status SIC_IAR1[7:4] IVG7 8 Bit 8 SPORT0 status SIC_IAR1[3:0] IVG7 7 Bit 7 Ethernet MAC status SIC_IAR0[31:28] IVG7 6 Bit 6 PPI error SIC_IAR0[27:24] IVG7 5 Bit 5 DMAR1 overflow error SIC_IAR0[23:20] IVG7 4 Bit 4 DMAR0 overflow error SIC_IAR0[19:16] IVG7 3 Bit 3 DMAR1 block interrupt SIC_IAR0[15:12] IVG7 2 Bit 2 DMAR0 block interrupt SIC_IAR0[11:8] ADSP-BF52x Blackfin Processor Hardware Reference IVG7 5-19 Table 5-3. Peripheral Interrupt Events (Part 1) (Continued) Peripheral ID# Bit Position SIC_ISR0, SIC_IMASK0, SIC_IWR0 SIC_IAR3–0 Default Mapping 1 Bit 1 DMA Error (generic) SIC_IAR0[7:4] IVG7 0 Bit 0 PLL Wakeup SIC_IAR0[3:0] IVG7 Table 5-4. Peripheral Interrupt Events (Part 2) Peripheral ID# Bit Position SIC_ISR1, SIC_IMASK1, SIC_IWR1 SIC_IAR7–4 Default Mapping 63 Bit 31 Reserved SIC_IAR7[31:28] IVG13 62 Bit 30 Reserved SIC_IAR7[27:24] IVG13 61 Bit 29 Reserved SIC_IAR7[23:20] IVG13 60 Bit 28 Reserved SIC_IAR7[19:16] IVG12 59 Bit 27 Reserved SIC_IAR7[15:12] IVG12 58 Bit 26 Reserved SIC_IAR7[11:8] IVG12 57 Bit 25 Reserved SIC_IAR7[7:4] IVG12 56 Bit 24 Reserved SIC_IAR7[3:0] IVG12 55 Bit 23 USB_DMAINT SIC_IAR6[31:28] IVG10 54 Bit 22 USB_INT2 SIC_IAR6[27:24] IVG10 53 Bit 21 USB_INT1 SIC_IAR6[23:20] IVG10 52 Bit 20 USB_INT0 SIC_IAR6[19:16] IVG10 51 Bit 19 Reserved SIC_IAR6[15:12] IVG10 50 Bit 18 Host read done SIC_IAR6[11:8] IVG7 49 Bit 17 HOSTDP status SIC_IAR6[7:4] IVG7 48 Bit 16 NFC status SIC_IAR6[3:0] IVG7 47 Bit 15 SPI status SIC_IAR5[31:28] IVG7 46 Bit 14 Port F interrupt B SIC_IAR5[27:24] IVG13 45 Bit 13 Port F interrupt A SIC_IAR5[23:20] IVG13 44 Bit 12 Watchdog timer SIC_IAR5[19:16] IVG13 5-20 ADSP-BF52x Blackfin Processor Hardware Reference Table 5-4. Peripheral Interrupt Events (Part 2) (Continued) Peripheral ID# Bit Position SIC_ISR1, SIC_IMASK1, SIC_IWR1 SIC_IAR7–4 Default Mapping 43 Bit 11 MDMA1 SIC_IAR5[15:12] IVG13 42 Bit 10 MDMA0 SIC_IAR5[11:8] IVG13 41 Bit 9 Port G interrupt B SIC_IAR5[7:4] IVG12 40 Bit 8 Port G interrupt A SIC_IAR5[3:0] IVG12 39 Bit 7 Timer 7 SIC_IAR4[31:28] IVG12 38 Bit 6 Timer 6 SIC_IAR4[27:24] IVG12 37 Bit 5 Timer 5 SIC_IAR4[23:20] IVG12 36 Bit 4 Timer 4 SIC_IAR4[19:16] IVG12 35 Bit 3 Timer 3 SIC_IAR4[15:12] IVG12 34 Bit 2 Timer 2 SIC_IAR4[11:8] IVG12 33 Bit 1 Timer 1 SIC_IAR4[7:4] IVG12 32 Bit 0 Timer 0 SIC_IAR4[3:0] IVG12 ADSP-BF52x Blackfin Processor Hardware Reference 5-21 5-22 ADSP-BF52x Blackfin Processor Hardware Reference 6 DIRECT MEMORY ACCESS This chapter describes the direct memory access (DMA) controller. Following an overview and list of key features is a description of operation and functional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. This chapter describes the features common to all the DMA channels, as well as how DMA operations are set up. For specific peripheral features, see the appropriate peripheral chapter for additional information. Performance and bus arbitration for DMA operations can be found in Chapter 2, “Chip Bus Hierarchy”. Specific Information for the ADSP-BF52x For details regarding the number of DMA controllers for the ADSP-BF52x product, please refer to the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. For DMA interrupt vector assignments, refer to Table 5-3 on page 5-18 in Chapter 5, “System Interrupts”. To determine how each of the DMAs is multiplexed with other functional pins, refer to Table 9-2 on page 9-5 through Table 9-5 on page 9-9 in Chapter 9, “General-Purpose Ports”. For a list of MMR addresses for each DMA, refer to Appendix A, “System MMR Assignments”. ADSP-BF52x Blackfin Processor Hardware Reference 6-1 DMA controller behavior for the ADSP-BF52x that differs from the general information in this chapter can be found in the section “Unique Behavior for the ADSP-BF52x Processor” on page 6-105 Overview and Features The processor uses DMA to transfer data between memory spaces or between a memory space and a peripheral. The processor can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of processor activity. The DMA controller can perform several types of data transfers: • Peripheral DMA transfers data between memory and on-chip peripherals. • Memory DMA (MDMA) transfers data between memory and memory. The processor has two MDMA modules, each consisting of independent memory read and memory write channels. • Handshaking memory DMA (HMDMA) transfers data between off-chip peripherals and memory. This enhancement of the MDMA channels enables external hardware to control the timing of individual data transfers or block transfers. is all products. Refer to The HMDMA featurethenot available forProcessor” on page 6-105 “Unique Behavior for ADSP-BF52x to determine whether it applies to this product. 6-2 ADSP-BF52x Blackfin Processor Hardware Reference All DMAs can transport data to and from on-chip and off-chip memories, including L1 and SDRAM. The L1 scratchpad memory cannot be accessed by DMA. and SRAM all products. to SDRAM Behavior forare not available onProcessor” on Refer 6-105 “Unique the ADSP-BF52x page to determine whether it applies to this product. DMA transfers on the processor can be descriptor-based or register-based. Register-based DMA allows the processor to directly program DMA control registers to initiate a DMA transfer. On completion, the control registers may be automatically updated with their original setup values for continuous transfer, if needed. Descriptor-based DMA transfers require a set of parameters stored within memory to initiate a DMA sequence. This sort of transfer allows the chaining together of multiple DMA sequences. In descriptor-based DMA operations, a DMA channel can be programmed to automatically set up and start another DMA transfer after the current sequence completes. Examples of DMA styles supported by flex descriptors include: • A single linear buffer that stops on completion (FLOW = stop mode) • A linear buffer with byte strides of any integer value, including negative values (DMAx_X_MODIFY register) • A circular, auto-refreshing buffer that interrupts on each full buffer • A similar buffer that interrupts on fractional buffers (for example, ½, ¼) (2-D DMA) • 1-D DMA, using a set of identical ping-pong buffers defined by a linked ring of 3-word descriptors, each containing a link pointer and a 32-bit address ADSP-BF52x Blackfin Processor Hardware Reference 6-3 • 1-D DMA, using a linked list of 5-word descriptors containing a link pointer, a 32-bit address, the buffer length, and a configuration • 2-D DMA, using an array of 1-word descriptors, specifying only the base DMA address within a common data page • 2-D DMA, using a linked list of 9-word descriptors specifying everything D MA Controller Overview A block diagram of the DMA controller can be found in the “Unique Behavior for the ADSP-BF52x Processor” on page 6-105. External Interfaces The DMA does not connect external memories and devices directly. Rather, data is passed through the EBIU port. Any kind of device that is supported by the EBIU can also be accessed by peripheral DMA or memory DMA operation. This is typically flash memory, SRAM, SDRAM, FIFOs, or memory-mapped peripheral devices. For products with handshaking MDMA (HMDMA), the operation is supported by two MDMA request input pins, DMAR0 and DMAR1. The DMAR0 pin controls transfer timing on the MDMA0 destination channel. The DMAR1 pin controls the destination channel of MDMA1. With these pins, external FIFO devices, ADC or DAC converters, or other streaming or block-processing devices can use the MDMA channels to exchange their data or data buffers with the Blackfin processor memory. 6-4 ADSP-BF52x Blackfin Processor Hardware Reference I nternal Interfaces Figure 2-1 on page 2-3 shows the dedicated DMA buses used by the DMA controller to interconnect L1 memory, the on-chip peripherals, and the EBIU port. The 16-bit DMA core bus (DCB) connects the DMA controller to a dedicated port of L1 memory. L1 memory has dedicated DMA ports featuring special DMA buffers to decouple DMA operation. See the Blackfin Processor Programming Reference for a description of the L1 memory architecture. The DCB bus operates at core clock (CCLK) frequency. It is the DMA controller’s responsibility to translate DCB transfers to the system clock (SCLK) domain. The 16-bit DMA access bus (DAB) connects the DMA controller to the on-chip peripherals. This bus operates at SCLK frequency. The 16-bit DMA external bus (DEB) connects the DMA controller to the EBIU port. This bus is used for all peripheral and memory DMA transfers to and from external memories and devices. It operates at SCLK frequency. Transferred data can be 8-, 16-, or 32-bits wide. The DMA controller, however, connects only to 16-bit buses. Memory DMA can pass data every SCLK cycle between L1 memory and the EBIU. Transfers from L1 memory to L1 memory require two cycles, as the DCB bus is used for both source and destination transfers. Similarly, transfers between two off-chip devices require EBIU and DEB resources twice. Peripheral DMA transfers can be performed every other SCLK cycle. For more details on DMA performance see “DMA Performance” on page 6-42. ADSP-BF52x Blackfin Processor Hardware Reference 6-5 P eripheral DMA The DMA controller features 12 channels that perform transfers between peripherals and on-chip or off-chip memories. The user has full control over the mapping of DMA channels and peripherals. The default DMA channel priority and mapping, shown in Table 6-7 on page 6-106, can be changed by altering the 4-bit PMAP field in the DMAx_PERIPHERAL_MAP registers for the peripheral DMA channels. The default configuration should suffice in most cases, but there are some cases where remapping the assignment can be helpful because of the DMA channel priorities. When competing for any of the system buses, DMA0 has higher priority than DMA1, and so on. DMA11 has the lowest priority of the peripheral DMA channels. should exist between DMA A 1:1 mapping responsible for ensuring thatchannels and peripherals. The user is multiple DMA channels are not mapped to the same peripheral and that multiple peripherals are not mapped to the same DMA port. If multiple channels are mapped to the same peripheral, only one channel is connected (the lowest priority channel). If a nonexistent peripheral (for example, 0xF in the PMAP field) is mapped to a channel, that channel is disabled—DMA requests are ignored, and no DMA grants are issued. The DMA requests are also not forwarded from the peripheral to the interrupt controller. All peripheral DMA channels work completely independently from each other. The transfer timing is controlled by the mapped peripheral. Every DMA channel features its own 4-deep FIFO that decouples DAB activity from DCB and DEB availability. DMA interrupt and descriptor fetch timing is aligned with the memory side (DCB/DEB side) of the FIFO. The user does, however, have an option to align interrupts with the peripheral side (DAB side) of the FIFO for transmit operations. Refer to the SYNC bit in the DMAx_CONFIG register for details. 6-6 ADSP-BF52x Blackfin Processor Hardware Reference M emory DMA This section describes the two pairs of MDMA channels, which provide memory-to-memory DMA transfers among the various memory spaces. These include L1 memory and external synchronous/asynchronous memories. Each MDMA channel contains a DMA FIFO, an 8-word by 16-bit FIFO block used to transfer data to and from either L1 or the DCB and DEB buses. Typically, it is used to transfer data between external memory and internal memory. It will also support DMA from the boot ROM on the DEB bus. The FIFO can be used to hold DMA data transferred between two L1 memory locations or between two external memory locations. Each page of MDMA channels consists of: • A source channel (for reading from memory) • A destination channel (for writing to memory) A memory-to-memory transfer always requires both the source and the destination channel to be enabled. Each source/destination channel forms a “stream,” and these two streams are hardwired for DMA priorities 12 through 15. • Priority 12: MDMA0 destination • Priority 13: MDMA0 source • Priority 14: MDMA1 destination • Priority 15: MDMA1 source ADSP-BF52x Blackfin Processor Hardware Reference 6-7 MDMA0 takes precedence over MDMA1, unless round-robin scheduling is used or priorities become urgent, as programmed by the DRQ bit field in the HMDMA_CONTROL register. It is illegal to program a source channel for memory write or a destination channel for memory read. The channels support 8-, 16-, and 32-bit memory DMA transfers, but both ends of the MDMA connect to 16-bit buses. Source and destination channels must be programmed to the same word size. In other words, the MDMA transfer does not perform packing or unpacking of data; each read results in one write. Both ends of the MDMA FIFO for a given stream are granted priority at the same time. Each pair shares an 8-word deep 16-bit FIFO. The source DMA engine fills the FIFO, while the destination DMA engine empties it. The FIFO depth allows the burst transfers of the external access bus (EAB) and DMA access bus (DAB) to overlap, significantly improving throughput on block transfers between internal and external memory. Two separate descriptor blocks are required to supply the operating parameters for each MDMA pair, one for the source channel and one for the destination channel. Because the source and destination DMA engines share a single FIFO buffer, the descriptor blocks must be configured to have the same data size. It is possible to have a different mix of descriptors on both ends as long as the total transfer count is the same. To start a MDMA transfer operation, the MMRs for the source and destination channels are written, each in a manner similar to peripheral DMA. The the before register for the source channel must be written DMAx_CONFIG register for the destination channel. DMAx_CONFIG 6-8 ADSP-BF52x Blackfin Processor Hardware Reference H andshaked Memory DMA (HMDMA) Mode This feature is not available for all products. Refer to the “Unique Behavior for the ADSP-BF52x Processor” on page 6-105 to determine whether it applies to this product. Handshaked operation applies only to memory DMA channels. Normally, memory DMA transfers are performed at maximum speed. Once started, data is transferred in a continuous manner until either the data count expires or the MDMA is stopped. In handshake mode, the MDMA does not transfer data automatically when enabled; it waits for an external trigger on the MDMA request input signals. The DMAR0 input is associated with MDMA0 and the DMAR1 input with MDMA1. Once a trigger event is detected, a programmable portion of data is transferred and then the MDMA stalls again and waits for the next trigger. Handshake operation is not only useful for controlling the timing of memory-to-memory transfers, it also enables the MDMA to operate with asynchronous FIFO-style devices connected to the EBIU port. The Blackfin processor acknowledges a DMA request by a proper number of read or write operations. It is up to the device connected to any of the AMSx strobes to deassert or pulse the request signal and to decrement the number of pending requests accordingly. Depending on HMDMA operating mode, an external DMA request may trigger individual data word transfers or block transfers. A block can consist of up to 65535 data words. For best throughput, DMA requests can be pipelined. The HMDMA controllers feature a request counter to decouple request timing from the data transfers. See “Handshaked Memory DMA Operation” on page 6-107 for a functional description. ADSP-BF52x Blackfin Processor Hardware Reference 6-9 M odes of Operation The following sections describe the DMA operation. Register-Based DMA Operation Register-based DMA is the traditional kind of DMA operation. Software configures the source or destination address and the length of the data to be transferred to memory-mapped registers and then starts DMA operation. For basic operation, the software performs these steps: • Write the source or destination address to the 32-bit DMAx_START_ADDR register. • Write the number of data words to be transferred to the 16-bit DMAx_X_COUNT register. • Write the address modifier to the 16-bit DMAx_X_MODIFY register. This is the two’s-complement value added to the address pointer after every transfer. This value must always be initialized as there is no default value. Typically, this register is set to 0x0004 for 32-bit DMA transfers, to 0x0002 for 16-bit transfers, and to 0x0001 for byte transfers. • Write the operation mode to the DMAx_CONFIG register. These bits in particular need to be changed as needed: • The DMAEN bit enables the DMA channel. • The WNR bit controls the DMA direction. DMAs that read from memory (peripheral transmit DMAs and source channel MDMAs) keep this bit cleared. Peripheral receive DMAs and destination channel MDMAs set this bit because they write to memory. 6-10 ADSP-BF52x Blackfin Processor Hardware Reference • The WDSIZE bit controls the data word width for the transfer. It can be 8-, 16-, or 32-bits wide. • The DI_EN bit enables an interrupt when the DMA operation has finished. • Set the FLOW field to 0x0 for stop mode or 0x1 for autobuffer mode. Once the DMAEN bit is set, the DMA channel starts its operation. While running, the DMAx_CURR_ADDR and the DMAx_CURR_X_COUNT registers can be monitored to determine the current progress of the DMA operation. However they should not be used to synchronize software and hardware. The DMAx_IRQ_STATUS register signals whether the DMA has finished (DMA_DONE bit), whether a DMA error has occurred (DMA_ERR bit), and whether the DMA is currently running (DMA_RUN bit). The DMA_DONE and the DMA_ERR bits also function as interrupt latch bits. They must be cleared by write-one-to-clear (W1C) operations by the interrupt service routine. Stop Mode In stop mode, the DMA operation is executed only once. When started, the DMA channel transfers the desired number of data words and stops itself when the transfer is complete. If the DMA channel is no longer used, software should clear the DMAEN enable bit to disable the otherwise paused channel. Stop mode is entered if the FLOW bit field in the DMA channel’s DMAx_CONFIG register is 0. The NDSIZE field must always be 0 in this mode. For receive (memory write) operation, the DMA_RUN bit functions almost the same as the inverted DMA_DONE bit. For transmit (memory read) operation, however, the two bits have different timing. Refer to the description of the SYNC bit in the DMAx_CONFIG register for details. ADSP-BF52x Blackfin Processor Hardware Reference 6-11 A utobuffer Mode In autobuffer mode, the DMA operates repeatedly in a circular manner. If all data words have been transferred, the address pointer DMAx_CURR_ADDR is reloaded automatically by the DMAx_START_ADDR value. An interrupt may also be generated. Autobuffer mode is entered if the FLOW field in the DMAx_CONFIG register is 1. The NDSIZE bit must be 0 in autobuffer mode. T wo-Dimensional DMA Operation Register-based and descriptor-based DMA can operate in one-dimensional mode or two-dimensional mode. In two-dimensional (2-D) mode, the DMAx_X_COUNT register is accompanied by the DMAx_Y_COUNT register, supporting arbitrary row and column sizes up to 64K × 64K elements, as well as arbitrary DMAx_X_MODIFY and DMAx_Y_MODIFY values up to ±32K bytes. Furthermore, DMAx_Y_MODIFY can be negative, allowing implementation of interleaved datastreams. The DMAx_X_COUNT and DMAx_Y_COUNT values specify the row and column sizes, where DMAx_X_COUNT must be 2 or greater. The start address and modify values are in bytes, and they must be aligned to a multiple of the DMA transfer word size (WDSIZE[1:0] in DMAx_CONFIG). Misalignment causes a DMA error. The DMAx_X_MODIFY value is the byte-address increment that is applied after each transfer that decrements the DMAx_CURR_X_COUNT register. The DMAx_X_MODIFY value is not applied when the inner loop count is ended by decrementing DMAx_CURR_X_COUNT from 1 to 0, except that it is applied on the final transfer when DMAx_CURR_Y_COUNT is 1 and DMAx_CURR_X_COUNT decrements from 1 to 0. The DMAx_Y_MODIFY value is the byte-address increment that is applied after each decrement of the DMAx_CURR_Y_COUNT register. However, the 6-12 ADSP-BF52x Blackfin Processor Hardware Reference value is not applied to the last item in the array on which the outer loop count (DMAx_CURR_Y_COUNT) also expires by decrementing from 1 to 0. DMAx_Y_MODIFY After the last transfer completes, DMAx_CURR_Y_COUNT = 1, DMAx_CURR_X_COUNT = 0, and DMAx_CURR_ADDR is equal to the last item’s address plus DMAx_X_MODIFY. is programmed refresh If the DMA channelthese registers willtobe loadedautomatically (autobuffer mode), then from DMAx_X_COUNT, DMAx_Y_COUNT, and DMAx_START_ADDR upon the first data transfer. The DI_SEL configuration bit enables DMA interrupt requests every time the inner loop rolls over. If DI_SEL is cleared, but DI_EN is still set, only one interrupt is generated after the outer loop completes. Examples of Two-Dimensional DMA Example 1: Retrieve a 16 × 8 block of bytes from a video frame buffer of size (N × M) pixels: DMAx_X_MODIFY = 1 DMAx_X_COUNT = 16 DMAx_Y_MODIFY = N–15 (offset from the end of one row to the start of another) DMAx_Y_COUNT = 8 This produces the following address offsets from the start address: 0,1,2,...15, N,N + 1, ... N + 15, 2N, 2N + 1,... 2N + 15, ... 7N, 7N + 1,... 7N + 15, ADSP-BF52x Blackfin Processor Hardware Reference 6-13 Example 2: Receive a video datastream of bytes, (R,G,B pixels) × (N × M image size): DMAx_X_MODIFY = (N * M) DMAx_X_COUNT = 3 DMAx_Y_MODIFY = 1 – 2(N * M) (negative) DMAx_Y_COUNT = (N * M) This produces the following address offsets from the start address: 0, (N * M), 2(N * M), 1, (N * M) + 1, 2(N * M) + 1, 2, (N * M) + 2, 2(N * M) + 2, ... (N * M) – 1, 2(N * M) – 1, 3(N * M) – 1, Descriptor-based DMA Operation In descriptor-based DMA operation, software does not set up DMA sequences by writing directly into DMA controller registers. Rather, software keeps DMA configurations, called descriptors, in memory. On demand, the DMA controller loads the descriptor from memory and overwrites the affected DMA registers by its own control. Descriptors can be fetched from L1 memory using the DCB bus or from external memory using the DEB bus. A descriptor describes what kind of operation should be performed next by the DMA channel. This includes the DMA configuration word as well as data source/destination address, transfer count, and address modify values. A DMA sequence controlled by one descriptor is called a work unit. Optionally, an interrupt can be requested at the end of any work unit by setting the DI_EN bit in the configuration word of the respective descriptor. 6-14 ADSP-BF52x Blackfin Processor Hardware Reference A DMA channel is started in descriptor-based mode by first writing the 32-bit address of the first descriptor into the DMAx_NEXT_DESC_PTR register (or the DMAx_CURR_DESC_PTR in case of descriptor array mode) and then performing a write to the DMAx_CONFIG register that sets the FLOW field to either 0x4, 0x6, or 0x7 and enables the DMAEN bit. This causes the DMA controller to immediately fetch the descriptor from the address pointed to by the DMAx_NEXT_DESC_PTR register. The fetch overwrites the DMAx_CONFIG register again. If the DMAEN bit is still set, the channel starts DMA processing. The DFETCH bit in the DMAx_IRQ_STATUS register tells whether a descriptor fetch is ongoing on the respective DMA channel. The DMAx_CURR_DESC_PTR points to the descriptor value that is to be fetched next. Descriptor List Mode Descriptor list mode is selected by setting the FLOW bit field in the DMA channel’s DMAx_CONFIG register to either 0x6 (small descriptor mode) or 0x7 (large descriptor mode). In either of these modes multiple descriptors form a chained list. Every descriptor contains a pointer to the next descriptor. When the descriptor is fetched, this pointer value is loaded into the DMAx_NEXT_DESC_PTR register of the DMA channel. In large descriptor mode this pointer is 32 bits wide. Therefore, the next descriptor may reside in any address space accessible through the DCB and DEB buses. In small descriptor mode this pointer is just 16 bits wide. For this reason, the next descriptor must reside in the same 64K byte address space as the first one because the upper 16 bits of the DMAx_NEXT_DESC_PTR register are not updated. Descriptor list modes are started by writing first to the register and then to the DMAx_CONFIG register. DMAx_NEXT_DESC_PTR ADSP-BF52x Blackfin Processor Hardware Reference 6-15 D escriptor Array Mode Descriptor array mode is selected by setting the FLOW bit field in the DMA channel’s DMAx_CONFIG register to 0x4. In this mode, the descriptors do not contain further descriptor pointers. The initial DMAx_CURR_DESC_PTR value is written by software. It points to an array of descriptors. The individual descriptors are assumed to reside next to each other and, therefore, their addresses are known. V ariable Descriptor Size In any descriptor-based mode the NDSIZE field in the configuration word specifies how many 16-bit words of the next descriptor need to be loaded on the next fetch. In descriptor-based operation, NDSIZE must be non-zero. The descriptor size can be any value from one entry (the lower 16 bits of DMAx_START_ADDR only) to nine entries (all the DMA parameters). Table 6-1 illustrates how a descriptor must be structured in memory. The values have the same order as the corresponding MMR addresses. If, for example, a descriptor is fetched in array mode with NDSIZE = 0x5, the DMA controller fetches the 32-bit start address, the DMA configuration word, and the XCNT and XMOD values. However, it does not load YCNT and YMOD. This might be the case if the DMA operates in one-dimensional mode or if the DMA is in two-dimensional mode, but the YCNT and YMOD values do not need to change. All the other registers not loaded from the descriptor retain their prior values, although the DMAx_CURR_ADDR, DMAx_CURR_X_COUNT, and DMAx_CURR_Y_COUNT registers are reloaded between the descriptor fetch and the start of DMA operation. Table 6-1 shows the offsets for descriptor elements in the three modes described above. Note the names in the table describe the descriptor elements in memory, not the actual MMRs into which they are eventually 6-16 ADSP-BF52x Blackfin Processor Hardware Reference loaded. For more information regarding descriptor element acronyms, see Table 6-4 on page 6-65. Table 6-1. Parameter Registers and Descriptor Offsets Descriptor Offset Descriptor Array Mode Small Descriptor List Mode Large Descriptor List Mode 0x0 SAL NDPL NDPL 0x2 SAH SAL NDPH 0x4 DMACFG SAH SAL 0x6 XCNT DMACFG SAH 0x8 XMOD XCNT DMACFG 0xA YCNT XMOD XCNT 0xC YMOD YCNT XMOD YMOD YCNT 0xE 0x10 YMOD Note that every descriptor fetch consumes bandwidth from either the DCB bus or the DEB bus and the external memory interface, so it is best to keep the size of descriptors as small as possible. M ixing Flow Modes The FLOW mode of a DMA is not a global setting. If the DMA configuration word is reloaded with a descriptor fetch, the FLOW and NDSIZE bit fields can also be altered. A small descriptor might be used to loop back to the first descriptor if a descriptor array is used in an endless manner. If the descriptor chain is not endless and the DMA is required to stop after a certain descriptor has been processed, the last descriptor is typically processed in stop mode. That is, its FLOW and NDSIZE fields are 0, but its DMAEN bit is still set. ADSP-BF52x Blackfin Processor Hardware Reference 6-17 F unctional Description The following sections provide a functional description of DMA. DMA Operation Flow Figure 6-1 and Figure 6-2 describe the DMA flow. DMA Startup This section discusses starting DMA “from scratch.” This is similar to starting it after it has been paused by the FLOW = 0 mode. Before initiating DMA for the first time on a given channel, all parameter registers must be initialized. Be sure to initialize the upper 16 bits of the DMAx_NEXT_DESC_PTR (or DMAx_CURR_DESC_PTR register in FLOW = 4 mode) and DMAx_START_ADDR registers, because they might not otherwise be accessed, depending upon the flow mode. Also note that the DMAx_X_MODIFY and DMAx_Y_MODIFY registers are not preset to a default value at reset. The user may wish to write other DMA registers that might be static during DMA activity (for example, DMAx_X_MODIFY, DMAx_Y_MODIFY). The contents of NDSIZE and FLOW in DMAx_CONFIG indicate which registers, if any, are fetched from descriptor elements in memory. After the descriptor 6-18 ADSP-BF52x Blackfin Processor Hardware Reference fetch, if any, is completed, DMA operation begins, initiated by writing DMAx_CONFIG with DMAEN = 1. USER WRITES SOME OR ALL DMA PARAMETER REGISTERS, AND THEN WRITES DMA_CONFIG Y BAD DMA_CONFIG? DMA ERROR N DMAEN = 0 TEST DMAEN DMAEN = 1 DI_EN = 0 OR (DI_EN = 1 AND DMA_DONE_IRQ = 1) C SET DMA_RUN IN IRQ_STATUS DMA STOPPED. CLEAR DMA_RUN IN IRQ_STATUS TEST FLOW FLOW = 0 OR 1 A FLOW = 4, 6, OR 7 SET DFETCH IN IRQ_STATUS D COPY FLOW, NDSIZE FROM DMA_CONFIG INTO TEMPORARY DESCRIPTOR FETCH COUNTERS TEST FLOW FLOW = 4 FLOW = 6 OR 7 COPY NEXT DESCRIPTOR POINTER TO CURRENT DESCRIPTOR POINTER B Figure 6-1. DMA Flow, From DMA Controller’s Point of View (1 of 2) ADSP-BF52x Blackfin Processor Hardware Reference 6-19 B NDSIZE = 0 OR NDSIZE > MAX_SIZE* TEST NDSIZE DMA ABORT OCCURS NDSIZE > 0 AND NDSIZE <= MAX_SIZE* READ NDSIZE ELEMENTS OF DESCRIPTOR INTO PARAMETER REGISTERS VIA CURRENT DESCRIPTOR POINTER A FLOW = 0 OR 1 CLEAR DFETCH IN IRQ_STATUS DMA TRANSFER BEGINS AND CONTINUES UNTIL COUNTS EXPIRE SYNC = 1 & MEMORY READ TEST SYNC, WNR SYNC = 0 OR MEMORY WRITE DI_EN = 1 TEST DI_EN TRANSFER DATA FROM FIFO TO PERIPHERAL UNTIL EMPTY SIGNAL AN INTERRUPT TO THE CORE DI_EN = 0 SET DMA_DONE IN IRQ_STATUS FLOW = 1 C TEST FLOW FLOW = 4, 6, 7 FLOW = 0 D SYNC = 0 & MEMORY READ TEST SYNC, WNR SYNC = 1 OR MEMORY WRITE TRANSFER DATA FROM FIFO TO PERIPHERAL UNTIL EMPTY MEMORY WRITE (DESTINATION) DMA STOPPED. CLEAR DMA_RUN IN IRQ_STATUS. *MAX SIZE DEPENDS ON FLOW IF FLOW = 4, MAX_SIZE = 7 IF FLOW = 6, MAX_SIZE = 8 IF FLOW = 7, MAX_SIZE = 9 Figure 6-2. DMA Flow, From DMA Controller’s Point of View (2 of 2) 6-20 ADSP-BF52x Blackfin Processor Hardware Reference When DMAx_CONFIG is written directly by software, the DMA controller recognizes this as the special startup condition that occurs when starting DMA for the first time on this channel or after the engine has been stopped (FLOW = 0). When the descriptor fetch is complete and DMAEN = 1, the DMACFG descriptor element that was read into DMAx_CONFIG assumes control. Before this point, the direct write to DMAx_CONFIG had control. In other words, the WDSIZE, DI_EN, DI_SEL, SYNC, and DMA2D fields will be taken from the DMACFG value in the descriptor read from memory, while these field values initially written to the DMAx_CONFIG register are ignored. As Figure 6-1 on page 6-19 and Figure 6-2 on page 6-20 show, at startup the FLOW and NDSIZE bits in DMAx_CONFIG determine the course of the DMA setup process. The FLOW value determines whether to load more current registers from descriptor elements in memory, while the NDSIZE bits detail how many descriptor elements to fetch before starting DMA. DMA registers not included in the descriptor are not modified from their prior values. If the FLOW value specifies small or large descriptor list modes, the DMAx_NEXT_DESC_PTR is copied into DMAx_CURR_DESC_PTR. Then, fetches of new descriptor elements from memory are performed, indexed by DMAx_CURR_DESC_PTR, which is incremented after each fetch. If NDPL and/or NDPH is part of the descriptor, then these values are loaded into DMAx_NEXT_DESC_PTR, but the fetch of the current descriptor continues using DMAx_CURR_DESC_PTR. After completion of the descriptor fetch, DMAx_CURR_DESC_PTR points to the next 16-bit word in memory past the end of the descriptor. If neither NDPH nor NDPL are part of the descriptor (that is, in descriptor array mode, FLOW = 4), then the transfer from NDPH/NDPL into DMAx_CURR_DESC_PTR does not occur. Instead, descriptor fetch indexing begins with the value in DMAx_CURR_DESC_PTR. ADSP-BF52x Blackfin Processor Hardware Reference 6-21 If DMACFG is not part of the descriptor, the previous DMAx_CONFIG settings (as written by MMR access at startup) control the work unit operation. If DMACFG is part of the descriptor, then the DMAx_CONFIG value programmed by the MMR access controls only the loading of the first descriptor from memory. The subsequent DMA work operation is controlled by the low byte of the descriptor’s DMACFG and by the parameter registers loaded from the descriptor. The bits DI_EN, DI_SEL, DMA2D, WDSIZE, and WNR in the value programmed by the MMR access are disregarded. The DMA_RUN and DFETCH status bits in the DMAx_IRQ_STATUS register indicate the state of the DMA channel. After a write to DMAx_CONFIG, the DMA_RUN and DFETCH bits can be automatically set to 1. No data interrupts are signaled as a result of loading the first descriptor from memory. After the above steps, DMA data transfer operation begins. The DMA channel immediately attempts to fill its FIFO, subject to channel priority—a memory write (RX) DMA channel begins accepting data from its peripheral, and a memory read (TX) DMA channel begins memory reads, provided the channel wins the grant for bus access. When the DMA channel performs its first data memory access, its address and count computations take their input operands from the start registers (DMAx_START_ADDR, DMAx_X_COUNT, DMAx_Y_COUNT), and write results back to the current registers (DMAx_CURR_ADDR, DMAx_CURR_X_COUNT, DMAx_CURR_Y_COUNT). Note also that the current registers are not valid until the first memory access is performed, which may be some time after the channel is started by the write to the DMA_CONFIG register. The current registers are loaded automatically from the appropriate descriptor elements, overwriting their previous contents, as follows. • • DMAx_X_COUNT is copied to DMAx_CURR_X_COUNT • 6-22 DMAx_START_ADDR DMAx_Y_COUNT is copied to DMAx_CURR_Y_COUNT is copied to DMAx_CURR_ADDR ADSP-BF52x Blackfin Processor Hardware Reference Then DMA data transfer operation begins, as shown in Figure 6-2 on page 6-20. DMA Refresh On completion of a work unit: • The DMA controller completes the transfer of all data between memory and the DMA unit. • If SYNC = 1 and WNR = 0 (memory read), the DMA controller selects a synchronized transition and transfers all data to the peripheral before continuing. • If enabled by DI_EN, the DMA controller signals an interrupt to the core and sets the DMA_DONE bit in the channel’s DMAx_IRQ_STATUS register. • If FLOW = 0 the DMA controller stops operation by clearing the DMA_RUN bit in DMAx_IRQ_STATUS register after all data in the channel’s DMA FIFO has been transferred to the peripheral. • During the fetch in FLOW modes 4, 6, and 7, the DMA controller sets the DFETCH bit in DMAx_IRQ_STATUS register to 1. At this point, the DMA operation depends on whether FLOW = 4, 6, or 7, as follows: If FLOW = 4 (descriptor array) the DMA controller loads a new descriptor from memory into the DMA registers using the contents of DMAx_CURR_DESC_PTR, and increments DMAx_CURR_DESC_PTR. The descriptor size comes from the NDSIZE field of the DMAx_CONFIG register prior to the beginning of the fetch. If FLOW = 6 (small descriptor list) the DMA controller copies the 32-bit DMAx_NEXT_DESC_PTR into DMAx_CURR_DESC_PTR. Next, the DMA controller fetches a descriptor from memory into the DMA ADSP-BF52x Blackfin Processor Hardware Reference 6-23 registers using the new contents of DMAx_CURR_DESC_PTR, and increments DMAx_CURR_DESC_PTR. The first descriptor element that is loaded is a new 16-bit value for the lower 16 bits of DMAx_NEXT_DESC_PTR, followed by the rest of the descriptor elements. The high 16 bits of DMAx_NEXT_DESC_PTR will retain their former value. This supports a shorter, more efficient descriptor than the large descriptor list model, which is suitable whenever the application can place the channel’s descriptors in the same 64K byte range of memory. If FLOW = 7 (large descriptor list) the DMA controller copies the 32-bit DMAx_NEXT_DESC_PTR into DMAx_CURR_DESC_PTR. Next, the DMA controller fetches a descriptor from memory into the DMA registers using the new contents of DMAx_CURR_DESC_PTR, and increments DMAx_CURR_DESC_PTR. The first descriptor element that is loaded is a new 32-bit value for the full DMAx_NEXT_DESC_PTR, followed by the rest of the descriptor elements. The high 16 bits of DMAx_NEXT_DESC_PTR may differ from their former value. This supports a fully flexible descriptor list which can be located anywhere in internal memory or external memory. • If it is necessary to link from a descriptor chain whose descriptors are in one 64K byte area to another chain whose descriptors are outside that area, only the descriptor containing the link to the new 64K byte range needs to use FLOW = 7. All descriptors that reference the same 64K byte area may use FLOW = 6. • If FLOW = 4, 6, or 7 (descriptor array, small descriptor list, or large descriptor list, respectively), the DMA controller clears the DFETCH bit in the DMAx_IRQ_STATUS register. • If FLOW = any value but 0 (Stop), the DMA controller begins the next work unit for that channel, which must contend with other channels for priority on the memory buses. On the first memory transfer of the new work unit, the DMA controller updates the cur- 6-24 ADSP-BF52x Blackfin Processor Hardware Reference rent registers from the start registers: loaded from DMAx_START_ADDR loaded from DMAx_X_COUNT DMAx_CURR_Y_COUNT loaded from DMAx_Y_COUNT The DFETCH bit in the DMAx_IRQ_STATUS register is then cleared, after which the DMA transfer begins again, as shown in Figure 6-2 on page 6-20. DMAx_CURR_ADDR DMAx_CURR_X_COUNT Work Unit Transitions Transitions from one work unit to the next are controlled by the SYNC bit in the DMAx_CONFIG register of the work units. In general, continuous transitions have lower latency at the cost of restrictions on changes of data format or addressed memory space in the two work units. These latency gains and data restrictions arise from the way the DMA FIFO pipeline is handled while the next descriptor is fetched. In continuous transitions (SYNC = 0), the DMA FIFO pipeline continues to transfer data to and from the peripheral or destination memory during the descriptor fetch and/or when the DMA channel is paused between descriptor chains. Synchronized transitions (SYNC = 1), on the other hand, provide better real-time synchronization of interrupts with peripheral state and greater flexibility in the data formats and memory spaces of the two work units, at the cost of higher latency in the transition. In synchronized transitions, the DMA FIFO pipeline is drained to the destination or flushed (RX data discarded) between work units. transitions Workbunit the MDMAfor MDMA streams are controlled by the it of source channel’s register. The SYNC DMAx_CONFIG bit of the MDMA destination channel is reserved and must be 0. In transmit (memory read) channels, the SYNC bit of the last descriptor prior to the transition controls the transition behavior. In contrast, in receive channels, the SYNC bit of the first descriptor of the next descriptor chain controls the transition. SYNC ADSP-BF52x Blackfin Processor Hardware Reference 6-25 DMA Transmit and MDMA Source In DMA transmit (memory read) and MDMA source channels, the SYNC bit controls the interrupt timing at the end of the work unit and the handling of the DMA FIFO between the current and next work units. If SYNC = 0, a continuous transition is selected. In a continuous transition, just after the last data item is read from memory, the following operations start in parallel: • The interrupt (if any) is signalled. • The DMA_DONE bit in the DMAx_IRQ_STATUS register is set. • The next descriptor begins to be fetched. • The final data items are delivered from the DMA FIFO to the destination memory or peripheral. This allows the DMA to provide data from the FIFO to the peripheral “continuously” during the descriptor fetch latency period. When SYNC = 0, the final interrupt (if enabled) occurs when the last data is read from memory. This interrupt is at the earliest time that the output memory buffer may safely be modified without affecting the previous data transmission. Up to four data items may still be in the DMA FIFO, however, and not yet at the peripheral, so the DMA interrupt should not be used as the sole means of synchronizing the shutdown or reconfiguration of the peripheral following a transmission. (continuous transition) If = 0 the next descriptor muston a transmit (memory read) descriptor, have the same data word size, SYNC read/write direction, and source memory (internal vs. external) as the current descriptor. = 0 selects continuous transition on a work unit in FLOW = 0 mode with interrupt enabled. The interrupt service routine may begin execution while the final data is still draining from the FIFO to the peripheral. This SYNC 6-26 ADSP-BF52x Blackfin Processor Hardware Reference is indicated by the DMA_RUN bit in the DMAx_IRQ_STATUS register; if it is 1, the FIFO is not empty yet. Do not start a new work unit with different word size or direction while DMA_RUN = 1. Further, if the channel is disabled (by writing DMAEN = 0), the data in the FIFO is lost. = 1 selects a synchronized transition in which the DMA FIFO is first drained to the destination memory or peripheral before any interrupt is signalled and before any subsequent descriptor or data is fetched. This incurs greater latency, but provides direct synchronization between the DMA interrupt and the state of the data at the peripheral. SYNC For example, if SYNC = 1 and DI_EN = 1 on the last descriptor in a work unit, the interrupt occurs when the final data has been transferred to the peripheral, allowing the service routine to properly switch to non-DMA transmit operation. When the interrupt service routine is invoked, the DMA_DONE bit is set and the DMA_RUN bit is cleared. A synchronized transition also allows greater flexibility in the format of the DMA descriptor chain. If SYNC = 1, the next descriptor may have any word size or read/write direction supported by the peripheral and may come from either memory space (internal or external). This can be useful in managing MDMA work unit queues, since it is no longer necessary to interrupt the queue between dissimilar work units. DMA Receive In DMA receive (memory write) channels, the SYNC bit controls the handling of the DMA FIFO between descriptor chains (not individual descriptors), when the DMA channel is paused. The DMA channel pauses after descriptors with FLOW = 0 mode, and may be restarted (for example, after an interrupt) by writing the channel’s DMAx_CONFIG register with DMAEN = 1. If the SYNC bit is 0 in the new work unit’s DMAx_CONFIG value, a continuous transition is selected. In this mode, any data items received into the DMA FIFO while the channel was paused are retained, and they are the first ADSP-BF52x Blackfin Processor Hardware Reference 6-27 items written to memory in the new work unit. This mode of operation provides lower latency at work unit transitions and ensures that no data items are dropped during a DMA pause, at the cost of certain restrictions on the DMA descriptors. the bit 0 first a IfDMA pause, isthe on the worddescriptor ofnewdescriptor chain after a DMA size of the chain must not SYNC change from the word size of the previous descriptor chain active before the pause, unless the DMA channel is reset between chains by writing the DMAEN bit to 0 and then to 1 again. If the SYNC bit is 1 in the new work unit’s DMAx_CONFIG value, a synchronized transition is selected. In this mode, only the data received from the peripheral by the DMA channel after the write to the DMAx_CONFIG register are delivered to memory. Any prior data items transferred from the peripheral to the DMA FIFO before this register write are discarded. This provides direct synchronization between the data stream received from the peripheral and the timing of the channel restart (when the DMAx_CONFIG register is written). For receive DMAs, the SYNC bit has no effect in transitions between work units in the same descriptor chain (that is, when the previous descriptor’s FLOW mode was not 0, so that DMA channel did not pause.) If a descriptor chain begins with a SYNC bit of 1, there is no restriction on DMA word size of the new chain in comparison to the previous chain. DMA size change one descriptor Thenext in wordDMAmust not(memorybetweenchannel within aand the any receive write) single descriptor chain, regardless of the SYNC bit setting. In other words, if a descriptor has WNR = 1 and FLOW = 4, 6, or 7, then the next descriptor must have the same word size. For any DMA receive (memory write) channel, there is no restriction on changes of memory space (internal vs. external) between descriptors or 6-28 ADSP-BF52x Blackfin Processor Hardware Reference descriptor chains. DMA transmit (memory read) channels may have such restrictions (see “DMA Transmit and MDMA Source” on page 6-26). Stopping DMA Transfers In FLOW = 0 mode, DMA stops automatically after the work unit is complete. If a list or array of descriptors is used to control DMA, and if every descriptor contains a DMACFG element, then the final DMACFG element should have a FLOW = 0 setting to gracefully stop the channel. In autobuffer (FLOW = 1) mode, or if a list or array of descriptors without DMACFG elements is used, then the DMA transfer process must be terminated by an MMR write to the DMAx_CONFIG register with a value whose DMAEN bit is 0. A write of 0 to the entire register will always terminate DMA gracefully (without DMA abort). channel to 0 If a any valuehas been stopped abruptly by writing that any mem= 0), the user must ensure (or with DMAx_CONFIG DMAEN ory read or write accesses in the pipelines have completed before enabling the channel again. If the channel is enabled again before an “orphan” access from a previous work unit completes, the state of the DMA interrupt and FIFO is unspecified. This can generally be handled by ensuring that the core allocates several consecutive idle cycles in its usage of the relevant memory space to allow up to three pending DMA accesses to issue, plus allowing enough memory access time for the accesses themselves to complete. DMA Errors (Aborts) The DMA controller flags conditions that cause the DMA process to end abnormally (abort). This functionality is provided as a tool for system development and debug to detect DMA-related programming errors. DMA errors (aborts) are detected by the DMA channel module in the ADSP-BF52x Blackfin Processor Hardware Reference 6-29 cases listed below. When a DMA error occurs, the channel is immediately stopped (DMA_RUN goes to 0) and any prefetched data is discarded. In addition, a DMA_ERROR interrupt is asserted. There is only one DMA_ERROR interrupt for the whole DMA controller, which is asserted whenever any of the channels has detected an error condition. The DMA_ERROR interrupt handler must: • Read each channel’s DMAx_IRQ_STATUS register to look for a channel with the DMA_ERR bit set (bit 1). • Clear the problem with that channel (for example, fix register values). • Clear the DMA_ERR bit (write DMAx_IRQ_STATUS with bit 1 set). The following error conditions are detected by the DMA hardware and result in a DMA abort interrupt. • The configuration register contains invalid values: • Incorrect WDSIZE value (WDSIZE = b#11) • Bit 15 not set to 0 • Incorrect FLOW value (FLOW = 2, 3, or 5) • NDSIZE value does not agree with FLOW. See Table 6-2 on page 6-32. • A disallowed register write occurred while the channel was running. Only the DMAx_CONFIG and DMAx_IRQ_STATUS registers can be written when DMA_RUN = 1. 6-30 ADSP-BF52x Blackfin Processor Hardware Reference • An address alignment error occurred during any memory access. For example, when DMAx_CONFIG register WDSIZE = 1 (16-bit) but the least significant bit (LSB) of the address is not equal to b#0, or when WDSIZE = 2 (32-bit) but the two LSBs of the address are not equal to b#00. • A memory space transition was attempted (internal-to-external or vice versa). For example, the value in the DMAx_CURR_ADDR register or DMAx_CURR_DESC_PTR register crossed a memory boundary. • A memory access error occurred. Either an access attempt was made to an internal address not populated or defined as cache, or an external access caused an error (signaled by the external memory interface). Some prohibited situations are not detected by the DMA hardware. No DMA abort is signaled for these situations: • DMAx_CONFIG direction bit (WNR) does not agree with the direction of the mapped peripheral. • DMAx_CONFIG • DMAx_CONFIG • DMAx_CONFIG direction bit does not agree with the direction of the MDMA channel. word size (WDSIZE) is not supported by the mapped peripheral. See Table 6-2 on page 6-32. word size in source and destination of the MDMA stream are not equal. ADSP-BF52x Blackfin Processor Hardware Reference 6-31 • Descriptor chain indicates data buffers that are not in the same internal/external memory space. • In 2-D DMA, X_COUNT = 1 Table 6-2. Legal NDSIZE Values FLOW NDSIZE Note 0 0 1 0 4 0 < NDSIZE 7 Descriptor array, no descriptor pointer fetched 6 0 < NDSIZE 8 Descriptor list, small descriptor pointer fetched 7 0 < NDSIZE 9 Descriptor list, large descriptor pointer fetched DMA Control Commands Advanced peripherals, such as an Ethernet MAC module, are capable of managing some of their own DMA operations, thus dramatically improving real-time performance and relieving control and interrupt demands on the Blackfin processor core. These peripherals may communicate to the DMA controller using DMA control commands, which are transmitted from the peripheral to the associated DMA channel over internal DMA request buses. Refer to “Unique Behavior for the ADSP-BF52x Processor” on page 6-105 to determine if DMA control commands are applicable to a particular product. The request buses consist of three wires per DMA-management-capable peripheral. The DMA control commands extend the set of operations available to the peripheral beyond the simple “request data” command used by peripherals in general. While these DMA control commands are not visible to or controllable by the user, their use by a peripheral has implications for the structure of the DMA transfers which that peripheral can support. It is important that 6-32 ADSP-BF52x Blackfin Processor Hardware Reference application software be written to comply with certain restrictions regarding work units and descriptor chains (described later in this section) so that the peripheral operates properly whenever it issues DMA control commands. MDMA channels do not service peripherals and therefore do not support DMA control commands. The DMA control commands are shown in Table 6-3. Table 6-3. DMA Control Commands Code Name Description 000 NOP No operation 001 Restart Restarts the current work unit from the beginning 010 Finish Finishes the current work unit and starts the next 011 - Reserved 100 Req Data Typical DMA data request 101 Req Data Urgent Urgent DMA data request 110 - Reserved 111 - Reserved Additional information for the control commands includes: • Restart The Restart command causes the current work unit to interrupt processing and start over, using the addresses and counts from DMAx_START_ADDR, DMAx_X_COUNT, and DMAx_Y_COUNT. No interrupt is signalled. If a channel programmed for transmit (memory read) receives a Restart command, the channel momentarily pauses while any pending memory reads initiated prior to the Restart command are completed. ADSP-BF52x Blackfin Processor Hardware Reference 6-33 During this period of time, the channel does not grant DMA requests. Once all pending reads have been flushed from the channel’s pipelines, the channel resets its counters and FIFO and starts prefetch reads from memory. DMA data requests from the peripheral are granted as soon as new prefetched data is available in the DMA FIFO. The peripheral can thus use the Restart command to re-attempt a failed transmission of a work unit. If a channel programmed for receive (memory write) receives a Restart command, the channel stops writing to memory, discards any data held in its DMA FIFO, and resets its counters and FIFO. As soon as this initialization is complete, the channel again grants DMA write requests from the peripheral. The peripheral can thus use the Restart command to abort transfer of received data into a work unit and re-use the memory buffer for a later data transfer. • Finish The Finish command causes the current work unit to terminate and move on to the next work unit. An interrupt is signalled as usual, if selected by the DI_EN bit. The peripheral can thus use the Finish command to partition the DMA stream into work units on its own, perhaps as a result of parsing the data currently passing though its supported communication channel, without direct real-time control by the processor. If a channel programmed for transmit (memory read) receives a command, the channel momentarily pauses while any pending memory reads initiated prior to the Finish command are completed. During this period of time, the channel does not grant DMA requests. Once all pending reads have been flushed from the channel’s pipelines, the channel signals an interrupt (if enabled), and begins fetching the next descriptor (if any). DMA data requests from the peripheral are granted as soon as new prefetched data is available in the DMA FIFO. Finish 6-34 ADSP-BF52x Blackfin Processor Hardware Reference If a channel programmed for receive (memory write) receives a Finish command, the channel stops granting new DMA requests while it drains its FIFO. Any DMA data received by the DMA controller prior to the Finish command is written to memory. When the FIFO reaches an empty state, the channel signals an interrupt (if enabled) and begins fetching the next descriptor (if any). Once the next descriptor has been fetched, the channel initializes its FIFO and then resumes granting DMA requests from the peripheral. • Request Data The Request Data command is identical to the DMA request operation of peripherals that are not DMA-management-capable. • Request Data Urgent The Request Data Urgent command behaves identically to the DMA Request command, except that the DMA channel performs its memory accesses with urgent priority while it is asserted. This includes both data and descriptor-fetch memory accesses. A DMA-management-capable peripheral might use this command if an internal FIFO is approaching a critical condition. Restrictions The proper operation of the 4-location DMA channel FIFO leads to certain restrictions in the sequence of DMA control commands. Transmit Restart or Finish No Restart or Finish command may be issued by a peripheral to a channel configured for memory read unless the peripheral has already performed at least one DMA transfer in the current work unit and the current work unit has more than four items remaining in DMAx_CURR_X_COUNT/ DMAx_CURR_Y_COUNT (thus not yet read from mem- ADSP-BF52x Blackfin Processor Hardware Reference 6-35 ory). Otherwise, the current work unit may already have completed memory operations and can no longer be restarted or finished properly. If the DMAx_CURR_X_COUNT/ DMAx_CURR_Y_COUNT value of the current work unit is sufficiently large that it is always at least five more than the maximum data count prior to any Restart or Finish command, the above restriction is satisfied. This implies that any work unit which might be managed by Restart or Finish commands must have DMAx_CURR_X_COUNT/ DMAx_CURR_Y_COUNT values representing at least five data items. Particularly if the DMAx_CURR_X_COUNT/ DMAx_CURR_Y_COUNT registers are programmed to 0 (representing 65,536 transfers, the maximum value) the channel will operate properly for 1-D work units up to 65,531 data items or 2-D work units up to 4,294,967,291 data items. Receive Restart or Finish No Restart or Finish command may be issued by a peripheral to a channel configured for memory write unless either the peripheral has already performed at least five DMA transfers in the current work unit or the previous work unit was terminated by a Finish command and the peripheral has performed at least one DMA transfer in the current work unit. If five data transfers have been performed, then at least one data item has been written to memory in the current work unit, which implies that the current work unit’s descriptor fetch completed before the data grant of the fifth item. Otherwise, if less than five data items have been transferred, it is possible that all of them are still in the DMA FIFO and the previous work unit is still in the process of completion and transition between work units. Similarly, if a Finish command ended the previous work unit and at least one subsequent DMA data transfer has occurred, then the fact that the DMA channel issued the grant guarantees that the previous work unit has already completed the process of draining its data to memory and transitioning to the new work unit. 6-36 ADSP-BF52x Blackfin Processor Hardware Reference If a peripheral terminates all work units with the Finish opcode (effectively assuming responsibility for all work unit boundaries for the DMA channel), then the peripheral need only ensure that it performs a single transfer in each work unit before any restart or finish. This requires, however, that the user programs the descriptors for all work units managed by the channel with DMAx_CURR_X_COUNT/ DMAx_CURR_Y_COUNT values representing more data items than the maximum work unit size that the peripheral will encounter. For example, DMAx_CURR_X_COUNT/ DMAx_CURR_Y_COUNT values of 0 allow the channel to operate properly on 1-D work units up to 65,535 data items and 2-D work units up to 4,294,967,295 data items. Handshaked Memory DMA Operation Handshaked memory DMA operation is not available for all products. Refer to the “Unique Behavior for the ADSP-BF52x Processor” on page 6-105 to determine whether this feature applies to this product. Each DMARx input has its own set of control and status registers. Handshake operation for MDMA0 is enabled by the HMDMAEN bit in the HMDMA0_CONTROL register. Similarly, the HMDMAEN bit in the HMDMA1_CONTROL register enables handshake mode for MDMA1. It is important to understand that the handshake hardware works completely independently from the descriptor and autobuffer capabilities of the MDMA, allowing most flexible combinations of logical data organization vs. data portioning as required by FIFO depths, for example. If, however, the connected device requires certain behavior of the address lines, these must be controlled by traditional DMA setup. unit controls only The HMDMAmemory DMA. Thethe destination (memory write) channel of the source channel (memory-read side) fills the 8-deep DMA buffers immediately after the receive side is enabled and issues eight read commands. ADSP-BF52x Blackfin Processor Hardware Reference 6-37 The HMDMAx_BCINIT registers control how many data transfers are performed upon every DMA request. If set to one, the peripheral can time every individual data transfer. If greater than one, the peripheral must have sufficient buffer size to provide or consume the number of words programmed. Once the transfer has been requested, no further handshake can hold off the DMA from transferring the entire block, except by stalling the EBIU accesses by the ARDY signal. Nevertheless, the peripheral may request a block transfer before the entire buffer is available by simply taking the minimum transfer time based on wait-state settings into consideration. block count defines how many are by TheMDMA engine. A single DMA data transferscauseperformedor the transfer can two read write operations on the EBIU port if the transfer word size is set to 32-bit in the MDMA_yy_CONFIG register (WDSIZE = b#10). Since the block count registers are 16 bits wide, blocks can group up to 65,535 transfers. Once a block transfer has been started, the HMDMAx_BCOUNT registers return the remaining number of transfers to complete the current block. When the complete block has been processed, the HMDMAx_BCOUNT register returns zero. Software can force a reload of the HMDMAx_BCOUNT from the HMDMAx_BCINIT register even during normal operation by setting the RBC bit in the HMDMAx_CONTROL register. Set RBC when the HMDMA module is already active, but only when the MDMA is not enabled. Pipelining DMA Requests The device mastering the DMA request lines is allowed to request additional transfers even before the former transfer has completed. As long as the device can provide or consume sufficient data it is permitted to pulse the DMARx inputs multiple times. The HMDMAx_ECOUNT registers are incremented every time a significant edge is detected on the respective DMARx input, and they are decremented when 6-38 ADSP-BF52x Blackfin Processor Hardware Reference the MDMA completes the block transfer. These read-only registers use a 16-bit twos-complement data representation: if they return zero, all requested block transfers have been performed. A positive value signals up to 32767 requests that haven’t been served yet and indicates that the MDMA is currently processing. Negative values indicate the number of DMA requests that will be ignored by the engine. This feature restrains initial pulses on the DMARx inputs at startup. The HMDMAx_ECINIT registers reload the HMDMAx_ECOUNT registers every time the handshake mode is enabled (when the HMDMAEN bit changes from 0 to 1). If the initial edge count value is 0, the handshake operation starts with a settled request budget. If positive, the engine starts immediately transferring the programmed number (up to 32767) of blocks once enabled, even without detecting any activity on the DMARx pins. If negative, the engine will disregard the programmed number (up to 32768) significant edges on the DMARx inputs before starting normal operation. Figure 6-3 illustrates how an asynchronous FIFO could be connected. In such a scenario the REP bit should be cleared to let the DMARx request pin listen to falling edges. The Blackfin processor does not evaluate the full flag such FIFOs usually provide because asynchronous polling of that signal would reduce the system throughput drastically. Moreover, the processor first fills the FIFO by initializing the HMDMAx_ECINIT register to 1024, which equals the depth of the FIFO. Once enabled, the MDMA automatically transmits 1024 data words. Afterward it continues to trans- ADSP-BF52x Blackfin Processor Hardware Reference 6-39 mit only if the FIFO is emptied by its read strobe again. Most likely, the HMDMAx_BCINIT register is programmed to 1 in this case. 1024K x 16 FIFO BLACKFIN D0 .. D15 I0 .. I15 O0 .. O15 FF AMSx AWE WR RD DMARx Figure 6-3. Transmit DMA Example Connection In the receive example shown in Figure 6-4, the Blackfin processor again does not use the FIFO’s internal control mechanism. Rather than testing the empty flag, the processor counts the number of data words available in the FIFO in its own HMDMAx_ECOUNT register. Theoretically, the MDMA could immediately process data as soon as it is written into the FIFO by the write strobe, but the fast MDMA engine would read out the FIFO quickly and stall soon if the FIFO was not promptly filled with new data. Streaming applications can balance the FIFO so that the producer is never held off by a full FIFO and the consumer is never held by an empty FIFO. This is accomplished by filling the FIFO halfway and then letting both consumer and producer run at the same speed. In this case the HMDMAx_ECINIT register can be written with a negative value, which corre- 6-40 ADSP-BF52x Blackfin Processor Hardware Reference sponds to half the FIFO depth. Then, the MDMA does not start consuming data as long as the FIFO is not half-filled. 1024K x 16 FIFO BLACKFIN D0 .. D15 I0 .. I15 O0 .. O15 FF AMSx AWE WR RD DMARx Figure 6-4. Receive DMA Example Connection On internal system buses, memory DMA channels have lower priority than other DMAs. In busy systems, the memory DMAs may tend to starve. As this is not acceptable when transferring data through high-speed FIFOs, the handshake mode provides a high-water functionality to increase the MDMA’s priority. With the UTE bit in the HMDMAx_CONTROL register set, the MDMA gets higher priority as soon as a (positive) value in the HMDMAx_ECOUNT register becomes higher than the threshold held by the HMDMAx_ECURGENT register. HMDMA Interrupts In addition to the normal MDMA interrupt channels, the handshake hardware provides two new interrupt sources for each DMARx input. The HMDMAx_CONTROL registers provide interrupt enable and status bits. The interrupt status bits require a write-1-to-clear operation to cancel the interrupt request. The block done interrupt signals that a complete MDMA block, as defined by the HMDMAx_BCINIT register, has been transferred (when the HMDMAx_BCOUNT register decrements to zero). While the BDIE bit enables this interrupt, the MBDI bit can gate it until the edge count also becomes zero, meaning that all requested MDMA transfers have been completed. ADSP-BF52x Blackfin Processor Hardware Reference 6-41 The overflow interrupt is generated when the HMDMA_ECOUNT register overflows. Since it can count up to 32767, which is much more than most peripheral devices can support, the Blackfin processor has another threshold register called HMDMA_ECOVERFLOW. It resets to 0xFFFF and should be written with any positive value by the user before enabling the function by the OIE bit. Then, the overflow interrupt is issued when the value of the HMDMA_ECOUNT register exceeds the threshold in the HMDMA_ECOVERFLOW register. DMA Performance The DMA system is designed to provide maximum throughput per channel and maximum utilization of the internal buses, while accommodating the inherent latencies of memory accesses. The Blackfin architecture features several mechanisms to customize system behavior for best performance. This includes DMA channel prioritization, traffic control, and priority treatment of bursted transfers. Nevertheless, the resulting performance of a DMA transfer often depends on application-level circumstances. For best performance consider the following system software architecture questions. • What is the required DMA bandwidth? • Which DMA transfers have real-time requirements and which do not? • How heavily is the DMA controller competing with the core for on-chip and off-chip resources? • How often do competing DMA channels require the bus systems to alter direction? • How often do competing DMA or core accesses cause the SDRAM to open different pages? • Is there a way to distribute DMA requests nicely over time? 6-42 ADSP-BF52x Blackfin Processor Hardware Reference A key feature of the DMA architecture is the separation of the activity on the DMA access bus (DAB) used by the peripherals from the activity on the buses between the DMA and memory. For DMA to/from on-chip memory the DMA core bus (DCB) is used, and the DMA external bus (DEB) is used for DMA transfers with off-chip memory. The “Chip Bus Hierarchy” chapter explains the bus architecture. Each peripheral DMA channel has its own data FIFO which lies between the DAB bus and the memory buses. These FIFOs automatically prefetch data from memory for transmission and buffer received data for later memory writes. This allows the peripheral to be granted a DMA transfer with very low latency compared to the total latency of a pipelined memory access, permitting the repeat rate (bandwidth) of each DMA channel to be as fast as possible. DMA Throughput Each peripheral DMA channel has a maximum transfer rate of one 16-bit word per two system clocks in either direction. Like the DAB and DEB buses, the DMA controller resides in the SCLK domain. The controller synchronizes accesses to and from the DCB bus, which runs at the CCLK rate. Each memory DMA channel has a maximum transfer rate of one 16-bit word per system clock (SCLK) cycle. When the traffic on all DMA channels is taken in the aggregate: • Transfers between the peripherals and the DMA unit have a maximum rate of one 16-bit transfer per system clock. • Transfers between the DMA unit and internal memory (L1) have a maximum rate of one 16-bit transfer per system clock. • Transfers between the DMA unit and external memory have a maximum rate of one 16-bit transfer per system clock. ADSP-BF52x Blackfin Processor Hardware Reference 6-43 Some considerations which limit the actual performance include: • Accesses to internal or external memory which conflict with core accesses to the same memory. This can cause delays, for example when both the core and the DMA access the same L1 bank, when SDRAM pages need to be opened/closed, or when cache lines are filled. • Direction changes from RX to TX on the DAB bus impose a one SCLK cycle delay. • Direction changes on the DCB bus (for example, write followed by read) to the same bank of internal memory can impose delays. • Direction changes (for example, read followed by write) on the DEB bus to external memory can each impose a several-cycle delay. • MMR accesses to DMA registers other than DMAx_CONFIG, DMAx_IRQ_STATUS, or DMAx_PERIPHERAL_MAP stall all DMA activity for one cycle per 16-bit word transferred. In contrast, MMR accesses to the control/status registers do not cause stalls or wait states. • Reads from DMA registers other than control/status registers use one PAB bus wait state, delaying the core for several core clocks. • Descriptor fetches consume one DMA memory cycle per 16-bit word read from memory, but do not delay transfers on the DAB bus. • Initialization of a DMA channel stalls DMA activity for one cycle. This occurs when DMAEN changes from 0 to 1 or when the SYNC bit is set in the DMAx_CONFIG register. Several of these factors may be minimized by proper design of the application software. It is often possible to structure the software to avoid internal and external memory conflicts by careful allocation of data buffers within banks and pages, and by planning for low cache activity during 6-44 ADSP-BF52x Blackfin Processor Hardware Reference critical DMA operations. Furthermore, unnecessary MMR accesses can be minimized, especially by using descriptors or autobuffering. Efficiency loss caused by excessive direction changes (thrashing) can be minimized by the processor’s traffic control features, described in the next section. The MDMA channels are clocked by SCLK. If the source and destination are in different memory spaces (one internal and one external), the internal and external memory transfers are typically simultaneous and continuous, maintaining 100% bus utilization of the internal and external memory interfaces. This performance is affected by core-to-system clock frequency ratios. At ratios below about 2.5:1, synchronization and pipeline latencies result in lower bus utilization in the system clock domain. For example DMA typically runs at 2/3 of the system clock rate when the core-to-system clock ratio is 2:1. At higher clock ratios, full bandwidth is maintained. If the source and destination are in the same memory space (both internal or both external), the MDMA stream typically prefetches a burst of source data into the FIFO, and then automatically turns around and delivers all available data from the FIFO to the destination buffer. The burst length is dependent on traffic, and is equal to three plus the memory latency at the DMA in SCLKs (which is typically seven for internal transfers and six for external transfers). Memory DMA Timing Details When the destination DMAx_CONFIG register is written, MDMA operation starts after a latency of three SCLK cycles. If either MDMA channel has been selected to use descriptors, the descriptors are fetched from memory. The destination channel descriptors are fetched first. Then the source MDMA channel begins fetching data from the source buffer, after a latency of four SCLK cycles after the last descriptor word is returned from memory. Due to memory pipelining, this is ADSP-BF52x Blackfin Processor Hardware Reference 6-45 typically eight SCLK cycles after the fetch of the last descriptor word. The resulting data is deposited in the MDMA channel’s 8-location FIFO. After a latency of two SCLK cycles, the destination MDMA channel begins writing data to the destination memory buffer. S tatic Channel Prioritization DMA channels are ordinarily granted service strictly according to their priority. The priority of a channel is simply its channel number, where lower priority numbers are granted first. Thus, peripherals with high data rates or low latency requirements should be assigned to lower numbered (higher priority) channels using the PMAP field in the DMAx_PERIPHERAL_MAP registers. The memory DMA streams are always lower static priority than the peripherals, but as they request service continuously, they ensure that any time slots unused by peripheral DMA are applied to MDMA transfers. Temporary DMA Urgency Typically, DMA transfers for a given peripheral occur at regular intervals. Generally, the shorter the interval, the higher the priority that should be assigned to the peripheral. If the average bandwidth of all the peripherals is not too large a fraction of the total, then all peripherals’ requests should be granted as required. Occasionally, instantaneous DMA traffic might exceed the available bandwidth, causing congestion. This may occur if L1 or external memory is temporarily stalled, perhaps for an SDRAM page swap or a cache line fill. Congestion might also occur if one or more DMA channels initiates a flurry of requests, perhaps for descriptor fetches or to fill a FIFO in the DMA or in the peripheral. If congestion persists, lower priority DMA peripherals may become starved for data. Even though the peripheral’s priority is low, if the necessary data transfer does not take place before the end of the peripheral’s regular interval, system failure may result. To minimize this possibility, 6-46 ADSP-BF52x Blackfin Processor Hardware Reference the DMA unit detects peripherals whose need for data has become urgent, and preferentially grants them service at the highest priority. A DMA channel’s request for memory service is defined as urgent if both: • The channel’s FIFO is not ready for a DAB bus transfer (that is, a transmit FIFO is empty or a receive FIFO is full), and • The peripheral is asserting its DMA request line. Descriptor fetches may be urgent if they are necessary to initiate or continue a DMA work unit chain for a starving peripheral. DMA requests from an MDMA channel become urgent when handshaked operation is enabled and the DMARx edge count exceeds the value stored in the HMDMAx_ECURGENT register. If handshaked operation is disabled, software can control urgency of requests directly by altering the DRQ bit field in the HMDMAx_CONTROL register. When one or more DMA channels express an urgent memory request, two events occur: • All non-urgent memory requests are decreased in priority by 32, guaranteeing that only an urgent request will be granted. The urgent requests compete with each other, if there is more than one, and directional preference among urgent requests is observed. • The resulting memory transfer is marked for expedited processing in the targeted memory system (L1 or external). All prior incomplete memory transfers ahead of it in that memory system are also marked for expedited processing. This may cause a series of external memory core accesses to be delayed for a few cycles so that a peripheral’s urgent request may be accommodated. The preferential handling of urgent DMA transfers is completely automatic. No user controls are required for this function to operate. ADSP-BF52x Blackfin Processor Hardware Reference 6-47 M emory DMA Priority and Scheduling All MDMA operations have lower precedence than any peripheral DMA operations. MDMA thus makes effective use of any memory bandwidth unused by peripheral DMA traffic. By default, when more than one MDMA stream is enabled and ready, only the highest priority MDMA stream is granted. If it is desirable for the MDMA streams to share the available bandwidth, the MDMA_ROUND_ROBIN_PERIOD may be programmed to select each stream in turn for a fixed number of transfers. If two MDMA streams are used (S0-D0 and S1-D1), the user may choose to allocate bandwidth either by fixed stream priority or by a round-robin scheme. This is selected by programming the MDMA_ROUND_ROBIN_PERIOD field in the DMA_TC_PER register (see “Static Channel Prioritization” on page 6-46). If this field is set to 0, then MDMA is scheduled by fixed priority. MDMA stream 0 takes precedence over MDMA stream 1 whenever stream 0 is ready to perform transfers. Since an MDMA stream is typically capable of transferring data on every available cycle, this could cause MDMA stream 1 traffic to be delayed for an indefinite time until any and all MDMA stream 0 operations are completed. This scheme could be appropriate in systems where low duration but latency-sensitive data buffers need to be moved immediately, interrupting long duration, low priority background transfers. If the MDMA_ROUND_ROBIN_PERIOD field is set to some nonzero value in the range 1 P 31, then a round-robin scheduling method is used. The two MDMA streams are granted bus access in alternation in bursts of up to P data transfers. This could be used in systems where two transfer processes need to coexist, each with a guaranteed fraction of the available bandwidth. For example, one stream might be programmed for internal-to-external moves while the other is programmed for exter- 6-48 ADSP-BF52x Blackfin Processor Hardware Reference nal-to-internal moves, and each would be allocated approximately equal data bandwidth. In round-robin operation, the MDMA stream selection at any time is either “free” or “locked.” Initially, the selection is free. On any free cycle available to MDMA (when no peripheral DMA accesses take precedence), if either or both MDMA streams request access, the higher precedence stream will be granted (stream 0 in case of conflict), and that stream’s selection is then “locked.” The MDMA_ROUND_ROBIN_COUNT counter field in the DMA_TC_CNT register is loaded with the period P from MDMA_ROUND_ROBIN_PERIOD, and MDMA transfers begin. The counter is decremented on every data transfer (as each data word is written to memory). After the transfer corresponding to a count of one, the MDMA stream selection is passed automatically to the other stream with zero overhead, and the MDMA_ROUND_ROBIN_COUNT counter is reloaded with the period value P from MDMA_ROUND_ROBIN_PERIOD. In this cycle, if the other MDMA stream is ready to perform a transfer, the stream selection is locked on the new MDMA stream. If the other MDMA stream is not ready to perform a transfer, then no transfer is performed, and the stream selection unlocks and becomes free again on the next cycle. If round-robin operation is used when only one MDMA stream is active, one idle cycle will occur for each P MDMA data cycles, slightly lowering the bandwidth by a factor of 1/(P+1). However if both MDMA streams are used, memory DMA can operate continuously with zero additional overhead for alternation of streams. (Other than overhead cycles normally associated with reversal of read/write direction to memory). By selection of various round-robin period values P, which limit how often the MDMA streams alternate, maximal transfer efficiency can be maintained. Traffic Control In the Blackfin DMA architecture, there are two completely separate but simultaneous prioritization processes—the DAB bus prioritization and the memory bus (DCB and DEB) prioritization. Peripherals that are request- ADSP-BF52x Blackfin Processor Hardware Reference 6-49 ing DMA via the DAB bus, and whose data FIFOs are ready to handle the transfer, compete with each other for DAB bus cycles. Similarly but separately, channels whose FIFOs need memory service (prefetch or post-write) compete together for access to the memory buses. MDMA streams compete for memory access as a unit, and source and destination may be granted together if their memory transfers do not conflict. In this way, internal-to-external or external-to-internal memory transfers may occur at the full system clock rate (SCLK). Examples of memory conflict include simultaneous access to the same memory space and simultaneous attempts to fetch descriptors. Special processing may occur if a peripheral is requesting DMA but its FIFO is not ready (for example, an empty transmit FIFO or full receive FIFO). For more information, see “Temporary DMA Urgency” on page 6-46. Traffic control is an important consideration in optimizing use of DMA resources. Traffic control is a way to influence how often the transfer direction on the data buses may change, by automatically grouping same direction transfers together. The DMA block provides a traffic control mechanism controlled by the DMA_TC_PER and DMA_TC_CNT registers. This mechanism performs the optimization without real-time processor intervention and without the need to program transfer bursts into the DMA work unit streams. Traffic can be independently controlled for each of the three buses (DAB, DCB, and DEB) with simple counters. In addition, alternation of transfers among MDMA streams can be controlled with the MDMA_ROUND_ROBIN_COUNT field of the DMA_TC_CNT register. See “Memory DMA Priority and Scheduling” on page 6-48. Using the traffic control features, the DMA system preferentially grants data transfers on the DAB or memory buses which are going in the same read/write direction as the previous transfer, until either the traffic control counter times out or traffic stops or changes direction on its own. When the traffic counter reaches zero, the preference is changed to the opposite flow direction. These directional preferences work as if the priority of the opposite direction channels were decreased by 16. 6-50 ADSP-BF52x Blackfin Processor Hardware Reference For example, if channels 3 and 5 were requesting DAB access, but lower priority channel 5 is going with traffic and higher priority channel 3 is going against traffic, then channel 3’s effective priority becomes 19, and channel 5 would be granted instead. If, on the next cycle, only channels 3 and 6 were requesting DAB transfers, and these transfer requests were both against traffic, then their effective priorities would become 19 and 22, respectively. One of the channels (channel 3) is granted, even though its direction is opposite to the current flow. No bus cycles are wasted, other than any necessary delay required for the bus turnaround. This type of traffic control represents a trade-off of latency to improve utilization (efficiency). Higher traffic timeouts might increase the length of time each request waits for its grant, but it often dramatically improves the maximum attainable bandwidth in congested systems, often to above 90%. To disable preferential DMA prioritization, program the DMA_TC_PER register to 0x0000. Programming Model Several synchronization and control methods are available for use in development of software tasks which manage peripheral DMA and memory DMA (see also “Memory DMA” on page 6-7). Such software needs to be able to accept requests for new DMA transfers from other software tasks, integrate these transfers into existing transfer queues, and reliably notify other tasks when the transfers are complete. In the processor, it is possible for each peripheral DMA and memory DMA stream to be managed by a separate task or to be managed together with any other stream. Each DMA channel has independent, orthogonal control registers, resources, and interrupts, so that the selection of the control scheme for one channel does not affect the choice of control scheme on other channels. For example, one peripheral can use a linked-descriptor-list, interrupt-driven scheme while another peripheral ADSP-BF52x Blackfin Processor Hardware Reference 6-51 can simultaneously use a demand-driven, buffer-at-a-time scheme synchronized by polling of the DMAx_IRQ_STATUS register. S ynchronization of Software and DMA A critical element of software DMA management is synchronization of DMA buffer completion with the software. This can best be done using interrupts, polling of DMAx_IRQ_STATUS, or a combination of both. Polling for address or count can only provide synchronization within loose tolerances comparable to pipeline lengths. Interrupt-based synchronization methods must avoid interrupt overrun, or the failure to invoke a DMA channel’s interrupt handler for every interrupt event due to excessive latency in processing of interrupts. Generally, the system design must either ensure that only one interrupt per channel is scheduled (for example, at the end of a descriptor list), or that interrupts are spaced sufficiently far apart in time that system processing budgets can guarantee every interrupt is serviced. Note, since every interrupt channel has its own distinct interrupt, interaction among the interrupts of different peripherals is much simpler to manage. Due to DMA FIFOs and DMA/memory pipelining, polling of the DMAx_CURR_ADDR, DMAx_CURR_DESC_PTR, or DMAx_CURR_X_COUNT/ DMAx_CURR_Y_COUNT registers is not recommended for precisely synchronizing DMA with data processing. The current address, pointer, and count registers change several cycles in advance of the completion of the corresponding memory operation, as measured by the time at which the results of the operation would first be visible to the core by memory read or write instructions. For example, in a DMA memory write operation to external memory, assume a DMA write by channel A is initiated that causes the SDRAM to perform a page open operation which takes many system clock cycles. The DMA engine may then move on to another DMA operation by channel B which does not in itself incur latency, but will be stalled behind the slow operation of channel A. Software monitoring of channel B, based on examination of the DMAx_CURR_ADDR register contents, 6-52 ADSP-BF52x Blackfin Processor Hardware Reference would not safely conclude whether the memory location pointed to by channel B’s DMAx_CURR_ADDR register has or has not been written. If allowances are made for the lengths of the DMA/memory pipeline, polling of the current address, pointer, and count registers can permit loose synchronization of DMA with software. The depth of the DMA FIFO is four locations (either four 8- or 16-bit data elements, or two 32-bit data elements) for a peripheral DMA channel, and eight locations (four 32-bit data elements) for an MDMA FIFO. The DMA will not advance current address/pointer/count registers if these FIFOs are filled with incomplete work (including reads that have been started but not yet finished). Additionally, the length of the combined DMA and L1 pipelines to internal memory is approximately six 8- or 16-bit data elements. The length of the DMA and external bus interface unit (EBIU) pipelines is approximately three data elements, when measured from the point where a DMA register update is visible to an MMR read to the point where DMA and core accesses to memory become strictly ordered. If the DMA FIFO length and the DMA/memory pipeline length are added, an estimate can be made of the maximum number of incomplete memory operations in progress at one time. This value is a maximum because the DMA/memory pipeline may include traffic from other DMA channels. For example, assume a peripheral DMA channel is transferring a work unit of 100 data elements into internal memory and its DMAx_CURR_X_COUNT register reads a value of 60 remaining elements, so that processing of the first 40 elements has at least been started. Since the total pipeline length is no greater than the sum of four (for the peripheral DMA FIFO) plus six (for the DMA/memory pipeline) or ten data elements, it is safe to conclude that the DMA transfer of the first 30 (40-10) data elements is complete. For precise synchronization, software should either wait for an interrupt or consult the channel’s DMAx_IRQ_STATUS register to confirm completion of DMA, rather than polling current address/pointer/count registers. When the DMA system issues an interrupt or changes a DMAx_IRQ_STATUS ADSP-BF52x Blackfin Processor Hardware Reference 6-53 bit, it guarantees that the last memory operation of the work unit has been completed and will definitely be visible to processor code. For memory read DMA, the final memory read data will have been safely received in the DMA’s FIFO. For memory write DMA, the DMA unit will have received an acknowledgement from L1 memory, or the EBIU, that the data has been written. The following examples show methods of synchronizing software with several different styles of DMA. Single-Buffer DMA Transfers Synchronization is simple if a peripheral’s DMA activity consists of isolated transfers of single buffers. DMA activity is initiated by software writes to the channel’s control registers. The user may choose to use a single descriptor in memory, in which case the software only needs to write the DMAx_CONFIG and the DMAx_NEXT_DESC_PTR registers. Alternatively, the user may choose to write all the MMR registers directly from software, ending with the write to the DMAx_CONFIG register. The simplest way to signal completion of DMA is by an interrupt. This is selected by the DI_EN bit in the DMAx_CONFIG register, and by the necessary setup of the system interrupt controller. If no interrupt is desired, the software can poll for completion by reading the DMAx_IRQ_STATUS register and testing the DMA_RUN bit. If this bit is zero, the buffer transfer has completed. Continuous Transfers Using Autobuffering If a peripheral’s DMA data consists of a steady, periodic stream of signal data, DMA autobuffering (FLOW = 1) may be an effective option. Here, DMA is transferred from or to a memory buffer with a circular addressing 6-54 ADSP-BF52x Blackfin Processor Hardware Reference scheme, using either one- or two-dimensional indexing with zero processor and DMA overhead for looping. Synchronization options include: • 1-D interrupt-driven—software is interrupted at the conclusion of each buffer. The critical design consideration is that the software must deal with the first items in the buffer before the next DMA transfer, which might overwrite or re-read the first buffer location before it is processed by software. This scheme may be workable if the system design guarantees that the data repeat period is longer than the interrupt latency under all circumstances. • 2-D interrupt-driven (double buffering)—the DMA buffer is partitioned into two or more sub-buffers, and interrupts are selected (set DI_SEL = 1 in DMAx_CONFIG) to be signaled at the completion of each DMA inner loop. In this way, a traditional double buffer or “ping-pong” scheme can be implemented. For example, two 512-word sub-buffers inside a 1K-word buffer could be used to receive 16-bit peripheral data with these settings: • DMAx_START_ADDR • DMAx_CONFIG • DMAx_X_COUNT • DMAx_X_MODIFY • DMAx_Y_COUNT • DMAx_Y_MODIFY = buffer base address = 0x10D7 (FLOW = 1, DI_EN = 1, DI_SEL = 1, DMA2D = 1, WDSIZE = b#01, WNR = 1, DMAEN = 1) = 512 = 2 for 16-bit data = 2 for two sub-buffers = 2 same as DMAx_X_MODIFY for contiguous sub-buffers • 2-D polled—if interrupt overhead is unacceptable but the loose synchronization of address/count register polling is acceptable, a 2-D multibuffer synchronization scheme may be used. For exam- ADSP-BF52x Blackfin Processor Hardware Reference 6-55 ple, assume receive data needs to be processed in packets of sixteen 32-bit elements. A four-part 2-D DMA buffer can be allocated where each of the four sub-buffers can hold one packet with these settings: • DMAx_START_ADDR • DMAx_CONFIG WDSIZE = buffer base address = 0x101B (FLOW = 1, DI_EN = 0, DMA2D = 1, = b#10, WNR = 1, DMAEN = 1) • DMAx_X_COUNT = 16 • DMAx_X_MODIFY • DMAx_Y_COUNT • DMAx_Y_MODIFY = 4 for 32-bit data = 4 for four sub-buffers = 4 same as DMAx_X_MODIFY for contiguous sub-buffers • The synchronization core might read DMAx_Y_COUNT to determine which sub-buffer is currently being transferred, and then allow one full sub-buffer to account for pipelining. For example, if a read of DMAx_Y_COUNT shows a value of 3, then the software should assume that sub-buffer 3 is being transferred, but some portion of sub-buffer 2 may not yet be received. The software could, however, safely proceed with processing sub-buffers 1 or 0. • 1-D unsynchronized FIFO—if a system’s design guarantees that the processing of a peripheral’s data and the DMA rate of the data will remain correlated in the steady state, but that short-term latency variations must be tolerated, it may be appropriate to build a simple FIFO. Here, the DMA channel may be programmed using 1-D autobuffer mode addressing without any interrupts or polling. 6-56 ADSP-BF52x Blackfin Processor Hardware Reference D escriptor Structures DMA descriptors may be used to transfer data to or from memory data structures that are not simple 1-D or 2-D arrays. For example, if a packet of data is to be transmitted from several different locations in memory (a header from one location, a payload from a list of several blocks of memory managed by a memory pool allocator, and a small trailer containing a checksum), a separate DMA descriptor can be prepared for each memory area, and the descriptors can be grouped in either an array or list by selecting the appropriate FLOW setting in DMAx_CONFIG. The software can synchronize with the progress of the structure’s transfer by selecting interrupt notification for one or more of the descriptors. For example, the software might select interrupt notification for the header’s descriptor and for the trailer’s descriptor, but not for the payload blocks’ descriptors. It is important to remember the meaning of the various fields in the DMAx_CONFIG descriptor elements when building a list or array of DMA descriptors. In particular: • The lower byte of DMAx_CONFIG specifies the DMA transfer to be performed by the current descriptor (for example 2-D interrupt-enable mode) • The upper byte of DMAx_CONFIG specifies the format of the next descriptor in the chain. The NDSIZE and FLOW fields in a given descriptor do not correspond to the format of the descriptor itself; they specify the link to the next descriptor, if any. On the other hand, when the DMA unit is being restarted, both bytes of the DMAx_CONFIG value written to the DMA channel’s DMAx_CONFIG register should correspond to the current descriptor. At a minimum, the FLOW, NDSIZE, WNR, and DMAEN fields must all agree with the current descriptor. The WDSIZE, DI_EN, DI_SEL, SYNC, and DMA2D fields will be taken from the DMAx_CONFIG value in the descriptor read from memory. The field values initially written to the register are ignored. See “Initializing Descriptors in ADSP-BF52x Blackfin Processor Hardware Reference 6-57 Memory” on page 6-97 in the “Programming Examples” section for information on how descriptors can be set up. Descriptor Queue Management A system designer might want to write a DMA manager facility which accepts DMA requests from other software. The DMA manager software does not know in advance when new work requests will be received or what these requests might contain. The software could manage these transfers using a circular linked list of DMA descriptors, where each descriptor’s NDPH and NDPL members point to the next descriptor, and the last descriptor points back to the first. The code that writes into this descriptor list could use the processor’s circular addressing modes (Ix, Lx, Mx, and Bx registers), so that it does not need to use comparison and conditional instructions to manage the circular structure. In this case, the NDPH and NDPL members of each descriptor could even be written once at startup and skipped over as each descriptor’s new contents are written. The recommended method for synchronization of a descriptor queue is through the use of an interrupt. The descriptor queue is structured so that at least the final valid descriptor is always programmed to generate an interrupt. There are two general methods for managing a descriptor queue using interrupts: • Interrupt on every descriptor • Interrupt minimally - only on the last descriptor Descriptor Queue Using Interrupts on Every Descriptor In this system, the DMA manager software synchronizes with the DMA unit by enabling an interrupt on every descriptor. This method should 6-58 ADSP-BF52x Blackfin Processor Hardware Reference only be used if system design can guarantee that each interrupt event will be serviced separately (no interrupt overrun). To maintain synchronization of the descriptor queue, the non-interrupt software maintains a count of descriptors added to the queue, while the interrupt handler maintains a count of completed descriptors removed from the queue. The counts are equal only when the DMA channel is paused after having processed all the descriptors. When each new work request is received, the DMA manager software initializes a new descriptor, taking care to write a DMAx_CONFIG value with a FLOW value of 0. Next, the software compares the descriptor counts to determine if the DMA channel is running or not. If the DMA channel is paused (counts are equal), the software increments its count and then starts the DMA unit by writing the new descriptor’s DMAx_CONFIG value to the DMA channel’s DMAx_CONFIG register. If the counts are unequal, the software instead modifies the next-to-last descriptor’s DMAx_CONFIG value so that its upper half (FLOW and NDSIZE) now describes the newly queued descriptor. This operation does not disrupt the DMA channel, provided the rest of the descriptor data structure is initialized in advance. It is necessary, however, to synchronize the software to the DMA to correctly determine whether the new or the old DMAx_CONFIG value was read by the DMA channel. This synchronization operation should be performed in the interrupt handler. First, upon interrupt, the handler should read the channel’s DMAx_IRQ_STATUS register. If the DMA_RUN status bit is set, then the channel has moved on to processing another descriptor, and the interrupt handler may increment its count and exit. If the DMA_RUN status bit is not set, however, then the channel has paused, either because there are no more descriptors to process, or because the last descriptor was queued too late (the modification of the next-to-last descriptor’s DMAx_CONFIG element occurred after that element was read into the DMA unit). In this case, the interrupt handler should write the DMAx_CONFIG value appropriate for the ADSP-BF52x Blackfin Processor Hardware Reference 6-59 last descriptor to the DMA channel’s DMAx_CONFIG register, increment the completed descriptor count, and exit. Again, this system can fail if the system’s interrupt latencies are large enough to cause any of the channel’s DMA interrupts to be dropped. An interrupt handler capable of safely synchronizing multiple descriptors’ interrupts would need to be complex, performing several MMR accesses to ensure robust operation. In such a system environment, a minimal interrupt synchronization method is preferred. Descriptor Queue Using Minimal Interrupts In this system, only one DMA interrupt event is possible in the queue at any time. The DMA interrupt handler for this system can also be extremely short. Here, the descriptor queue is organized into an “active” and a “waiting” portion, where interrupts are enabled only on the last descriptor in each portion. When each new DMA request is processed, the software’s non-interrupt code fills in a new descriptor’s contents and adds it to the waiting portion of the queue. The descriptor’s DMAx_CONFIG word should have a FLOW value of zero. If more than one request is received before the DMA queue completion interrupt occurs, the non-interrupt code should queue later descriptors, forming a waiting portion of the queue that is disconnected from the active portion of the queue being processed by the DMA unit. In other words, all but the last active descriptors contain FLOW values 4 and have no interrupt enable set, while the last active descriptor contains a FLOW of 0 and an interrupt enable bit DI_EN set to 1. Also, all but the last waiting descriptors contain FLOW values 4 and no interrupt enables set, while the last waiting descriptor contains a FLOW of 0 and an interrupt enable bit set. This ensures that the DMA unit can automatically process the whole active queue and then issue one interrupt. Also, this arrangement makes it easy to start the waiting queue within the interrupt handler with a single DMAx_CONFIG register write. 6-60 ADSP-BF52x Blackfin Processor Hardware Reference After queuing a new waiting descriptor, the non-interrupt software should leave a message for its interrupt handler in a memory mailbox location containing the desired DMAx_CONFIG value to use to start the first waiting descriptor in the waiting queue (or 0 to indicate no descriptors are waiting). Once processing by the DMA unit has started, it is critical that the software not directly modify the contents of the active descriptor queue unless careful synchronization measures are taken. In the most straightforward implementation of a descriptor queue, the DMA manager software would never modify descriptors on the active queue; instead, the DMA manager waits until the DMA queue completion interrupt indicates the processing of the entire active queue is complete. When a DMA queue completion interrupt is received, the interrupt handler reads the mailbox from the non-interrupt software and writes the value in it to the DMA channel’s DMAx_CONFIG register. This single register write restarts the queue, effectively transforming the waiting queue to an active queue. The interrupt handler should then pass a message back to the non-interrupt software indicating the location of the last descriptor accepted into the active queue. If, on the other hand, the interrupt handler reads its mailbox and finds a DMAx_CONFIG value of zero, indicating there is no more work to perform, then it should pass an appropriate message (for example zero) back to the non-interrupt software indicating that the queue has stopped. This simple handler should be able to be coded in a very small number of instructions. The non-interrupt software which accepts new DMA work requests needs to synchronize the activation of new work with the interrupt handler. If the queue has stopped (the mailbox from the interrupt software is zero), the non-interrupt software is responsible for starting the queue (writing the first descriptor’s DMAx_CONFIG value to the channel’s DMAx_CONFIG register). If the queue is not stopped, the non-interrupt software must not write to the DMAx_CONFIG register (which would cause a DMA error). ADSP-BF52x Blackfin Processor Hardware Reference 6-61 Instead the descriptor should queue to the waiting queue, and update its mailbox directed to the interrupt handler. Software Triggered Descriptor Fetches If a DMA has been stopped in FLOW = 0 mode, the DMA_RUN bit in the DMAx_IRQ_STATUS register remains set until the content of the internal DMA FIFOs has been completely processed. Once the DMA_RUN bit clears, it is safe to restart the DMA by simply writing again to the DMAx_CONFIG register. The DMA sequence is repeated with the previous settings. Similarly, a descriptor-based DMA sequence that has been stopped temporarily with a FLOW = 0 descriptor can be continued with a new write to the configuration register. When the DMA controller detects the FLOW = 0 condition by loading the DMACFG field from memory, it has already updated the next descriptor pointer, regardless of whether operating in descriptor array mode or descriptor list mode. The next descriptor pointer remains valid if the DMA halts and is restarted. As soon as the DMA_RUN bit clears, software can restart the DMA and force the DMA controller to fetch the next descriptor. To accomplish this, the software writes a value with the DMAEN bit set and with proper values in the FLOW and NDSIZE fields into the configuration register. The next descriptor is fetched if FLOW equals 0x4, 0x6, or 0x7. In this mode of operation, the NDSIZE field should at least span up to the DMACFG field to overwrite the configuration register immediately. One possible procedure is: 1. Write to DMAx_NEXT_DESC_PTR 2. Write to DMAx_CONFIG with = 0x8 • • 6-62 FLOW NDSIZE 0xA ADSP-BF52x Blackfin Processor Hardware Reference • DI_EN =0 • DMAEN =1 3. Automatically fetched DMACFG has • FLOW = 0x0 • NDSIZE • SYNC • DI_EN =1 • DMAEN =1 = 0x0 = 1 (for transmitting DMAs only) 4. In the interrupt routine, repeat step 2. The DMAx_NEXT_DESC_PTR is updated by the descriptor fetch. To avoid polling of bit, it in case memory read DMAsthe transmitset the bsource). of (DMA or MDMA DMA_RUN SYNC If all DMACFG fields in a descriptor chain have the FLOW and NDSIZE fields set to zero, the individual DMA sequences do not start until triggered by software. This is useful when the DMAs need to be synchronized with other events in the system, and it is typically performed by interrupt service routines. A single MMR write is required to trigger the next DMA sequence. Especially when applied to MDMA channels, such scenarios play an important role. Usually, the timing of MDMAs cannot be controlled (See “Handshaked Memory DMA Operation” on page 6-107). By halting descriptor chains or rings this way, the whole DMA transaction can be broken into pieces that are individually triggered by software. may Source and destination channels of a MDMAmust differ in descriptor structure. However, the total work count match when the DMA stops. Whenever a MDMA is stopped, destination and ADSP-BF52x Blackfin Processor Hardware Reference 6-63 source channels should both provide the same FLOW = 0 mode after exactly the same number of words. Accordingly, both channels need to be started afterward. Software-triggered descriptor fetches are illustrated in Listing 6-7 on page 6-100. MDMA channels can be paused by software at any time by writing a 0 to the DRQ bit field in the HMDMAx_CONTROL register. This simply disables the self-generated DMA requests, whether or not the HMDMA is enabled. DMA Registers DMA registers fall into three categories: • DMA channel registers • Handshaked MDMA registers • Global DMA traffic control registers DMA Channel Registers A processor features up to twelve peripheral DMA channels and two channel pairs for memory DMA. All channels have an identical set of registers as summarized in Table 6-4. Table 6-4 lists the generic names of the DMA registers. For each register, the table also shows the MMR offset, a brief description of the register, 6-64 ADSP-BF52x Blackfin Processor Hardware Reference the register category, and where applicable, the corresponding name for the data element in a DMA descriptor. Table 6-4. Generic Names of the DMA Memory-mapped Registers MMR Generic MMR Offset Name MMR Description Register Name of Category Corresponding Descriptor Element in Memory 0x00 NEXT_DESC_PTR Link pointer to next descriptor Parameter 0x04 START_ADDR Start address of current buffer Parameter SAH (upper 16 bits), SAL (lower 16 bits) 0x08 CONFIG DMA Configuration register, Parameincluding enable bit ter DMACFG 0x0C Reserved Reserved 0x10 X_COUNT Inner loop count 0x14 X_MODIFY Inner loop address increment, Paramein bytes ter XMOD 0x18 Y_COUNT Outer loop count (2-D only) Parameter YCNT 0x1C Y_MODIFY Outer loop address increment, in bytes Parameter YMOD 0x20 CURR_DESC_PTR Current descriptor pointer Current N/A 0x24 CURR_ADDR Current DMA address Current N/A 0x28 IRQ_STATUS Interrupt status register contains completion and DMA error interrupt status and channel state (run/fetch/paused) Control/ Status N/A Parameter ADSP-BF52x Blackfin Processor Hardware Reference NDPH (upper 16 bits), NDPL (lower 16 bits) XCNT 6-65 Table 6-4. Generic Names of the DMA Memory-mapped Registers (Continued) MMR Generic MMR Offset Name MMR Description Register Name of Category Corresponding Descriptor Element in Memory 0x2C PERIPHERAL_MAP Peripheral to DMA channel Control/ mapping contains a 4-bit Status value specifying the peripheral associated with this DMA channel (read-only for MDMA channels) N/A 0x30 CURR_X_COUNT Current count (1-D) or intra-row X count (2-D); counts down from X_COUNT Current N/A 0x34 Reserved Reserved 0x38 CURR_Y_COUNT Current row count (2-D only); counts down from Y_COUNT Current N/A 0x3C Reserved Reserved Channel-specific register names are composed of a prefix and the generic MMR name shown in Table 6-4. For peripheral DMA channels the prefix “DMAx_” is used, where “x” stands for a channel number between 0 and 11. For memory DMA channels, the prefix is “MDMA_yy_”, where “yy” stands for either “D0”, “S0”, “D1”, or “S1” to indicate destination and source channel registers of MDMA0 and MDMA1. For example the peripheral DMA channel 6 configuration register is called DMA6_CONFIG. The register for the MDMA1 source channel is called MDMA_S1_CONFIG. MMR The genericresourcesnames shown in Table 6-4 are not actually mapped to in the processor. For convenience, discussions in this chapter use generic (non-peripheral specific) DMA and memory DMA register names. 6-66 ADSP-BF52x Blackfin Processor Hardware Reference DMA channel registers fall into three categories. • Parameter registers such as DMAx_CONFIG and DMAx_X_COUNT that can be loaded directly from descriptor elements as shown in Table 6-4 • Current registers such as DMAx_CURR_ADDR and DMAx_CURR_X_COUNT • Control/status registers such as DMAx_IRQ_STATUS and DMAx_PERIPHERAL_MAP All DMA registers can be accessed as 16-bit entities. However, the following registers may also be accessed as 32-bit registers. • DMAx_NEXT_DESC_PTR • DMAx_START_ADDR • DMAx_CURR_DESC_PTR • DMAx_CURR_ADDR these When16 bitsfour registers are accessed as 16-bit entities, only the lower can be accessed. Because confusion might arise between descriptor element names and generic DMA register names, this chapter uses different naming conventions for physical registers and their corresponding elements in descriptors that reside in memory. Table 6-4 shows the relation. ADSP-BF52x Blackfin Processor Hardware Reference 6-67 D MA Peripheral Map Registers(DMAx_PERIPHERAL_MAP/ MDMA_yy_PERIPHERAL_MAP) Each DMA channel’s DMAx_PERIPHERAL_MAP register contains bits that: • Map the channel to a specific peripheral • Identify whether the channel is a peripheral DMA channel or a memory DMA channel DMA Peripheral Map Registers (DMAx_PERIPHERAL_MAP/MDMA_yy_PERIPHERAL_MAP) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 X X X X X X 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X PMAP[3:0] (Peripheral is mapped to this channel) CTYPE (DMA Channel Type) - RO 0 - Peripheral DMA 1 - Memory DMA Default peripheral mappings are provided in Table 6-7 on page 6-106. Figure 6-5. DMA Peripheral Map Registers Follow these steps to swap the DMA channel priorities of two channels. Assume that channels 6 and 7 are involved. 1. Make sure DMA is disabled on channels 6 and 7. 2. Write DMA6_PERIPHERAL_MAP with 0x7000 and DMA7_PERIPHERAL_MAP with 0x6000. 3. Enable DMA on channels 6 and/or 7. DMA Configuration Registers (DMAx_CONFIG/MDMA_yy_CONFIG) The DMAx_CONFIG register, shown in Figure 6-6, is used to set up DMA parameters and operating modes. Writing the DMAx_CONFIG register while 6-68 ADSP-BF52x Blackfin Processor Hardware Reference DMA is already running will cause a DMA error unless writing with the DMAEN bit set to 0. DMA Configuration Registers (DMAx_CONFIG/MDMA_yy_CONFIG) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 FLOW[2:0] (Next Operation) 0x0 - Stop 0x1 - Autobuffer mode 0x4 - Descriptor array 0x6 - Descriptor list (small model) 0x7 - Descriptor list (large model) NDSIZE[3:0] (Flex Descriptor Size) Size of next descriptor 0000 - Required if in Stop or Autobuffer mode 0001 - 1001 - Descriptor size 1010 - 1111 - Reserved DI_EN (Data Interrupt Enable) 0 - Do not allow completion of work unit to generate an interrupt 1 - Allow completion of work unit to generate a data interrupt DI_S EL (Data Interrupt Timing Select) Applies only when DMA2D = 1 0 - Interrupt after completing whole buffer (outer loop) 1 - Interrupt after completing each row (inner loop) Reset = 0x0000 DMAEN (DMA Channel Enable) 0 - Disable DMA channel 1 - Enable DMA channel WNR (DMA Direction) 0 - DMA is a memory read (source) operation 1 - DMA is a memory write (destination) operation WDSIZE[1:0] (Transfer Word Size) 00 - 8-bit transfers 01 - 16-bit transfers 10 - 32-bit transfers 11 - Reserved DMA2D (DMA Mode) 0 - Linear (One-dimensional) 1 - Two-dimensional (2-D) SYNC (Work Unit Transitions) 0 - Continuous transition 1 - Synchronized transition Figure 6-6. DMA Configuration Registers The fields of the DMAx_CONFIG register are used to set up DMA parameters and operating modes. • (next operation). This field specifies the type of DMA transfer to follow the present one. The flow options are: FLOW[2:0] • 0x0 - stop. When the current work unit completes, the DMA channel stops automatically, after signaling an interrupt (if selected). The DMA_RUN status bit in the DMAx_IRQ_STATUS register changes ADSP-BF52x Blackfin Processor Hardware Reference 6-69 from 1 to 0, while the DMAEN bit in the DMAx_CONFIG register is unchanged. In this state, the channel is paused. Peripheral interrupts are still filtered out by the DMA unit. The channel may be restarted simply by another write to the DMAx_CONFIG register specifying the next work unit, in which the DMAEN bit is set to 1. 0x1 - autobuffer mode. In this mode, no descriptors in memory are used. Instead, DMA is performed in a continuous circular buffer fashion based on user-programmed DMA MMR settings. Upon completion of the work unit, the parameter registers are reloaded into the current registers, and DMA resumes immediately with zero overhead. Autobuffer mode is stopped by a user write of 0 to the DMAEN bit in the DMAx_CONFIG register. 0x4 - descriptor array mode. This mode fetches a descriptor from memory that does not include the NDPH or NDPL elements. Because the descriptor does not contain a next descriptor pointer entry, the DMA engine defaults to using the DMAx_CURR_DESC_PTR register to step through descriptors, thus allowing a group of descriptors to follow one another in memory like an array. 0x6 - descriptor list (small model) mode. This mode fetches a descriptor from memory that includes NDPL, but not NDPH. Therefore, the high 16 bits of the next descriptor pointer field are taken from the upper 16 bits of the DMAx_NEXT_DESC_PTR register, thus confining all descriptors to a specific 64K page in memory. 6-70 ADSP-BF52x Blackfin Processor Hardware Reference 0x7 - descriptor list (large model) mode. This mode fetches a descriptor from memory that includes NDPH and NDPL, thus allowing maximum flexibility in locating descriptors in memory. • NDSIZE[3:0] (flex descriptor size). This field specifies the number of descriptor elements in memory to load. This field must be 0 if in stop or autobuffer mode. If NDSIZE and FLOW specify a descriptor that extends beyond YMOD, a DMA error results. • DI_EN • DI_SEL • SYNC (data interrupt enable). This bit specifies whether to allow completion of a work unit to generate a data interrupt. (data interrupt timing select). This bit specifies the timing of a data interrupt—after completing the whole buffer or after completing each row of the inner loop. This bit is used only in 2-D DMA operation. (work unit transitions). This bit specifies whether the DMA channel performs a continuous transition (SYNC = 0) or a synchronized transition (SYNC = 1) between work units. For more information, see “Work Unit Transitions” on page 6-25. In DMA transmit (memory read) and MDMA source channels, the bit controls the interrupt timing at the end of the work unit and the handling of the DMA FIFO between the current and next work unit. SYNC transitions Workbunit the MDMAfor MDMA streams are controlled by the it of source channel’s register. The SYNC SYNC DMAx_CONFIG bit of the MDMA destination channel is reserved and must be 0. ADSP-BF52x Blackfin Processor Hardware Reference 6-71 • DMA2D • WDSIZE[1:0] (DMA mode). This bit specifies whether DMA mode involves only DMAx_X_COUNT and DMAx_X_MODIFY (one-dimensional DMA) or also involves DMAx_Y_COUNT and DMAx_Y_MODIFY (two-dimensional DMA). (transfer word size). The DMA engine supports transfers of 8-, 16-, or 32-bit items. Each request/grant results in a single memory access (although two cycles are required to transfer 32-bit data through a 16-bit memory port or through the 16-bit DMA access bus). The increment sizes (strides) of the DMA address pointer registers must be a multiple of the transfer unit size—one for 8-bit, two for 16-bit, four for 32-bit. Only SPORT DMA and Memory DMA can operate with a transfer size of 32 bits. All other peripherals have a maximum DMA transfer size of 16 bits. • WNR • DMAEN (DMA direction). This bit specifies DMA direction—memory read (0) or memory write (1). (DMA channel enable). This bit specifies whether to enable a given DMA channel. DMA channel is enabled, interrupts from When a peripheralDMA requests. When a channel is disabled,the peripheral denote the DMA unit ignores the peripheral interrupt and passes it directly to the interrupt controller. To avoid unexpected results, take care to enable the DMA channel before enabling the peripheral, and to disable the peripheral before disabling the DMA channel. 6-72 ADSP-BF52x Blackfin Processor Hardware Reference D MA Interrupt Status Registers (DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) The DMAx_IRQ_STATUS register, shown in Figure 6-7, contains bits that record whether the DMA channel: • Is enabled and operating, enabled but stopped, or disabled. • Is fetching data or a DMA descriptor. • Has detected that a global DMA interrupt or a channel interrupt is being asserted. • Has logged occurrence of a DMA error. Note the DMA_DONE interrupt is asserted when the last memory access (read or write) has completed. transfer For a memorychannel’s to a peripheral, there may be up to four data words in the DMA FIFO when the interrupt occurs. At this point, it is normal to immediately start the next work unit. If, however, the application needs to know when the final data item is ADSP-BF52x Blackfin Processor Hardware Reference 6-73 actually transferred to the peripheral, the application can test or poll the DMA_RUN bit. As long as there is undelivered transmit data in the FIFO, the DMA_RUN bit is 1. a memory write b has Formeaning after theDMA channel,ethe state of thesignaled. Ititdoes no last vent has been DMA_RUN DMA_DONE not indicate the status of the DMA FIFO. For MDMA transfers where an interrupt is not desired to notify when the DMA operation has ended, software should poll the DMA_DONE bit, rather than the DMA_RUN bit to determine when the transaction has completed. DMA Interrupt Status Registers (DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_RUN (DMA Channel Running) - RO This bit is set to 1 automatically when the DMAx_CONFIG register is written 0 - This DMA channel is disabled, or it is enabled but paused (FLOW mode 0) 1 - This DMA channel is enabled and operating, either transferring data or fetching a DMA descriptor DFETCH (DMA Descriptor Fetch) - RO This bit is set to 1 automatically when the DMAx_CONFIG register is written with FLOW modes 4–7 0 - This DMA channel is disabled, or it is enabled but stopped (FLOW mode 0) 1 - This DMA channel is enabled and presently fetching a DMA descriptor Reset = 0x0000 DMA_DONE (DMA Completion Interrupt Status) - W1C 0 - No interrupt is being asserted for this channel 1 - DMA work unit has completed, and this DMA channel’s interrupt is being asserted DMA_ERR (DMA Error Interrupt Status) - W1C 0 - No DMA error has occurred 1 - A DMA error has occurred, and the global DMA Error interrupt is being asserted. After this error occurs, the contents of the DMA Current registers are unspecified. Control/ Status and Parameter registers are unchanged. Figure 6-7. DMA Interrupt Status Registers 6-74 ADSP-BF52x Blackfin Processor Hardware Reference The processor supports a flexible interrupt control structure with three interrupt sources: • Data driven interrupts (see Table 6-5) • Peripheral error interrupts • DMA error interrupts (for example, bad descriptor or bus error) Separate interrupt request (IRQ) levels are allocated for data, peripheral error, and DMA error interrupts. Table 6-5. Data Driven Interrupts Interrupt Name Description No Interrupt Interrupts can be disabled for a given work unit. Peripheral Interrupt These are peripheral (non-DMA) interrupts. Row Completion DMA Interrupts can occur on the completion of a row ( CURR_X_COUNT expiration). Buffer Completion DMA Interrupts can occur on the completion of an entire buffer (when CURR_X_COUNT and CURR_Y_COUNT expire). The DMA error conditions for all DMA channels are OR’d together into one system-level DMA error interrupt. The individual IRQ_STATUS words of each channel can be read to identify the channel that caused the DMA error interrupt. and interrupt indicators are Note the write-one-to-clear (W1C). When switching a peripheral from DMA to non-DMA mode, the peripheral’s interrupts should be disabled during the mode switch DMA_DONE DMA_ERR (via the appropriate peripheral register or SIC_IMASK register) so that no unintended interrupt is generated on the shared DMA/interrupt request line. ADSP-BF52x Blackfin Processor Hardware Reference 6-75 D MA Start Address Registers (DMAx_START_ADDR/MDMA_yy_START_ADDR) The DMAx_START_ADDR register, shown in Figure 6-8, contains the start address of the data buffer currently targeted for DMA. DMA Start Address Registers (DMAx_START_ADDR/ MDMA_yy_START_ADDR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Reset = Undefined DMA Start Address[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X DMA Start Address[15:0] Figure 6-8. DMA Start Address Registers DMA Current Address Registers (DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) The 32-bit DMAx_CURR_ADDR register shown in Figure 6-9, contains the present DMA transfer address for a given DMA session. On the first memory transfer of a DMA work unit, the DMAx_CURR_ADDR register is loaded 6-76 ADSP-BF52x Blackfin Processor Hardware Reference from the DMAx_START_ADDR register, and it is incremented as each transfer occurs. DMA Current Address Registers (DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X Reset = Undefined Current Address[31:16] Upper 16 bits of present DMA transfer address for a given DMA session X X X X X X Current Address[15:0] Lower 16 bits of present DMA transfer address for a given DMA session Figure 6-9. DMA Current Address Registers DMA Inner Loop Count Registers (DMAx_X_COUNT/MDMA_yy_X_COUNT) For 2-D DMA, the DMAx_X_COUNT register, shown in Figure 6-10, contains the inner loop count. For 1-D DMA, it specifies the number of elements ADSP-BF52x Blackfin Processor Hardware Reference 6-77 to transfer. For details, see “Two-Dimensional DMA Operation” on page 6-12. A value of 0 in DMAx_X_COUNT corresponds to 65,536 elements. DMA Inner Loop Count Registers (DMAx_X_COUNT/MDMA_yy_X_COUNT) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Reset = Undefined X_COUNT[15:0] (Inner Loop Count) The number of elements to transfer (1-D); the number of rows in the inner loop (2-D) Figure 6-10. DMA Inner Loop Count Registers DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT /MDMA_yy_CURR_X_COUNT) The DMAx_CURR_X_COUNT register, shown in Figure 6-11, holds the number of transfers remaining in the current DMA row (inner loop). On the first memory transfer of each DMA work unit, it is loaded with the value in the DMAx_X_COUNT register and then decremented. For 2-D DMA, on the last memory transfer in each row except the last row, it is reloaded with the value in the DMAx_X_COUNT register; this occurs at the same time that the value in the DMAx_CURR_Y_COUNT register is decremented. Otherwise it is decremented each time an element is transferred. Expiration of the count in this register signifies that DMA is complete. In 2-D DMA, the DMAx_CURR_X_COUNT register value is 0 only when the entire transfer is 6-78 ADSP-BF52x Blackfin Processor Hardware Reference complete. Between rows it is equal to the value of the DMAx_X_COUNT register. DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT/ MDMA_yy_CURR_X_COUNT) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Reset = Undefined CURR_X_COUNT[15:0] (Current Inner Loop Count) Loaded by X_COUNT at the beginning of each DMA session (1-D DMA), or at the beginning of each row (2-D DMA) Figure 6-11. DMA Current Inner Loop Count Registers DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) The DMAx_X_MODIFY register, shown in Figure 6-12, contains a signed, two’s-complement byte-address increment. In 1-D DMA, this increment is the stride that is applied after transferring each element. size. DMAx_X_MODIFY is specified in bytes, regardless of the DMA transfer In 2-D DMA, this increment is applied after transferring each element in the inner loop, up to but not including the last element in each inner loop. After the last element in each inner loop, the DMAx_Y_MODIFY register is applied instead, except on the very last transfer of each work unit. The DMAx_X_MODIFY register is always applied to the last transfer of a work unit. The DMAx_X_MODIFY field may be set to 0. In this case, DMA is performed repeatedly to or from the same address. This is useful, for example, in ADSP-BF52x Blackfin Processor Hardware Reference 6-79 transferring data between a data register and an external memory-mapped peripheral. DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Reset = Undefined X_MODIFY[15:0] (Inner Loop Address Increment) Stride (in bytes) to take after each decrement of CURR_X_COUNT Figure 6-12. DMA Inner Loop Address Increment Registers DMA Outer Loop Count Registers (DMAx_Y_COUNT/MDMA_yy_Y_COUNT) For 2-D DMA, the DMAx_Y_COUNT register, shown in Figure 6-13, contains the outer loop count. It is not used in 1-D DMA mode. This register contains the number of rows in the outer loop of a 2-D DMA sequence. For details, see “Two-Dimensional DMA Operation” on page 6-12. DMA Outer Loop Count Registers (DMAx_Y_COUNT/MDMA_yy_Y_COUNT) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Reset = Undefined Y_COUNT[15:0] (Outer Loop Count) The number of rows in the outer loop of a 2-D DMA sequence Figure 6-13. DMA Outer Loop Count Registers 6-80 ADSP-BF52x Blackfin Processor Hardware Reference D MA Current Outer Loop Count Registers (DMAx_CURR_Y_COUNT/ MDMA_yy_CURR_Y_COUNT) The DMAx_CURR_Y_COUNT register, used only in 2-D mode, holds the number of full or partial rows (outer loops) remaining in the current work unit. See Figure 6-14. On the first memory transfer of each DMA work unit, it is loaded with the value of the DMAx_Y_COUNT register. The register is decremented each time the DMAx_CURR_X_COUNT register expires during 2-D DMA operation (1 to DMAx_X_COUNT or 1 to 0 transition), signifying completion of an entire row transfer. After a 2-D DMA session is complete, DMAx_CURR_Y_COUNT = 1 and DMAx_CURR_X_COUNT = 0. DMA Current Outer Loop Count Registers (DMAx_CURR_Y_COUNT/MDMA_yy_CURR_Y_COUNT) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Reset = Undefined CURR_Y_COUNT[15:0] (Current Outer Loop Count) Loaded by Y_COUNT at the beginning of each 2-D DMA session; not used for 1-D DMA Figure 6-14. DMA Current Outer Loop Count Registers DMA Outer Loop Address Increment Registers (DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) The DMAx_Y_MODIFY register contains a signed, two’s-complement value. See Figure 6-15. This byte-address increment is applied after each decrement of the DMAx_CURR_Y_COUNT register except for the last item in the 2-D array where the DMAx_CURR_Y_COUNT also expires. The value is the offset ADSP-BF52x Blackfin Processor Hardware Reference 6-81 between the last word of one row and the first word of the next row. For details, see “Two-Dimensional DMA Operation” on page 6-12. size. DMAx_Y_MODIFY is specified in bytes, regardless of the DMA transfer DMA Outer Loop Address Increment Registers (DMAx_Y_MODIFY/ MDMA_yy_Y_MODIFY) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Reset = Undefined Y_MODIFY[15:0] (Outer Loop Address Increment) Stride to take after each decrement of CURR_Y_COUNT Figure 6-15. DMA Outer Loop Address Increment Registers DMA Next Descriptor Pointer Registers (DMAx_NEXT_DESC_PTR/ MDMA_yy_NEXT_DESC_PTR) The 32-bit DMAx_NEXT_DESC_PTR register, shown in Figure 6-16, specifies where to look for the start of the next descriptor block when the DMA activity specified by the current descriptor block finishes. This register is used in small and large descriptor list modes. At the start of a descriptor fetch in either of these modes, this register is copied into the DMAx_CURR_DESC_PTR register. Then, during the descriptor fetch, the DMAx_CURR_DESC_PTR register increments after each element of the descriptor is read in. and large descriptor list modes, the In small and not the register, register, must be pro- DMAx_NEXT_DESC_PTR DMAx_CURR_DESC_PTR grammed directly via MMR access before starting DMA operation. 6-82 ADSP-BF52x Blackfin Processor Hardware Reference In descriptor array mode, the next descriptor pointer register is disregarded, and fetching is controlled only by the DMAx_CURR_DESC_PTR register. DMA Next Descriptor Pointer Registers (DMAx_NEXT_DESC_PTR/MDMA_yy_NEXT_DESC_PTR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Reset = Undefined Next Descriptor Pointer[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Next Descriptor Pointer[15:0] Figure 6-16. DMA Next Descriptor Pointer Registers DMA Current Descriptor Pointer Registers (DMAx_CURR_DESC_PTR/ MDMA_yy_CURR_DESC_PTR) The 32-bit DMAx_CURR_DESC_PTR register, shown in Figure 6-17, contains the memory address for the next descriptor element to be loaded. For FLOW mode settings that involve descriptors (FLOW = 4, 6, or 7), this register is used to read descriptor elements into appropriate MMRs before a DMA work block begins. For descriptor list modes (FLOW = 6 or 7), this register is initialized from the DMAx_NEXT_DESC_PTR register before loading each descriptor. Then, the address in the DMAx_CURR_DESC_PTR register increments as each descriptor element is read in. When the entire descriptor has been read, the DMAx_CURR_DESC_PTR register contains this value: ADSP-BF52x Blackfin Processor Hardware Reference 6-83 Descriptor Start Address + (2 Descriptor Size) (# of elements) = not the For descriptor array mode ( must4), this register, and MMR register, be programmed by FLOW DMAx_NEXT_DESC_PTR access before starting DMA operation. DMA Next Descriptor Pointer Registers (DMAx_NEXT_DESC_PTR/MDMA_yy_NEXT_DESC_PTR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Reset = Undefined Next Descriptor Pointer[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Next Descriptor Pointer[15:0] Figure 6-17. DMA Current Descriptor Pointer Registers HMDMA Registers Some processors have two HMDMA blocks, while others have none. See the “Unique Behavior for the ADSP-BF52x Processor” on page 6-105 to determine whether this feature is applicable to your product. HMDMA0 is associated with MDMA0, and HMDMA1 is associated with MDMA1. Handshake MDMA Control Registers (HMDMAx_CONTROL) The HMDMAx_CONTROL register, shown in Figure 6-18, is used to set up HMDMA parameters and operating modes. 6-84 ADSP-BF52x Blackfin Processor Hardware Reference The DRQ[1:0] field is used to control the priority of the MDMA channel when the HMDMA is disabled, that is, when handshake control is not being used (see Table 6-6). Table 6-6. DRQ[1:0] Values DRQ[1:0] Priority Description 00 Disabled The MDMA request is disabled. 01 Enabled/S Normal MDMA channel priority. The channel in this mode is limited to single memory transfers separated by one idle system clock. Request single transfer from MDMA channel. 10 Enabled/ M Normal MDMA channel functionality and priority. Request multiple transfers from MDMA channel (default). 11 Urgent The MDMA channel priority is elevated to urgent. In this state, it has higher priority for memory access than non-urgent channels. If two channels are both urgent, the lower-numbered channel has priority. ADSP-BF52x Blackfin Processor Hardware Reference 6-85 The RBC bit forces the BCOUNT register to be reloaded with the BCINIT value while the module is already active. Do not set this bit in the same write that sets the HMDMAEN bit to active. Handshake MDMA Control Registers (HMDMAx_CONTROL) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0200 HMDMAEN (Handshake MDMA Enable) 0 - Disable handshake Operation 1 - Enable handshake Operation REP (HMDMA Request Polarity) 0 - Increment ECOUNT on falling edges of DMARx input 1 - Increment ECOUNT on rising edges of DMARx input BDI (Block Done Interrupt Generated) - W1C 0 - Block done interrupt not generated 1 - Block done interrupt generated OI (Overflow Interrupt Generated) - W1C 0 - Overflow interrupt not generated 1 - Overflow interrupt generated PS (Pin Status) - RO 0 - Request pin is 0 1 - Request pin is 1 RBC (Force Reload of BCOUNT) - WO 0 - Reload not active 1 - Force reload of BCOUNT with BCINIT. Write 1 to activate DRQ[1:0] (Default MDMA Request When Handshake DMA is Disabled EN=0) 00 - No request 01 - Request single transfer from MDMA channel 10 - Request multiple transfers from MDMA channel (default) 11 - Request urgent multiple transfers from MDMA channel UTE (Urgency Threshold Enable) 0 - Disable urgency threshold 1 - Enable urgency threshold OIE (Overflow Interrupt Enable) 0 - Disable overflow interrupt 1 - Enable overflow interrupt BDIE (Block Done Interrupt Enable) 0 - Disable block done interrupt 1 - Enable block done interrupt MBDI (Mask Block Done Interrupt) BDIE must = 1 0 - Interrupt generated when BCOUNT decrements to 0 1 - Interrupt generated when BCOUNT decrements to 0 and ECOUNT = 0 Figure 6-18. Handshake MDMA Control Registers 6-86 ADSP-BF52x Blackfin Processor Hardware Reference H andshake MDMA Initial Block Count Registers (HMDMAx_BCINIT) The HMDMAx_BCINIT register, shown in Figure 6-19, holds the number of transfers to do per edge of the DMARx control signal. Handshake MDMA Initial Block Count Registers (HMDMAx_BCINIT) 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 BCINIT[15:0] (Initial Block Count) Figure 6-19. Handshake MDMA Initial Block Count Registers Handshake MDMA Current Block Count Registers (HMDMAx_BCOUNT) The HMDMAx_BCOUNT register, shown in Figure 6-20, holds the number of transfers remaining for the current edge. MDMA requests are generated if this count is greater than 0. Examples: • 0000 = 0 transfers remaining • FFFF = 65535 transfers remaining The BCOUNT field is loaded with BCINIT when ECOUNT is greater than 0 and BCOUNT is expired (0). Also, if the RBC bit in the HMDMAx_CONTROL register is written to 1, BCOUNT is loaded with BCINIT. The BCOUNT field is decremented with each MDMA grant. It is cleared when HMDMA is disabled. A block done interrupt is generated when BCOUNT decrements to 0. If the MBDI bit in the HMDMAx_CONTROL register is set, the interrupt is suppressed ADSP-BF52x Blackfin Processor Hardware Reference 6-87 until ECOUNT is 0. If BCINIT is 0, no block done interrupt is generated, since no DMA requests were generated or grants received. Handshake MDMA Current Block Count Register (HMDMAx_BCOUNT) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 BCOUNT[15:0] (Transfers Remaining for Current Edge) Figure 6-20. Handshake MDMA Current Block Count Registers Handshake MDMA Current Edge Count Registers (HMDMAx_ECOUNT) The HMDMAx_ECOUNT register, shown in Figure 6-21, holds a signed number of edges remaining to be serviced. This number is in a signed two’s complement representation. When an edge is detected on the respective DMARx input, requests occur if this count is greater than or equal to 0 and BCOUNT is greater than 0. When the handshake mode is enabled, ECOUNT is loaded and the resulting number of requests is: Number of edges + N, where N is the number loaded from ECINIT. The number N can be positive or negative. Examples: • 0x7FFF = 32,767 edges remaining • 0x0000 = 0 edges remaining • 0x8000 = –32,768: ignore the next 32,768 edges 6-88 ADSP-BF52x Blackfin Processor Hardware Reference Each time that BCOUNT expires, ECOUNT is decremented and BCOUNT is reloaded from BCINIT. When a handshake request edge is detected, ECOUNT is incremented. The ECOUNT field is cleared when HMDMA is disabled. Handshake MDMA Current Edge Count Register (HMDMAx_ECOUNT) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 ECOUNT[15:0] (Edges Remaining to be Serviced) Figure 6-21. Handshake MDMA Current Edge Count Registers Handshake MDMA Initial Edge Count Registers (HMDMAx_ECINIT) The HMDMAx_ECINIT register, shown in Figure 6-22, holds a signed number that is loaded into HMDMAx_ECOUNT when handshake DMA is enabled. This number is in a signed two’s complement representation. Handshake MDMA Initial Edge Count Registers (HMDMAx_ECINIT) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 ECINIT[15:0] (Initial Edge Count) Figure 6-22. Handshake MDMA Initial Edge Count Registers Handshake MDMA Edge Count Urgent Registers (HMDMAx_ECURGENT) The HMDMAx_ECURGENT register, shown in Figure 6-23, holds the urgent threshold. If the ECOUNT field in the HMDMAx_ECOUNT register is greater than ADSP-BF52x Blackfin Processor Hardware Reference 6-89 this threshold, the MDMA request is urgent and might get higher priority. Handshake MDMA Edge Count Urgent Registers (HMDMAx_ECURGENT) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset = 0xFFFF UTHE[15:0] (Urgent Threshold) Figure 6-23. Handshake MDMA Edge Count Urgent Registers Handshake MDMA Edge Count Overflow Interrupt Registers (HMDMAx_ECOVERFLOW) The HMDMAx_ECOVERFLOW register, shown in Figure 6-24, holds the interrupt threshold. If the ECOUNT field in the HMDMAx_ECOUNT register is greater than this threshold, an overflow interrupt is generated. Handshake MDMA Edge Count Overflow Interrupt Registers (HMDMAx_ECOVERFLOW) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset = 0xFFFF ITHR[15:0] (Interrupt Threshold) Figure 6-24. Handshake MDMA Edge Count Overflow Interrupt Registers DMA Traffic Control Registers (DMA_TC_PER and DMA_TC_CNT) The DMA_TC_PER register (see Figure 6-25) and the DMA_TC_CNT register (see Figure 6-26) work with other DMA registers to define traffic control. 6-90 ADSP-BF52x Blackfin Processor Hardware Reference D MA_TC_PER Register DMA Traffic Control Counter Period Register (DMA_TC_PER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDMA_ROUND_ROBIN_PERIOD[4:0] Maximum length of MDMA round robin bursts. If not zero, any MDMA stream which receives a grant is allowed up to that number of DMA transfers, to the exclusion of the other MDMA streams. DAB_TRAFFIC_PERIOD[2:0] 000 - No DAB bus transfer grouping performed Other - Preferred length of unidirectional bursts on the DAB bus between the DMA and the peripherals Reset = 0x0000 DCB_TRAFFIC_PERIOD[3:0] 0000 - No DCB bus transfer grouping performed Other - Preferred length of unidirectional bursts on the DCB bus between the DMA and internal L1 memory DEB_TRAFFIC_PERIOD[3:0] 0000 - No DEB bus transfer grouping performed Other - Preferred length of unidirectional bursts on the DEB bus between the DMA and external memory Figure 6-25. DMA Traffic Control Counter Period Register ADSP-BF52x Blackfin Processor Hardware Reference 6-91 D MA_TC_CNT Register DMA Traffic Control Counter Register (DMA_TC_CNT) RO 15 14 13 12 11 10 0 0 0 MDMA_ROUND_ROBIN_COUNT[4:0] 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Current transfer count remaining in the MDMA round-robin period DCB_TRAFFIC_COUNT[3:0] Current cycle count remaining in the DCB traffic period DAB_TRAFFIC_COUNT[2:0] Current cycle count remaining in the DAB traffic period DEB_TRAFFIC_COUNT[3:0] Current cycle count remaining in the DEB traffic period Figure 6-26. DMA Traffic Control Counter Register The MDMA_ROUND_ROBIN_COUNT field shows the current transfer count remaining in the MDMA round-robin period. It initializes to MDMA_ROUND_ROBIN_PERIOD whenever DMA_TC_PER is written, whenever a different MDMA stream is granted, or whenever every MDMA stream is idle. It then counts down to 0 with each MDMA transfer. When this count decrements from 1 to 0, the next available MDMA stream is selected. The DAB_TRAFFIC_COUNT field shows the current cycle count remaining in the DAB traffic period. It initializes to DAB_TRAFFIC_PERIOD whenever DMA_TC_PER is written, or whenever the DAB bus changes direction or becomes idle. It then counts down from DAB_TRAFFIC_PERIOD to 0 on each system clock (except for DMA stalls). While this count is nonzero, same direction DAB accesses are treated preferentially. When this count decrements from 1 to 0, the opposite direction DAB access is treated preferentially, which may result in a direction change. When this count is 0 and a DAB bus access occurs, the count is reloaded from DAB_TRAFFIC_PERIOD to begin a new burst. The DEB_TRAFFIC_COUNT field shows the current cycle count remaining in the DEB traffic period. It initializes to DEB_TRAFFIC_PERIOD whenever 6-92 ADSP-BF52x Blackfin Processor Hardware Reference is written or whenever the DEB bus changes direction or becomes idle. It then counts down from DEB_TRAFFIC_PERIOD to 0 on each system clock (except for DMA stalls). While this count is nonzero, same direction DEB accesses are treated preferentially. When this count decrements from 1 to 0, the opposite direction DEB access is treated preferentially, which may result in a direction change. When this count is 0 and a DEB bus access occurs, the count is reloaded from DEB_TRAFFIC_PERIOD to begin a new burst. DMA_TC_PER The DCB_TRAFFIC_COUNT field shows the current cycle count remaining in the DCB traffic period. It initializes to DCB_TRAFFIC_PERIOD whenever DMA_TC_PER is written or whenever the DCB bus changes direction or becomes idle. It then counts down from DCB_TRAFFIC_PERIOD to 0 on each system clock (except for DMA stalls). While this count is nonzero, same direction DCB accesses are treated preferentially. When this count decrements from 1 to 0, the opposite direction DCB access is treated preferentially, which may result in a direction change. When this count is 0 and a DCB bus access occurs, the count is reloaded from DCB_TRAFFIC_PERIOD to begin a new burst. Programming Examples The following examples illustrate memory DMA and handshaked memory DMA basics. Examples for peripheral DMAs can be found in the respective peripheral chapters. ADSP-BF52x Blackfin Processor Hardware Reference 6-93 R egister-Based 2-D Memory DMA Listing 6-1 shows a register-based, two-dimensional MDMA. While the source channel processes linearly, the destination channel re-sorts elements by transposing the two-dimensional data array. See Figure 6-27. 1 7 13 19 25 1 2 3 4 2 8 14 20 26 7 8 9 10 11 12 3 9 15 21 27 4 10 16 22 28 5 11 17 23 29 5 6 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 6 12 18 24 30 Figure 6-27. DMA Example, 2-D Array The two arrays reside in two different L1 data memory blocks. However, the arrays could reside in any internal or external memory, including L1 instruction memory and SDRAM. For the case where the destination array resided in SDRAM, it is a good idea to let the source channel re-sort elements and to let the destination buffer store linearly. Listing 6-1. Register-Based 2-D Memory DMA #include <defBF527.h>/*For ADSP-BF527 product, as an example.*/ #define X 5 #define Y 6 .section L1_data_a; .byte2 aSource[X*Y] = 1, 7, 13, 19, 25, 2, 8, 14, 20, 26, 3, 9, 15, 21, 27, 4, 10, 16, 22, 28, 5, 11, 17, 23, 29, 6-94 ADSP-BF52x Blackfin Processor Hardware Reference 6, 12, 18, 24, 30; .section L1_data_b; .byte2 aDestination[X*Y]; .section L1_code; .global _main; _main: p0.l = lo(MDMA_S0_CONFIG); p0.h = hi(MDMA_S0_CONFIG); call memdma_setup; call memdma_wait; _main.forever: jump _main.forever; _main.end: The setup routine shown in Listing 6-2 initializes either MDMA0 or MDMA1, depending on whether the MMR address of MDMA_S0_CONFIG or MDMA_S1_CONFIG is passed in the P0 register. Note that the source channel is enabled before the destination channel. Also, it is common to synchronize interrupts with the destination channel because only those interrupts indicate completion of both DMA read and write operations. Listing 6-2. Two-Dimensional Memory DMA Setup Example memdma_setup: [--sp] = r7; /* setup 1D source DMA for 16-bit transfers */ r7.l = lo(aSource); r7.h = hi(aSource); [p0 + MDMA_S0_START_ADDR - MDMA_S0_CONFIG] = r7; r7.l = 2; w[p0 + MDMA_S0_X_MODIFY - MDMA_S0_CONFIG] = r7; r7.l = X * Y; w[p0 + MDMA_S0_X_COUNT - MDMA_S0_CONFIG] = r7; ADSP-BF52x Blackfin Processor Hardware Reference 6-95 r7.l = WDSIZE_16 | DMAEN; w[p0] = r7; /* setup 2D destination DMA for 16-bit transfers */ r7.l = lo(aDestination); r7.h = hi(aDestination); [p0 + MDMA_D0_START_ADDR - MDMA_S0_CONFIG] = r7; r7.l = 2*Y; w[p0 + MDMA_D0_X_MODIFY - MDMA_S0_CONFIG] = r7; r7.l = Y; w[p0 + MDMA_D0_Y_COUNT - MDMA_S0_CONFIG] = r7; r7.l = X; w[p0 + MDMA_D0_X_COUNT - MDMA_S0_CONFIG] = r7; r7.l = -2 * (Y * (X-1) - 1); w[p0 + MDMA_D0_Y_MODIFY - MDMA_S0_CONFIG] = r7; r7.l = DMA2D | DI_EN | WDSIZE_16 | WNR | DMAEN; w[p0 + MDMA_D0_CONFIG - MDMA_S0_CONFIG] = r7; r7 = [sp++]; rts; memdma_setup.end: For simplicity the example shown in Listing 6-3 polls the DMA status rather than using interrupts, which is the normal case in a real application. Listing 6-3. Polling DMA Status memdma_wait: [--sp] = r7; memdma_wait.test: r7 = w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] (z); CC = bittst (r7, bitpos(DMA_DONE)); if !CC jump memdma_wait.test; r7 = DMA_DONE (z); w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] = r7; r7 = [sp++]; 6-96 ADSP-BF52x Blackfin Processor Hardware Reference rts; memdma_wait.end: I nitializing Descriptors in Memory Descriptor-based DMAs expect the descriptor data to be available in memory by the time the DMA is enabled. Often, the descriptors are programmed by software at run-time. Many times, however, the descriptors—or at least large portions of them—can be static and therefore initialized at boot time. How to set up descriptors in global memory depends heavily on the programming language and the tool set used. The following examples show how this is best performed in the VisualDSP++ tools’ assembly language. Listing 6-4 uses multiple variables of either 16-bit or 32-bit size to describe DMA descriptors. This example has two descriptors in small list flow mode that point to each other. At the end of the second work unit, an interrupt is generated without discontinuing the DMA processing. The trailing .end label is required to let the linker know that a descriptor forms a logical unit. It prevents the linker from removing variables when optimizing. Listing 6-4. Two Descriptors in Small List Flow Mode .section sdram; .byte2 arrBlock1[0x400]; .byte2 arrBlock2[0x800]; .section L1_data_a; .byte2 descBlock1 = lo(descBlock2); .var descBlock1.addr = arrBlock1; .byte2 descBlock1.cfg = FLOW_SMALL|NDSIZE_5|WDSIZE_16|DMAEN; .byte2 descBlock1.len = length(arrBlock1); ADSP-BF52x Blackfin Processor Hardware Reference 6-97 descBlock1.end: .byte2 descBlock2 = lo(descBlock1); .var descBlock2.addr = arrBlock2; .byte2 descBlock2.cfg = FLOW_SMALL|NDSIZE_5|DI_EN|WDSIZE_16|DMAEN; .byte2 descBlock2.len = length(arrBlock2); descBlock2.end: Another method featured by the VisualDSP++ tools takes advantage of C-style structures in global header files. The header file descriptors.h could look like Listing 6-5. Listing 6-5. Header File to Define Descriptor Structures #ifndef __INCLUDE_DESCRIPTORS__ #define __INCLUDE_DESCRIPTORS__ #ifdef _LANGUAGE_C typedef struct { void *pStart; short dConfig; short dXCount; short dXModify; short dYCount; short dYModify; } dma_desc_arr; typedef struct { void *pNext; void *pStart; short dConfig; short dXCount; short dXModify; short dYCount; short dYModify; 6-98 ADSP-BF52x Blackfin Processor Hardware Reference } dma_desc_list; #endif // _LANGUAGE_C #endif // __INCLUDE_DESCRIPTORS__ Note that near pointers are not natively supported by the C language and, thus, pointers are always 32 bits wide. Therefore, the scheme above cannot be used directly for small list mode without giving up pointer syntax. The variable definition file is required to import the C-style header file and can finally take advantage of the structures. See Listing 6-6. Listing 6-6. Using Descriptor Structures #include "descriptors.h" .import "descriptors.h"; .section L1_data_a; .align 4; .var arrBlock3[N]; .var arrBlock4[N]; .struct dma_desc_list descBlock3 = { descBlock4, arrBlock3, FLOW_LARGE | NDSIZE_7 | WDSIZE_32 | DMAEN, length(arrBlock3), 4, 0, 0 /* unused values */ }; .struct dma_desc_list descBlock4 = { descBlock3, arrBlock4, FLOW_LARGE | NDSIZE_7 | DI_EN | WDSIZE_32 | DMAEN, length(arrBlock4), 4, 0, 0 /* unused values */ }; ADSP-BF52x Blackfin Processor Hardware Reference 6-99 S oftware-Triggered Descriptor Fetch Example Listing 6-7 demonstrates a large list of descriptors that provide FLOW = 0 (stop mode) configuration. Consequently, the DMA stops by itself as soon as the work unit has finished. Software triggers the next work unit by simply writing the proper value into the DMA configuration registers. Since these values instruct the DMA controller to fetch descriptors in large list mode, the DMA immediately fetches the descriptor, thus overwriting the configuration value again with the new settings when it is started. Note the requirement that source and destination channels stop after the same number of transfers. Between stops, the two channels can have completely individual structures. Listing 6-7. Software-Triggered Descriptor Fetch .import "descriptors.h"; #define N 4 .section L1_data_a; .byte2 arrSource1[N] = { 0x1001, 0x1002, 0x1003, 0x1004 }; .byte2 arrSource2[N] = { 0x2001, 0x2002, 0x2003, 0x2004 }; .byte2 arrSource3[N] = { 0x3001, 0x3002, 0x3003, 0x3004 }; .byte2 arrDest1[N]; .byte2 arrDest2[2*N]; .struct dma_desc_list descSource1 = { descSource2, arrSource1, WDSIZE_16 | DMAEN, length(arrSource1), 2, 0, 0 /* unused values */ }; .struct dma_desc_list descSource2 = { descSource3, arrSource2, FLOW_LARGE | NDSIZE_7 | WDSIZE_16 | DMAEN, 6-100 ADSP-BF52x Blackfin Processor Hardware Reference length(arrSource2), 2, 0, 0 /* unused values */ }; .struct dma_desc_list descSource3 = { descSource1, arrSource3, WDSIZE_16 | DMAEN, length(arrSource3), 2, 0, 0 /* unused values */ }; .struct dma_desc_list descDest1 = { descDest2, arrDest1, DI_EN | WDSIZE_16 | WNR | DMAEN, length(arrDest1), 2, 0, 0 /* unused values */ }; .struct dma_desc_list descDest2 = { descDest1, arrDest2, DI_EN | WDSIZE_16 | WNR | DMAEN, length(arrDest2), 2, 0, 0 /* unused values */ }; .section L1_code; _main: /* write descriptor address to next descriptor pointer */ p0.h = hi(MDMA_S0_CONFIG); p0.l = lo(MDMA_S0_CONFIG); r0.h = hi(descDest1); r0.l = lo(descDest1); [p0 + MDMA_D0_NEXT_DESC_PTR - MDMA_S0_CONFIG] = r0; r0.h = hi(descSource1); r0.l = lo(descSource1); [p0 + MDMA_S0_NEXT_DESC_PTR - MDMA_S0_CONFIG] = r0; ADSP-BF52x Blackfin Processor Hardware Reference 6-101 /* start first work unit */ r6.l = FLOW_LARGE|NDSIZE_7|WDSIZE_16|DMAEN; w[p0 + MDMA_S0_CONFIG - MDMA_S0_CONFIG] = r6; r7.l = FLOW_LARGE|NDSIZE_7|WDSIZE_16|WNR|DMAEN; w[p0 + MDMA_D0_CONFIG - MDMA_S0_CONFIG] = r7; /* wait until destination channel has finished and W1C latch */ _main.wait: r0 = w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] (z); CC = bittst (r0, bitpos(DMA_DONE)); if !CC jump _main.wait; r0.l = DMA_DONE; w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] = r0; /* wait for any software or hardware event here */ /* start next work unit */ w[p0 + MDMA_S0_CONFIG - MDMA_S0_CONFIG] = r6; w[p0 + MDMA_D0_CONFIG - MDMA_S0_CONFIG] = r7; jump _main.wait; _main.end: Handshaked Memory DMA Example The functional block for the handshaked MDMA operation can be considered completely separately from the MDMA channels themselves. Therefore the following HMDMA setup routine can be combined with any of the MDMA examples discussed above. Be sure that the HMDMA module is enabled before the MDMA channels. Listing 6-8 enables the HMDMA1 block, which is controlled by the DMAR1 pin and is associated with the MDMA1 channel pair. 6-102 ADSP-BF52x Blackfin Processor Hardware Reference Listing 6-8. HMDMA1 Block Enable /* optionally, enable all four bank select strobes */ p1.l = lo(EBIU_AMGCTL); p1.h = hi(EBIU_AMGCTL); r0.l = 0x0009; w[p1] = r0; /* function enable for DMAR1 */ p1.l = lo(PORTG_FER); r0.l = PG12; w[p1] = r0; p1.l = lo(PORTG_MUX); r0.l = 0x0000; w[p1] = r0; /* every single transfer requires one DMAR1 event */ p1.l = lo(HMDMA1_BCINIT); r0.l = 1; w[p1] = r0; /* start with balanced request counter */ p1.l = lo(HMDMA1_ECINIT); r0.l = 0; w[p1] = r0; /* enable for rising edges */ p1.l = lo(HMDMA1_CONTROL); r2.l = REP | HMDMAEN; w[p1] = r2; If the HMDMA is intended to copy from internal memory to external devices, the above setup is sufficient. If, however, the data flow is from outside the processor to internal memory, then this small issue must be considered—the HMDMA only controls the destination channel of the ADSP-BF52x Blackfin Processor Hardware Reference 6-103 memory DMA. It does not gate requests to the source channel at all. Thus, as soon as the source channel is enabled, it starts filling the DMA FIFO immediately. In 16-bit DMA mode, this results in eight read strobes on the EBIU even before the first DMAR1 event has been detected. In other words, the transferred data and the DMAR1 strobes are eight positions off. The example in Listing 6-9 delays processing until eight DMAR1 requests have been received. By doing so, the transmitter is required to add eight trailing dummy writes after all data words have been sent. This is because the transmit channel still has to drain the DMA FIFO. Listing 6-9. HMDMA With Delayed Processing /* wait for eight requests */ p1.l = lo(HMDMA1_ECOUNT); r0 = 7 (z); initial_requests: r1 = w[p1] (z); CC = r1 < r0; if CC jump initial_requests; /* disable and reenable to clear edge count */ p1.l = lo(HMDMA1_CONTROL); r0.l = 0; w[p1] = r0; w[p1] = r2; If the polling operation shown in Listing 6-9 is too expensive, an interrupt version of it can be implemented by using the HMDMA overflow feature. Temporarily set the HMDMAx_OVERFLOW register to eight. 6-104 ADSP-BF52x Blackfin Processor Hardware Reference U nique Behavior for the ADSP-BF52x Processor Figure 6-28 provides a block diagram of the DMA controller. CCLK DMAR0 DMAR1 SCLK DMA TRAFFIC CONTROL IRQ 1 MDMA 0 SOURCE CONTROL FIFO IRQ 29 MDMA 0 DESTINATION CONTROL HMDMA 0 MDMA 1 SOURCE CONTROL FIFO HMDMA 1 IRQ 14 PMAP DMA 10 CONTROL IRQ 13 PMAP DMA 9 CONTROL IRQ 12 FIFO PMAP DMA 8 CONTROL IRQ 11 FIFO PMAP DMA 7 CONTROL IRQ 10 FIFO PMAP DMA 6 CONTROL IRQ 8 FIFO PMAP DMA 5 CONTROL IRQ 7 FIFO PMAP DMA 4 CONTROL IRQ 6 FIFO PMAP DMA 3 CONTROL IRQ 5 FIFO PMAP DMA 2 CONTROL IRQ 18 FIFO PMAP DMA 1 CONTROL IRQ 17 FIFO 16 DMA 11 CONTROL FIFO DEB PMAP FIFO 16 IRQ 30 FIFO DCB MDMA 1 DESTINATION CONTROL PMAP DMA 0 CONTROL IRQ 4 16 12 3 x 12 DAB DGT DRQ 16 PAB Figure 6-28. ADSP-BF52x DMA Controller Block Diagram ADSP-BF52x Blackfin Processor Hardware Reference 6-105 S tatic Channel Prioritization The default configuration shown in Table 6-7 can be changed by altering the 4-bit PMAP field in the DMAx_PERIPHERAL_MAP registers for the peripheral DMA channels. Table 6-7. Priority and Default Mapping of Peripheral to DMA Priority DMA Channel PMAP Default Value Peripheral Mapped by Default Highest DMA 0 0x0 PPI receive/transmit or NFC DMA 1 0x1 Ethernet MAC receive1 or HOSTDP DMA 2 0x2 Ethernet MAC transmit1 or NFC DMA 3 0x3 SPORT0 receive1 DMA 4 0x4 SPORT0 transmit1 DMA 5 0x5 SPORT1 receive1 DMA 6 0x6 SPORT1 transmit1 DMA 7 0x7 SPI DMA 8 0x8 UART0 receive DMA 9 0x9 UART0 transmit DMA 10 0xA UART1 receive DMA 11 0xB UART1 transmit MDMA D01 N/A N/A MDMA S01 N/A N/A MDMA D11 N/A N/A MDMA S11 N/A N/A Lowest 1 Can be set to use 32-bit DMA. The 32-bit DMA setting causes the DMA channel to do back-to-back 16-bit transactions which can lead to improved performance. 6-106 ADSP-BF52x Blackfin Processor Hardware Reference only the ADSP-BF526 and ADSP-BF527 processors fea AlthoughEthernet MAC module, the DMA1 and DMA2 channels ture the are still present on all parts and can be used for the HOSTDP or NFC. Peripherals which share a set of multiplexed pins can also share a DMA channel. Whichever peripheral is configured in PORTx_MUX to utilize the shared pins and is enabled will get the shared DMA channel. It is up to the user to ensure that multiple peripherals which share pins aren't enabled simultaneously. DMA Control Commands The ADSP-BF52x processors have two DMA-management-capable peripherals; the Ethernet MAC and the Host DMA Port. Refer to the “Ethernet MAC”, and “Host DMA Port” chapters for a description of how these peripherals use DMA control commands. Handshaked Memory DMA Operation HMDMA Interrupts All interrupt sources are routed to the global DMA error interrupt channel. ADSP-BF52x Blackfin Processor Hardware Reference 6-107 6-108 ADSP-BF52x Blackfin Processor Hardware Reference 7 EXTERNAL BUS INTERFACE UNIT The external bus interface unit (EBIU) provides glueless interfaces to external memories. The processor supports Synchronous DRAM (SDRAM) including mobile SDRAM. The EBIU also supports asynchronous interfaces such as SRAM, ROM, FIFOs, flash memory, and ASIC/FPGA designs. EBIU Overview The EBIU services requests for external memory from the core or from a DMA channel. The priority of the requests is determined by the external bus controller. The address of the request determines whether the request is serviced by the EBIU SDRAM controller or the EBIU asynchronous memory controller. The DMA controller provides high-bandwidth data movement capability. The Memory DMA (MDMA) channels can perform block transfers of code or data between the internal memory and the external memory spaces. The MDMA channels also feature a Handshake Operation mode (HMDMA) via dual external DMA request pins. When used in conjunction with the EBIU, this functionality can be used to interface high-speed external devices, such as FIFOs and USB 2.0 controllers, in an automatic manner. For more information on HMDMA and the external DMA request pins, please refer to Chapter 6, “Direct Memory Access”. The EBIU is clocked by the system clock (SCLK). All synchronous memories interfaced to the processor operate at the SCLK frequency. The ratio between core clock frequency (CCLK) and SCLK frequency is programmable ADSP-BF52x Blackfin Processor Hardware Reference 7-1 using a Phase Locked Loop (PLL) system Memory-Mapped Register (MMR). For more information, see “Core Clock/System Clock Ratio Control” on page 18-5. The external memory space is shown in Figure 7-1. One memory region is dedicated to SDRAM support. SDRAM interface timing and the size of the SDRAM region are programmable. The SDRAM memory space can range in size from 16M byte to 128M byte. The start address of the SDRAM memory space is 0x0000 0000. The area from the end of the SDRAM memory space up to address 0x2000 0000 is reserved. The next four regions are dedicated to supporting asynchronous memories. Each asynchronous memory region can be independently programmed to support different memory device characteristics. Each region has its own memory select output pin from the EBIU. The next region is reserved memory space. References to this region do not generate external bus transactions. Writes have no effect on external memory values, and reads return undefined values. The EBIU generates an error response on the internal bus, which will generate a hardware 7-2 ADSP-BF52x Blackfin Processor Hardware Reference exception for a core access or will optionally generate an interrupt from a DMA channel. EXTERNAL MEMORY MAP 0xEEFF FFFF RESERVED 0x2040 0000 ASYNC MEMORY BANK 3 (1 MByte) 0x2030 0000 ASYNC MEMORY BANK 2 (1 MByte) 0x2020 0000 ASYNC MEMORY BANK 1 (1 MByte) 0x2010 0000 ASYNC MEMORY BANK 0 (1 MByte) 0x2000 0000 RESERVED SDRAM MEMORY (16 MByte–128 MByte) 0x0000 0000 NOTE: RESERVED OFF-CHIP MEMORY AREAS ARE LABELED IN THE DIAGRAM ABOVE. ALL OTHER OFF-CHIP SYSTEM RESOURCES ARE ADDRESSABLE BY BOTH THE CORE AND THE SYSTEM. Figure 7-1. External Memory Map ADSP-BF52x Blackfin Processor Hardware Reference 7-3 B lock Diagram Figure 7-2 is a conceptual block diagram of the EBIU and its interfaces. Signal names shown with an overbar are active low signals. Since only one external memory device can be accessed at a time, control, address, and data pins for each memory type are multiplexed together at the pins of the device. The Asynchronous Memory Controller (AMC) and the SDRAM Controller (SDC) effectively arbitrate for the shared pin resources. DEB ASYNCHRONOUS MEMORY CONTROLLER (AMC) DEVICE PADS EAB EXTERNAL BUS CONTROLLER (EBC) EBIU SDRAM CONTROLLER (SDC) DATA [15:0] ADDR [19:1] ABE [1:0]/SDQM [1:0] AMS [3:0] ARDY AOE ARE AWE SMS CLKOUT SCKE SA10 SRAS SCAS SWE PAB Figure 7-2. External Bus Interface Unit (EBIU) 7-4 ADSP-BF52x Blackfin Processor Hardware Reference I nternal Memory Interfaces The EBIU functions as a slave on three buses internal to the processor: • External Access Bus (EAB), mastered by the core memory management unit on behalf of external bus requests from the core • DMA External Bus (DEB), mastered by the DMA controller on behalf of external bus requests from any DMA channel • Peripheral Access Bus (PAB), mastered by the core on behalf of system MMR requests from the core These are synchronous interfaces, clocked by SCLK, as is the EBIU. The EAB provides access to both asynchronous external memory and synchronous DRAM external memory. The external access is controlled by either the AMC or the SDC, depending on the internal address used to access the EBIU. Since the AMC and SDC share the same interface to the external pins, access is sequential and must be arbitrated based on requests from the EAB. The third bus (PAB) is used only to access the memory-mapped control and status registers of the EBIU. The PAB connects separately to the AMC and SDC. It does not need to arbitrate with, nor take access cycles from, the EAB bus. The External Bus Controller (EBC) logic must arbitrate access requests for external memory coming from the EAB and DEB buses. The EBC logic routes read and write requests to the appropriate memory controller based on the bus selects. The AMC and SDC compete for access to the shared resources. This competition is resolved in a pipelined fashion, in the order dictated by the EBC arbiter. Transactions from the core have priority over DMA accesses in most circumstances. However, if the DMA controller detects an excessive backup of transactions, it can request its priority to be temporarily raised above the core. ADSP-BF52x Blackfin Processor Hardware Reference 7-5 R egisters There are six control registers and one status register in the EBIU. They are: • Asynchronous memory global control register (EBIU_AMGCTL) • Asynchronous memory bank control 0 register (EBIU_AMBCTL0) • Asynchronous memory bank control 1 register (EBIU_AMBCTL1) • SDRAM memory global control register (EBIU_SDGCTL) • SDRAM memory bank control register (EBIU_SDBCTL) • SDRAM refresh rate control register (EBIU_SDRRC) • SDRAM control status register (EBIU_SDSTAT) Each of these registers is described in detail in the AMC and SDC sections later in this chapter. Shared Pins Both the AMC and the SDC share the external interface address and data pins, as well as some of the control signals. These pins are shared: • ADDR[19:1], address bus • DATA[15:0], data bus • ABE[1:0]/SDQM[1:0], • CLKOUT, AMC byte enables/SDC data masks system clock for SDC and AMC No other signals are multiplexed between the two controllers. 7-6 ADSP-BF52x Blackfin Processor Hardware Reference S ystem Clock The CLKOUT pin is shared by both the SDC and AMC. Two different registers are used to control this: • EBIU_SDGCTL register, SCTLE bit for SDC clock • EBIU_AMGCTL register, AMCKEN bit for AMC clock If enabling or disabling the system clock, software control for both registers is required. Error Detection The EBIU responds to any bus operation which addresses the range of 0x0000 0000 – 0xEEFF FFFF, even if that bus operation addresses reserved or disabled memory or functions. It responds by completing the bus operation (asserting the appropriate number of acknowledges as specified by the bus master) and by asserting the bus error signal for these error conditions: • Any access to a disabled external memory bank • Any access to reserved SDRAM memory space • Any access to unpopulated SDRAM space If the core requested the faulting bus operation, the bus error response from the EBIU is gated into the hardware error interrupt (IVHW) internal to the core (this interrupt can be masked off in the core). If a DMA master requested the faulting bus operation, then the bus error is captured in that controller and can optionally generate an interrupt to the core. AMC Overview and Features The following sections describe the features of the AMC. ADSP-BF52x Blackfin Processor Hardware Reference 7-7 F eatures The EBIU AMC features include: • 16-bit I/O width • 1.8, 2.5 or 3.3 V I/O supply • Supports up to 4M bytes of SRAM in four external banks • AMC supports 8-bit data masking writes • AMC has control of the EBIU while auto-refresh is performed to SDRAM • AMC supports asynchronous access extension (ARDY pin) • Supports instruction fetch • Allows booting from bank 0 (AMS0) Asynchronous Memory Interface The asynchronous memory interface allows a glueless interface to a variety of memory and peripheral types. These include SRAM, ROM, EPROM, flash memory, and FPGA/ASIC designs. Four asynchronous memory regions are supported. Each has a unique memory pin select associated with it, shown in Table 7-1. Table 7-1. Asynchronous Memory Bank Address Range Memory Bank Select Address Start Address End AMS[3] 0x203F FFFF AMS[2] 0x2020 0000 0x202F FFFF AMS[1] 0x2010 0000 0x201F FFFF AMS[0] 7-8 0x2030 0000 0x2000 0000 0x200F FFFF ADSP-BF52x Blackfin Processor Hardware Reference A synchronous Memory Address Decode The address range allocated to each asynchronous memory bank is fixed at 1M bytes; however, not all of an enabled memory bank need be populated. memory AMC Accesses to unpopulatedbus error or partially populated AMC banks do not result in a and will alias to valid addresses. The asynchronous memory signals are defined in Table 7-2. The timing of these pins is programmable to allow a flexible interface to devices of different speeds. For example interfaces, see Chapter 19, “System Design”. AMC Pin Description The following table describes the signals associated with each interface. Table 7-2. Asynchronous Memory Interface Signals Pad Pin Type 1 Description DATA[15:0] I/O External data bus CLKOUT O Switches at system clock frequency. Connect to the peripheral if required. ADDR[19:1] O External address bus AMS[3:0] O Asynchronous memory bank selects AWE O Asynchronous memory write enable ARE O Asynchronous memory read enable AOE O Asynchronous memory output enable In most cases, the AOE pin should be connected to the OE pin of an external memory-mapped asynchronous device. Please refer to the product data sheet for specific timing information between the AOE and ARE signals to determine which interface signal should be used in your system. ADSP-BF52x Blackfin Processor Hardware Reference 7-9 Table 7-2. Asynchronous Memory Interface Signals (Continued) Pad Pin Type 1 Description ARDY I Asynchronous memory ready response ABE[1:0]/SDQM[1:0] O Byte enables 1 Pin Types: I = Input, O = Output A MC Description of Operation The following sections describe the operation of the AMC. Avoiding Bus Contention Because the three-stated data bus is shared by multiple devices in a system, be careful to avoid contention. Contention causes excessive power dissipation and can lead to device failure. Contention occurs during the time one device is getting off the bus and another is getting on. If the first device is slow to three-state and the second device is quick to drive, the devices contend. There are two cases where contention can occur. The first case is a read followed by a write to the same memory space. In this case, the data bus drivers can potentially contend with those of the memory device addressed by the read. The second case is back-to-back reads from two different memory spaces. In this case, the two memory devices addressed by the two reads could potentially contend at the transition between the two read operations. To avoid contention, program the turnaround time (bank transition time) appropriately in the asynchronous memory bank control registers. This feature allows software to set the number of clock cycles between these types of accesses on a bank-by-bank basis. Minimally, the EBIU provides one cycle for the transition to occur. 7-10 ADSP-BF52x Blackfin Processor Hardware Reference E xternal Access Extension Each bank can be programmed to sample the ARDY input after the read or write access timer has counted down or to ignore this input signal. If enabled and disabled at the sample window, ARDY can be used to extend the access time as required. The polarity of ARDY is programmable on a per-bank basis. Since ARDY is not sampled until an access is in progress to a bank in which the ARDY enable is asserted, ARDY does not need to be driven by default. For more information, see “Adding External Access Extension” on page 7-15. AMC Functional Description The following sections provide a functional description of the AMC. Programmable Timing Characteristics This section describes the programmable timing characteristics for the EBIU. Timing relationships depend on the programming of the AMC, no matter whether the transaction is initiated from the core or from memory DMA, or what the sequence of transactions is (read followed by read, read followed by write, and so on). Asynchronous Reads Figure 7-3 shows an asynchronous read bus cycle with timing programmed as setup = 2 cycles, read access = 2 cycles, hold = 1 cycle, and transition time = 1 cycle. ADSP-BF52x Blackfin Processor Hardware Reference 7-11 Asynchronous read bus cycles proceed as follows. 1. At the start of the setup period, AMS[x] and AOE assert. The address bus becomes valid. The ABE[1:0] signals are low during the read. 2. At the beginning of the read access period and after the 2 setup cycles, ARE asserts. 3. At the beginning of the hold period, read data is sampled on the rising edge of the EBIU clock. The ARE pin deasserts after this rising edge. 7-12 ADSP-BF52x Blackfin Processor Hardware Reference 4. At the end of the hold period, AOE deasserts unless this bus cycle is followed by another asynchronous read to the same memory space. Also, AMS[x] deasserts unless the next cycle is to the same memory bank. 5. Unless another read of the same memory bank is queued internally, the AMC appends the programmed number of memory transition time cycles. SETUP READ ACCESS 2 CYCLES 2 CYCLES HOLD TRANSITION TIME 1 CYCLE 1 CYCLE CLKOUT AMS[3:0] ABE [1:0] ADDR[19:1] DATA[15:0] AOE ARE AWE Figure 7-3. Asynchronous Read Bus Cycles Asynchronous Writes Figure 7-4 shows an asynchronous write bus cycle followed by an asynchronous read cycle to the same bank, with timing programmed as setup = ADSP-BF52x Blackfin Processor Hardware Reference 7-13 2 cycles, write access = 2 cycles, read access = 3 cycles, hold = 1 cycle, and transition time = 1 cycle. DATA LATCHED SETUP 2 CYCLES WRITE ACCESS 2 CYCLES HOLD SETUP READ ACCESS 1 CYCLE 2 CYCLES 3 CYCLES HOLD TRANSITION TIME 1 CYCLE 1 CYCLE CLKOUT AMS[X] ABE [1:0] BE1 ADDR[19:1] A1 DATA[15:0] D1 A2 D2 AOE ARE AWE Figure 7-4. Asynchronous Write and Read Bus Cycles 7-14 ADSP-BF52x Blackfin Processor Hardware Reference Asynchronous write bus cycles proceed as follows. 1. At the start of the setup period, AMS[x], the address bus, data buses, and ABE[1:0] become valid. See “Byte Enables” on page 7-17 for more information. 2. At the beginning of the write access period, AWE asserts. 3. At the beginning of the hold period, AWE deasserts. Asynchronous read bus cycles proceed as follows. 1. At the start of the setup period, AMS[x] and AOE assert. The address bus becomes valid. The ABE[1:0] signals are low during the read. 2. At the beginning of the read access period, ARE asserts. 3. At the beginning of the hold period, read data is sampled on the rising edge of the EBIU clock. The ARE signal deasserts after this rising edge. 4. At the end of the hold period, AOE deasserts unless this bus cycle is followed by another asynchronous read to the same memory space. Also, AMS[x] deasserts unless the next cycle is to the same memory bank. 5. Unless another read of the same memory bank is queued internally, the AMC appends the programmed number of memory transition time cycles. A dding External Access Extension The ARDY pin is used to insert extra wait states. The EBIU starts sampling on the clock cycle before the end of the programmed strobe period. If ARDY is sampled as deasserted, the access period is extended. The ARDY pin is then sampled on each subsequent clock edge. Read data is latched on the clock edge after ARDY is sampled as asserted. The read- or write-enable remains asserted for one clock cycle after ARDY is sampled as ARDY ADSP-BF52x Blackfin Processor Hardware Reference 7-15 asserted. An example of this behavior is shown in Figure 7-5, where setup = 2 cycles, read access = 4 cycles, and hold = 1 cycle. access period must programmed The read make use of the beinput. to a minimum of two cycles to ARDY SETUP 2 CYCLES PROGRAMMED READ ACCESS ACCESS EXTENDED HOLD 3 CYCLES 4 CYCLES 1 CYCLE READY SAMPLED DATA LATCHED CLKOUT AMS[X] ABE [1:0] ADDR[19:1] ADDRESS DATA[15:0] READ D EAD AOE ARE AWE ARDY Figure 7-5. Inserting Wait States Using ARDY 7-16 ADSP-BF52x Blackfin Processor Hardware Reference B yte Enables The AMC provides byte enable pins to allow the processor to perform efficient byte-wide arithmetic and byte-wide processing in external memory. In general, there are two different ways to modify a single byte within the 16-bit interface. First, it can be done by a read/modify/write sequence. However, this is not very efficient because multiple accesses are required (that is, it takes many cycles for reads and writes to external memory). Another option is available where just a specific byte can be modified for a 16-bit devices using the ABE[1:0] pins. See Table 7-3. The ABE[1:0] pins are both low during all asynchronous reads and 16-bit asynchronous writes. When an asynchronous write is made to the upper byte of a 16-bit memory, ABE1 = 0 and ABE0 = 1. When an asynchronous write is made to the lower byte of a 16-bit memory, ABE1 = 1 and ABE0 = 0. Table 7-3. Byte Enables 8-Bit Write Accesses Internal Address Internal Transfer Size IA[0] byte 2 bytes 0 ABE[1] ABE[0] = 1 ABE[1] = 0 = 0 ABE[0] = 0 1 ABE[1] ABE[0] = 0 ABE[1] = 0 = 1 ABE[0] = 0 (invalid) AMC Programming Model The asynchronous memory global control register (EBIU_AMGCTL) configures global aspects of the controller. It contains bank enables and other information as described in this section. This register should not be programmed while the AMC is in use. The EBIU_AMGCTL register should be ADSP-BF52x Blackfin Processor Hardware Reference 7-17 the last control register written to when configuring the processor to access external memory-mapped asynchronous devices. Additional information for the EBIU_AMGCTL register bits includes: • Asynchronous memory clock enable (AMCKEN) For external devices that need a clock, CLKOUT can be enabled by setting the AMCKEN bit in the EBIU_AMGCTL register. In systems that do not use CLKOUT, set the AMCKEN bit to 0. • Asynchronous memory bank enable (AMBEN). If a bus operation accesses a disabled asynchronous memory bank, the EBIU responds by acknowledging the transfer and asserting the error signal on the requesting bus. The error signal propagates back to the requesting bus master. This generates a hardware exception to the core, if it is the requester. For DMA mastered requests, the error is captured in the respective status register. If a bank is not fully populated with memory, then the memory likely aliases into multiple address regions within the bank. This aliasing condition is not detected by the EBIU, and no error response is asserted. • Core/DMA priority (CDPRIO). This bit configures the AMC to control the priority over requests that occur simultaneously to the EBIU from either processor core or the DMA controller. When this bit is set to 0, a request from the core has priority over a request from the DMA controller to the AMC, unless the DMA is urgent. When the CDPRIO bit is set, all requests from the DMA controller, including the memory DMAs, have priority over core accesses. For the purposes of this discussion, core accesses include both data fetches and instruction fetches. bit also applies to the SDC. Theasynchronous memory controller has two asynchronous memThe EBIU CDPRIO ory bank control registers (EBIU_AMBCTL0 and EBIU_AMBCTL1). They 7-18 ADSP-BF52x Blackfin Processor Hardware Reference contain bits for counters for setup, access, and hold time; bits to determine memory type and size; and bits to configure use of ARDY. These registers should not be programmed while the AMC is in use. The timing characteristics of the AMC can be programmed using these four parameters: • Setup: the time between the beginning of a memory cycle (AMS[x] low) and the read-enable assertion (ARE low) or write-enable assertion (AWE low). • Read access: the time between read-enable assertion (ARE low) and deassertion (ARE high). • Write access: the time between write-enable assertion (AWE low) and deassertion (AWE high). • Hold: the time between read-enable deassertion (ARE high) or write-enable deassertion (AWE high) and the end of the memory cycle (AMS[x] high). Each of these parameters can be programmed in terms of EBIU clock cycles. In addition, there are minimum values for these parameters: • Setup 1 cycle • Read access 1 cycle • Write access 1 cycle • Hold 0 cycles AMC Registers The following sections describe the AMC registers. ADSP-BF52x Blackfin Processor Hardware Reference 7-19 E BIU_AMGCTL Register Figure 7-6 shows the asynchronous memory global control register (EBIU_AMGCTL). Asynchronous Memory Global Control Register (EBIU_AMGCTL) 15 14 13 12 11 10 0xFFC0 0A00 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 CDPRIO 0 - Core has priority over DMA for external accesses 1 - DMA has priority over core for external accesses For more information, please see Chapter 2, “Chip Bus Hierarchy”. Reset = 0x00F2 AMCKEN 0 - Disable CLKOUT for asynchronous memory region accesses 1 - Enable CLKOUT for asynchronous memory region accesses AMBEN[2:0] Enable asynchronous memory banks 000 - All banks disabled 001 - Bank0 enabled 010 - Bank0 and Bank1 enabled 011 - Bank0, Bank1, and Bank2 enabled 1xx - All banks (Bank0, Bank1, Bank2, Bank3) enabled Figure 7-6. Asynchronous Memory Global Control Register EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers Figure 7-7 and Figure 7-8 show the asynchronous memory bank control registers (EBIU_AMBCTL0 and EBIU_AMBCTL1). 7-20 ADSP-BF52x Blackfin Processor Hardware Reference Asynchronous Memory Bank Control 0 Register (EBIU_AMBCTL0) 31 30 29 28 0xFFC0 0A04 27 26 25 24 1 1 1 1 1 1 1 1 23 22 1 1 21 20 0 0 19 18 17 16 0 0 1 0 Reset = 0xFFC2 FFC2 B1RDYEN Bank 1 ARDY enable 0 - Ignore ARDY for accesses to this memory bank 1 - After access time countdown, use state of ARDY to determine completion of access B1RDYPOL Bank 1 ARDY polarity 0 - Transaction completes if ARDY sampled low 1 - Transaction completes if ARDY sampled high B1TT[1:0] Bank 1 memory transition time (number of cycles inserted after a read access to this bank, and before a write access to this bank or a read access to another bank) 00 - 4 cycles for bank transition 01 - 1 cycle for bank transition 10 - 2 cycles for bank transition 11 - 3 cycles for bank transition B1WAT[3:0] Bank 1 write access time (number of cycles AWE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B1RAT[3:0] Bank 1 read access time (number of cycles ARE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B1HT[1:0] Bank 1 hold time (number of cycles between AWE or ARE deasserted, and AOE deasserted) 00 - 0 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles B1 ST[1:0] Bank 1 setup time (number of cycles after AOE asserted, before AWE or ARE asserted) 00 - 4 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 1 B0WAT[3:0] Bank 0 write access time (number of cycles AWE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B0RAT[3:0] Bank 0 read access time (number of cycles ARE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B0HT[1:0] Bank 0 hold time (number of cycles between AWE or ARE deasserted, and AOE deasserted) 00 - 0 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles B0 ST[1:0] Bank 0 setup time (number of cycles after AOE asserted, before AWE or ARE asserted) 00 - 4 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles B0RDYEN Bank 0 ARDY enable 0 - Ignore ARDY for accesses to this memory bank 1 - After access time countdown, use state of ARDY to determine completion of access B0RDYPOL Bank 0 ARDY polarity 0 - Transaction completes if ARDY sampled low 1 - Transaction completes if ARDY sampled high B0TT[1:0] Bank 0 memory transition time (number of cycles inserted after a read access to this bank, and before a write access to this bank or a read access to another bank) 00 - 4 cycles for bank transition 01 - 1 cycle for bank transition 10 - 2 cycles for bank transition 11 - 3 cycles for bank transition Figure 7-7. Asynchronous Memory Bank Control 0 Register ADSP-BF52x Blackfin Processor Hardware Reference 7-21 Asynchronous Memory Bank Control 1 Register (EBIU_AMBCTL1) 31 30 29 28 0xFFC0 0A08 27 26 25 24 1 1 1 1 1 1 1 1 23 22 1 1 21 20 0 0 19 18 17 16 0 0 1 0 Reset = 0xFFC2 FFC2 B3RDYEN Bank 3 ARDY enable 0 - Ignore ARDY for accesses to this memory bank 1 - After access time countdown, use state of ARDY to determine completion of access B3RDYPOL Bank 3 ARDY polarity 0 - Transaction completes if ARDY sampled low 1 - Transaction completes if ARDY sampled high B3TT[1:0] Bank 3 memory transition time (number of cycles inserted after a read access to this bank, and before a write access to this bank or a read access to another bank) 00 - 4 cycles for bank transition 01 - 1 cycle for bank transition 10 - 2 cycles for bank transition 11 - 3 cycles for bank transition B3WAT[ 3:0] Bank 3 write access time (number of cycles AWE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B3 RAT[3:0] Bank 3 read access time (number of cycles ARE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B3HT[1:0] Bank 3 hold time (number of cycles between AWE or ARE deasserted, and AOE deasserted) 00 - 0 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles B3ST[1:0] Bank 3 setup time (number of cycles after AOE asserted, before AWE or ARE asserted) 00 - 4 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 B2WAT[3:0] Bank 2 write access time (number of cycles AWE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B2RAT[3:0] Bank 2 read access time (number of cycles ARE is held asserted) 0000 - Not supported 0001 to 1111 - 1 to 15 cycles B2HT[1:0] Bank 2 hold time (number of cycles between AWE or ARE deasserted, and AOE deasserted) 00 - 0 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles B2ST[1:0] Bank 2 setup time (number of cycles after AOE asserted, before AWE or ARE asserted) 00 - 4 cycles 01 - 1 cycle 10 - 2 cycles 11 - 3 cycles 1 B2RDYEN Bank 2 ARDY enable 0 - Ignore ARDY for accesses to this memory bank 1 - After access time countdown, use state of ARDY to determine completion of access B2RDYPOL Bank 2 ARDY polarity 0 - Transaction completes if ARDY sampled low 1 - Transaction completes if ARDY sampled high B2TT[1:0] Bank 2 memory transition time (number of cycles inserted after a read access to this bank, and before a write access to this bank or a read access to another bank) 00 - 4 cycles for bank transition 01 - 1 cycle for bank transition 10 - 2 cycles for bank transition 11 - 3 cycles for bank transition Figure 7-8. Asynchronous Memory Bank Control 1 Register 7-22 ADSP-BF52x Blackfin Processor Hardware Reference A MC Programming Examples Listing 7-1 and Listing 7-2 provide examples for working with the AMC. Listing 7-1. 16-Bit Core Transfers to SRAM .section L1_data_b; .byte2 source[N] = 0x1122, 0x3344, 0x5566, 0x7788; .section SRAM_bank_0; .byte2 dest[N]; .section L1_code; I0.L = lo(source); I0.H = hi(source); I1.L = lo(dest); I1.H = hi(dest); R0.L = w[I0++]; P5=N-1; lsetup(lp, lp) LC0=P5; lp: R0.L = w[I0++] || w[I1++] = R0.L; w[I1++] = R0.L; Listing 7-2. 8-Bit Core Transfers to SRAM Using Byte Mask ABE[1:0] Pins .section L1_data_b; .byte source[N] = 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88; .section SRAM_bank_0; .byte dest[N]; p0.L = lo(source); p0.H = hi(source); p1.L = lo(dest); p1.H = hi(dest); ADSP-BF52x Blackfin Processor Hardware Reference 7-23 p5=N; lsetup(start, end) LC0=P5; start: R0 = b[p0++](z); end: b[p1++] = R0; /* byte data masking */ SDC Overview and Features The SDRAM Controller (SDC) enables the processor to transfer data to and from Synchronous DRAM (SDRAM) with a maximum frequency specified in the product data sheet. The processor supports a glueless interface with one external bank of standard SDRAMs of 64M bit to 512M bit, with configurations x4, x8, and x16, up to a maximum total capacity of 128M bytes of SDRAM. F eatures The EBIU SDC provides a glueless interface with standard SDRAMs. Features include: • I/O width 16-bit, I/O supply 1.8, 2.5 or 3.3 V • Supports up to 128M byte of SDRAM in external bank • Types of 64, 128, 256, and 512M bit with I/O of x4, x8, and x16 • Supports SDRAM page sizes of 512 byte, 1K, 2K, and 4K byte • Supports multibank operation within the SDRAM • Supports mobile SDRAMs • SDC uses no-burst mode (BL = 1) with sequential burst type • SDC supports 8-bit data masking writes • SDC uses open page policy—any open page is closed only if a new access in another page of the same bank occurs 7-24 ADSP-BF52x Blackfin Processor Hardware Reference • Uses a programmable refresh counter to coordinate between varying clock frequencies and the SDRAM’s required refresh rate • Provides multiple timing options to support additional buffers between the processor and SDRAM • Allows independent auto-refresh while the asynchronous memory controller has control of the EBIU port • Supports self-refresh mode for power savings • During hibernate state, self-refresh mode is supported • Supports instruction fetch SDRAM Configurations Supported Table 7-4 shows all possible bank sizes, and SDRAM discrete component configurations that can be gluelessly interfaced to the SDC. The bank width for all cases is 16 bits. Table 7-4. SDRAM Discrete Component Configurations Supported System Size System Size SDRAM Number of (M byte) (M bit) Configuration Chips 16 8M x 16 8M x 8 2 16 8M x 16 8M x 16 1 32 16M x 16 16M x 4 4 32 16M x 16 16M x 8 2 32 16M x 16 16M x 16 1 64 32M x 16 32M x 4 4 64 32M x 16 32M x 8 2 64 32M x 16 32M x 16 1 128 64M x 16 64M x 4 4 ADSP-BF52x Blackfin Processor Hardware Reference 7-25 Table 7-4. SDRAM Discrete Component Configurations Supported (Continued) System Size System Size SDRAM Number of (M byte) (M bit) Configuration Chips 128 64M x 16 64M x 8 2 128 64M x 16 64M x 16 1 S DRAM External Bank Size The total amount of external SDRAM memory addressed by the processor is controlled by the EBSZ bits of the EBIU_SDBCTL register (see Table 7-5). Accesses above the range shown for a specialized EBSZ value results in an internal bus error and the access does not occur. For more information, see “Error Detection” on page 7-7. S DC Address Mapping The address mapping scheme describes how the SDC maps the address into SDRAM. To access SDRAM, the SDC uses the bank interleaving map scheme, which fills each internal SDRAM bank before switching to the next internal bank. Since the SDRAMs have four internal banks, the entire SDRAM address space is therefore divided into four sub-address regions containing the addresses of each internal bank. (See Figure 7-10 on page 7-39.) It starts with address 0x0 for internal bank A and ends with the last valid address (specified with EBSZ and EBCAW parameters) containing the internal bank D. The internal 29-bit non-multiplexed address (See Figure 7-9) is multiplexed into: • Byte data mask (IA[0]) • SDRAM column address 7-26 ADSP-BF52x Blackfin Processor Hardware Reference • SDRAM row address • Internal SDRAM bank address the SDC A good understanding ofoperation address maptoscheme in conjunction with the multibank is required obtain optimized system performance. 31 28 0 Internal 32-bit Address Bank Address Row Address Column Address Byte Mask Figure 7-9. Multiplexed SDRAM Addressing Scheme Table 7-5. External Bank Size Encodings EBSZ Bank Size (M byte) Valid SDRAM Addresses 000 16 0x0000 0000 – 0x00FF FFFF 001 32 0x0000 0000 – 0x01FF FFFF 010 64 0x0000 0000 – 0x03FF FFFF 011 128 0x0000 0000 – 0x07FF FFFF Internal SDRAM Bank Select The internal SDRAM banks are driven by the ADSP-BF52x ADDR[19:18] which are part of the row and column address and connected to the SDRAM BA[1:0]. flip up select connections, if Do not SDRAMboth internal bankthis is done, the systemusing the mobile PASR feature. If will not work properly because the selected internal banks are not refreshed during partial array self-refresh. ADSP-BF52x Blackfin Processor Hardware Reference 7-27 P arallel Connection of SDRAMs To specify an SDRAM system, multiple possibilities are given based on the different architectures. (See Table 7-13 on page 7-63.) For the ADSP-BF52x processors, I/O capabilities of 1 x 16-bit, 2 x 8-bit or 4 x 4-bit are given. The reason to use a system of 4 x 4-bit vs. 2 x 8-bit or 1 x 16-bit is determined by the SDRAM page size. All 3 systems have the same external bank size, but different page sizes. On one hand, the higher the page size, the higher the performance. On the other hand, the higher the page size, the higher the hardware layout requirements. if connecting Evenentire system asSDRAMs in parallel, the SDC always considers the one external SDRAM bank ( pin) because SMS all address and control lines feed the parallel parts. However, access to a single cluster part is achieved using the mask feature (SDQM[1:0] pins). This allows masked 8-bit I/O writes to dedicated chips whereby the other 8-bit I/O is masked at its input buffer of the other chips. See Listing 7-4 on page 7-77. SDC Interface Overview The following sections describe the SDC interface. 7-28 ADSP-BF52x Blackfin Processor Hardware Reference S DC Pin Description The SDRAM interface signals are shown in Table 7-6. Table 7-6. SDRAM Interface Signals Pad Pin Type 1 Description DATA[15:0] I/O External data bus ADDR[19:18], ADDR[16:12], ADDR[10:1] O External address bus Connect to SDRAM address pins. Bank address is output on ADDR[19:18] and should be connected to SDRAM BA[1:0] pins. SRAS O SDRAM row address strobe pin Connect to SDRAM’s RAS pin. SCAS O SDRAM column address strobe pin Connect to SDRAM’s CAS pin. SWE O SDRAM write enable pin Connect to SDRAM’s WE pin. ABE[1:0]/ SDQM[1:0] O SDRAM data mask pins Connect to SDRAM’s DQM pins. SMS O Memory select pin of external memory bank configured for SDRAM Connect to SDRAM’s CS (Chip Select) pin. Active low. SA10 O SDRAM A10 pin SDRAM interface uses this pin to be able to do refreshes while the AMC is using the bus. Connect to SDRAM’s A[10] pin. SCKE O SDRAM clock enable pin Connect to SDRAM’s CKE pin. CLKOUT O SDRAM clock output pin Switches at system clock frequency. Connect to the SDRAM’s CLK pin. 1 Pin Types: I = Input, O = Output ADSP-BF52x Blackfin Processor Hardware Reference 7-29 S DRAM Performance On-page sequential or non-sequential accesses are from internal data memory to SDRAM. Table 7-7 summarizes SDRAM performance for these on-page accesses. Table 7-7. SDRAM Performance Between Internal Data Memory and SDRAM1 Type of access Performance DAG access, write 1 SCLK cycle per 16-bit word DAG access, read 8 SCLK cycles per 16-bit word MemDMA access, write 1 SCLK cycle per 16-bit word MemDMA access, read 1.1 SCLK cycles per 16-bit word 1 Valid for core/system clock > 2:1 On-page sequential instruction fetches from SDRAM are summarized in Table 7-8. Table 7-8. SDRAM Performance For On-Page Instruction Fetches Type of access Performance Ifetch from SDRAM 1.1 SCLK cycles per 16-bit word I/Dcache line fill from SDRAM 1.1 SCLK cycles per 16-bit word Off-page accesses are summarized in Table 7-9. Table 7-9. SDRAM Stall Cycles For Off-Page Accesses Type of access Stall Cycles Write tWR + tRP + tRCD Read tRP + tRCD + CL 7-30 ADSP-BF52x Blackfin Processor Hardware Reference S DC Description of Operation The following sections describe the operation of the SDC. Definition of SDRAM Architecture Terms The following are definitions of SDRAM architecture terms used in the remainder of this chapter. Refresh Since the information is stored in a low-capacitance cell that suffers from leakage effects, the SDRAM must be refreshed periodically. Row Activation SDRAM accesses are multiplexed, which means any first access will open a row/page before the column access is performed. It stores the row in a “row cache” called row activation. Column Read/Write The row’s columns represent a page, which can be accessed with successive read or write commands without needing to activate another row. This is called column access and performs transfers from the “row cache.” Row Precharge If the next access is in a different row, the current row is closed before another is opened. The current “row cache” is written back to the row. This is called row precharge. ADSP-BF52x Blackfin Processor Hardware Reference 7-31 I nternal Bank There are up to 4 internal memory banks on a given SDRAM. Each of these banks can be accessed with the bank select lines BA[1:0]. The bank address can be thought of as part of the row address. External Bank This is the address region where the SDC address the SDRAM. internal to Do not confuse the internal banks, which areins with the the SDRAM and are selected with the p external BA[1:0] bank that is enabled by the CS pin. Memory Size Since the 2-D memory is based on rows and columns, the size is: mem size = (# rows) x (# columns) x (# internal banks) x I/O (Mbit) Burst Length The burst length determines the number of words that the SDRAM device stores or delivers after detecting a single write or read command followed by a NOP (no operation) command, respectively (Number of NOPs = burst length - 1). Burst lengths of full page, 8, 4, 2, and 1 (no burst) are available. The burst length is selected by writing the BL bits in the SDRAM mode register during the SDRAM powerup sequence. Burst Type The burst type determines the address order in which the SDRAM delivers burst data. The burst type is selected by writing the BT bits in the SDRAM mode register during the SDRAM powerup sequence. 7-32 ADSP-BF52x Blackfin Processor Hardware Reference C AS Latency The CAS latency, or read latency, specifies the time between latching a read address and driving the data off chip. This specification is normalized to the system clock and varies from 2 to 3 cycles based on the speed. The CAS latency is selected by writing the CL bits in the SDRAM mode register during the SDRAM powerup sequence. Data I/O Mask Function SDRAMs allow a data byte-masking capability on writes. The DQM[1:0] mask pins are used to block the data input buffer of the SDRAM during write operations. SDRAM Commands SDRAM commands are not based on typical read or write strobes. The pulsed CS, RAS, CAS, and WE lines determine the command on the rising clock edge by a truth table. Mode Register Set (MRS) command SDRAM devices contain an internal extended configuration register which allows specification of the mobile SDRAM device’s functionality. Extended Mode Register Set (EMRS) command Mobile SDRAM devices contain an internal extended configuration register which allows specification of the mobile SDRAM device’s functionality. Bank Activate command The bank activate command causes the SDRAM to open an internal bank (specified by the bank address) in a row (specified by the row address). When the bank activate command is issued, it opens a new row address in ADSP-BF52x Blackfin Processor Hardware Reference 7-33 the dedicated bank. The memory in the open internal bank and row is referred to as the open page. The bank activate command must be applied before a read or write command. Read/Write command For the read command, the SDRAM latches the column address. The start address is set according to the column address. For the write command, SDRAM latches the column address. Data is also asserted in the same cycle. The start address is set according to the column address. Precharge/Precharge All Command The precharge command closes a specific active page in an internal bank and the precharge all command closes all 4 active pages in all 4 banks. Auto-refresh command When the SDC refresh counter times out, the SDC precharges all four banks of SDRAM and then issues an auto-refresh command to them. This causes the SDRAM to generate an internal auto-refresh cycle. When the internal refresh completes, all four internal SDRAM banks are precharged. Enter Self-Refresh Mode When the SDRAM enters self-refresh mode, the SDRAM’s internal timer initiates refresh cycles periodically, without external control input. Exit Self-Refresh Mode When the SDRAM exits self-refresh mode, the SDRAM’s internal timer stops refresh cycles and relinquishes control to external SDC. 7-34 ADSP-BF52x Blackfin Processor Hardware Reference S DC Timing Specifications The following SDRAM timing specifications are used by the SDC and SDRAM. To program the SDRAM interface, see the SDRAM specific datasheet information timing parameter Any absolute allows the SDC tomust betonormalized to the system clock, which adapt the timing parameter of the device. t MRD This is the required delay between issuing a mode register set and an activate command during powerup. Dependency: system clock frequency SDC setting: 3 system clock cycles SDC usage: MRS command t RAS This is the required delay between issuing a bank A activate command and issuing a bank A precharge command. Dependency: system clock frequency SDC setting: 1–15 normalized system clock cycles SDC usage: single column read/write, auto-refresh, self-refresh command t CL The CAS latency, or read latency, is the delay between when the SDRAM detects the read command and when it provides the data off-chip. This specification does not apply to writes. ADSP-BF52x Blackfin Processor Hardware Reference 7-35 Dependency: system clock frequency and speed grade SDC setting: 2–3 normalized system clock cycles SDC usage: first read command t RCD This is the required delay between a bank A activate command and the first bank A read or write command. Dependency: system clock frequency SDC setting: 1–7 normalized system clock cycles SDC usage: first read/write command t RRD This is the required delay between a bank A activate command and a bank B activate command. This specification is used for multibank operation. Dependency: system clock frequency SDC setting: tRCD + 1 normalized system clock cycles SDC usage: multiple bank activation t WR This is the required delay between a bank A write command and a bank A precharge command. This specification does not apply to reads. Dependency: system clock frequency SDC setting: 1–3 normalized system clock cycles SDC usage: during off-page write command t RP This is the required delay between a bank A precharge command and a bank A activation command. 7-36 ADSP-BF52x Blackfin Processor Hardware Reference Dependency: system clock frequency SDC setting: 1–7 normalized system clock cycles SDC usage: off-page read/write, auto-refresh, self-refresh command t RC This is the required delay between issuing successive bank activate commands. Dependency: system clock frequency SDC setting: user must ensure that tRP + tRAS max(tRC, tRFC, tXSR) SDC usage: single column read/write command t RFC This is the required delay between issuing successive auto-refresh commands (all banks). Dependency: system clock frequency SDC setting: user must ensure that tRP + tRAS max(tRC, tRFC, tXSR) SDC usage: auto-refresh, exit self-refresh command t XSR This is the required delay between exiting self-refresh mode and the auto-refresh command. Dependency: system clock frequency SDC setting: user must ensure that tRP + tRAS max(tRC, tRFC, tXSR) SDC usage: exit self-refresh command t REF This is the row refresh period, and typically takes 64 ms. ADSP-BF52x Blackfin Processor Hardware Reference 7-37 Dependency: system clock frequency SDC setting: none SDC usage: auto-refresh command t REFI This is the row refresh interval and typically takes 15.6 s for < 8k rows and 7.8 s for 8k rows. This specification is available by dividing tREF by the number of rows. This number is used by the SDC refresh counter. Dependency: system clock frequency SDC setting: tREFI normalized system clock cycles (RDIV register) SDC usage: auto-refresh command making In typical applications the t sequential (not random) accesses to timing parameter is less critical the SDRAM memory, RAS than tRP. Be aware that whenever the sum of tRP + tRAS is violating one of the other timing specifications, the tRAS parameter should be increased. SDC Functional Description The functional description of the SDC is provided in the following sections. SDC Operation The AMC normally generates an external memory address, which then asserts the corresponding CS select, along with RD and WR strobes. However these control signals are not used by the SDC. The internal strobes are used to generate pulsed commands (SMS, SCKE, SRAS, SCAS, SWE) within a truth table (see Table 7-11 on page 7-46). The memory access to SDRAM is based by mapping ADDR[28:0] causing an internal memory select to SDRAM space (see Figure 7-10). 7-38 ADSP-BF52x Blackfin Processor Hardware Reference The configuration is programmed in the SDBCTL register. The SDRAM controller can hold off the processor core or DMA controller with an internally connected acknowledge signal, as controlled by refresh, or page miss latency overhead. A programmable refresh counter is provided which generates background auto-refresh cycles at the required refresh rate based on the clock frequency used. The refresh counter period is specified with the RDIV field in the SDRAM refresh rate control register. To allow auto-refresh commands to execute in parallel with any AMC access, a separate A10 pin (SA10) is provided. ADSP-BF527 SDRAM COMMAND LOGIC CLKOUT CLK INT RD SCKE CKE INT WR SRAS SCAS RAS SWE WE SMS CS A10 INT RESET INT ACK BUSY SMS CORE DMA A[28:0] ADDRESS BUFFER REFRESH COUNTER SA10 CAS ADDRESS MULTIPLEXER A[11] A[0]/SDQM[1:0] DQMx A[18] BA0 A[19] BA1 A[1:10], A[12:13] DATA LATCH/ DRIVE D[15:0] A[0:9], A[11:12] DQ15:0 Figure 7-10. Simplified SDC Architecture ADSP-BF52x Blackfin Processor Hardware Reference 7-39 The internal 32-bit non-multiplexed address is multiplexed into: • Data mask for bytes • SDRAM column address • SDRAM row address • Internal SDRAM bank address Bit A[0] is used for 8-bit wide SDRAMs to generate the data masks. The next lowest bits are mapped into the column address, next bits are mapped into the row address, and the final two bits are mapped into the internal bank address. This mapping is based on the EBCAW and EBSZ values programmed into the SDRAM memory bank control register. The SDC uses no burst mode ( BL = 1) for read and write operations. This requires the SDC to post every read or write address on the bus as for non-sequential reads or writes, but does not cause any performance degradation. For read commands, there is a latency from the start of the read command to the availability of data from the SDRAM, equal to the CAS latency. This latency is always present for any single read transfer. Subsequent reads do not have latency. Whenever a page miss to the same bank occurs, the SDC executes a precharge command followed by a bank activate command before executing the read or write command. If there is a page hit, the read or write command can be given immediately without requiring the precharge command. 7-40 ADSP-BF52x Blackfin Processor Hardware Reference S DC Address Muxing Table 7-10 shows the connection of the address pins with the SDRAM device pins. Table 7-10. SDRAM Address Connections for 16-bit Banks External Address Pin SDRAM Address Pin ADDR[19] BA[1] ADDR[18] BA[0] ADDR[16] A[15] ADDR[15] A[14] ADDR[14] A[13] ADDR[13] A[12] ADDR[12] A[11] ADDR[11] Not used SA[10] A[10] ADDR[10] A[9] ADDR[9] A[8] ADDR[8] A[7] ADDR[7] A[6] ADDR[6] A[5] ADDR[5] A[4] ADDR[4] A[3] ADDR[3] A[2] ADDR[2] A[1] ADDR[1] A[0] ADSP-BF52x Blackfin Processor Hardware Reference 7-41 M ultibank Operation Since every SDRAM chip contains 4 independent internal banks (A-D), the SDC is capable of supporting multibank operation thus taking advantage of the architecture. Any first access to SDRAM bank (A) will force an activate command before a read or write command. However, if any new access falls into the address space of the other banks (B, C, D) the SDC leaves bank (A) open and activates any of the other banks (B, C, D). Bank (A) to bank (B) active time is controlled by tRRD = tRCD + 1. This scenario is repeated until all 4 banks (A-D) are opened and results in an effective page size up to 4 pages because no latency causes switching between these open pages (compared to 1 page in only one bank at the time). Any access to any closed page in any opened bank (A-D) forces a precharge command only to that bank. If, for example, 2 MemDMA channels are pointing to the same internal SDRAM bank, this always forces precharge and activation cycles to switch between the different pages. However, if the 2 MemDMA 7-42 ADSP-BF52x Blackfin Processor Hardware Reference channels are pointing to different internal SDRAM banks, it does not cause additional overhead. See Figure 7-11. of multibank operation precharge and activa The benefitby mapping opcode/data reduces different internal tion cycles among SDRAM banks driven by the A[19:18] pins. MULTIBANK OPERATION SINGLE BANK OPERATION ACCESS TO PAGE X ACCESS TO PAGE X ACCESS TO PAGE Y BANK A BANK A ACCESS TO PAGE Y BANK B BANK B ACCESS TO PAGE X BANK C BANK C BANK D ACCESS TO PAGE Y BANK D Figure 7-11. SDRAM Bank Operation Types Core and DMA Arbitration The CDPRIO bit configures the SDC to control the priority over requests that occur simultaneously to the EBIU from either the processor core or the DMA controller. When this bit is set to 0, a request from the core has priority over a request from the DMA controller to the SDC, unless the DMA is urgent. When it is set to 1, all requests from the DMA controller, including the memory DMAs, have priority over core accesses. For the purposes of this discussion, core accesses include both data fetches and instruction fetches. For additional information see “Using the CDPRIO Bit to Change Priorities” on page 2-13. ADSP-BF52x Blackfin Processor Hardware Reference 7-43 C hanging System Clock During Runtime All timing specifications are normalized to the system clock. Since most of them are minimum specifications, except tREF, which is a maximum specification, a variation of system clock will on one hand violate a specific specification and on the other hand cause a performance degradation for the other specifications. The reduction of system clock will violate the minimum specifications, while increasing system clock will violate the maximum tREF specification. Therefore, careful software control is required to adapt these changes. most applications, the writing Forthe mode register needs SDRAM powerup sequence and powof to be done only once. Once the erup sequence has completed, the PSSE bit should not be set again unless a change to the mode register is desired. The recommended procedure for changing the PLL VCO frequency is: 1. Issue an SSYNC instruction to ensure all pending memory operations have completed. 2. Set the SDRAM to self-refresh mode by writing a 1 to the SRFS bit of EBIU_SDGCTL. 3. Execute the desired PLL programming sequence. (For details, refer to Chapter 18, “Dynamic Power Management”.) 4. After the wakeup occurs that signifies the PLL has settled to the new VCO frequency, reprogram the SDRAM registers (EBIU_SDRRC, EBIU_SDGCTL) with values appropriate to the new SCLK frequency, and assure that the PSSE bit is set. 5. Bring the SDRAM out of self-refresh mode by clearing the SRFS bit of EBIU_SDGCTL. The SDRAM will stay within the self-refresh until the first access. 7-44 ADSP-BF52x Blackfin Processor Hardware Reference Changing the SCLK frequency using the SSEL bits in PLL_DIV, as opposed to actually changing the VCO frequency, should be done using these steps: 1. Issue an SSYNC instruction to ensure all pending memory operations have completed. 2. Set the SDRAM to self-refresh mode by writing a 1 to the SRFS bit of EBIU_SDGCTL. 3. Execute the desired write to the SSEL bits. 4. Reprogram the SDRAM registers with values appropriate to the new SCLK frequency, and assure that the PSSE bit is set. 5. Bring the SDRAM out of self-refresh mode by clearing the SRFS bit of EBIU_SDGCTL. Changing Power Management During Runtime Deep Sleep Mode During deep sleep mode, the core and system clock will halt. Therefore, a careful software control is required to enter SDRAM in self-refresh before the device enters deep sleep mode. Hibernate State In the hibernate state the core voltage is 0 (core reset), but the I/O voltage can still be applied. In order to save the SDRAM volatile data, the ADSP-BF52x processor supports driving the SCKE signal low during core reset. Setting the SCKELOW bit of VR_CTL keeps the SCKE signal low. This ensures that the self-refresh mode is not exited during the reset sequence initiated by a hibernate wake-up event. Normally, the SCKE pin is toggled high during reset to comply with PC-133 specifications. For details about the SCKELOW bit, refer to Chapter 18, “Dynamic Power Management”. ADSP-BF52x Blackfin Processor Hardware Reference 7-45 S DC Commands This section provides a description of each of the commands that the SDC uses to manage the SDRAM interface. These commands are initiated automatically upon a memory read or memory write. A summary of the various commands used by the on-chip controller for the SDRAM interface is as follows. • MODE REGISTER SET • EXTENDED MODE REGISTER SET • BANK ACTIVATION • READ • SINGLE PRECHARGE • PRECHARGE ALL • AUTO-REFRESH • SELF-REFRESH ENTRY • NOP and WRITE and SELF-REFRESH EXIT Table 7-11 shows the SDRAM pin state during SDC commands. Table 7-11. Pin State During SDC Commands Command SCKE SCKE SMS (n - 1) (n) SRAS SCAS SWE SA10 (E)/Mode register set High High Low Low Low Low Op-code Op-code Activate High High Low Low High High Valid address bit Valid Read High High Low High Low High Low (CMD) Valid 7-46 Addresses ADSP-BF52x Blackfin Processor Hardware Reference Table 7-11. Pin State During SDC Commands (Continued) Command SCKE SCKE SMS (n - 1) (n) SRAS SCAS SWE SA10 Addresses Single precharge High High Low Low High Low Low Valid Precharge all High High Low Low High Low High Don’t care Write High High Low High Low Low Low (CMD) Valid Auto-refresh High High Low Low Low High Don’t care Don’t care Self-refresh entry High Low Low Low Low High Don’t care Don’t care Self-refresh Low Low Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Self-refresh exit Low High High Don’t care Don’t care Don’t care Don’t care Don’t care NOP High High Low High High Don’t care Don’t care Inhibit High High High Don’t care Don’t Care Don’t care Don’t care Don’t care High M ode Register Set Command The MODE REGISTER SET (MRS) command initializes SDRAM operation parameters. This command is a part of the SDRAM power-up sequence. The MRS command uses the address bus of the SDRAM as data input. The power-up sequence is initiated by setting the PSSE bit in the SDRAM memory global control register (EBIU_SDGCTL) and then writing or reading from any enabled address within the SDRAM address space to trigger the power-up sequence. The exact order of the power-up sequence is determined by the PSM bit of the EBIU_SDGCTL register. ADSP-BF52x Blackfin Processor Hardware Reference 7-47 The MRS command initializes these parameters: • Burst length = 1, bits A[2–0], always 0 • Burst type = sequential, bit A[3], always 0 • CAS latency, bits A[6–4], programmable in the EBIU_SDGCTL register • Bits A[12–7], always 0 After power-up and before executing a read or write to the SDRAM memory space, the application must trigger the SDC to write the SDRAM mode register. The write of the SDRAM mode register is triggered by setting the PSSE bit in the SDRAM memory global control register (EBIU_SDGCTL) and then issuing a read or write transfer to the SDRAM address space. The initial read or write triggers the SDRAM power-up sequence to be run, which programs the SDRAM mode register with burst length, burst type, and CAS latency from the EBIU_SDGCTL register and optionally the content to the extended mode register. This initial read or write to SDRAM takes many cycles to complete. While executing an MRS command, the unused address pins are cleared. During the two clock cycles following the MRS command (tMRD), the SDC issues only NOP commands. Extended Mode Register Set Command (Mobile SDRAM) The extended mode register is a subset of the mode register. The EBIU enables programming of the extended mode register during power-up via the EMREN bit in the EBIU_SDGCTL register. 7-48 ADSP-BF52x Blackfin Processor Hardware Reference The extended mode register is initialized with these parameters: • Partial array self-refresh, bits A[2–0], bit A[2] always 0, bits A[1–0] programmable in EBIU_SDGCTL • Temperature compensated self-refresh, bits A[4–3], bit A[3] always 1, bit A[4] programmable in EBIU_SDGCTL • Drive strength control, bits A[6–5], always 0 • Bits A[12–7], always 0, and bit A[13] always 1 the extended Not programmingsettings for the mode register upon initialization results in default low-power features. The extended mode defaults with the temperature sensor enabled, full drive strength, and full array refresh. Bank Activation Command The BANK ACTIVATION command is required for first access to any internal bank in SDRAM. Any subsequent access to the same internal bank but different row will be preceded by a precharge and activation command to that bank. However, if an access to another bank occurs, the SDC leaves the current page open and issues a BANK ACTIVATION command before executing the read or write command to that bank. With this method, called multibank operation, one page per bank can be open at a time, which results in a maximum of four pages. Read/Write Command A read/write command is executed if the next read/write access is in the present active page. During the read command, the SDRAM latches the column address. The delay between activate and read commands is determined by the tRCD parameter. Data is available from the SDRAM after the CAS latency has been met. ADSP-BF52x Blackfin Processor Hardware Reference 7-49 In the write command, the SDRAM latches the column address. The write data is also valid in the same cycle. The delay between activate and write commands is determined by the tRCD parameter. The SDC does not use the auto-precharge function of SDRAMs, which is enabled by asserting SA10 high during a read or write command. Write Command With Data Mask During partial writes to SDRAM, the SDQM[1:0] pins are used to mask writes to bytes that are not accessed. Table 7-12 shows the SDQM[1:0] encodings based on the internal transfer address bit IA[0] and the transfer size. During read transfers to SDRAM banks, reads are always done of all bytes in the bank regardless of the transfer size. This means for 16-bit SDRAM banks, SDQM[1:0] are all 0s. Table 7-12. SDQM[1:0] Encodings During Writes Internal Address Internal Transfer Size IA[0] byte 2 bytes 0 SDQM[1] = 1 SDQM[1] = 0 SDQM[0] = 0 SDQM[1] = 0 1 SDQM[0] = 0 SDQM[1] = 0 SDQM[0] = 1 SDQM[1] = 0 For 16-bito SDRAMs, connect t . SDQM[1] 7-50 SDQM[0] to DQML, and connect DQMH ADSP-BF52x Blackfin Processor Hardware Reference S ingle Precharge Command For a page miss during reads or writes in a specific internal SDRAM bank, the SDC uses the SINGLE PRECHARGE command to that bank. the auto-precharge write command The SDC does not useenabled by asserting read origh during a read of SDRAMs, which is h SA10 or write command. Precharge All Command The PRECHARGE ALL command is used to precharge all internal banks at the same time before executing an auto-refresh. All open banks will be automatically closed. This is possible since the SDC uses a separate SA10 pin which is asserted high during this command. This command precedes the AUTO-REFRESH command. Auto-Refresh Command The SDRAM internally increments the refresh address counter and causes an auto-refresh to occur internally for that address when the AUTO-REFRESH command is given. The SDC generates an AUTO-REFRESH command after the SDC refresh counter times out. The RDIV value in the SDRAM refresh rate control register must be set so that all addresses are refreshed within the tREF period specified in the SDRAM timing specifications. This command is issued to the external bank whether or not it is enabled (EBE in the SDRAM memory global control register). Before executing the AUTO-REFRESH command, the SDC executes a PRECHARGE ALL command to the external bank. The next activate command is not given until the tRFC specification (tRFC = tRAS + tRP) is met. Auto-refresh commands are also issued by the SDC as part of the powerup sequence and after exiting self-refresh mode. ADSP-BF52x Blackfin Processor Hardware Reference 7-51 S elf-Refresh Mode The self-refresh mode is controlled by the SELF-REFRESH ENTRY and SELF-REFRESH EXIT commands. The SDC must issue a series of commands, including the SELF-REFRESH ENTRY command, to put the SDRAM into this low power operation, and it must issue another series of commands, including the SELF-REFRESH EXIT command, to re-access the SDRAM. Self-Refresh Entry Command The SELF-REFRESH ENTRY command causes refresh operations to be performed internally by the SDRAM without any external control. This means that the SDC does not generate any auto-refresh commands while the SDRAM is in self-refresh mode. Before executing the SELF-REFRESH ENTRY command, all internal banks are precharged. The SELF-REFRESH ENTRY command is started by setting the SRFS bit of the SDRAM memory global control register (EBIU_SDGCTL). The SDC now drives SCKE low. p keeps during all other Only the pins areinallowedcontroldisabled.self-refresh,the SDC still SDRAM to be However SCKE drives the SCLK during self-refresh mode. Software may disable the clock by clearing the SCTLE bit in EBIU_SDGCTL. Self-Refresh Exit Command Leaving self-refresh mode is performed with the SELF-REFRESH EXIT command, whereby the SDC asserts SCKE. Any internal core/DMA access causes the SDC to perform an SELF-REFRESH EXIT command. The SDC waits to meet the tXSR specification (tXSR = tRAS + tRP) and then issues an AUTO-REFRESH command. After the AUTO-REFRESH command, the SDC waits for the tRFC specification (tRFC = tRAS + tRP) to be met before executing the activate command for the transfer that caused the SDRAM to exit self-refresh mode. The latency from when a transfer is received by the SDC while in self-refresh mode, until the activate command occurs for that transfer, is: 7-52 ADSP-BF52x Blackfin Processor Hardware Reference Time to exit self-refresh: 2 x (tRAS + tRP) minimum a subsequent The the time betweencommand is at least t and SELF-REFRESH ENTRY cycles. If a self-refresh entry command is issued during any MDMA transfer, the SDC satisfies this core request with the minimum self-refresh period (tRAS). SELF-REFRESH EXIT RAS The application software should ensure that all applicable clock timing specifications are met before the transfer to SDRAM address space which causes the controller to exit self-refresh mode. If a transfer occurs to SDRAM address space when the SCTLE bit is cleared, an internal bus error is generated, and the access does not occur externally, leaving the SDRAM in self-refresh mode. For more information, see “Error Detection” on page 7-7. No Operation Command The no operation (NOP) command to the SDRAM has no effect on operations currently in progress. The command inhibit command is the same as a NOP command; however, the SDRAM is not chip-selected. When the SDC is actively accessing the SDRAM to insert additional wait states, the NOP command is given. When the SDC is not accessing the SDRAM, the command inhibit command is given (SMS = 1). ADSP-BF52x Blackfin Processor Hardware Reference 7-53 S DC SA10 Pin The SDRAM’s A[10] pin follows the truth table below: • During the precharge command, it is used to indicate a precharge all • During a bank activate command, it outputs the row address bit • During read and write commands, it is used to disable auto-precharge Therefore, the SDC uses a separate SA10 pin with these rules. Connect the pin with in. Because ADSP-BF52x processor usesthe SDRAM itpstarts with the. byte addressing, SA10 A[10] A[1] The A[11] pin is left unconnected for SDRAM accesses and is replaced by the SA10 pin. SDC Programming Model The following sections provide programming model information for the SDC. SDC Configuration After a processor’s hardware or software reset, the SDC clocks are enabled; however, the SDC must be configured and initialized. Before programming the SDC and executing the powerup sequence, these steps are required: 1. Ensure the clock to the SDRAM is stable after the power has stabilized for the proper amount of time (typically 100 ms). 2. Write to the SDRAM refresh rate control register (EBIU_SDRRC). 7-54 ADSP-BF52x Blackfin Processor Hardware Reference 3. Write to the SDRAM memory bank control register (EBIU_SDBCTL). 4. Write to the SDRAM memory global control register (EBIU_SDGCTL). 5. Perform SDRAM access. The SDRS bit of the SDRAM control status register can be checked to determine the current state of the SDC. If this bit is set, the SDRAM powerup sequence has not been initiated. The RDIV field of the EBIU_SDRRC register should be written to set the SDRAM refresh rate. The EBIU_SDBCTL register should be written to describe the sizes /configuration of SDRAM memory (EBSZ and EBCAW) and to enable the external bank (EBE). Prior to the start of the SDRAM powerup sequence, any access to SDRAM address space, regardless of the state of the EBE bit, generates an internal bus error, and the access does not occur externally. For more information, see “Error Detection” on page 7-7. The powerup latency can be estimated as: tRP + (8 x tRFC) + tMRD + tRCD If the external bank remains disabled after the SDRAM powerup sequence has completed, any transfers to it will result in a hardware error interrupt and the SDRAM transfer will not occur. ADSP-BF52x Blackfin Processor Hardware Reference 7-55 The EBIU_SDGCTL register is written: • To set the SDRAM cycle timing options (CL, TRAS, TRP, TRCD, TWR, EBUFE) • To enable the SDRAM clock (SCTLE) • To select and enable the start of the SDRAM powerup sequence (PSM, PSSE) If SCTLE is disabled, any access to SDRAM address space generates an internal bus error and the access does not occur externally. For more information, see “Error Detection” on page 7-7. Once the PSSE bit in the EBIU_SDGCTL register is set, and a transfer occurs to enabled SDRAM address space, the SDC initiates the SDRAM powerup sequence. The exact sequence is determined by the PSM bit in the EBIU_SDGCTL register. The transfer used to trigger the SDRAM powerup sequence can be either a read or a write. This transfer occurs when the SDRAM powerup sequence has completed. This initial transfer takes many cycles to complete since the SDRAM powerup sequence must take place. Example SDRAM System Block Diagrams Figure 7-12 shows a block diagram of an SDRAM interface. In this example, the SDC is connected to 2 x (8M x 8) = 8M x 16 to form one external 7-56 ADSP-BF52x Blackfin Processor Hardware Reference 128M bit / 16M byte bank of memory. The system’s page size is 1024 bytes. The same address and control bus feeds both SDRAM devices. SDRAM 1 8Mx8 BLACKFIN SMS SRAS SCAS SWE A[18] A[19] SA10 ADDR[12,10:1] CLKOUT SCKE SDQM[0] SDQM[1] CS RAS CAS WE BA0 DQ[7:0] BA1 A[10] A[11,9:0] CLK CKE DQM DATA[7:0] DATA[15:0] DATA[15:8] SDRAM 2 8Mx8 CS RAS CAS WE BA0 DQ[7:0] BA1 A[10] A[11,9:0] CLK CKE DQM Figure 7-12. SDRAM System Block Diagram, Example 1 Figure 7-13 shows a block diagram of an SDRAM interface. In this example, the SDC is connected to 4 x (16M x 4) = 16M x 16 to form one external 256M bit / 32M byte bank of memory. The system’s page size is ADSP-BF52x Blackfin Processor Hardware Reference 7-57 2048 bytes. The same address and control bus pass a registered buffer before they feed all 4 SDRAM devices. ADSP-BF527 CS RAS CAS WE SMS SRAS SCAS SWE A[18] A[19] SA10 ADDR[12,10:1] SCKE CLKOUT REGISTERED BUFFER SDRAM 1 16Mx4 BA0 BA1 A[10] A[11,9:0] CLK CKE DQ[3:0] CS RAS CAS WE D[3:0] DQM SDRAM 2 16Mx4 BA0 BA1 A[10] A[11,9:0] CLK CKE DQ[3:0] D[7:4] DQM CLKOUT DATA[15:0] SDQM[0] SDQM[1] CS RAS CAS WE SDRAM 3 16Mx4 BA0 BA1 A[10] A[11,9:0] CLK CKE DQ[3:0] CS RAS CAS WE D[11:8] DQM SDRAM 4 16Mx4 BA0 BA1 A[10] A[11,9:0] CLK CKE DQ[3:0] DQM Figure 7-13. SDRAM System Block Diagram, Example 2 Furthermore, the EBUFE bit should be used to enable or disable external buffer timing. When buffered SDRAM modules or discrete register-buffers are used to drive the SDRAM control inputs, EBUFE should be set. Using this setting adds a cycle of data buffering to read and write accesses. 7-58 ADSP-BF52x Blackfin Processor Hardware Reference D[15:12] S DC Register Definitions The following sections describe the SDC registers. EBIU_SDRRC Register The SDRAM refresh rate control register (EBIU_SDRRC, shown in Figure 7-14) provides a flexible mechanism for specifying the auto-refresh timing. Since the clock supplied to the SDRAM can vary, the SDC provides a programmable refresh counter, which has a period based on the value programmed into the RDIV field of this register. This counter coordinates the supplied clock rate with the SDRAM device’s required refresh rate. The desired delay (in number of SDRAM clock cycles) between consecutive refresh counter time-outs must be written to the RDIV field. A refresh counter time-out triggers an auto-refresh command to all external SDRAM devices. Write the RDIV value to the EBIU_SDRRC register before the SDRAM powerup sequence is triggered. Change this value only when the SDC is idle. SDRAM Refresh Rate Control Register (EBIU_SDRRC) 15 14 13 12 11 10 0xFFC0 0A18 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 Reset = 0x081A RDIV[11:0] Figure 7-14. SDRAM Refresh Rate Control Register To calculate the value that should be written to the EBIU_SDRRC register, use the following equation: RDIV = ((fSCLK tREF) / NRA) – (tRAS + tRP) = (fSCLK tREFI) - (tRAS + tRP) ADSP-BF52x Blackfin Processor Hardware Reference 7-59 Where: • fSCLK = SDRAM clock frequency (system clock frequency) • tREF = SDRAM row refresh period • tREFI = SDRAM row refresh interval • NRA = Number of row addresses in SDRAM (refresh cycles to refresh whole SDRAM) • tRAS = Active to precharge time (TRAS in the SDRAM memory global control register) in number of clock cycles • tRP = RAS to precharge time (TRP in the SDRAM memory global control register) in number of clock cycles This equation calculates the number of clock cycles between required refreshes and subtracts the required delay between bank activate commands to the same internal bank (tRC = tRAS + tRP). The tRC value is subtracted, so that in the case where a refresh time-out occurs while an SDRAM cycle is active, the SDRAM refresh rate specification is guaranteed to be met. The result from the equation should always be rounded down to an integer. Below is an example of the calculation of RDIV for a typical SDRAM in a system with a 133 MHz clock: • fSCLK = 133 MHz • tREF = 64 ms • NRA = 8192 row addresses • tRAS = 6 • tRP = 3 7-60 ADSP-BF52x Blackfin Processor Hardware Reference The equation for RDIV yields: RDIV = ( (133 x 106 x 64 x 10-3) / 8192) – (6 + 3) = 1030 clock cycles This means RDIV is 0x406 and the EBIU_SDRRC register should be written with 0x406. be programmed the SDRAM trollermisustenabled. When to a= nonzero valueofifthe SDRAM con0, operation RDIV RDIV controller is not supported and can produce undesirable behavior. Values for RDIV can range from 0x001 to 0xFFF. EBIU_SDBCTL Register The SDRAM memory bank control register (EBIU_SDBCTL), shown in Figure 7-15, includes external bank-specific programmable parameters. It allows software to control some parameters of the SDRAM. The external bank can be configured for a different size of SDRAM. It uses the access timing parameters defined in the SDRAM memory global control register (EBIU_SDGCTL). The EBIU_SDBCTL register should be programmed before powerup and should be changed only when the SDC is idle. • External bank enable (EBE) The EBE bit is used to enable or disable the external SDRAM bank. If the SDRAM is disabled, any access to the SDRAM address space generates an internal bus error, and the access does not occur externally. For more information, see “Error Detection” on page 7-7. • External bank size (EBSZ) The EBSZ encoding stores the configuration information for the SDRAM bank interface. The EBIU supports 64M bit, 128M bit, 256M bit, and 512M bit SDRAM devices with x4, x8, and x16 ADSP-BF52x Blackfin Processor Hardware Reference 7-61 configurations. Table 7-13 maps SDRAM density and I/O width. See “SDRAM External Bank Size” on page 7-26 for more information regarding the decoding of bank start addresses. • External bank column address width (EBCAW) The SDC determines the internal SDRAM page size from the parameters. Page sizes of 512 B, 1K byte, 2K byte, and 4K byte are supported. Table 7-13 shows the page size and breakdown of the internal address (IA[31:0], as seen from the core or DMA) into the row, bank, column, and byte address. The bank width in all cases is 16 bits. The column address and the byte address together make up the address inside the page. EBCAW SDRAM Memory Bank Control Register (EBIU_SDBCTL) 15 14 13 12 11 10 0xFFC0 0A14 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBCAW[1:0] SDRAM external bank column address width 00 - 8 bits 01 - 9 bits 10 - 10 bits 11 - 11 bits 0 0 0 Reset = 0x0000 EBE SDRAM external bank enable 0 - Disabled 1 - Enabled EBSZ[2:0] SDRAM external bank size 000 - 16M byte 001 - 32M byte 010 - 64M byte 011 - 128M byte Figure 7-15. SDRAM Memory Bank Control Register The page size can be calculated for 16-bit SDRAM banks with this formula: page size = 2(CAW + 1) 7-62 ADSP-BF52x Blackfin Processor Hardware Reference where CAW is the column address width of the SDRAM, plus 1 because the SDRAM bank is 16 bits wide (1 address bit = 2 bytes). Bank Size (M byte) EBSZ bits Col. Addr. Width (CAW) EBCAW bits Page Size (K Byte) Bank Address Row Address Column Address Byte Address Table 7-13. Internal Address Mapping 128 11 4 IA[26:25] IA[24:12] IA[11:1] IA[0] 128 10 2 IA[26:25] IA[24:11] IA[10:1] IA[0] 128 9 1 1A[26:25] IA[24:10] IA[9:1] IA[0] 128 8 0.5 IA[26:25] IA[24:9] IA[8:1] IA[0] 64 11 4 IA[25:24] IA[23:12] IA[11:1] IA[0] 64 10 2 IA[25:24] IA[23:11] IA[10:1] IA[0] 64 9 1 IA[25:24] IA[23:10] IA[9:1] IA[0] 64 8 0.5 IA[25:24] IA[23:9] IA[8:1] IA[0] 32 11 4 IA[24:23] IA[22:12] IA[11:1] IA[0] 32 10 2 IA[24:23] IA[22:11] IA[10:1] IA[0] 32 9 1 IA[24:23] IA[22:10] IA[9:1] IA[0] 32 8 0.5 IA[24:23] IA[22:9] IA[8:1] IA[0] 16 11 4 IA[23:22] IA[21:12] IA[11:1] IA[0] 16 10 2 IA[23:22] IA[21:11] IA[10:1] IA[0] 16 9 1 IA[23:22] IA[21:10] IA[9:1] IA[0] 16 8 0.5 IA[23:22] IA[21:9] IA[8:1] IA[0] Page Using SDRAMs With Systems Smaller than 16M byte It is possible to use SDRAMs smaller than 16M byte on the ADSP-BF52x, as long as it is understood how the resulting memory map is altered. Figure 7-16 shows an example where a 2M byte SDRAM (512K x 16 bits x 2 banks) is mapped to the external memory interface. In this example, ADSP-BF52x Blackfin Processor Hardware Reference 7-63 there are 11 row addresses and eight column addresses per bank. Referring to Table 7-4 on page 7-25, the lowest available bank size (16M byte) for a device with eight column addresses has two bank address lines (IA[23:22]) and 13 row address lines (IA[21:9]). Therefore, one processor bank address line and two row address lines are unused when hooking up to the SDRAM in the example. This causes aliasing in the processor’s external memory map, which results in the SDRAM being mapped into non-contiguous regions of the processor’s memory space. Referring to the table in Figure 7-16, note that each line in the table corresponds to 219 bytes, or 512K byte. Thus, the mapping of the 2M byte SDRAM is non-contiguous in Blackfin memory, as shown by the memory mapping in the left side of the figure. EXAMPLE: 2M BYTE SDRAM WITH 512K x 16 x 2 BANKS, 11 ROW ADDRESSES AND 8 COLUMN ADDRESSES PER BANK BANK ADDRESS ROW ADDRESS IA22 IA21 IA20 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 IA23 = 1 IA23 0 BLACKFIN MEMORY MAP IA19 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0x0000 0000 0 0 0 1M BYTE 0 1 0 1M BYTE 1 0 IA23 = 0 0 0 X X X X UNAVAILABLE COMBINATIONS ARE SHADED Figure 7-16. Using Small SDRAMs 7-64 ADSP-BF52x Blackfin Processor Hardware Reference E BIU_SDGCTL Register The SDRAM memory global control register (EBIU_SDGCTL) includes all programmable parameters associated with the SDRAM access timing and configuration. Figure 7-17 shows the EBIU_SDGCTL register bit definitions. SDRAM clock enable (SCTLE) The SCTLE bit is used to enable or disable the SDC. If SCTLE is cleared, any access to SDRAM address space generates an internal bus error, and the access does not occur externally. For more information, see “Error Detection” on page 7-7. When SCTLE is cleared, all SDC control pins are in their inactive states and the SDRAM clock is not running. The SCTLE bit must be set for SDC operation and is set by default at reset. The CAS latency (CL), SDRAM tRAS timing (TRAS), SDRAM tRP timing (TRP), SDRAM tRCD timing (TRCD), and SDRAM tWR timing (TWR) bits should be programmed based on the system clock frequency and the timing specifications of the SDRAM used. The SCTLE bit allows software to disable all SDRAM control pins. These pins are SDQM[3:0], SCAS, SRAS, SWE, SCKE, and CLKOUT. =0 Disable all SDRAM control pins (control pins negated, CLKOUT low). • SCTLE • SCTLE =1 Enable all SDRAM control pins (CLKOUT toggles). Note that the CLKOUT function is also shared with the AMC. Even if SCTLE is disabled, CLKOUT can be enabled independently by the CLKOUT enable in the AMC (AMCKEN in the EBIU_AMGCTL register). If the system does not use SDRAM, SCTLE should be set to 0. ADSP-BF52x Blackfin Processor Hardware Reference 7-65 SDRAM Memory Global Control Register (EBIU_SDGCTL) 31 30 29 28 27 26 25 24 1 0xFFC0 0A10 0 1 1 0 0 0 0 23 22 0 0 21 20 0 19 18 17 16 0 1 0 0 Reset = 0xE008 8 849 0 TRCD[2:1] SDRAM tRCD in SCLK cycles 000 - Reserved 001-111 - 1 to 7 cycles TWR[1:0] SDRAM tWR in SCLK cycles 00 - Reserved 01-11 - 1 to 3 cycles PUPSD Powerup start delay 0 - No extra delay added before first Precharge command 1 - Fifteen SCLK cycles of delay before first Precharge command PSM SDRAM powerup sequence 0 - Precharge, 8 CBR refresh cycles, mode register set 1 - Precharge, mode register set, 8 CBR refresh cycles PSSE SDRAM powerup sequence start enable. Always reads 0 0 - No effect 1 - Enables SDRAM powerup sequence on next SDRAM access Reserved TCSR Temperature compensated self-refresh value in extended mode register 0 - 45 degrees C 1 - 85 degrees C EMREN Extended mode register enable 0 - Disabled 1 - Enabled FBBRW Fast back-to-back read to write 0 - Disabled 1 - Enabled EBUFE SDRAM timing for external buffering of address and control 0 - External buffering timing disabled 1 - External buffering timing enabled SRFS SDRAM self-refresh enable 0 - Disable self-refresh 1 - Enable self-refresh during inactivity 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 TRCD[0] SDRAM tRCD in SCLK cycles 000 - Reserved 001-111 - 1 to 7 cycles TRP[2:0] SDRAM tRP in SCLK cycles 000 - No effect 001-111 - 1 to 7 cycles TRAS[3:0] SDRAM tRAS in SCLK cycles 0000 - No effect 0001-1111 - 1 to 15 cycles 0 1 0 SCTLE Enable CLKOUT, SRAS, SCAS, SWE, SDQM[1:0] 0 - Disabled 1 - Enabled CL[1:0] SDRAM CAS latency 00–01 - Reserved 10 - 2 cycles 11 - 3 cycles PASR[1:0] Partial array self-refresh in extended mode register 00 - All 4 banks refreshed 01 - Int banks 0, 1 refreshed 10 - Int bank 0 only refreshed 11 - Reserved Figure 7-17. SDRAM Memory Global Control Register 7-66 ADSP-BF52x Blackfin Processor Hardware Reference If an access occurs to the SDRAM address space while SCTLE is 0, the access generates an internal bus error and the access does not occur externally. For more information, see “Error Detection” on page 7-7. With careful the b can used in con junction withsoftware control,further loweritpowerbeconsumption by the bit to SCTLE SRFS freezing the CLKOUT pin. However, SCTLE must remain enabled at all times when the SDC is needed to generate auto-refresh commands to SDRAM. CAS latency (CL) The CL bits in the SDRAM memory global control register (EBIU_SDGCTL) select the CAS latency value: CL = b#00 reserved CL = b#01 reserved CL = b#10 two clock cycles CL = b#11 three clock cycles Partial array self refresh (PASR) The PASR bits determine how many internal SDRAM banks are refreshed during self-refresh. PASR = b#00 all 4 banks PASR = b#01 internal banks 0 and 1 refreshed PASR = b#10 only internal bank 0 refreshed PASR = b#11 reserved ADSP-BF52x Blackfin Processor Hardware Reference 7-67 Internal banks are decoded with the A[19:18] pins. f Theinternaleature requires careful software control with regard to the bank used. PASR Bank activate command delay (TRAS) The TRAS bits in the SDRAM memory global control register (EBIU_SDGCTL) select the tRAS value. Any value between 1 and 15 clock cycles can be selected. For example: TRAS = b#0000 no effect TRAS = b#0001 one clock cycle TRAS = b#0010 two clock cycles TRAS = b#1111 fifteen clock cycles Bank precharge delay (TRP) The TRP bits in the SDRAM memory global control register (EBIU_SDGCTL) select the tRP value. Any value between 1 and 7 clock cycles may be selected. For example: TRP = b#000 no effect TRP = b#001 one clock cycle TRP = b#010 two clock cycles TRP = b#111 seven clock cycles RAS to CAS delay (TRCD) The TRCD bits in the SDRAM memory global control register (EBIU_SDGCTL) select the tRCD value Any value between 1 and 7 clock cycles may be selected. For example: 7-68 ADSP-BF52x Blackfin Processor Hardware Reference TRCD = b#000 reserved, no effect TRCD = b#001 one clock cycle TRCD = b#010 two clock cycles TRCD = b#111 seven clock cycles Write to precharge delay (TWR) The TWR bits in the SDRAM memory global control register (EBIU_SDGCTL) select the tWR value. Any value between 1 and 3 clock cycles may be selected. For example: TWR = b#00 reserved TWR = b#01 one clock cycle TWR = b#10 two clock cycles TWR = b#11 three clock cycles Power-Up Start Delay (PUPSD) The power-up start delay bit (PUPSD) optionally delays the power-up start sequence for 15 SCLK cycles. This is useful for multiprocessor systems sharing an external SDRAM. If the bus has been previously granted to the other processor before power-up and self-refresh mode is used when switching bus ownership, then the PUPSD bit can be used to guarantee a sufficient period of inactivity from self-refresh to the first Precharge command in the power-up sequence in order to meet the exit self-refresh time (tXSR) of the SDRAM. ADSP-BF52x Blackfin Processor Hardware Reference 7-69 P ower-Up Sequence Mode (PSM) If the PSM bit is set to 1, the SDC command sequence is: 1. precharge all 2. mode register set 3. eight auto-refresh cycles If the PSM bit is cleared, the SDC command sequence is: 1. precharge all 2. eight auto-refresh cycles 3. mode register set Power-Up Sequence Start Enable (PSSE) The PSM and PSSE bits work together to specify and trigger an SDRAM power-up (initialization) sequence. Two events must occur before the SDC does the SDRAM power-up sequence: • The PSSE bit must be set to enable the SDRAM power-up sequence. • A read or write access must be done to enabled SDRAM address space in order to have the external bus granted to the SDC so that the SDRAM power-up sequence may occur. The SDRAM power-up sequence occurs and is followed immediately by the read or write transfer to SDRAM that was used to trigger the SDRAM power-up sequence. Note that there is a latency for this first access to 7-70 ADSP-BF52x Blackfin Processor Hardware Reference SDRAM because the SDRAM power-up sequence takes many cycles to complete. that Before executing the SDC power-upis sequence,forensureproperthe SDRAM receives stable power and clocked the amount of time, as described in the SDRAM specifications. Self-Refresh Setting (SRFS) The SRFS and SCTLE bits work together in EBIU_SDGCTL for self-refresh control. SRFS = b#0 disable self-refresh mode SRFS = b#1 enter self-refresh mode When SRFS is set, self-refresh mode is triggered. Once the SDC completes any active transfers, the SDC executes a sequence of commands to put the SDRAM into self-refresh mode. When the device comes out of reset, the SCKE pin is driven high. If it is necessary to enter self-refresh mode after reset, program SRFS = b#1. Enter Self-Refresh Mode When SRFS is set, once the SDC enters an idle state it issues a precharge all command and then issues a self-refresh entry command. If an internal access is pending, the SDC delays issuing the self-refresh entry command until it completes the pending SDRAM access and any subsequent pending access requests. ADSP-BF52x Blackfin Processor Hardware Reference 7-71 Once the SDRAM device enters into self-refresh mode, the SDRAM controller asserts the SDSRA bit in the SDRAM control status register (EBIU_SDSTAT). the it is set 1, the Once it finishesbpendingtoaccesses.SDC enters self-refresh mode when There is no way to cancel the SRFS entry into self-refresh mode. Before disabling the CLKOUT pin with the SCTLE bit, be sure to place the SDC in self-refresh mode (SRFS bit). If this is not done, the SDRAM is unclocked and will not work properly. Exit Self-Refresh Mode The SDRAM device exits self-refresh mode only when the SDC receives core or DMA requests. In conjunction with the SRFS bit, two possibilities are given to exit self-refresh mode. • If the SRFS bit remains set before the core/DMA request, the SDC exits self-refresh mode temporarily for a single request and returns back to self-refresh mode until a new request is latched. • If the SRFS bit is cleared before the core/DMA request, the SDC exits self-refresh mode and returns to auto-refresh mode. Before exiting self-refresh mode with the SRFS bit, be sure to enable the CLKOUT pin (SCTLE bit). If this is not done, the SDRAM is unclocked and will not work properly. E xternal buffering enabled (EBUFE) With the total I/O width of 16 bits, a maximum of 4x4 bits can be connected in parallel in order to increase the system’s overall page size. To meet overall system timing requirements, systems that employ several SDRAM devices connected in parallel may require buffering between the 7-72 ADSP-BF52x Blackfin Processor Hardware Reference processor and the multiple SDRAM devices. This buffering generally consists of a register and driver. To meet such timing requirements and to allow intermediary registration, the SDC supports pipelining of SDRAM address and control signals. The EBUFE bit in the EBIU_SDGCTL register enables this mode: EBUFE = 0 disable external buffering timing EBUFE = 1 enable external buffering timing When EBUFE = 1, the SDRAM controller delays the data in write accesses by one cycle, enabling external buffer registers to latch the address and controls. In read accesses, the SDRAM controller samples data one cycle later to account for the one-cycle delay added by the external buffer registers. When external buffering timing is enabled, the latency of all accesses is increased by one cycle. 4 bits rather than 16 bits increases the page Connection of 4ofxfour, thus resulting1inx fewer off-page penalties. size by a factor Fast Back-to-Back Read to Write (FBBRW) The FBBRW bit enables an SDRAM read followed by write to occur on consecutive cycles. In many systems, this is not possible because the turn-off time of the SDRAM data pins is too long, leading to bus contention with the succeeding write from the processor. When this bit is cleared, a clock cycle is inserted between read accesses followed immediately by write accesses. Extended Mode Register Enabled (EMREN) The EMREN bit enables programming of the extended mode register during startup. The extended mode register is used to control SDRAM power consumption in certain mobile low power SDRAMs. If the EMREN bit is ADSP-BF52x Blackfin Processor Hardware Reference 7-73 enabled, then the TCSR and PASR[1:0] bits control the value written to the extended mode register. T emperature Compensated Self-Refresh (TCSR) The TCSR bit signals to the SDRAM the worst case temperature range for the system, and thus how often the SDRAM internal banks need to be refreshed during self-refresh. All reserved bits in this register must always be written with 0s. EBIU_SDSTAT Register The SDRAM control status register (EBIU_SDSTAT), shown in Figure 7-18, provides information on the state of the SDC. This information can be 7-74 ADSP-BF52x Blackfin Processor Hardware Reference used to determine when it is safe to alter SDC control parameters or it can be used as a debug aid. SDRAM Control Status Register (EBIU_SDSTAT) 15 14 13 12 11 10 0xFFC0 0A1C 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reserved SDEASE - W1C SDRAM EAB sticky error status. Write 1 to this bit to clear it. 0 - No error detected 1 - EAB access generated an error SDRS 0 - Will not power up on next SDRAM access (SDRAM already powered up) 1 - Will power up on next SDRAM access if SDRAM enabled Reset = 0x0008 SDCI SDRAM controller idle 0 - SDC is busy performing an access or an AutoRefresh 1 - SDC is idle SDSRA SDRAM self-refresh active 0 - SDRAMs not in selfrefresh mode 1 - SDRAMs in self-refresh mode SDPUA SDRAM powerup active 0 - SDC not in powerup sequence 1 - SDC in powerup sequence Figure 7-18. SDRAM Control Status Register • SDC idle (SDCI) If the SDCI bit is cleared, the SDC is performing a user access or auto-refresh. If the SDCI bit is set, no commands are issued and the SDC is in idle state. • SDC self-refresh active (SDSRA) If the SDSRA bit is cleared, the SDC is performing auto-refresh (SCKE pin = 0). If the SDSRA bit is set, the SDC performs self-refresh mode (SCKE pin = 1). • SDC powerup active (SDPUA) ADSP-BF52x Blackfin Processor Hardware Reference 7-75 If the SDPUA bit is cleared, the SDC is not in powerup sequence. If the SDPUA bit is set, the SDC performs the powerup sequence. • SDC powerup delay (SDRS) If the SDRS bit is cleared, the SDC has already powered up. If the SDRS bit is set, the SDC will still perform the powerup sequence. • SDC EAB sticky error status (SDEASE) If the SDEASE bit is cleared, there were no errors detected on the EAB core bus. If the SDEASE bit is set, there were errors detected on the EAB core bus. The SDEASE bit is sticky. Once it has been set, software must explicitly write a 1 to the bit to clear it. Writes have no effect on the other status bits, which are updated by the SDC only. SDC Programming Examples Listing 7-3 through Listing 7-6 provide examples for working with the SDC. Listing 7-3. 16-Bit Core Transfers to SDRAM .section L1_data_b; .byte2 source[N] = 0x1122, 0x3344, 0x5566, 0x7788; .section SDRAM; .byte2 dest[N]; .section L1_code; I0.L = lo(source); I0.H = hi(source); I1.L = lo(dest); I1.H = hi(dest); R0.L = w[I0++]; p5=N-1; 7-76 ADSP-BF52x Blackfin Processor Hardware Reference lsetup(lp, lp) lc0=p5; lp:R0.L = w[I0++] || w[I1++] = R0.L; w[I1++] = R0.L; Listing 7-4. 8-Bit Core Transfers to SDRAM Using Byte Mask SDQM[1:0] Pins .section L1_data_b; .byte source[N] = 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88; .section SDRAM; .byte dest[N]; p0.L = lo(source); p0.H = hi(source); p1.L = lo(dest); p1.H = hi(dest); p5=N; lsetup(start, end) lc0=p5; start: R0 = b[p0++](z); end: b[p1++] = R0; /* byte data masking */ Listing 7-5. Self-refresh Mode Power Savings with Disabled CLKOUT r0.l = w[I1++]; ssync; /* SDRAM access */ /* force last SDRAM access to finish */ P0.L = lo(EBIU_SDGCTL); P0.H = hi(EBIU_SDGCTL); R1 = [P0]; bitset(R1, bitpos(SRFS)); /* enter self-refresh */ [P0] = R1; ssync; P0.L = lo(EBIU_SDSTAT); ADSP-BF52x Blackfin Processor Hardware Reference 7-77 P0.H = hi(EBIU_SDSTAT); self_refresh_status: R0 = [P0]; ssync; cc = bittst(R0, bitpos(SDSRA)); /* poll self-refresh status */ if !cc jump self_refresh_status; P0.L = lo(EBIU_SDGCTL); P0.H = hi(EBIU_SDGCTL); R1 = [P0]; bitclr(R1, bitpos(SCTLE)); /* disable CLKOUT after approx 20 cycles */ [P0] = R1; ssync; P5 = 30000; LSETUP(lp,lp) LC0 = P5; lp: nop; /* dummy loop */ R1 = [P0]; bitset(R1, bitpos(SCTLE)); /* enable CLKOUT after approx 20 cycles */ [P0] = R1; ssync; R1 = [P0]; bitclr(R1, bitpos(SRFS)); /* exit self-refresh */ [P0] = R1; ssync; w[I1++] = r0.l; 7-78 /* SDRAM access */ ADSP-BF52x Blackfin Processor Hardware Reference Listing 7-6. Init /*********************************************************/ /* SDRAM part# Micron MT48LC32M8A2-75 (32Mx8/256Mbit) */ /* 8k rows, 1k columns -> EBCAW = 10 */ /* 2xSDRAM: 32Mx16 = 64Mbytes -> EBSZ = 010 */ /* populated SDRAM addresses -> 0x00000000 - 0x01FFFFFF */ /* internal SDRAM bank A 0x00000000 - 0x007FFFFF */ /* internal SDRAM bank B 0x00800000 - 0x00FFFFFF */ /* internal SDRAM bank C 0x01000000 - 0x017FFFFF */ /* internal SDRAM bank D 0x01800000 - 0x01FFFFFF */ /* powerup: PRE-REF-MRS -> PSM = 0 */ /* SCLK = 133 MHz */ /* tCK = 7.5ns min@CL=3 -> CL = 3 */ /* tRAS = 44ns min -> TRAS = 6 */ /* tRP = 20ns min -> TRP = 3 */ /* tRCD = 20ns min -> TRCD = 3 */ /* tWR = 15ns min -> TWR = 2 */ /* tREF = 64ms max ->RDIV = (133MHz*64ms)/8192-(6+3)=0x406 cycles */ /*********************************************************/ #ifdef INIT_SDRAM /* Check if already enabled */ p0.l = lo(EBIU_SDSTAT); p0.h = hi(EBIU_SDSTAT); r0 = [p0]; cc = bittst(r0, bitpos(SDRS)); if !cc jump skip init_sdram; /* SDRAM Refresh Rate Control Register */ ADSP-BF52x Blackfin Processor Hardware Reference 7-79 P0.L = lo(EBIU_SDRRC); P0.H = hi(EBIU_SDRRC); R0.L = 0x0406; W[P0] = R0.L; /* SDRAM Memory Bank Control Register */ P0.L = lo(EBIU_SDBCTL); P0.H = hi(EBIU_SDBCTL); R0.L = 0x0025; W[P0] = R0.L; /* SDRAM Memory Global Control Register */ P0.L = lo(EBIU_SDGCTL); P0.H = hi(EBIU_SDGCTL); R0.L = 0x998d; R0.H = 0x8491; [P0] = R0; ssync; 7-80 /* wait until executed */ ADSP-BF52x Blackfin Processor Hardware Reference 8 HOST DMA PORT This chapter describes the Host DMA Port (HOSTDP). Following an overview and a list of key features are a description of operation and functional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview The HOSTDP facilitates a host device external to the ADSP-BF52x processor to be a Direct Memory Access (DMA) master and transfer data back and forth. The host device always masters the transactions and the Blackfin processor is always a DMA slave device. necessary to pay particular attention nomenclature involv It isthe Host DMA Port. The Host DMAtoPort is sometimes ing abbreviated as HOSTDP. Register and pin names all have the prefix HOST_. The HOSTDP is a peripheral on the ADSP-BF52x processor, which is referred to as the slave processor or Blackfin slave. The host processor is also referred to as the host, master, external host, or external master. The HOSTDP is enabled through the Peripheral Access Bus (PAB) interface. Once enabled, the DMA is controlled by an external host. The external host can then program the DMA to send/receive data to any valid internal or external memory location. ADSP-BF52x Blackfin Processor Hardware Reference 8-1 F eatures The HOSTDP controller includes the following features: • Allows external master to configure DMA READ/WRITE data transfers and read port status • Uses a flexible asynchronous memory protocol for external interface • 8/16-bit external data interface to host device • Half-duplex operation • Little/Big Endian data transfer • Internal FIFO which holds sixteen 16-bit words • Acknowledge Mode allows flow control on host transactions • Interrupt Mode guarantees a burst of FIFO depth host transactions • Ability to enable and disable data reads/writes • DMA bandwidth control 8-2 ADSP-BF52x Blackfin Processor Hardware Reference I nterface Overview Table 8-1 defines the pins for the HOSTDP interface. The interface uses a flexible asynchronous memory interface, which can be gluelessly connected to a variety of host processors. Table 8-1. HOSTDP External Pins Pin Description Port H - HOST_DATA <15:0> 16-bit data port PG15- HOST_CE Chip Enable for the HOSTDP PG11 - HOST_WR Write strobe PG14- HOST_RD Read strobe PH13 - HOST_ADDR Address pin 0: data port access 1: configuration port access PH12 - HOST_ACK (HRDY/FRDY) Flow control pin: HRDY-Acknowledge mode & FRDY- Interrupt mode to of multiplexed pins, utilizing DueHostthe Blackfin processor’s usethe use of other peripherals. The the DMA Port can preclude Ethernet MAC and NAND flash are unavailable when using the HOSTDP. Refer to “General-Purpose Ports” on page 9-1 for a complete description of the pin multiplexing scheme. Description of Operation The following sections describe the operation of the HOSTDP interface. ADSP-BF52x Blackfin Processor Hardware Reference 8-3 A rchitecture The HOSTDP block diagram, shown in Figure 8-1, illustrates the overall architecture of the HOSTDP. HOST_DATA15–0 HOST_CE DMA DAB (16-BIT) FIFO HOSTDP EXTERNAL INTERFACE (HEI) I N T E R F A C E HOST_RD HOST_WR HOST_ADDR HOST_ACK CONTROL P A B PAB INTERFACE ASYNCHRONOUS MEMORY INTERFACE CONTROL REGS INTERRUPT Figure 8-1. HOSTDP Block Diagram The HOSTDP is enabled/disabled through PAB writes to the HOST_CONTROL register. Once enabled, the HOSTDP interfaces to the external world using asynchronous memory protocol and handshakes with the DMA controller internally using the DMA Access Bus (DAB). The HOSTDP allows the external host to program the DMA to transfer data in either direction. The HOSTDP can be broken into five functional blocks, identified as follows: • Host External Interface (HEI) This block interfaces to the external host and, based on inputs from the host device, initiates data or control message transfer. • PAB Interface 8-4 ADSP-BF52x Blackfin Processor Hardware Reference The HOSTDP is programmed/queried for status by reads or writes to appropriate registers in this block through the PAB. • FIFO A port FIFO is used for data transfers and can store up to sixteen 16-bit words. • Control The Control block handles the HOSTDP’s different states as well as the handshakes between the external host device and DMA Interfaces. • DMA Interface This block is connected to the DAB and interacts with the DMA to transfer control messages and data between DMA and external host device. F unctional Description The following sections describe the functional operation of the Host DMA Port. HOSTDP Configuration Before any data transfer can occur, the DMA engine must be configured by the host processor. Because the host is unaware of the internal state of the Host DMA Port peripheral and its associated DMA activity, the host processor is required to check the ALLOW_CNFG bit in HOST_STATUS register before attempting configuration writes. Additionally, this status read sets some internal states inside the Host DMA Port. Configuration requires seven 16-bit words to be written in the following order to the configura- ADSP-BF52x Blackfin Processor Hardware Reference 8-5 tion port before Host Read Data or Host Write Data operations can occur: • HOST_CONFIG • START_ADDR.L • START_ADDR.H • XCOUNT • XMODIFY • YCOUNT • YMODIFY The only word different from the standard DMA described in the DMA chapter is the HOST_CONFIG word, as shown in Figure 8-2. HOSTDP Config Word (HOST_CONFIG) 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 1 0 0 1 Default = 0x00A9 WNR (DMA Direction) 0 - DMA is a host read operation 1 - DMA is a host write operation FLOW (Next Operation) 0 - Stop Mode 1 - Autobuffer Mode DMA2D (DMA Mode) 0 - Linear (One-dimensional) 1 - Two-dimensional (2-D) Figure 8-2. HOSTDP Configuration Word Additional information for the HOST_CONFIG bits includes the following: • Host DMA Direction (WNR) When this bit is set, the DMA will write to memory (host write). When this bit is cleared, the DMA will read from memory (host read). 8-6 ADSP-BF52x Blackfin Processor Hardware Reference • Host DMA Mode (DMA2D) When this bit is cleared, the DMA is linear one-dimension (1-D). When this bit is set, the DMA is in two-dimension mode (2-D). • FLOW (FLOW) When this bit is cleared, the DMA runs in STOP mode. When this bit is set, the DMA runs in AUTOBUFFER mode. For information on how these words are used to configure the DMA, refer to “Direct Memory Access” on page 6-1. Before accessing the data port, the host processor must write all seven descriptor words. The HOSTDP module does not forward descriptors to the DMA channel until it has received all seven words. Similarly, the host processor is not permitted to provide new descriptor data before all data words of the former work unit have been transferred. However, the host can truncate an initiated transfer using the DMA_FINISH control command. As always, ALLOW_CNFG in the HOST_STATUS register must be polled before writing a new configuration to the Host DMA Port. Please see “Control Commands Between the External Host and HOSTDP” on page 8-19 for additional information. Additional latency is incurred when a Host Read Data operation follows a Host Write Data operation. Even though the configuration for the Host Read is complete, the DMA engine must first empty the FIFO for the Host Write operation and then change directions and start filling the FIFO for the Host Read Data operation. HOSTDP Transactions The HOSTDP is enabled by writing to the HOSTDP_EN bit of the HOST_CONTROL register. In order to disable the HOSTDP, the HOSTDP_RST bit must be asserted before clearing HOSTDP_EN. There are four types of HOSTDP transactions. Each type of access is based on the HOST_ADDR and whether the HOST_RD or HOST_WR signal is asserted. ADSP-BF52x Blackfin Processor Hardware Reference 8-7 When chip enable (HOST_CE) is inactive, the HOSTDP stays idle. Modes listed in Table 8-2 are only possible when HOST_CE is active. Table 8-2. Types of HOSTDP Transactions Address HOST_RD HOST_WR HOST_CE Function 0x0 0 1 0 Host Read Data Operation 0x0 1 0 0 Host Write Data Operation 0x1 1 0 0 Host Write Configuration or Control Command 0x1 0 1 0 Host Read HOST_STATUS register Host Read Status The Host DMA Port is robust against on-the-fly changes of data direction. However, in acknowledge mode, it is encouraged not to initiate a new work unit with different data direction before the FIFOEMPTY bit in the HOST_STATUS register is cleared. This is to avoid excessive wait states inserted by HRDY. The external host can read the HOST_STATUS register at any time. By performing this operation, the external host can query the status of the HOSTDP. Note that in 8-bit configurations, the host can only read the lower byte of the HOST_STATUS register. HOST_STATUS can also be read through a PAB access. When accessed through the PAB, all 16 bits of HOST_STATUS are always read. The contents of HOST_STATUS are detailed in “Host DMA Port Registers” on page 8-26. 8-8 ADSP-BF52x Blackfin Processor Hardware Reference Host Read Data and Host Write Data Operations After the HOSTDP has been configured and enabled by way of PAB accesses and the DMA channel has been configured through Host Write Configuration accesses, data can be transferred. All DMAs betweenisthe HOSTDP FIFO and memoryaare 16-bit . transactions. This important when setting nd XMODIFY YMODIFY The amount of data moved between the host processor and the HOSTDP must be a multiple of the FIFO depth (sixteen 16-bit words). The user is required to set the XCOUNT/YCOUNT values such that this is true and to also ensure that the correct number of host data reads or host data writes are performed. A Host Write Data operation is used to transfer data from the host to the slave processor. The host performs write transactions and the HOSTDP writes the data from these transactions into its FIFO. The DMA engine concurrently moves data from the HOSTDP’s FIFO to the location in memory specified by the DMA configuration words. A Host Read Data operation is used to transfer data from the slave processor to the host. The DMA engine moves data from the specified location in the Blackfin slave’s memory into the HOSTDP’s FIFO. The host performs read accesses to read data out of this FIFO. In the case of host writes, the host processor must “pad” the end of the transfer with dummy data to ensure this (for example, if the host wants 31 words it must send an extra dummy word to equal 32). In the case of host reads, dummy reads must be performed at the end and the host can then throw away the results. This is true in both interrupt mode and acknowledge mode. When in 8-bit mode, since all DMAs from the HOSTDP are 16 bits, data will be packed into 16-bit words in the HOSTDP FIFO during Host Data Write operations. For Host Data Read operations in 8-bit mode, data will be unpacked in the FIFO into 8-bit words for transmission. Because all DMAs are 16-bit and the data bus is either 8-bit or 16-bit, the total of ADSP-BF52x Blackfin Processor Hardware Reference 8-9 * YCOUNT should be 1/2 (8-bit mode) or equal to (16-bit mode) the number of data reads or writes the host processor will perform. XCOUNT interrupts are Differenthost data writetriggered upon completion of host data read and DMA work units. In order to synchronize work unit transitions, a separate interrupt is provided for host read operations. This interrupt will not be triggered until the host has read the final data in the work unit from the HOSTDP's FIFO. It is cleared by writing 1 to the HOSTRD_DONE bit in HOST_STATUS. A host data write operation will not trigger an interrupt until all data from the work unit has been written from the HOSTDP's FIFO to the specified location in memory. The interrupt is triggered on the selected DMA channel's assigned IRQ channel. It is cleared by writing 1 to the DMA_DONE bit in the appropriate DMAx_IRQ_STATUS register. HOSTDP Modes of Operation There are two modes of flow control in the HOSTDP—Acknowledge mode and Interrupt mode. These two modes provide flow control between the host and the slave processor by way of a single hardware signal. This signal has different names depending upon the mode of operation. The flow control mode is configured by the slave processor when enabling the HOSTDP (see HOST_CONTROL register). In Acknowledge Mode, the signal is called HRDY and is used to add wait states to a host transaction when the HOSTDP isn't ready to transfer data. The HRDY signal is level-sensitive. In Interrupt Mode, the signal is called FRDY and is used as an edge-triggered signal. This signal is connected to the host as an interrupt input. A falling edge on it signals to the host that the HOSTDP is ready for a guaranteed FIFO depth number of back to back transactions. For Host Write operations, this occurs when the FIFO is empty. For Host Read operations, this occurs when the FIFO is full. 8-10 ADSP-BF52x Blackfin Processor Hardware Reference Acknowledge Mode For Host Data Write operations, HRDY will negate when the FIFO is full, thereby inserting wait states. As soon as the DMA engine moves data out of the FIFO, HRDY will assert, indicating to the host that the Host Data Write operation has completed. For Host Data Read operations, HRDY will negate when the FIFO is empty, thereby inserting wait states. As soon as the DMA engine moves data into the FIFO, HRDY will assert, indicating to the host that the Host Data Read operation has completed. The HRDY signal must be pulled high through an external pull-up resistor by default at power up/reset and when the HOSTDP is not enabled. HRDY is only driven when HOST_CE is asserted low. When the host is performing a host write configuration or HOST_STATUS reads, HRDY will always remain asserted and no wait states will be added. Acknowledge Mode Timing Diagrams This section gives further details on the HOSTDP timings for acknowledge mode. The host processor must follow these rules on every bus cycle, independent of the nature of the access and the status of slave processor. It is assumed that the Blackfin slave processor has booted and the HOSTDP is functional. As discussed in the following, HRDY has an external pull-up resistor: 1. If HOST_CE is high, HRDY is three-state (not driven). 2. is driven by the slave processor (according to the rules shown below) only when HOST_CE is asserted low by the external host device. HRDY ADSP-BF52x Blackfin Processor Hardware Reference 8-11 3. If HOST_CE and either HOST_RD or HOST_WR are asserted, and HOST_ADDR is high (configuration port access), HRDY will remain driven high. 4. If HOST_CE and either HOST_RD or HOST_WR are asserted, and HOST_ADDR is low (data port access), one of two things will happen: a. If HOST_RD is asserted and the desired FIFO data can be transferred on the data bus pins within time T, HRDY will remain driven high. If HOST_WR is asserted and the data can be stored in the FIFO within time T, HRDY will remain high. b. If the desired FIFO data cannot be transferred on the data bus pins or stored in the FIFO within time T, HRDY will be driven low quickly. Some time after the desired data operation is complete, HRDY is driven high. The two timing diagrams, shown in Figure 8-3 and Figure 8-4, are necessary to understand the function of HRDY. HOST_ADDR HOST_CE HOST_RD OR HOST_WR HDATA VALID 8 OR 16 BITS HRDY MINIMUM ACCESS TIME “T” Figure 8-3. No delay in Host Bus Cycle 8-12 ADSP-BF52x Blackfin Processor Hardware Reference HOST_ADDR HOST_CE HOST_RD OR HOST_WR VALID 8 OR 16 BITS HDATA HRDY ACCESS TIME > “T” DUE TO HRDY ASSERTION Figure 8-4. Delay in Host Bus Cycle caused by HRDY Host Bus Timeout In acknowledge mode, an optional Host Bus Timeout feature is implemented as a mechanism to alert the host when a programmed period of time has expired during a Host Read/Write Data transaction and the HOSTDP is still unable to complete the transaction with HRDY assertion. This condition can occur when the internal shared DMA bus has a lot of traffic from other peripherals on it. An internal timer is started when HOST_CE and either HOST_RD or HOST_WR are asserted. The timer is reset whenever HRDY is asserted. This feature can be enabled by setting the BT_EN bit in the HOST_CONTROL register. When set, the HOSTDP will generate an interrupt when a pre-programmed time-out value in the HOST_TIMEOUT register expires. In a typical application the interrupt service routine toggles a GPIO pin, which is connected to the host processor to alert it of this condition. Addition- ADSP-BF52x Blackfin Processor Hardware Reference 8-13 ally, the interrupt service routine can perform writes to the HOST_CONTROL register to perform the following: • Stop the DMA channel • Assert the HRDY pin to allow the Host Bus cycles to continue while the host is being signaled of this condition by way of a GPIO pin • Disable the HOSTDP Because it's important for the host to be aware that a timeout condition occurred, it is required that the host processor read the HOST_STATUS register and check the HOSTDP_TOUT bit. The ADSP-BF52x slave processor reads the actual bit, allowing it to take the timeout interrupt, and write-one-to-clear the HOSTDP_TOUT bit. The host processor reads a special shadow version of this bit which will remain set until the host has read it or a hard reset occurs. Interrupt Mode The FRDY signal will act as an edge-sensitive (high-to-low transition) signal to provide an interrupt to the external host to indicate when data transfers can proceed. The interrupt provided by the slave processor to the external host device by way of the FRDY signal is used to indicate the status of the Host DMA Port’s FIFO. Host Data Read and Host Data Write accesses are described next. The host device always masters the transactions and the Blackfin processor is always a DMA slave device. In Interrupt Mode, the FRDY signal will always be driven by the slave processor and does not require an external pull-up resistor. For Host Write operations, FRDY will transition from high to low whenever the FIFO is empty, causing an interrupt to the host to tell it to write to HOSTDP. The host can then perform a buffer depth number of write cycles to fill the FIFO. During these writes, FRDY will transition high again, but this is ignored by the host. After the FIFO's contents have been moved to memory by the DMA engine, the FIFO will become empty. At 8-14 ADSP-BF52x Blackfin Processor Hardware Reference this time, FRDY will once again transition from high to low to interrupt the host to do another buffer depth number of write cycles to fill the FIFO. This process continues until the configured number of words have been transferred. For Host Read operations, FRDY will transition from high to low whenever the FIFO is full, causing an interrupt to the host to tell it to read from the HOSTDP. The host can then perform a buffer depth number of read cycles to empty the FIFO. During these reads, FRDY will transition high again, but this is ignored by the host. The DMA engine will fill the FIFO from data in memory. Once the FIFO becomes full again, FRDY will once again transition from high to low to interrupt the host to do another buffer depth number of write cycles to fill the FIFO. This process continues until the configured number of words have been transferred. In interrupt mode, the FRDY signal always reflects the status of the FIFO. For Host Configuration writes or Host reads of HOST_STATUS, accesses will always meet the minimum cycle time T and FRDY will not be used for flow control of these accesses. Figure 8-5 shows the timing of the interrupt mode transactions. The total number of words in the transfer are divided into blocks that contain a FIFO depth's number of words. These blocks are transferred whenever a high-to-low transition occurs on FRDY. 1st BLOCK 2nd BLOCK ... LAST BLOCK FIFO DEPTH # OF TRANSFERS FIFO DEPTH # OF TRANSFERS ... FIFO DEPTH # OF TRANSFERS FRDY Figure 8-5. Interrupt Mode Bus Cycles ADSP-BF52x Blackfin Processor Hardware Reference 8-15 D MA STOP Mode and AUTOBUFFER Mode The FLOW bit in HOST_CONFIG controls whether the DMA channel runs in stop mode or autobuffer mode. In stop mode the DMA performs a block transfer once, as programmed by the HOST_CONFIG, XCOUNT/YCOUNT, XMODIFY/YMODIFY, and START_ADDR.L/H registers. Performing another block transfer requires the host to reconfigure these parameters. For stop mode, the interrupt service routine is required to set the DMA_CMPLT bit in the HOST_STATUS register. This prepares the HOSTDP for the next transfer. The host is not required to poll the DMA_CMPLT bit before starting a new work unit. In autobuffer mode, the DMA performs continuous block transfers based on the parameters programmed by the HOST_CONFIG, XCOUNT/YCOUNT, XMODIFY/YMODIFY, and START_ADDR.L/H registers. Once the number of words specified by XCOUNT/YCOUNT are transferred, the DMA engine sets its address pointer back to START_ADDR.L/H and performs another block transfer. For autobuffer mode, the interrupt service routine should only set the DMA_CMPLT bit in the HOST_STATUS when it wishes to complete the transfers. After this bit is set, the HOSTDP block expects to be reprogrammed with a new set of DMA register values. Bus Widths and Endian Order The HOSTDP can be programmed to be either 16 bits wide or 8 bits wide. Additionally the byte order can be programmed as little endian or big endian. All ensuing data and configuration transactions with the host will occur in the programmed endian setting. For 16-bit transfers, shown in Figure 8-6, the upper and lower bytes will be based on the big/little endian setting. When set to little endian, the order of the bytes on the HOST_DATA[15:0] bus is unchanged. For big 8-16 ADSP-BF52x Blackfin Processor Hardware Reference endian, the upper and lower bytes of HOST_DATA[15:0] are swapped before being stored internally. MEMORY ADDRESS: DATA: 0x0 A 0x1 B HOST_DATA BUS LITTLE ENDIAN 0 15 B A HOST_DATA BUS BIG ENDIAN 0 15 A B Figure 8-6. 16-bit Transfer Byte Order For 8-bit transfers the order in which the bytes are sent will be based on the big/little endian setting as shown in Figure 8-7. Consider a 16-bit word stored in internal memory: ADDRESS: DATA: LITTLE ENDIAN: 0x0 A 1st A, 2nd B 0x1 B BIG ENDIAN: 1st B, 2nd A Figure 8-7. 8-bit Transfer Byte Order Access Control Configurations only occur when they are allowed. If the access type is disallowed, the ALLOW_CNFG bit will not go low after configuration words are written. In the case of a disallowed configuration, the configuration words do not show up on the DAB bus, the DMA controller does not get programmed, and no NACK is provided to the host. By default, the HOSTDP module prohibits the external host from performing host data reads and writes. Blackfin software is required to enable host reads or writes. Host data reads and writes are enabled or disabled separately by the EHR and EHW bits in the HOST_CONTROL register. Once enabled, the host can perform read or write transactions. Writes to the ADSP-BF52x Blackfin Processor Hardware Reference 8-17 configuration port, control commands, and status reads are permitted regardless of the EHR and EHW settings. For more information, see the memory configuration discussion in “Security” on page 16-1. In acknowledge mode, if the transactions are disabled, host writes will still be allowed on the bus, but the actual write data is ignored. Similarly, host reads will still occur on the bus, but the data returned is indeterminate. In interrupt mode, transitions on FRDY will never occur. Note that the host cannot interrogate the HOSTDP to see whether only read or write access is granted. Therefore, it is recommended to keep EHR and EHW settings global without altering them. Improving HOSTDP DMA Bus Bandwidth Since the HOSTDP can be configured as a 16-bit wide parallel interface, data can move into and out of the peripheral quickly as compared to other serial peripherals on the chip. A FIFO is used to buffer this data and internal DMA bus requests are made judiciously to minimize the amount of DMA bandwidth that is used on the DMA bus. DAB bus arbitration overhead and direction change penalties are minimized. This is the default behavior (BDR=1). The HOSTDP follows the algorithm shown in Table 8-3, for receive (host write) operations. Table 8-3. Host Write Operation 16-bit Words in FIFO DMA Request Frequency Bursts per DMA Request (SCLK cycles) 1–4 24 Up to 4 5–8 16 4 9 – 12 8 4 >12 2 0 8-18 ADSP-BF52x Blackfin Processor Hardware Reference For example if there are ten words written into the FIFO by the host processor DMA will be requested on the eighth SCLK cycle. Once the DAB approves the request, it will transfer four words. Assuming the host processor does not write any new words to the FIFO, the HOSTDP will request DMA 16 cycles again and another four words will be transferred. Twenty-four SCLK cycles later, the remaining two words are transferred. Note that words stored in the FIFO are 16-bit. For transmit (host read) operation, the algorithm looks similar. Refer to Table 8-4. Table 8-4. Host Read Operation 16-bit Words in FIFO DMA Request Freq (SCLK cycles) Bursts per DMA Request 0–4 2 0 5–8 8 4 9 – 12 16 4 >12 24 Up to 4 This default behavior can be overridden by clearing the Burst DMA Requests (BDR) bit in the HOST_CONTROL register. This is to allow the HOSTDP to perform internal DMA bus requests whenever there is a single word of data in the FIFO for host writes, and at least one empty slot for host reads. In this case DMA bus requests are made more often. This allows higher throughput through the HOSTDP at the expense of the other peripherals on the chip. Control Commands Between the External Host and HOSTDP Control commands can be sent from the host to the HOSTDP by writing to the configuration port with bits 3 and 2 of the data high. When the Host DMA port is waiting for configuration, a control command cannot be sent because it will be misinterpreted as a configuration write. After ADSP-BF52x Blackfin Processor Hardware Reference 8-19 configuration is finished, control commands can then be issued at any time. If the host is unsure of whether configuration is pending, it will need to read the HOST_STATUS register to check. The commands that are supported are shown in Table 8-5. Table 8-5. Control Commands HOST_DATA[7:0] Command b#000111xx HOST IRQ b#001011xx DMA FINISH b#001111xx to b#111111xx ignored The HOST IRQ command provides a mechanism for the host to interrupt the HOSTDP. When the host writes a HOST IRQ command to the configuration port, the HIRQ bit in the HOST_STATUS register is set and a HOSTDP status interrupt is signaled. The handshake bit (HSHK) in HOST_STATUS can be set or cleared anytime by the slave processor. This bit can be used as a flag that the host can read. In an application, the host might interrupt with the HOST IRQ command requesting information. The interrupt service routine could then set or clear the HSHK bit. The host could then read the status register and test for the value of the HSHK bit. The DMA FINISH command performs the same functions as the HOSTDP reset (HOSTDP_RST) bit in the HOST_CONTROL register, except that it modifies the HOST_STATUS register contents and stops any DMA activity. The DMA FINISH command may not complete immediately but completes only after the DAB state machine has moved to a particular idle state. There are additional restrictions on when a DMA FINISH command may be sent by the host processor, refer to “DMA Control Commands” on page 6-107. 8-20 ADSP-BF52x Blackfin Processor Hardware Reference When the HOSTDP module receives a DMA FINISH command from the host during a write operation, the DMA channel's FIFO is still drained gracefully and requests a DMA completion interrupt. However, the HOSTDP’s FIFO is flushed immediately. To avoid loss of data, the host may want to wait until the FIFOEMPTY bit in HOST_STATUS is asserted before issuing the DMA FINISH command. Programming Model Figure 8-8 on page 8-22 and Figure 8-9 on page 8-23 show how to enable the Host DMA Port. They also show how to properly set up interrupt ser- ADSP-BF52x Blackfin Processor Hardware Reference 8-21 vice routines for both host read and write which clear the interrupts and prepare the HOSTDP to be configured by the host again. BF52X SLAVE PROGRAMMING MODEL STOP MODE HOST WRITE START ENABLE PORT IN HOST_CONTROL WAIT FOR INTERRUPTS IN THE SELECTED IVG DMA_DONE = 0 FIND AND CLEAR INTERRUPT CAUSE TEST DMA_DONE IN DMA_IRQ_STATUS DMA_DONE = 1 W1C DMA_DONE SET DMA_CMPLT IN HOST_STATUS RTI DMA CHANNEL INTERRUPT SERVICE ROUTINE. ENTRY CAUSED BY INTERRUPTS, EXITS AFTER AN RTI INSTRUCTION. Figure 8-8. Stop Mode Host Write 8-22 ADSP-BF52x Blackfin Processor Hardware Reference BF52X SLAVE PROGRAMMING MODEL STOP MODE HOST READ START ENABLE PORT IN HOST_CONTROL WAIT FOR INTERRUPTS IN THE SELECTED IVG HOSTRD_DONE = 0 FIND AND CLEAR INTERRUPT CAUSE TEST HOSTRD_DONE IN HOST_STATUS HOSTRD_DONE = 1 HOSTRD_DONE SET DMA_CMPLT IN HOST_STATUS RTI HOST READ DONE INTERRUPT SERVICE ROUTINE. ENTRY CAUSED BY INTERRUPTS, EXITS AFTER AN RTI INSTRUCTION. Figure 8-9. Stop Mode Host Read Figure 8-10 on page 8-24 and Figure 8-11 on page 8-25 show how to program a host processor to send a configuration to the ADSP-BF52x slave. ADSP-BF52x Blackfin Processor Hardware Reference 8-23 They also show when to send data in both acknowledge and interrupt modes. START ALLOW_CNFG = 0 POLL ALLOW_CNFG IN HOST_STATUS ALLOW_CNFG = 1 WRITE ALL SEVEN CONFIGURATION WORDS POLL DMA_RDY IN HOST_STATUS DMA_RDY - 0 DMA_RDY = 1 READ OR WRITE THE AMOUNT OF DATA SPECIFIED IN CONFIG VALUES YES FOLLOW-ON TRANSACTION? NO END Figure 8-10. Acknowledge Mode with DMA Set to Stop Mode 8-24 ADSP-BF52x Blackfin Processor Hardware Reference HOST PROCESSOR INTERRUPT MODE WITH DMA SET TO STOP MODE START ALLOW_CNFG = 0 POLL ALLOW_CNFG IN HOST_STATUS ALLOW_CNFG = 1 WRITE ALL SEVEN CONFIGURATION WORDS WAIT FOR FALLING EDGE ON FRDY READ OR WRITE FIFO DEPTH OF DATA ALL DATA READ OR WRITTEN? NO YES YES FOLLOW-ON TRANSACTION? NO FRDY INTERRUPT SERVICE ROUTINE END Figure 8-11. Interrupt Mode with DMA Set to Stop Mode ADSP-BF52x Blackfin Processor Hardware Reference 8-25 H ost DMA Port Registers Descriptions and bit diagrams for each of the MMRs discussed in this chapter are provided in Figure 8-12 through Figure 8-14. HOSTDP Control (HOST_CONTROL) Register The Host Control register (HOST_CONTROL), shown in Figure 8-12, is used to enable the HOSTDP module and to establish transfer modes of operation. HOSTDP Control Register (HOST_CONTROL) 15 14 13 12 11 10 0xFFC0 3400 0 0 0 0 0 1 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0400 HOSTDP Enable (HOSTDP_EN) HOSTDP Endian (HOSTDP_END) 8/16-bit mode (HOSTDP_DATA_SIZE) Burst DMA Requests (BDR) Enable Host Reads (EHR) Enable Host Writes (EHW) Bus Timeout Enable (BT_EN) HOSTDP Reset (HRST) Interrupt Mode (INT_MODE) HRDY Override (HRDY_OVR) Figure 8-12. HOSTDP Control Register Additional information for HOST_CONTROL register bits include: • HOSTDP Enable (HOSTDP_EN) This bit enables the HOSTDP interface. It is used as a control signal to steer the PPI’s resources to the HOSTDP. Always reset HOSTDP before disabling it. • Little/Big Endian (HOSTDP_END) 8-26 ADSP-BF52x Blackfin Processor Hardware Reference When set, this bit swaps the lower and upper byte of data when reading or writing the HOSTDP FIFO. A value of 0 represents little endian and a value of 1 represents big endian. • 8/16-bit Host Data Transfer (HOSTDP_DATA_SIZE) This bit sets the HOSTDP external data transfer width. This bit, along with HOSTDP_EN, is used as a control signal to steer the PPI resources to the HOSTDP. A value of 0 is 8-bit data and a value of 1 is 16-bit • HOSTDP Reset (HOSTDP_RST) This is a soft reset which does not affect the contents of HOST_CONTROL. Programming this bit causes the FIFO to flush, turns off the DMA channel, and returns the HOSTDP to a state where it waits for configuration. It also causes HOST_STATUS to clear to the same value as a hard reset with the exception of the BTE bit, which is always the same as BT_EN in HOST_CTL. A host DMA port reset does complete immediately, but completes only after the DAB state machine has moved to a particular idle state. This bit always reads as b#0. • HRDY Override (HRDY_OVR) Setting this bit high will force HRDY high. When set, HRDY will be driven high for all remaining FIFO transfers and the ALLOW_CNFG bit will be driven low to prevent accidental configurations. • Interrupt Mode (INT_MODE) When set this bit is used to select Interrupt mode. When cleared it selects Acknowledge Mode. • Bus Timeout Enable (BT_EN) ADSP-BF52x Blackfin Processor Hardware Reference 8-27 When set this bit enables the HOSTDP interrupt to occur when a current host transaction has not finished before a programmed timeout value occurs. • Enable HOSTDP Write (EHW) When set this bit enables HOSTDP writes to occur. When cleared, host writes appear to occur on the pins, but the actual write data is ignored. • Enable HOSTDP Read (EHR) When set this bit enables HOSTDP reads to occur. When cleared, host reads return zero data. • Burst DMA Requests (BDR) When set, as by default, the HOSTDP module groups multiple data words and requests DMA bursts to the DAB bus. When cleared, every individual data word requests a separate DMA transfer. HOSTDP Status (HOST_STATUS) Register The HOSTDP status register (HOST_STATUS), shown in Figure 8-13, holds the key status information of the HOSTDP. Bits in this register are read by the external host to query the status of the transaction. This register 8-28 ADSP-BF52x Blackfin Processor Hardware Reference can also be read and written through the PAB. Note the differences in how to write and clear bits as well as the many bits which are read-only. HOSTDP Status Register (HOST_STATUS) 15 14 13 12 11 10 0xFFC0 3404 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 0 0 Host Read Done (HOSTRD_DONE) Bus Timeout Enabled (BTE) DMA direction (DMA_DIR) Allow Config (ALLOW_CNFG) Host Interrupt Request (HIRQ) Reset = 0x000C DMA ready (DMA_RDY) FIFO full (FIFOFULL) FIFO empty (FIFOEMPTY) DMA complete (DMA_CMPLT) Host handshake (HSHK) HOSTDP timeout (HOSTDP_TOUT) Figure 8-13. HOSTDP Status Register Additional information for the HOST_STATUS register bits include: • DMA ready (DMA_RDY) - Read-Only This bit is set one cycle after the last control word (YMODIFY) is written to the DMA. The bit is cleared when the DMA_CMPLT bit is set by software. • FIFO full (FIFOFULL) - Read-Only This bit is set when the HOSTDP FIFO is full. • FIFO empty (FIFOEMPTY) - Read-Only This bit is set when the HOSTDP FIFO is empty. • DMA complete (DMA_CMPLT) - Write-1-to-set This bit must be set by software in the interrupt service routine called when the DMA operation is completed. This bit is cleared after the last control word (YMODIFY) is written to the DMA controller. ADSP-BF52x Blackfin Processor Hardware Reference 8-29 • HOSTDP handshake (HSHK) - Read/Write This bit is set and cleared by software and functions as a general-purpose handshake bit. It is often used to indicate an error to the host device. This bit does not control HOSTDP hardware and is cleared by the HOSTDP_RST bit. • HOSTDP timeout (HOSTDP_TOUT) - Write-one-to-clear This bit is set when the HOSTDP time-out occurs. When set, it requests a HOSTDP status interrupt. The interrupt service routine (ISR) must clear this bit. • Allow Configurations (ALLOW_CNFG) - Read-Only The host processor is required to poll this bit to see when the Host DMA port has been enabled and configuration writes are allowed. This bit is cleared when the last configuration word (YMODIFY) is written by the host. The bit is set again when the descriptor has been completely passed to the DMA channel. • HOSTDP Interrupt Request (HIRQ) - write-1-to-clear This bit is set when the host writes a HOSTDP IRQ control command to the configuration port. When set, this bit requests a HOSTDP status interrupt. The interrupt service routine (ISR) must write this bit to one to clear it. • DMA direction (DMA_DIR) - Read-Only This bit is cleared for read DMA and set for write DMA. It reflects the WNR bit in the DMA_CONFIG word. If a former work unit was active, the bit does not update until the DMA_CMPLT bit is set by software. • Bus Timeout Enabled (BTE) - Read-Only 8-30 ADSP-BF52x Blackfin Processor Hardware Reference This bit is just a copy of the BT_EN bit in the HOST_CONTROL register. The host can read this bit to determine if software has enabled the Bus Timeout feature. by This bit must be setDMAthe interrupt service routine software which is called when the is finished. • Host Read Done (HOSTRD_DONE) - Write-one-to-clear This bit is set when a Host Data read DMA work unit has completed. It must be cleared by software in the associated interrupt service routine. HOSTDP Timeout (HOST_TIMEOUT) Register The Host Bus Timeout feature is previously described in “Acknowledge Mode” on page 8-11. HOSTDP Timeout Register (HOST_TIMEOUT) 15 14 13 12 11 10 0xFFC0 3408 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Figure 8-14. HOSTDP Timeout Register The HOSTDP Time-out register (HOST_TIMEOUT), shown in Figure 8-14, holds the time-out value. A timer is loaded with this value when a host transaction is started. If HOSTDP doesn't respond with HRDY within the programmed amount of time, the HOSTDP_TOUT bit in the HOST_STATUS register is set and an interrupt is generated. This feature takes effect only when the BT_EN bit in the HOST_CONTROL register is set to 1. The length of the timeout generated by this register is governed by the following equation: timeout = 2 ^16 * HOST_TIMEOUT sclk ADSP-BF52x Blackfin Processor Hardware Reference 8-31 For example, using an SCLK frequency of 133 MHz and HOST_TIMEOUT = 0x7ED, the timeout period is approximately one second. Programming Examples Information for this section will be added when it becomes available. 8-32 ADSP-BF52x Blackfin Processor Hardware Reference 9 GENERAL-PURPOSE PORTS This chapter describes the general-purpose ports. Following an overview and a list of key features is a block diagram of the interface and a description of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview The ADSP-BF52x Blackfin processors feature a rich set of peripherals, which through a powerful pin multiplexing scheme, provides great flexibility to the external application space. Table 9-1shows all the peripheral signals that can be accessed off chip. Table 9-1. General-Purpose and Special Function Signals Peripheral 10/100 Ethernet Signals MAC1 MII interface (18) or RMII (11) Host DMA Data (16), control (5)) TWI Controller Data (1), clock (1) PPI Interface Data (16), frame sync (3), clock (1) SPI Interface Data (2), clock (1), slave select (1), slave enable (7) SPORTs Data (8), clock (4), frame sync (4) UARTs Data (4) Timers PWM/capture/clock (8), alternate clock input (4), alternate capture input (7) ADSP-BF52x Blackfin Processor Hardware Reference 9-1 Table 9-1. General-Purpose and Special Function Signals (Continued) Peripheral Signals General-Purpose I/O GPIO (48) Handshake MemDMA MemDMA request (2) 1 ADSP-BF526 and ADSP-BF527 only. F eatures The peripheral pins are functionally organized into general-purpose ports designated port F, port G, port H, and port J. Port F provides 16 pins: • UART1 signals • PPI data signals • Up/Down Counter • SPORT0 and SPORT1 signals • NFC data signals • Alternate timer inputs • Additional SPI slave selects • GPIOs Port G provides 16 pins: • SPORT0 signals • Primary SPI signals • UART0 and UART1 signals 9-2 ADSP-BF52x Blackfin Processor Hardware Reference • Host DMA control signals • Handshake memDMA request signals • Primary timer signals • MII/RMII pins • GPIOs Port H provides 16 pins: • MII/RMII signals (ADSP-BF526 and ADSP-BF527 processors only) • Alternate timer inputs • Additional SPI slave selects • Host DMA • NFC control and data signals • GPIOs Port J provides 4 pins: • TWI signals • PPI clock and frame sync signals • Timer clock and primary timer signals Interface Overview By default, all pins of port F, port G, and port H are in general-purpose I/O (GPIO) mode. Port J does not provide GPIO functionality. In this mode, a pin can function as either digital input, digital output, or interrupt input. See “General-Purpose I/O Modules” on page 9-13 for details. ADSP-BF52x Blackfin Processor Hardware Reference 9-3 Peripheral functionality must be explicitly enabled by the function enable registers (PORTF_FER, PORTG_FER, and PORTH_FER). The competing peripherals on port F, port G, and port H are controlled by the respective multiplexer control register (PORTF_MUX, PORTG_MUX, PORTH_MUX). chapter, the naming convention and bits In thiscase to represent F, G, or H. Forfor registersthe name uses a lower example, x represents PORTF_FER, PORTG_FER, and PORTH_FER. The bit name Px0 represents PF0, PG0, and PH0. This convention is used to discuss registers common to these three ports. PORTx_FER External Interface The external interface of the general-purpose ports are described in the following sections. Port F Structure Table 9-2 on page 9-5 shows the multiplexer scheme for port F. Port F is controlled by the PORTF_MUX and the PORTF_FER registers. Port F consists of 16 pins, referred to as PF0 to PF15, as shown in Table 9-2 on page 9-5. Besides the 16 GPIOs, this port supports all SPORT0 and SPORT1 signals. If the secondary data pins are not needed, the corresponding pins can be used for GP Timer purposes. SPORT1 pins are multiplexed with PPI data signals PPID15-8. Thus, with an 8-bit PPI configuration, no restrictions apply to SPORT1. All the input signals in the Additional Use column are enabled by their module only, regardless of the state of PORTx_MUX and PORTx_FER registers. 9-4 ADSP-BF52x Blackfin Processor Hardware Reference Any GPIO can be enabled individually and overrides the peripheral function if the respective bit in the PORTF_FER is cleared. Table 9-2. Port F Multiplexing Scheme PORTF_MUX 00 01 10 11 1st Function 2nd Function 3rd Function 4th Function Additional Use GPIO Bit[1:0] PPI D0 PPI D1 PPI D2 PPI D3 PPI D4 PPI D5 PPI D6 PPI D7 DR0PRI RFS0 RSCLK0 DT0PRI TFS0 TSCLK0 DT0SEC DR0SEC NFC D0 NFC D1 NFC D2 NFC D3 NFC D4 NFC D5 NFC D6 NFC D7 - PPI D8 PPI D9 DR1PRI RSCLK1 SPI_SSEL6 - PF8 PF9 Bit[5:4] PPI D10 RFS1 SPI_SSEL7 - PF10 Bit[7:6] PPI D11 TFS1 Bit[9:8] PPI D12 PPI D13 DT1PRI TSCLK1 Bit[11:10] PPI D14 PPI D15 DT1SEC DR1SEC Bit[3:2] Bit 12 of the TACLK0 TACLK1 TACI0 TACI1 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 - CZM PF11 SPI SSEL2 SPI SSEL3 - CDG CUD PF12 PF13 UART1TX UART1 RX - TACI3 PF14 PF15 register controls the input enable for the P PICLK/TMRCLK pin available in Port J. If bit 12 is set to 1, the PPICLK/TMRCLK is enabled. If bit 12 is set to 0, the PPICLK/TMRCLK is disabled. Bits 13-15 in the PORTF_MUX register are reserved. PORTF_MUX Port G Structure Table 9-3 on page 9-6 shows the multiplexer scheme for port G. It is controlled by the PORTG_MUX and the PORTG_FER registers. Port G consists of 16 pins, referred to as PG0 to PG15, as shown in Table 9-3. Besides the 16 GPIOs, this port supports both UART0 and ADSP-BF52x Blackfin Processor Hardware Reference 9-5 UART1 signals along with Host DMA control signals. If only one UART is required in the target application, the user has the option to enable either two additional timers or the handshake memDMA request pins. For more information, see “Handshaked Memory DMA Operation” in Chapter 6, Direct Memory Access. Table 9-3. Port G Multiplexing Scheme PORTG_MUX 00 01 1st Function 2nd Function 10 11 3rd Function 4th Function Additional GPIO Use - Bit[1:0] Bit[3:2] SPI SS SPI SCK SPI MISO SPI MOSI DR0SEC DT0SEC PG0 (HWAIT) SPI SSEL1 SPI SCK SPI MISO SPI MOSI - PG1 PG2 PG3 PG4 PG5 PG6 TMR1/ PPI FS2 DT0PRI TMR2 TMR1/ PPI FS2 PPI FS3 - TMR3 TMR4 DR0PRI RFS0 UART0 TX UART0 RX - TACI4 PG7 PG8 Bit[7:6] TMR5 RSCLK0 - TACI5 PG9 Bit[9:8] TMR6 TSCLK0 - TACI6 PG10 Bit[11:10] TMR7 DMAR1 DMAR0 TMR7 UART1TX UART1RX TACI2 PG11 PG12 PG13 TSCLK0 TFS0 RMII MDC HOST RD RMII PHYINT HOST_CE Bit[5:4] Bit[13:12] HOST WR HOST ACK HOST ADDR - PG14 PG15 TMR6 is When on PG14. an output, SPORT0 ignores the external TSCLK0 signal Special attention is required for the use of the timers with PPI enabled. Timer 0 and Timer 1 are typically used for PPI frame sync generation. 9-6 ADSP-BF52x Blackfin Processor Hardware Reference Any GPIO can be enabled individually and overrides the peripheral function if the respective bit in the PORTG_FER is cleared. Bits 14-15 in the PORTG_MUX register are reserved. Port H Structure Figure 9-4 shows the multiplexer scheme for port H. It is controlled by the PORTH_MUX and the PORTH_FER registers. Port H consists of 16 pins, referred to as PH0 to PH15, as shown in Figure 9-4. Besides the 16 GPIOs, this port supports MII/RMII signals (ADSP-BF526 and ADSP-BF527 processors only) along with Host DMA signals. This port also contains the NFC control and data signals. ADSP-BF52x Blackfin Processor Hardware Reference 9-7 Any GPIO can be enabled individually and overrides the peripheral function if the respective bit in the PORTH_FER is cleared. Table 9-4. Port H Multiplexing Scheme PORTH_MUX 00 01 10 11 1st Function 2nd Function 3rd Function 4th Function Additional Use GPIO Bit[1:0] NFC D0 NFC D1 NFC D2 NFC D3 NFC D4 NFC D5 NFC D6 NFC D7 RMII CRS RMII ERxER RMII MDIO RMII ETxEN RMII TxCLK RMII ETxD0 RMII ERxD0 RMII ETxD1 HOST D0 HOST D1 HOST D2 HOST D3 HOST D4 HOST D5 HOST D6 HOST D7 - Bit[3:2] SPI SSEL4 RMII ERxD1 HOST D8 - TACLK2 PH8 Bit[5:4] SPI SSEL5 ND_CE ND_WE_B ND_RE_B ND_BUSY ND_CLE ND_ALE MII ETxD2 MII ERxD2 MII ETxD3 MII ERxD3 MII ERxCLK MII ERxDV MII COL - TACLK3 PH9 PH10 PH11 PH12 PH13 PH14 PH15 Bits 6-15 in the 9-8 PORTH_MUX HOST D9 HOST D10 HOST D11 HOST D12 HOST D13 HOST D14 HOST D15 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 register are reserved. ADSP-BF52x Blackfin Processor Hardware Reference P ort J Structure Figure 9-5 shows the multiplexer scheme for port J. Port J does not provide GPIO functionality. This port contains TWI signals. Table 9-5. Port J Multiplexing Scheme PJ0: TMR0/PPI FS1 PJ1: PPI CLK/TMRCLK PJ2: SCL PJ3: SDA The PPICLK/TMRCLK PORTF_MUX pin is enabled by setting bit 12 in the register. I nput Tap Considerations Input taps are shown in Table 9-2 on page 9-5, Table 9-3 on page 9-6, and Table 9-4 on page 9-8 under the “Additional Use” column. When input taps (as well as GPIO based taps) are used with other functionality enabled on the GPIO pins, the signals seen by the input tap modules might be different from what is seen on the pins. This is because different pin functions have different signal requirements with respect to when the signal is latched, if at all. Because of this, input taps multiplexed on certain pins may behave differently than those on other pins, depending on which pin function is selected. The input taps will see different signals than at the pins in the following cases: • All GPIO inputs except PG0, PG1, PG2, PG9, PG10, PG11, PG12, PG13, PG14, PH3, PH4, PH5, PH7, PH9, PH11, PH13, PH15 when GPIO is tapped with PORTx_FER set to 1. • TACLK0 if PORTF_FER[4] = 1 and PORTF_MUX[1:0] = b#00 or b#01 • TACLK1 if PORTF_FER[5] = 1 and PORTF_MUX[1:0] = b#00 ADSP-BF52x Blackfin Processor Hardware Reference 9-9 • TACI0 if PORTF_FER[6] = 1 and PORTF_MUX[1:0] = b#00 or b#01 • TACI1 if PORTF_FER[7] = 1 and PORTF_MUX[1:0] = b#00 or b#01 • CZM if PORTF_FER[11] = 1 and PORTF_MUX[7:6] = b#00 or b#01 • CDG if PORTF_FER[12]= 1 and PORTF_MUX[9:8] = b#00 or b#01 • CUD if PORTF_FER[13] = 1 and PORTF_MUX[9:8] = b#00 • TACI3 if PORTF_FER[15] = 1 and PORTF_MUX[11:10] = b#00 or b#01 • TACI4 if PORTG_FER[8] = 1 and PORTG_MUX[5:4] = b#01 • TACLK2 if PORTH_FER[8] = 1 and PORTH_MUX[3:2] = b#01 Internal Interfaces Port control and GPIO registers are part of the system memory-mapped registers (MMRs). The addresses of the GPIO module MMRs appear in Appendix B. Core access to the GPIO configuration registers is through the system bus. The PORTx_MUX register controls the muxing schemes of port F, port G and port J. The function enable register (PORTF_FER, PORTG_FER, PORTH_FER) enables the peripheral functionality for each individual pin of port x. Internal Signals • and TACLK6 connect to buffered USB clock internally • TACLK5 and TACLK4 connect to CLKBUF signal internally • 9-10 TACLK7 TACI7 connects to the COUNTER0 TO output internally ADSP-BF52x Blackfin Processor Hardware Reference • TMR0 • TMR1 • TACI3 • PPI_CLK/TMRCLK is internally looped back to PPI_FS1 (to be used as internally generated frame sync). In this case, PPI_CLK is the clock input for the timer 0 module is internally looped back to PPI_FS2 (to be used as internally generated frame sync) In this case, PPI_CLK is the clock input for the timer 1 module (or TACI2) and TACI4 can be used for autobaud detection of UART can be used as a clock input for any of the timers • If TMR5 is output and PORTG_MUX[7:6] == 00 and the RSCLK0 input enable is active, TMR5 is the clock input for RSCLK0 • If RSCLK0 is output and PORTG_MUX[7:6] == 01 and the TMR5 input enable is active, RSCLK0 is the clock input for TMR5 • If TACI5 is selected for the timer 5 module, then the signal from the PG9 pin is fed to both RSCLK0 and TACI5 • If TMR6 is output and PG_MUX[9:8] == 00, and the TSCLK0 input enable is active, then TMR6 is the clock input for TSCLK0. • If TSCLK0 is output and PG_MUX[9:8] == 01 and the TMR6 input enable is active, then TSCLK0 is the clock input for TMR6. • If TACI6 is selected for the timer 6 module, the signal from the PG10 pin is fed to both TACI6 and TSCLK0. Performance/Throughput The PFx, PGx, and PHx pins are synchronized to the system clock (SCLK). When configured as outputs, the GPIOs can transition at every other SCLK cycle. ADSP-BF52x Blackfin Processor Hardware Reference 9-11 When configured as inputs, the overall system design should take into account the potential latency between the core and system clocks. Changes in the state of port pins have a latency of 3 SCLK cycles before being detectable by the processor. When configured for level-sensitive interrupt generation, there is a minimum latency of 4 SCLK cycles between the time the signal is asserted on the pin and the time that program flow is interrupted. When configured for edge-sensitive interrupt generation, an additional SCLK cycle of latency is introduced, giving a total latency of 5 SCLK cycles between the time the edge is asserted and the time that the core program flow is interrupted. Description of Operation The operation of the general-purpose ports is described in the following sections. Operation The GPIO pins on port F, port G, and port H can be controlled individually by the function enable registers (PORTx_FER). With a control bit in these registers cleared, the peripheral function is fully decoupled from the pin. It functions as a GPIO pin only. To drive the pin in GPIO output mode, set the respective direction bit in the PORTxIO_DIR register. To make the pin a digital input or interrupt input, enable its input driver in the PORTxIO_INEN register. configured inputs after reset. By default allG,peripheral pins areare in GPIOasmode. However, port F, port and port H pins GPIO input drivers are disabled to minimize power consumption and any need of external pulling resistors. When the control bit in the function enable registers (PORTx_FER) is set, the pin is set to its peripheral functionality and is no longer controlled by the GPIO module. However, the GPIO module can still sense the state of 9-12 ADSP-BF52x Blackfin Processor Hardware Reference the pin. When using a particular peripheral interface, pins required for the peripheral must be individually enabled. Keep the related function enable bit cleared if a signal provided by the peripheral is not required by your application. This allows it to be used in GPIO mode. General-Purpose I/O Modules The processor supports 48 bidirectional or general-purpose I/O (GPIO) signals. These 48 GPIOs are managed by three different GPIO modules, which are functionally identical. One is associated with port F, one with port G, and one with port H. Every module controls 16 GPIOs available through the pins PF15–0, PG15–0, and PH15–0. Each GPIO can be individually configured as either an input or an output by using the GPIO direction registers (PORTxIO_DIR). When configured as output, the GPIO data registers (PORTFIO, PORTGIO, and PORTHIO) can be directly written to specify the state of the GPIOs. The GPIO direction registers are read-write registers with each bit position corresponding to a particular GPIO. A logic 1 configures a GPIO as an output, driving the state contained in the GPIO data register if the peripheral function is not enabled by the function enable registers. A logic 0 configures a GPIO as an input. GPIO as corresponding bit Note when using thethe GPIO an input, the register. Otherwise, should also be set in input enable changes at the input pins will not be recognized by the processor. The GPIO input enable registers (PORTFIO_INEN, PORTGIO_INEN, and PORTHIO_INEN) are used to enable the input buffers on any GPIO that is being used as an input. Leaving the input buffer disabled eliminates the ADSP-BF52x Blackfin Processor Hardware Reference 9-13 need for pull-ups and pull-downs when a particular PFx, PGx, or PHx pin is not used in the system. By default, the input buffers are disabled. of a GPIO pin is enabled, the GPIO is not Once thetoinput driveran output anymore. Never enable the input allowed operate as driver (by setting PORTxIO_INEN bits) and the output driver (by setting PORTxIO_DIR bits) for the same GPIO. A write operation to any of the GPIO data registers sets the value of all GPIOs in this port that are configured as outputs. GPIOs configured as inputs ignore the written value. A read operation returns the state of the GPIOs defined as outputs and the sense of the inputs, based on the polarity and sensitivity settings, if their input buffers are enabled. Table 9-6 helps to interpret read values in GPIO mode, based on the settings of the PORTxIO_POLAR, PORTxIO_EDGE, and PORTxIO_BOTH registers. Table 9-6. GPIO Value Register Pin Interpretation POLAR EDGE BOTH Effect of MMR Settings 0 0 X Pin that is high reads as 1; pin that is low reads as 0 0 1 0 If rising edge occurred, pin reads as 1; otherwise, pin reads as 0 1 0 X Pin that is low reads as 1; pin that is high reads as 0 1 1 0 If falling edge occurred, pin reads as 1; otherwise, pin reads as 0 X 1 1 If any edge occurred, pin reads as 1; otherwise, pin reads as 0 GPIOs configured as one Forthese registers is sticky. edge-sensitive,ita isreadback of 1 fromuntil of That is, once set it remains set cleared by user code. For level-sensitive GPIOs, the pin state is checked every cycle, so the readback value will change when the original level on the pin changes. The state of the output is reflected on the associated pin only if the function enable bit in the PORTx_FER register is cleared. 9-14 ADSP-BF52x Blackfin Processor Hardware Reference Write operations to the GPIO data registers modify the state of all GPIOs of a port. In cases where only one or a few GPIOs need to be changed, the user may write to the GPIO set registers, PORTxIO_SET, the GPIO clear registers, PORTxIO_CLEAR, or to the GPIO toggle registers, PORTxIO_TOGGLE instead. While a direct write to a GPIO data register alters all bits in the register, writes to a GPIO set register can be used to set a single or a few bits only. No read-modify-write operations are required. The GPIO set registers are write-1-to-set registers. All 1s contained in the value written to a GPIO set register sets the respective bits in the GPIO data register. The 0s have no effect. For example, assume that PF0 is configured as an output. Writing 0x0001 to the GPIO set register drives a logic 1 on the PF0 pin without affecting the state of any other PFx pins. The GPIO set registers are typically also used to generate GPIO interrupts by software. Read operations from the GPIO set registers return the content of the GPIO data registers. The GPIO clear registers provide an alternative port to manipulate the GPIO data registers. While a direct write to a GPIO data register alters all bits in the register, writes to a GPIO clear register can be used to clear individual bits only. No read-modify-write operations are required. The clear registers are write-1-to-clear registers. All 1s contained in the value written to the GPIO clear register clears the respective bits in the GPIO data register. The 0s have no effect. For example, assume that PF4 and PF5 are configured as outputs. Writing 0x0030 to the PORTFIO_CLEAR register drives a logic 0 on the PF4 and PF5 pins without affecting the state of any other PFx pins. the service If an edge-sensitive pin generates an interrupt request,respective routine must acknowledge the request by clearing the GPIO latch. This is usually performed through the clear registers. Read operations from the GPIO clear registers return the content of the GPIO data registers. ADSP-BF52x Blackfin Processor Hardware Reference 9-15 The GPIO toggle registers provide an alternative port to manipulate the GPIO data registers. While a direct write to a GPIO data register alters all bits in the register, writes to a toggle register can be used to toggle individual bits. No read-modify-write operations are required. The GPIO toggle registers are write-1-to-toggle registers. All 1s contained in the value written to a GPIO toggle register toggle the respective bits in the GPIO data register. The 0s have no effect. For example, assume that PG1 is configured as an output. Writing 0x0002 to the PORTGIO_TOGGLE register changes the pin state (from logic 0 to logic 1, or from logic 1 to logic 0) on the PG1 pin without affecting the state of any other PGx pins. Read operations from the GPIO toggle registers return the content of the GPIO data registers. The state of the GPIOs can be read through any of these data, set, clear, or toggle registers. However, the returned value reflects the state of the input pin only if the proper input enable bit in the PORTxIO_INEN register is set. Note that GPIOs can still sense the state of the pin when the function enable bits in the PORTx_FER registers are set. Since function enable registers and GPIO input enable registers reset to zero, no external pull-ups or pull-downs are required on the unused pins of port F, port G, and port H. GPIO Interrupt Processing Each GPIO can be configured to generate an interrupt. The processor can sense up to 48 asynchronous off-chip signals, requesting interrupts through five interrupt channels. To make a pin function as an interrupt pin, the associated input enable bit in the PORTxIO_INEN register must be set. The function enable bit in the PORTx_FER register is typically cleared. Then, an interrupt request can be generated according to the state of the pin (either high or low), an edge transition (low to high or high to low), or on both edge transitions (low to high and high to low). Input sensitivity is defined on a per-bit basis by the GPIO polarity registers (PORTFIO_POLAR, PORTGIO_POLAR, and PORTHIO_POLAR), and the GPIO interrupt sensitivity registers (PORTFIO_EDGE, PORTGIO_EDGE, and PORTHIO_EDGE). If configured 9-16 ADSP-BF52x Blackfin Processor Hardware Reference for edge sensitivity, the GPIO set on both edges registers (PORTFIO_BOTH, PORTGIO_BOTH, and PORTHIO_BOTH) let the interrupt request generate on both edges. The GPIO polarity registers are used to configure the polarity of the GPIO input source. To select active high or rising edge, set the bits in the GPIO polarity register to 0. To select active low or falling edge, set the bits in the GPIO polarity register to 1. This register has no effect on GPIOs that are defined as outputs. The contents of the GPIO polarity registers are cleared at reset, defaulting to active high polarity. The GPIO interrupt sensitivity registers are used to configure each of the inputs as either a level-sensitive or an edge-sensitive source. When using an edge-sensitive mode, an edge detection circuit is used to prevent a situation where a short event is missed because of the system clock rate. The GPIO interrupt sensitivity register has no effect on GPIOs that are defined as outputs. The contents of the GPIO interrupt sensitivity registers are cleared at reset, defaulting to level sensitivity. The GPIO set on both edges registers are used to enable interrupt generation on both rising and falling edges. When a given GPIO has been set to edge-sensitive in the GPIO interrupt sensitivity register, setting the respective bit in the GPIO set on both edges register to both edges results in an interrupt being generated on both the rising and falling edges. This register has no effect on GPIOs that are defined as level-sensitive or as outputs. See Table 9-6 on page 9-14 for information on how the GPIO set on both edges register interacts with the GPIO polarity and GPIO interrupt sensitivity registers. Each of the three GPIO modules provides two independent interrupt channels. Identical in functionality, these are called interrupt A and interrupt B. Both interrupt channels have their own mask register which lets you assign the individual GPIOs to none, either, or both interrupt channels. ADSP-BF52x Blackfin Processor Hardware Reference 9-17 Since all mask registers reset to zero, none of the GPIOs is assigned any interrupt by default. Each GPIO represents a bit in each of these registers. Setting a bit means enabling the interrupt on this channel. Interrupt A and interrupt B operate independently. For example, writing 1 to a bit in the mask interrupt A register does not affect interrupt channel B. This facility allows GPIOs to generate GPIO interrupt A, GPIO interrupt B, both GPIO interrupts A and B, or neither. A GPIO interrupt is generated by a logical OR of all unmasked GPIOs for that interrupt. For example, if PF0 and PF1 are both unmasked for GPIO interrupt channel A, GPIO interrupt A will be generated when triggered by PF0 or PF1. The interrupt service routine must evaluate the GPIO data register to determine the signaling interrupt source. Figure 9-1 illustrates the interrupt flow of any GPIO module's interrupt A channel. interrupts, the When using either rising or falling edge-triggeredcorresponding interrupt condition must be cleared each time a interrupt is serviced by writing 1 to the appropriate bit in the GPIO clear register. At reset, all interrupts are masked and disabled. Similarly to the GPIOs themselves, the mask register can either be written through the GPIO mask data registers (PORTxIO_MASKA, PORTxIO_MASKB) or be controlled by the mask A/mask B set, clear and toggle registers. The GPIO mask interrupt set registers (PORTxIO_MASKA_SET, PORTxIO_MASKB_SET) provide an alternative port to manipulate the GPIO mask interrupt registers. While a direct write to a mask interrupt register alters all bits in the register, writes to a mask interrupt set register can be used to set a single or a few bits only. No read-modify-write operations are required. The mask interrupt set registers are write-1-to-set registers. All ones contained in the value written to the mask interrupt set register set the 9-18 ADSP-BF52x Blackfin Processor Hardware Reference respective bits in the mask interrupt register. The zeroes have no effect. Writing a one to any bit enables the interrupt for the respective GPIO. START IS THE GPIO ENABLED IN PORTxIO_MASKA_D? YES IS THE GPIO SET AS AN OUTPUT IN PORTxIO_DIR? NO (INPUT) IS THE INPUT DRIVER ENABLED IN PORTxIO_INEN? YES (OUTPUT) IS THE GPIO SET TO ONE? YES YES NO (LEVEL SENSITIVE) IS THE GPIO EDGE-SENSITIVE AS DEFINED IN PORTxIO_EDGE? IS THE INPUT AN ACTIVE LEVEL AS DEFINED IN PORTxIO_POLAR? YES YES (EDGE SENSITIVE) IS EDGE DETECTED AS DEFINED IN PORTxIO_POLAR & PORTxIO_BOTH? YES GENERATE INTERRUPT A Figure 9-1. GPIO Interrupt Generation Flow for Interrupt Channel A ADSP-BF52x Blackfin Processor Hardware Reference 9-19 The GPIO mask interrupt clear registers (PORTxIO_MASKA_CLEAR, PORTxIO_MASKB_CLEAR) provide an alternative port to manipulate the GPIO mask interrupt registers. While a direct write to a mask interrupt register alters all bits in the register, writes to the mask interrupt clear register can be used to clear a single bit or a few bits only. No read-modify-write operations are required. The mask interrupt clear registers are write-1-to-clear registers. All ones contained in the value written to the mask interrupt clear register clear the respective bits in the mask interrupt register. The zeroes have no effect. Writing a one to any bit disables the interrupt for the respective GPIO. The GPIO mask interrupt toggle registers (PORTxIO_MASKA_TOGGLE, provide an alternative port to manipulate the GPIO mask interrupt registers. While a direct write to a mask interrupt register alters all bits in the register, writes to a mask interrupt toggle register can be used to toggle a single bit or a few bits only. No read-modify-write operations are required. PORTxIO_MASKB_TOGGLE) The mask interrupt toggle registers are write-1-to-clear registers. All ones contained in the value written to the mask interrupt toggle register toggle the respective bits in the mask interrupt register. The zeroes have no effect. Writing a one to any bit toggles the interrupt for the respective GPIO. Figure 9-1 illustrates the interrupt flow of any GPIO module’s interrupt A channel. The interrupt B channel behaves identically. All GPIOs assigned to the same interrupt channel are OR’ed. If multiple GPIOs are assigned to the same interrupt channel, it is up to the interrupt service routine to evaluate the GPIO data registers to determine the signaling interrupt source. Although each GPIO module provides two independent interrupt channels, the interrupt A channels of port F and port G are OR’ed as shown in 9-20 ADSP-BF52x Blackfin Processor Hardware Reference Figure 9-2. Therefore the total number of GPIO interrupt channels is five. IRQ45 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTFIO_MASKA_D PG15 PG14 PG13 PG12 PG11 PG10 PG9 PG8 PG7 PG6 IRQ40 PG5 PG4 PG3 PG2 PG1 IRQ46 PORTGIO_MASKA_D PG0 PORTFIO_MASKB_D PORTHIO_MASKB_D PH15 PH14 PH13 PH12 PH11 PH10 PH9 PH8 PH7 PH6 IRQ29 PH5 PH4 PH3 PH2 PH1 IRQ41 PORTHIO_MASKA_D PH0 PORTGIO_MASKB_D IRQ31 Figure 9-2. GPIO Interrupt Channels ADSP-BF52x Blackfin Processor Hardware Reference 9-21 P rogramming Model Figure 9-3 and Figure 9-4 on page 9-23 show the programming model for the general-purpose ports. GPIO OR PERIPHERAL? PERIPHERAL WRITE PORTx_MUX, WRITE PORTx_FER TO SET APPROPRIATE PERIPHERAL BITS GPIO SEE PERIPHERAL FOR MORE DETAILS WRITE PORTx_FER TO CLEAR APPROPRIATE PFx, PGx, AND PHx BITS OUTPUT GPIO OUTPUT OR INPUT? WRITE PORTxIO_DIR TO SET APPROPRIATE BITS FOR OUTPUT DIRECTION INPUT WRITE PORTxIO_DIR TO CLEAR APPROPRIATE BITS FOR INPUT DIRECTION SET OR CLEAR GPIO? SET CLEAR WRITE PORTxIO_INEN TO SET APPROPRIATE BITS TO ENABLE INPUT DRIVERS DIRECTION WRITE PORTxIO_CLEAR TO SET APPROPRIATE BITS TO LOWER INDIVIDUAL GPIO A WRITE PORTxIO_SET TO SET APPROPRIATE BITS TO RAISE INDIVIDUAL GPIO Figure 9-3. GPIO Flow Chart (Part 1 of 2) 9-22 ADSP-BF52x Blackfin Processor Hardware Reference A EDGE WRITE PORTxIO_EDGE TO SET APPROPRIATE BITS FOR EDGE SENSITIVITY EDGE OR LEVEL SENSITIVE? LEVEL EDGE RISING/ FALLING OR BOTH? WRITE PORTxIO_EDGE TO CLEAR APPROPRIATE BITS FOR LEVEL SENSITIVITY RISING OR FALLING BOTH LEVEL HIGH OR LOW? HIGH LOW WRITE PORTxIO_BOTH TO SET APPROPRIATE BITS FOR BOTH EDGE SENSITIVITY WRITE PORTxIO_BOTH TO CLEAR APPROPRIATE BITS FOR EDGE SENSITIVITY WRITE PORTxIO_POLAR TO SET APPROPRIATE BITS FOR LOW LEVEL SENSITIVITY EDGE RISING OR FALLING? WRITE PORTxIO_POLAR TO CLEAR APPROPRIATE BITS FOR HIGH LEVEL SENSITIVITY RISING FALLING WRITE PORTxIO_POLAR TO SET APPROPRIATE BITS FOR FALLING EDGE SENSITIVITY WRITE PORTxIO_POLAR TO CLEAR APPROPRIATE BITS FOR RISING EDGE SENSITIVITY INTERRUPT ABILITY? NO SOFTWARE CAN INTERROGATE PORTx_DATA BITS TO DETERMINE EVENTS YES WRITE EITHER PORTxIO_MASKA, PORTxIO_MASKB, PORTxIO_MASKA_SET, PORTxIO_MASKB_SET, PORTxIO_MASKA_TOGGLE, OR PORTxIO_MASKB_TOGGLE TO SET APPROPRIATE BITS ON WHICH TO GENERATE AN INTERRUPT INTERRUPTS MUST THEN BE CONFIGURED AT THE SYSTEM INTERRUPT CONTROLLER AND CORE EVENT CONTROLLER Figure 9-4. GPIO Flow Chart (Part 2 of 2) ADSP-BF52x Blackfin Processor Hardware Reference 9-23 G PIO Drive Hysteresis Control The ADSP-BF52x contains additional registers that control input hysteresis for Port F, Port G and Port H. These are also included for pins other than GPIOs. Figure 9-5 on page 9-24 to Figure 9-9 on page 9-27 show the bit descriptions of these registers. Portx Control (PORTx_HYSTERESIS) Register This register configures Schmitt triggering (SE) for the PORTx inputs. The Schmitt trigger can be set only for pin groups, classified by the pin muxing controls. For each controlled group of pins, 00 implies disable and 01 implies enable Schmitt trigger. Combinations of 1x are reserved. Port F Hysteresis Register (PORTF_HYSTERESIS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 PF7 to PF0 SE Reserved PF9 to PF8 SE PF15 to PF14 SE PF10 SE PF13 to PF12 SE PF11 SE Figure 9-5. Port F Hysteresis Register 9-24 ADSP-BF52x Blackfin Processor Hardware Reference Port G Hysteresis Register (PORTG_HYSTERESIS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 PG15 to PG14 SE PG0 SE PG13 to PG11 SE PG4 to PG1 SE PG10 SE PG6 to PG5 SE PG9 SE PG8 to PG7 SE Figure 9-6. Port G Hysteresis Register Port H Hysteresis Register (PORTH_HYSTERESIS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Reset = 0x0000 PH7 to PH0 SE PH8 SE PH15 to PH9 SE Figure 9-7. Port H Hysteresis Register ADSP-BF52x Blackfin Processor Hardware Reference 9-25 H ysteresis Control Register This register sets the Schmitt trigger (SE) for various BF52x signals. For each controlled group of pins, 00 implies disable and 01 implies enable Schmitt trigger. Combinations of 1x are reserved. Non-GPIO Hysteresis Control Register (NONGPIO_HYSTERESIS) 15 14 13 12 11 10 0xFFC0 3288 Reserved 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 TMR0_FS1_PPICLK_SE SE for pin PPI_FS1/TMR0 and PPICLK NMI_RST_BMODE_SE SE for pins NMI, RESET and BMODE JTAG_SE SE for JTAG input pins Figure 9-8. Non-GPIO Hysteresis Control Register 9-26 ADSP-BF52x Blackfin Processor Hardware Reference T WI Drive Strength Control Register This register sets the drive strength and tolerance for the TWI signals on the ADSP-BF52x as specified in the diagram. TWI Drive Strength Control Register (NONGPIO_DRIVE) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 Reset = 0x0555 Reserved Reserved TWI_DT VDDEXT/VBUSTWI for TWI pins SCL and SDA 000: VDDEXT = 3.3V, VBUSTWI 001: VDDEXT = 1.8V, VBUSTWI 010: VDDEXT = 2.5V, VBUSTWI 011: VDDEXT = 1.8V, VBUSTWI 100: VDDEXT = 3.3V, VBUSTWI 101: VDDEXT = 1.8V, VBUSTWI 110: VDDEXT = 2.5V, VBUSTWI 111: Reserved = = = = = = = 3.3V 1.8V 3.3V 3.3V 5V 2.5V 2.5V Figure 9-9. TWI Drive Strength Control Register Memory-Mapped GPIO Registers The GPIO registers are part of the system memory-mapped registers (MMRs). Figure 9-10 through Figure 9-30 on page 9-42 illustrate the GPIO registers. The addresses of the programmable flag MMRs appear in Appendix A, “System MMR Assignments”. ADSP-BF52x Blackfin Processor Hardware Reference 9-27 P ort Multiplexer Control Register (PORTx_MUX) Port F Multiplexer Control Register (PORTF_MUX) 15 14 13 12 11 10 Port F 0xFFC0 3210 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Reserved PPICLK/TMRCLK Enable 0 - Enable PPICLK/TMRCLK on Port J 1 - Disable PPICLK/TMRCLK on Port J PF15to14_MUX PF13to12_MUX PF7to0_MUX PF9to8_MUX PF10_MUX PF11_MUX For all bit fields: 00 = first peripheral function 01 = first alternate peripheral function 10 = second alternate peripheral function 11 = Reserved Refer to Table 9-2 on page 9-5 to Table 9-4 on page 9-8 for reserved bits in the PORTF_MUX register. Figure 9-10. Port F Multiplexer Control Register Port G Multiplexer Control Register (PORTG_MUX) 15 14 13 12 11 10 Port G 0xFFC0 3214 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Reserved PG4to1_MUX PG15to14_MUX PG6to5_MUX PG13to11_MUX PG8to7_MUX PG10_MUX PG9_MUX For all bit fields: 00 = first peripheral function 01 = first alternate peripheral function 10 = second alternate peripheral function 11 = Reserved Refer to Table 9-2 on page 9-5 to Table 9-4 on page 9-8 for reserved bits in the PORTG_MUX register. Figure 9-11. Port G Multiplexer Control Register 9-28 ADSP-BF52x Blackfin Processor Hardware Reference Port H Multiplexer Control Register (PORTH_MUX) 15 14 13 12 11 10 Port H 0xFFC0 3218 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Reset = 0x0000 PH7to0_MUX PH8_MUX PH15to9_MUX For all bit fields: 00 = first peripheral function 01 = first alternate peripheral function 10 = second alternate peripheral function 11 = Reserved Refer to Table 9-2 on page 9-5 to Table 9-4 on page 9-8 for reserved bits in the PORTH_MUX register. Figure 9-12. Port H Multiplexer Control Register ADSP-BF52x Blackfin Processor Hardware Reference 9-29 F unction Enable Registers (PORTx_FER) Function Enable Registers (PORTx_FER) For all bits, 0 - GPIO mode, 1 - Enable peripheral function 15 14 13 12 11 10 Port F: 0xFFC0 3200 Port G: 0xFFC0 3204 Port H: 0xFFC0 3208 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Px0 Px1 Px2 Px3 Px15 Px4 Px14 Px5 Px13 Px6 Px12 Px7 Px11 Px8 Px10 Px9 Figure 9-13. Function Enable Registers 9-30 ADSP-BF52x Blackfin Processor Hardware Reference G PIO Direction Registers (PORTxIO_DIR) GPIO Direction Registers (PORTxIO_DIR) For all bits, 0 - Input, 1 - Output 15 14 13 12 11 10 Port F: 0xFFC0 0730 Port G: 0xFFC0 1530 Port H: 0xFFC0 1730 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Px0 Direction Px1 Direction Px2 Direction Px 3 Direction Px15 Direction Px14 Direction Px13 Direction Px12 Direction Px11 Direction Px10 Direction Px4 Direction Px5 Direction Px6 Direction Px7 Direction Px8 Direction Px9 Direction Figure 9-14. GPIO Direction Registers ADSP-BF52x Blackfin Processor Hardware Reference 9-31 G PIO Input Enable Registers (PORTxIO_INEN) GPIO Input Enable Registers (PORTxIO_INEN) For all bits, 0 - Input Buffer Disabled, 1 - Input Buffer Enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Port F: 0xFFC0 0740 Port G: 0xFFC0 1540 Port H: 0xFFC0 1740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Px0 Input Enable Px1 Input Enable Px2 Input Enable Px3 Input Enable Px15 Input Enable Px4 Input Enable Px14 Input Enable Px5 Input Enable Px13 Input Enable Px6 Input Enable Px12 Input Enable Px7 Input Enable Px 8 Input Enable Px9 Input Enable Px11 Input Enable Px10 Input Enable Figure 9-15. GPIO Input Enable Registers GPIO Data Registers (PORTxIO) GPIO Data Registers (PORTxIO) 1 - Set, 0 - Clear 15 14 13 12 11 10 Port F: 0xFFC0 0700 Port G: 0xFFC0 1500 Port H: 0xFFC0 1700 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Program Px0 Program Px1 Program Px2 Program Px3 Program Px15 Program Px4 Program Px14 Program Px5 Program Px13 Program Px6 Program Px12 Program Px7 Program Px8 Program Px9 Program Px11 Program Px10 Figure 9-16. GPIO Data Registers 9-32 ADSP-BF52x Blackfin Processor Hardware Reference G PIO Set Registers (PORTxIO_SET) GPIO Set Registers (PORTxIO_SET) Write-1-to-set 15 14 13 12 11 10 Port F: 0xFFC0 0708 Port G: 0xFFC0 1508 Port H: 0xFFC0 1708 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Set Px0 Set Px1 Set Px2 Set Px3 Set Px15 Set Px4 Set Px14 Set Px5 Set Px13 Set Px6 Set Px12 Set Px7 Set Px8 Set Px9 Set Px11 Set Px10 Figure 9-17. GPIO Set Registers GPIO Clear Registers (PORTxIO_CLEAR) GPIO Clear Registers (PORTxIO_CLEAR) Write-1-to-clear 15 14 13 12 11 10 Port F: 0xFFC0 0704 Port G: 0xFFC0 1504 Port H: 0xFFC0 1704 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Clear Px0 Clear Px1 Clear Px2 Clear Px3 Clear Px15 Clear Px4 Clear Px14 Clear Px5 Clear Px13 Clear Px6 Clear Px12 Clear Px7 Clear Px8 Clear Px9 Clear Px11 Clear Px10 Figure 9-18. GPIO Clear Registers ADSP-BF52x Blackfin Processor Hardware Reference 9-33 G PIO Toggle Registers (PORTxIO_TOGGLE) GPIO Toggle Registers (PORTxIO_TOGGLE) Write-1-to-toggle 15 14 13 12 11 10 Port F: 0xFFC0 070C Port G: 0xFFC0 150C Port H: 0xFFC0 170C 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Toggle Px0 Toggle Px1 Toggle Px2 Toggle Px 3 Toggle Px15 Toggle Px4 Toggle Px14 Toggle Px5 Toggle Px13 Toggle Px6 Toggle Px12 Toggle Px7 Toggle Px11 Toggle Px8 Toggle Px9 Toggle Px10 Figure 9-19. GPIO Toggle Registers GPIO Polarity Registers (PORTxIO_POLAR) GPIO Polarity Registers (PORTxIO_POLAR) For all bits, 0 - Active high or rising edge, 1 - Active low or falling edge 15 14 13 12 11 10 Port F: 0xFFC0 0734 Port G: 0xFFC0 153 4 Port H: 0xFFC0 1734 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Px0 Polarity Px1 Polarity Px2 Polarity Px3 Polarity Px15 Polarity Px4 Polarity Px14 Polarity Px5 Polarity Px13 Polarity Px6 Polarity Px12 Polarity Px7 Polarity Px8 Polarity Px9 Polarity Px11 Polarity Px10 Polarity Figure 9-20. GPIO Polarity Registers 9-34 ADSP-BF52x Blackfin Processor Hardware Reference I nterrupt Sensitivity Registers (PORTxIO_EDGE) Interrupt Sensitivity Registers (PORTxIO_EDGE) For all bits, 0 - Level, 1 - Edge 15 14 13 12 11 10 Port F: 0xFFC0 0738 Port G: 0xFFC0 1538 Port H: 0xFFC0 1738 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Px0 Sensitivity Px1 Sensitivity Px2 Sensitivity Px3 Sensitivity Px15 Sensitivity Px4 Sensitivity Px14 Sensitivity Px5 Sensitivity Px13 Sensitivity Px6 Sensitivity Px12 Sensitivity Px7 Sensitivity Px8 Sensitivity Px9 Sensitivity Px11 Sensitivity Px10 Sensitivity Figure 9-21. Interrupt Sensitivity Registers GPIO Set on Both Edges Registers (PORTxIO_BOTH) GPIO Set on Both Edges Registers (PORTxIO_BOTH) For all bits when enabled for edge-sensitivity, 0 - Single edge, 1 - Both edges 15 14 13 12 11 10 Port F: 0xFFC0 073C Port G: 0xFFC0 153C Port H: 0xFFC0 173C 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Px0 Both Edges Px1 Both Edges Px2 Both Edges Px3 Both Edges Px15 Both Edges Px4 Both Edges Px14 Both Edges Px5 Both Edges Px13 Both Edges Px6 Both Edges Px12 Both Edges Px7 Both Edges Px8 Both Edges Px9 Both Edges Px11 Both Edges Px10 Both Edges Figure 9-22. GPIO Set on Both Edges Registers ADSP-BF52x Blackfin Processor Hardware Reference 9-35 G PIO Mask Interrupt Registers (PORTxIO_MASKA/B) GPIO Mask Interrupt A Registers (PORTxIO_MASKA) For all bits, 1 - Enable, 0 - Disable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Port F: 0xFFC0 0710 Port G: 0xFFC0 1510 Port H: 0xFFC0 1710 0 0 0 0 0 Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Px15 Interrupt A Enable Enable Enable Enable Enable Px14 Px13 Px12 Px11 Px10 Interrupt Interrupt Interrupt Interrupt Interrupt Reset = 0x0000 A A A A A Px0 Px1 Px2 Px3 Px4 Px5 Px6 Px7 Px8 Px9 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt A A A A A A A A A A Figure 9-23. GPIO Mask Interrupt A Registers GPIO Mask Interrupt B Registers (PORTxIO_MASKB) For all bits, 1 - Enable 15 14 13 12 11 10 Enable Enable Enable Enable Enable Enable Px15 Px14 Px13 Px12 Px11 Px10 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt 9 8 7 6 5 4 3 2 1 0 0 Port F: 0xFFC0 0720 Port G: 0xFFC0 1520 Port H: 0xFFC0 1720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable B B B B B B Px0 Px1 Px2 Px3 Px4 Px5 Px6 Px7 Px8 Px9 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt B B B B B B B B B B Figure 9-24. GPIO Mask Interrupt B Registers 9-36 ADSP-BF52x Blackfin Processor Hardware Reference G PIO Mask Interrupt Set Registers (PORTxIO_MASKA/B_SET) GPIO Mask Interrupt A Set Registers (PORTxIO_MASKA_SET) For all bits, 1 - Set 15 14 13 12 11 10 Set Set Set Set Set Set Px15 Px14 Px13 Px12 Px11 Px10 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt A A A A A A 9 8 7 6 5 4 3 2 1 0 0 Port F: 0xFFC0 0718 Port G: 0xFFC0 1518 Port H: 0xFFC0 1718 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Enable Enable Enable Enable Enable Enable Reset = 0x0000 Set Set Set Set Set Set Set Set Set Set Px0 Px1 Px2 Px3 Px4 Px5 Px6 Px7 Px8 Px9 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt A A A A A A A A A A Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Figure 9-25. GPIO Mask Interrupt A Set Registers ADSP-BF52x Blackfin Processor Hardware Reference 9-37 GPIO Mask Interrupt B Set Registers (PORTxIO_MASKB_SET) For all bits, 1 - Set 15 14 13 12 11 10 Port F: 0xFFC0 0728 Port G: 0xFFC0 1528 Port H: 0xFFC0 1728 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Set Px0 Interrupt B Enable Set Px1 Interrupt B Enable Set Px2 Interrupt B Enable Set Px15 Interrupt B Enable Set Px3 Interrupt B Enable Set Px14 Interrupt B Enable Set Px4 Interrupt B Enable Set Px13 Interrupt B Enable Set Px5 Interrupt B Enable Set Px6 Interrupt B Enable Set Px12 Interrupt B Enable Set Px11 Interrupt B Enable Set Px10 Interrupt B Enable Set Px7 Interrupt B Enable Set Px8 Interrupt B Enable Set Px9 Interrupt B Enable Figure 9-26. GPIO Mask Interrupt B Set Registers 9-38 ADSP-BF52x Blackfin Processor Hardware Reference G PIO Mask Interrupt Clear Registers (PORTxIO_MASKA/B_CLEAR) GPIO Mask Interrupt A Clear Registers (PORTxIO_MASKA_CLEAR) For all bits, 1 - Clear 15 14 13 12 11 10 Port F: 0xFFC0 0714 Port G: 0xFFC0 1514 Port H: 0xFFC0 1714 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clear Px15 Interrupt A Enable Clear Px14 Interrupt A Enable Clear Px1 3 Interrupt A Enable Clear Px12 Interrupt A Enable Clear Px11 Interrupt A Enable Clear Px10 Interrupt A Enable Reset = 0x0000 Clear Px0 Interrupt A Enable Clear Px1 Interrupt A Enable Clear Px2 Interrupt A Enable Clear Px3 Interrupt A Enable Clear Px4 Interrupt A Enable Clear Px5 Interrupt A Enable Clear Px6 Interrupt A Enable Clear Px7 Interrupt A Enable Clear Px8 Interrupt A Enable Clear Px9 Interrupt A Enable Figure 9-27. GPIO Mask Interrupt A Clear Registers ADSP-BF52x Blackfin Processor Hardware Reference 9-39 GPIO Mask Interrupt B Clear Registers (PORTxIO_MASKB_CLEAR) For all bits, 1 - Clear 15 14 13 12 11 10 Port F: 0xFFC0 0724 Port G: 0xFFC0 1524 Port H: 0xFFC0 1724 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Clear Px0 Interrupt B Enable Clear Px1 Interrupt B Enable Clear Px2 Interrupt B Enable Clear Px15 Interrupt B Enable Clear Px14 Interrupt B Enable Clear Px3 Interrupt B Enable Clear Px4 Interrupt B Enable Clear Px5 Interrupt B Enable Clear Px6 Interrupt B Enable Clear Px7 Interrupt B Enable Clear Px8 Interrupt B Enable Clear Px9 Interrupt B Enable Clear Px13 Interrupt B Enable Clear Px12 Interrupt B Enable Clear Px11 Interrupt B Enable Clear Px10 Interrupt B Enable Figure 9-28. GPIO Mask Interrupt B Clear Registers 9-40 ADSP-BF52x Blackfin Processor Hardware Reference G PIO Mask Interrupt Toggle Registers (PORTxIO_MASKA/B_TOGGLE) GPIO Mask Interrupt A Toggle Registers (PORTxIO_MASKA_TOGGLE) For all bits, 1 - Toggle 15 14 13 12 11 10 Port F: 0xFFC0 071C Port G: 0xFFC0 151C Port H: 0xFFC0 171C 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Toggle Px15 Interrupt A Enable Toggle Px14 Interrupt A Enable Toggle Px13 Interrupt A Enable Toggle Px12 Interrupt A Enable Toggle Px11 Interrupt A Enable Toggle Px10 Interrupt A Enable Reset = 0x0000 Toggle Px0 Interrupt A Enable Toggle Px1 Interrupt A Enable Toggle Px2 Interrupt A Enable Toggle Px3 Interrupt A Enable Toggle Px4 Interrupt A Enable Toggle Px5 Interrupt A Enable Toggle Px6 Interrupt A Enable Toggle Px7 Interrupt A Enable Toggle Px8 Interrupt A Enable Toggle Px9 Interrupt A Enable Figure 9-29. GPIO Mask Interrupt A Toggle Registers ADSP-BF52x Blackfin Processor Hardware Reference 9-41 GPIO Mask Interrupt B Toggle Registers (PORTxIO_MASKB_TOGGLE) For all bits, 1 - Toggle 15 14 13 12 11 10 Port F: 0xFFC0 072C Port G: 0xFFC0 152C Port H: 0xFFC0 172C 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Toggle Px0 Interrupt B Enable Toggle Px1 Interrupt B Enable Toggle Px15 Interrupt B Enable Toggle Px14 Interrupt B Enable Toggle Px2 Interrupt B Enable Toggle Px3 Interrupt B Enable Toggle Px4 Interrupt B Enable Toggle Px5 Interrupt B Enable Toggle Px6 Interrupt B Enable Toggle Px7 Interrupt B Enable Toggle Px8 Interrupt B Enable Toggle Px9 Interrupt B Enable Toggle Px13 Interrupt B Enable Toggle Px12 Interrupt B Enable Toggle Px11 Interrupt B Enable Toggle Px10 Interrupt B Enable Figure 9-30. GPIO Mask Interrupt B Toggle Registers P rogramming Examples Listing 9-1 provides examples for using the general-purpose ports. Listing 9-1. General-Purpose Ports /* set port f function enable register to GPIO (not peripheral) */ p0.l = lo(PORTF_FER); p0.h = hi(PORTF_FER); R0.h = 0x0000; r0.l = 0x0000; 9-42 ADSP-BF52x Blackfin Processor Hardware Reference w[p0] = r0; /* set port f direction register to enable some GPIO as output, remaining are input */ p0.l = lo(PORTFIO_DIR); p0.h = hi(PORTFIO_DIR); r0.h = 0x0000; r0.l = 0x0FC0; w[p0] = r0; ssync; /* set port f clear register */ p0.l = lo(PORTFIO_CLEAR); p0.h = hi(PORTFIO_CLEAR); r0.l = 0xFC0; w[p0] = r0; ssync; /* set port f input enable register to enable input drivers of some GPIOs */ p0.l = lo(PORTFIO_INEN); p0.h = hi(PORTFIO_INEN); r0.h = 0x0000; r0.l = 0x003C; w[p0] = r0; ssync; /* set port f polarity register */ p0.l = lo(PORTFIO_POLAR); p0.h = hi(PORTFIO_POLAR); r0 = 0x00000; w[p0] = r0; ssync; ADSP-BF52x Blackfin Processor Hardware Reference 9-43 9-44 ADSP-BF52x Blackfin Processor Hardware Reference 1 0 GENERAL-PURPOSE TIMERS This chapter describes the general-purpose (GP) timer module. Following an overview and a list of key features is a description of operation and functional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Specific Information for the ADSP-BF52x For details regarding the number of GP timers for the ADSP-BF52x product, please refer to the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. For GP Timer interrupt vector assignments, refer to Table 5-3 on page 5-18 in Chapter 5, “System Interrupts”. To determine how each of the GP Timers is multiplexed with other functional pins, refer to Table 9-2 on page 9-5 through Table 9-5 on page 9-9 in Chapter 9, “General-Purpose Ports”. For a list of MMR addresses for each GP Timer, refer to Appendix A, “System MMR Assignments”. GP timer behavior for the ADSP-BF52x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Behavior for the ADSP-BF52x Processor” on page 10-57 ADSP-BF52x Blackfin Processor Hardware Reference 10-1 O verview The general-purpose timers support the following operating modes: • Single-shot mode for interval timing and single pulse generation • Pulse width modulation (PWM) generation with consistent update of period and pulse width values • External signal capture mode with consistent update of period and pulse width values • External event counter mode Feature highlights are: • Synchronous operation • Consistent management of period and pulse width values • Interaction with PPI module for video frame sync operation • Autobaud detection for UART module • Graceful bit pattern termination when stopping • Support for center-aligned PWM patterns • Error detection on implausible pattern values • All read and write accesses to 32-bit registers are atomic • Every timer has its dedicated interrupt request output • Unused timers can function as edge-sensitive pin interrupts The internal structure of the individual timers is illustrated by Figure 10-1, which shows the details of timer 0 as a representative example. The other timers have identical structure. 10-2 ADSP-BF52x Blackfin Processor Hardware Reference PAB 16 TIMER 0 TIMER0_CONFIG LEADING EDGE TIMER0_PERIOD (WRITE) 32 32 ENABLE LATCH TIMER0_PERIOD (READ) 32 COMPARATOR SCLK TMRCLK TACLK0 TMR0 PERIOD MATCH TIMDIS0 TRUN0 INTERRUPT CONTROL 32 TIMER0_COUNTER TIMEN0 OVERFLOW TOVF_ERR0 TIMIL0 32 WIDTH MATCH COMPARATOR 32 PIN CONTROL TMR0 TIMER0_WIDTH (READ) EDGE DETECTOR 32 TIMER0_WIDTH (WRITE) TACI0 TRAILING EDGE Figure 10-1. Internal Timer Structure E xternal Interface Every timer has a dedicated TMR pin. If enabled, the TMR pins output the single-pulse or PWM signals generated by the timer. The TMR pins function as input in capture and counter modes. Polarity of the signals is programmable. When clocked internally, the clock source is the processor’s peripheral clock (SCLK). Assuming the peripheral clock is running at 133 MHz, the maximum period for the timer count is ((232-1) / 133 MHz) = 32.2 seconds. ADSP-BF52x Blackfin Processor Hardware Reference 10-3 Clock and capture input pins are sampled every SCLK cycle. The duration of every low or high state must be at least one SCLK. Therefore, the maximum allowed frequency of timer input signals is SCLK/2. Internal Interface Timer registers are always accessed by the core through the 16-bit PAB bus. Hardware ensures that all read and write operations from and to 32-bit timer registers are atomic. Every timer has a dedicated interrupt request output that connects to the system interrupt controller (SIC). Description of Operation The core of every timer is a 32-bit counter, that can be interrogated through the read-only TIMER_COUNTER register. Depending on the mode of operation, the counter is reset to either 0x0000 0000 or 0x0000 0001 when the timer is enabled. The counter always counts upward. Usually, it is clocked by SCLK. In PWM mode it can be clocked by the alternate clock input TACLK or, alternatively, the common timer clock input TMRCLK. In counter mode, the counter is clocked by edges on the TMR input pin. The significant edge is programmable. After 232-1 clocks, the counter overflows. This is reported by the overflow/error bit TOVF_ERR in the TIMER_STATUS register. In PWM and counter mode, the counter is reset by hardware when its content reaches the values stored in the TIMER_PERIOD register. In capture mode, the counter is reset by leading edges on the TMR or TACI input pin. If enabled, these events cause the interrupt latch TIMIL in the TIMER_STATUS register to be set and issue a system interrupt request. The TOVF_ERR and TIMIL latches are sticky and should be cleared by software using W1C (write-1-to-clear) operations to clear the interrupt request. The global 10-4 ADSP-BF52x Blackfin Processor Hardware Reference register is 32-bits wide. A single atomic 32-bit read can report the status of all corresponding timers. TIMER_STATUS Before a timer can be enabled, its mode of operation is programmed in the individual timer-specific TIMER_CONFIG register. Then, the timers are started by writing a "1" to the representative bits in the global TIMER_ENABLE register. The TIMER_ENABLE register can be used to enable all timers simultaneously. The register contains W1S (write-1-to-set) control bits, one for each timer. Correspondingly, the TIMER_DISABLE register contains W1C control bits to allow simultaneous or independent disabling of the timers. Either register can be read to check the enable status of the timers. A "1" indicates that the corresponding timer is enabled. The timer starts counting three SCLK cycles after the TIMEN bit is set. While the PWM mode is used to generate PWM patterns, the capture mode (WDTH_CAP) is designed to “receive” PWM signals. A PWM pattern is represented by a pulse width and a signal period. This is described by the TIMER_WIDTH and TIMER_PERIOD register pair. In capture mode these registers are read only. Hardware always captures both values. Regardless of whether in PWM or capture mode, shadow buffers always ensure consistency between the TIMER_WIDTH and TIMER_PERIOD values. In PWM mode, hardware performs a plausibility check by the time the timer is enabled. If there is an error, the type is reported by the TIMER_CONFIG register and signalled by the TOVF_ERR bit. I nterrupt Processing Each timer can generate a single interrupt. The resulting interrupt signals are routed to the system interrupt controller block for prioritization and masking. The timer status (TIMER_STATUS) register latches the timer interrupts to provide a means for software to determine the interrupt source. ADSP-BF52x Blackfin Processor Hardware Reference 10-5 Figure 10-2 shows the interrupt structure of the timers. ILLEGAL TIMER_WIDTH COUNT = WIDTH COUNT = PERIOD ILLEGAL TIMER _PERIOD TRAILING EDGE COUNTER OVERFLOW LEADING EDGE PERIOD_CNT TMODE PWM_OUT WDTH_CAP EXT_CLK TMODE 1 0 1 0 PWM_OUT WDTH_CAP EXT_CLK INTERRUPT EVENT ERROR EVENT IRQ_ENA PWM_OUT SET TOVF_ERR RST SET TIMER IRQ TIMIL SYSTEM INTERRUPT CONTROLLER PROCESSOR CORE RST RESET MMR WRITE TO TIMER_STATUS TIMIL WRITE DATA TOVF_ERR WRITE DATA Figure 10-2. Timers Interrupt Structure To enable interrupt generation, set the IRQ_ENA bit and unmask the interrupt source in the IMASK and SIC_IMASK registers. To poll the TIMIL bit 10-6 ADSP-BF52x Blackfin Processor Hardware Reference without interrupt generation, set IRQ_ENA but leave the interrupt masked at the system level. If enabled by IRQ_ENA, interrupt requests are also generated by error conditions as reported by the TOVF_ERR bits. The system interrupt controller enables flexible interrupt handling. All timers may or may not share the same CEC interrupt channel, so that a single interrupt routine services more than one timer. In PWM mode, multiple timers may run with the same period settings and issue their interrupt requests simultaneously. In this case, the service routine might clear all TIMIL latch bits at once by writing 0x000F 000F to the TIMER_STATUS register. If interrupts are enabled, make sure that the interrupt service routine (ISR) clears the TIMIL bit in the TIMER_STATUS register before the RTI instruction executes. This ensures that the interrupt is not reissued. Remember that writes to system registers are delayed. If only a few instructions separate the TIMIL clear command from the RTI instruction, an extra SSYNC instruction may be inserted. In EXT_CLK mode, reset the TIMIL bit in the TIMER_STATUS register at the very beginning of the interrupt service routine to avoid missing any timer events. Illegal States Every timer features an error detection circuit. It handles overflow situations but also performs pulse width vs. period plausibility checks. Errors are reported by the TOVF_ERR bits in the TIMER_STATUS register and the ERR_TYP bit field in the individual TIMER_CONFIG registers. Table 10-1 provides a summary of error conditions, using these terms: • Startup. The first clock period during which the timer counter is running after the timer is enabled by writing TIMER_ENABLE. • Rollover. The time when the current count matches the value in TIMER_PERIOD and the counter is reloaded with the value "1". ADSP-BF52x Blackfin Processor Hardware Reference 10-7 • Overflow. The timer counter was incremented instead of doing a rollover when it was holding the maximum possible count value of 0xFFFF FFFF. The counter does not have a large enough range to express the next greater value and so erroneously loads a new value of 0x0000 0000. • Unchanged. No new error. • When ERR_TYP is unchanged, it displays the previously reported error code or 00 if there has been no error since this timer was enabled. • When TOVF_ERR is unchanged, it reads "0" if there has been no error since this timer was enabled, or if software has performed a W1C to clear any previous error. If a previous error has not been acknowledged by software, TOVF_ERR reads "1". Software should read TOVF_ERR to check for an error. If TOVF_ERR is set, software can then read ERR_TYP for more information. Once detected, software should write "1" to clear TOVF_ERR to acknowledge the error. The following table can be read as: “In mode __ at event __, if TIMER_PERIOD is __ and TIMER_WIDTH is __, then ERR_TYP is __ and TOVF_ERR is __.” do not from Startup error conditionsrollover prevent the timerdo notstarting. Similarly, overflow and error conditions stop the timer. Illegal cases may cause unwanted behavior of the TMR pin. 10-8 ADSP-BF52x Blackfin Processor Hardware Reference Mode Event TIMER_WIDTH ERR_TYP TOVF_ERR TIMER_PERIOD Table 10-1. Overview of Illegal States PWM_OUT, PERIOD_CNT = 1 Startup == 0 (No boundary condition == 1 tests performed on TIMER_WIDTH) 2 Anything b#10 Set Anything b#10 Set Anything No No change change Rollover == 0 Anything b#10 Set == 1 Anything b#11 Set 2 == 0 b#11 Set 2 < TIMER_PERIOD No No change change 2 TIMER_PERIOD b#11 Set Overflow, not possible unless there is also another error, such as TIMER_PERIOD == 0 Anything Anything b#01 Set Startup Anything == 0 b#01 Set PWM_OUT, PERIOD_CNT = 0 This case is not detected at startup, but results in an overflow error once the counter counts through its entire range. Anything 1 No No change change Rollover Rollover is not possible in this mode. Overflow, not possible unless there is also another error, such as TIMER_WIDTH == 0 Anything Anything ADSP-BF52x Blackfin Processor Hardware Reference b#01 Set 10-9 TOVF_ERR ERR_TYP Event TIMER_WIDTH Mode TIMER_PERIOD Table 10-1. Overview of Illegal States (Continued) WDTH_CAP Startup TIMER_PERIOD and TIMER_WIDTH are read-only in this mode, no error possible. Rollover TIMER_PERIOD and TIMER_WIDTH are read-only in this mode, no error possible. Overflow Anything Anything b#01 Set Startup == 0 Anything b#10 Set 1 Anything No No change change == 0 Anything b#10 1 Anything No No change change Anything Anything b#01 EXT_CLK Rollover Overflow, not possible unless there is also another error, such as TIMER_PERIOD == 0 Set Set M odes of Operation The following sections provide a functional description of the general-purpose timers in various operating modes. Pulse Width Modulation (PWM_OUT) Mode Use the PWM_OUT mode for PWM signal or single-pulse generation, for interval timing or for periodic interrupt generation. Figure 10-3 illustrates PWM_OUT mode. 10-10 ADSP-BF52x Blackfin Processor Hardware Reference Setting the TMODE field to b#01 in the TIMER_CONFIG register enables PWM_OUT mode. Here, the TMR pin is an output, but it can be disabled by setting the OUT_DIS bit in the TIMER_CONFIG register. In PWM_OUT mode, the bits PULSE_HI, PERIOD_CNT, IRQ_ENA, OUT_DIS, CLK_SEL, EMU_RUN, and TOGGLE_HI enable orthogonal functionality. They may be set individually or in any combination, although some combinations are not useful (such as TOGGLE_HI = 1 with OUT_DIS = 1 or PERIOD_CNT = 0). DATA BUS TIMER_PERIOD TMRCLK 1 TACLK TIMER_WIDTH 0 PWM_CLK CLOCK RESET TIMER_COUNTER SCLK TIN_SEL 1 0 CLK_SEL EQUAL? YES EQUAL? TIMER_ENABLE YES ASSERT PULSE_HI TOGGLE_HI OUT_DIS 1 INTERRUPT 0 DEASSERT PWMOUT LOGIC TMR pin PERIOD_CNT Figure 10-3. Timer Flow Diagram, PWM_OUT Mode ADSP-BF52x Blackfin Processor Hardware Reference 10-11 Once a timer has been enabled, the timer counter register is loaded with a starting value. If CLK_SEL = 0, the timer counter starts at 0x1. If CLK_SEL = 1, it is reset to 0x0 as in EXT_CLK mode. The timer counts upward to the value of the timer period register. For either setting of CLK_SEL, when the timer counter equals the timer period, the timer counter is reset to 0x1 on the next clock. In PWM_OUT mode, the PERIOD_CNT bit controls whether the timer generates one pulse or many pulses. When PERIOD_CNT is cleared (PWM_OUT single pulse mode), the timer uses the TIMER_WIDTH register, generates one asserting and one deasserting edge, then generates an interrupt (if enabled) and stops. When PERIOD_CNT is set (PWM_OUT continuous pulse mode), the timer uses both the TIMER_PERIOD and TIMER_WIDTH registers and generates a repeating (and possibly modulated) waveform. It generates an interrupt (if enabled) at the end of each period and stops only after it is disabled. A setting of PERIOD_CNT = 0 counts to the end of the width; a setting of PERIOD_CNT = 1 counts to the end of the period. a The modes. Bend to set the operation sure registers are read-only in some field in the TIMER_CONFIG register to b#01 before writing to these registers. TIMER_PERIOD TIMER_WIDTH TMODE Output Pad Disable The output pin can be disabled in PWM_OUT mode by setting the OUT_DIS bit in the TIMER_CONFIG register. The TMR pin is then three-stated regardless of the setting of PULSE_HI and TOGGLE_HI. This can reduce power consumption when the output signal is not being used. The TMR pin can also be disabled by the function enable and the multiplexer control registers. Single Pulse Generation If the PERIOD_CNT bit is cleared, the PWM_OUT mode generates a single pulse on the TMR pin. This mode can also be used to implement a precise delay. 10-12 ADSP-BF52x Blackfin Processor Hardware Reference The pulse width is defined by the TIMER_WIDTH register, and the TIMER_PERIOD register is not used. See Figure 10-4. At the end of the pulse, the timer interrupt latch bit TIMIL is set, and the timer is stopped automatically. No writes to the TIMER_DISABLE register are required in this mode. If the PULSE_HI bit is set, an active high pulse is generated on the TMR pin. If PULSE_HI is not set, the pulse is active low. EXAMPLE TIMER ENABLE AND AUTOMATIC DISABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 0) SCLK TIMER_WIDTH 3 TIMER_COUNTER X 1 2 3 TIMEN TRUN TMR, PULSE_HI = 0 TMR, PULSE_HI = 1 W1S TO TIMER_ENABLE Figure 10-4. Timer Enable and Automatic Disable Timing The pulse width may be programmed to any value from 1 to (232-1), inclusive. Pulse Width Modulation Waveform Generation If the PERIOD_CNT bit is set, the internally clocked timer generates rectangular signals with well-defined period and duty cycle (PWM patterns). This mode also generates periodic interrupts for real-time signal processing. ADSP-BF52x Blackfin Processor Hardware Reference 10-13 The 32-bit TIMER_PERIOD and TIMER_WIDTH registers are programmed with the values required by the PWM signal. When the timer is enabled in this mode, the TMR pin is pulled to a deasserted state each time the counter equals the value of the pulse width register, and the pin is asserted again when the period expires (or when the timer gets started). To control the assertion sense of the TMR pin, the PULSE_HI bit in the corresponding TIMER_CONFIG register is used. For a low assertion level, clear this bit. For a high assertion level, set this bit. When the timer is disabled in PWM_OUT mode, the TMR pin is driven to the deasserted level. Figure 10-5 shows timing details. EXAMPLE TIMER ENABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 1) SCLK TIMER_PERIOD 4 4 4 TIMER_WIDTH 1 1 1 TIMER_COUNTER X 1 2 3 4 1 2 3 TIMEN TRUN TMR pin, PULSE_HI = 0 TMR pin, PULSE_HI = 1 W1S TO TIMER_ENABLE Figure 10-5. Timer Enable Timing If enabled, a timer interrupt is generated at the end of each period. An interrupt service routine must clear the interrupt latch bit (TIMIL) and might alter period and/or width values. In PWM applications, the software needs to update period and pulse width values while the timer is 10-14 ADSP-BF52x Blackfin Processor Hardware Reference running. When software updates either the TIMER_PERIOD or TIMER_WIDTH registers, the new values are held by special buffer registers until the period expires. Then the new period and pulse width values become active simultaneously. Reads from TIMER_PERIOD and TIMER_WIDTH registers return the old values until the period expires. The TOVF_ERR status bit signifies an error condition in PWM_OUT mode. The TOVF_ERR bit is set if TIMER_PERIOD = 0 or TIMER_PERIOD = 1 at startup, or when the timer counter register rolls over. It is also set if the timer pulse width register is greater than or equal to the timer period register by the time the counter rolls over. The ERR_TYP bits are set when the TOVF_ERR bit is set. Although the hardware reports an error if the TIMER_WIDTH value equals the TIMER_PERIOD value, this is still a valid operation to implement PWM patterns with 100% duty cycle. If doing so, software must generally ignore the TOVL_ERR flags. Pulse width values greater than the period value are not recommended. Similarly, TIMER_WIDTH = 0 is not a valid operation. Duty cycles of 0% are not supported. To generate the maximum frequency on the TMR output pin, set the period value to “2” and the pulse width to "1". This makes the pin toggle each SCLK clock, producing a duty cycle of 50%. The period may be programmed to any value from 2 to (232 – 1), inclusive. The pulse width may be programmed to any value from 1 to (period – 1), inclusive. PULSE_HI Toggle Mode The waveform produced in PWM_OUT mode with PERIOD_CNT = 1 normally has a fixed assertion time and a programmable deassertion time (via the TIMER_WIDTH register). When two or more timers are running synchro- ADSP-BF52x Blackfin Processor Hardware Reference 10-15 nously by the same period settings, the pulses are aligned to the asserting edge as shown in Figure 10-6. PERIOD 1 TOGGLE_HI = 0 PULSE_HI = 1 TMR0 ACTIVE HIGH TOGGLE_HI = 0 PULSE_HI = 1 TMR1 ACTIVE HIGH TOGGLE_HI = 0 PULSE_HI = 1 TMR2 ACTIVE HIGH TIMER ENABLE Figure 10-6. Example of Timers With Pulses Aligned to Asserting Edge The TOGGLE_HI mode enables control of the timing of both the asserting and deasserting edges of the output waveform produced. The phase between the asserting edges of two timer outputs is programmable. The effective state of the PULSE_HI bit alternates every period. The adjacent active low and active high pulses, taken together, create two halves of a symmetrical rectangular waveform. The effective waveform is active high when PULSE_HI is set and active low when PULSE_HI is cleared. The value of the TOGGLE_HI bit has no effect unless the mode is PWM_OUT and PERIOD_CNT = 1. In TOGGLE_HI mode, when PULSE_HI is set, an active low pulse is generated in the first, third, and all odd-numbered periods, and an active high pulse is generated in the second, fourth, and all even-numbered periods. When PULSE_HI is cleared, an active high pulse is generated in the first, third, and all odd-numbered periods, and an active low pulse is generated in the second, fourth, and all even-numbered periods. The deasserted state at the end of one period matches the asserted state at the beginning of the next period, so the output waveform only transitions 10-16 ADSP-BF52x Blackfin Processor Hardware Reference when Count = Pulse Width. The net result is an output waveform pulse that repeats every two counter periods and is centered around the end of the first period (or the start of the second period). Figure 10-7 shows an example with three timers running with the same period settings. When software does not alter the PWM settings at run-time, the duty cycle is 50%. The values of the TIMER_WIDTH registers control the phase between the signals. WAVEFORM PERIOD 1 WAVEFORM PERIOD 2 TIMER PERIOD 1 ACTIVE HIGH ACTIVE LOW ACTIVE HIGH ACTIVE HIGH ACTIVE LOW ACTIVE HIGH ACTIVE LOW TOGGLE_HI = 1 PULSE_HI = 1 TIMER PERIOD 4 ACTIVE LOW TOGGLE_HI = 1 PULSE_HI = 1 TIMER PERIOD 3 ACTIVE LOW TOGGLE_HI = 1 PULSE_HI = 1 TIMER PERIOD 2 ACTIVE HIGH ACTIVE LOW ACTIVE HIGH TMR0 TMR1 TMR2 TIMER ENABLE Figure 10-7. Three Timers With Same Period Settings ADSP-BF52x Blackfin Processor Hardware Reference 10-17 Similarly, two timers can generate non-overlapping clocks, by center-aligning the pulses while inverting the signal polarity for one of the timers (see Figure 10-8). WAVEFORM PERIOD 1 WAVEFORM PERIOD 2 TIMER PERIOD 1 TIMER PERIOD 2 TIMER PERIOD 3 TIMER PERIOD 4 ACTIVE HIGH ACTIVE LOW ACTIVE HIGH ACTIVE LOW ACTIVE LOW ACTIVE HIGH ACTIVE LOW ACTIVE HIGH TOGGLE_HI = 1 PULSE_HI = 0 TMR0 TOGGLE_HI = 1 PULSE_HI = 1 TMR1 TIMER ENABLE Figure 10-8. Two Timers With Non-overlapping Clocks When TOGGLE_HI = 0, software updates the TIMER_PERIOD and TIMER_WIDTH registers once per waveform period. When TOGGLE_HI = 1, software updates the TIMER_PERIOD and TIMER_WIDTH registers twice per waveform. Period values are half as large. In odd-numbered periods, write (Period – Width) instead of Width to the TIMER_WIDTH register in order to obtain center-aligned pulses. For example, if the pseudo-code when TOGGLE_HI = 0 is: int period, width; for (;;) { period = generate_period(...) ; width = generate_width(...) ; waitfor (interrupt) ; write (TIMER_PERIOD, period) ; 10-18 ADSP-BF52x Blackfin Processor Hardware Reference write (TIMER_WIDTH, width) ; } Then when TOGGLE_HI = 1, the pseudo-code would be: int period, width ; int per1, per2, wid1, wid2 ; for (;;) { period = generate_period(...) ; width = generate_width(...) ; per1 = period/2 ; wid1 = width/2 ; per2 = period/2 ; wid2 = width/2 ; waitfor (interrupt) ; write (TIMER_PERIOD, per1) ; write (TIMER_WIDTH, per1 - wid1) ; waitfor (interrupt) ; write (TIMER_PERIOD, per2) ; write (TIMER_WIDTH, wid2) ; } As shown in this example, the pulses produced do not need to be symmetric (wid1 does not need to equal wid2). The period can be offset to adjust the phase of the pulses produced (per1 does not need to equal per2). The TRUN bit in the TIMER_STATUS register is updated only at the end of even-numbered periods in TOGGLE_HI mode. When TIMER_DISABLE is writ- ADSP-BF52x Blackfin Processor Hardware Reference 10-19 ten to "1", the current pair of counter periods (one waveform period) completes before the timer is disabled. As when TOGGLE_HI = 0, errors are reported if the TIMER_PERIOD register is either set to “0” or "1", or when the width value is greater than or equal to the period value. Externally Clocked PWM_OUT By default, the timer is clocked internally by SCLK. Alternatively, if the CLK_SEL bit in the TIMER_CONFIG register is set, the timer is clocked by PWM_CLK. The PWM_CLK is normally input from the TACLK pin, but may be taken from the common TMRCLK pin regardless of whether the timers are configured to work with the PPI. Different timers may receive different signals on their PWM_CLK inputs, depending on configuration. As selected by the PERIOD_CNT bit, the PWM_OUT mode either generates pulse width modulation waveforms or generates a single pulse with pulse width defined by the TIMER_WIDTH register. When CLK_SEL is set, the counter resets to 0x0 at startup and increments on each rising edge of PWM_CLK. The TMR pin transitions on rising edges of PWM_CLK. There is no way to select the falling edges of PWM_CLK. In this mode, the PULSE_HI bit controls only the polarity of the pulses produced. The timer interrupt may occur slightly before the corresponding edge on the TMR pin (the interrupt occurs on an SCLK edge, the pin transitions on a later PWM_CLK edge). It is still safe to program new period and pulse width values as soon as the interrupt occurs. After a period expires, the counter rolls over to a value of 0x1. The PWM_CLK clock waveform is not required to have a 50% duty cycle, but the minimum PWM_CLK clock low time is one SCLK period, and the minimum PWM_CLK clock high time is one SCLK period. This implies the maximum PWM_CLK clock frequency is SCLK/2. 10-20 ADSP-BF52x Blackfin Processor Hardware Reference The alternate timer clock inputs (TACLK) are enabled when a timer is in PWM_OUT mode with CLK_SEL = 1 and TIN_SEL = 0, without regard to the content of the multiplexer control and function enable registers. Using PWM_OUT Mode With the PPI Some timers may be used to generate frame sync signals for certain PPI modes. For detailed instructions on how to configure the timers for use with the PPI, refer to “Frame Synchronization in GP Modes” in the “Parallel Peripheral Interface” chapter of the ADSP-BF52x Blackfin Processor Hardware Reference. Stopping the Timer in PWM_OUT Mode In all PWM_OUT mode variants, the timer treats a disable operation (W1C to TIMER_DISABLE) as a “stop is pending” condition. When disabled, it automatically completes the current waveform and then stops cleanly. This prevents truncation of the current pulse and unwanted PWM patterns at the TMR pin. The processor can determine when the timer stops running by polling for the corresponding TRUN bit in the TIMER_STATUS register to read "0" or by waiting for the last interrupt (if enabled). Note the timer cannot be reconfigured (TIMER_CONFIG cannot be written to a new value) until after the timer stops and TRUN reads "0". In PWM_OUT single pulse mode (PERIOD_CNT = 0), it is not necessary to write TIMER_DISABLE to stop the timer. At the end of the pulse, the timer stops automatically, the corresponding bit in TIMER_ENABLE (and TIMER_DISABLE) is cleared, and the corresponding TRUN bit is cleared. See Figure 10-4 on page 10-13. To generate multiple pulses, write a "1" to TIMER_ENABLE, wait for the timer to stop, then write another "1" to TIMER_ENABLE. In continuous PWM generation mode (PWM_OUT, PERIOD_CNT = 1) software can stop the timer by writing to the TIMER_DISABLE register. To prevent the ongoing PWM pattern from being stopped in an unpredictable way, the timer does not stop immediately when the corresponding "1" has been ADSP-BF52x Blackfin Processor Hardware Reference 10-21 written to the TIMER_DISABLE register. Rather, the write simply clears the enable latch and the timer still completes the ongoing PWM patterns gracefully. It stops cleanly at the end of the first period when the enable latch is cleared. During this final period the TIMEN bit returns "0", but the TRUN bit still reads as a "1". If the TRUN bit is not cleared explicitly, and the enable latch can be cleared and re-enabled all before the end of the current period will continue to run as if nothing happened. Typically, software should disable a PWM_OUT timer and then wait for it to stop itself. Figure 10-9 shows detailed timing. EXAMPLE TIMER DISABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 1) SCLK TIMER_PERIOD 7 7 7 TIMER_WIDTH 5 5 5 TIMER_COUNTER 7 1 2 3 4 5 6 7 TIMEN TRUN TMR PIN, PULSE_HI = 0 TMR PIN, PULSE_HI = 1 W1C TO TIMER_DISABLE Figure 10-9. Timer Disable Timing If necessary, the processor can force a timer in PWM_OUT mode to abort immediately. Do this by first writing a "1" to the corresponding bit in TIMER_DISABLE, and then writing a "1" to the corresponding TRUN bit in TIMER_STATUS. This stops the timer whether the pending stop was waiting for the end of the current period (PERIOD_CNT = 1) or the end of the cur- 10-22 ADSP-BF52x Blackfin Processor Hardware Reference rent pulse width (PERIOD_CNT = 0). This feature may be used to regain immediate control of a timer during an error recovery sequence. Use this feature carefully, because it may corrupt the PWM pattern generated at the pin. TMR When a timer is disabled, the TIMER_COUNTER register retains its state; when a timer is re-enabled, the timer counter is reinitialized based on the operating mode. The TIMER_COUNTER register is read-only. Software cannot overwrite or preset the timer counter value directly. Pulse Width Count and Capture (WDTH_CAP) Mode Use the WDTH_CAP mode, often simply called “capture mode,” to measure pulse widths on the TMR or TACI input pins, or to “receive” PWM signals. Figure 10-10 shows a flow diagram for WDTH_CAP mode. In WDTH_CAP mode, the TMR pin is an input pin. The internally clocked timer is used to determine the period and pulse width of externally applied rectangular waveforms. Setting the TMODE field to b#10 in the TIMER_CONFIG register enables this mode. When enabled in this mode, the timer resets the count in the TIMER_COUNTER register to 0x0000 0001 and does not start counting until it detects a leading edge on the TMR pin. When the timer detects the first leading edge, it starts incrementing. When it detects a trailing edge of a waveform, the timer captures the current 32-bit value of the TIMER_COUNTER register into the width buffer. At the next leading edge, the timer transfers the current 32-bit value of the TIMER_COUNTER register into the period buffer. The count register is reset to 0x0000 0001 again, and the timer continues counting and capturing until it is disabled. In this mode, software can measure both the pulse width and the pulse period of a waveform. To control the definition of leading edge and trail- ADSP-BF52x Blackfin Processor Hardware Reference 10-23 DATA BUS TIMER_PERIOD TIMER_WIDTH SCLK RESET TIMER_COUNTER PULSE_HI PULSE_HI TMR PIN TMR PIN LEADING EDGE DETECT TIMER_ENABLE TRAILING EDGE DETECT TOVF_ERR PERIOD_CNT INTERRUPT LOGIC INTERRUPT Figure 10-10. Timer Flow Diagram, WDTH_CAP Mode ing edge of the TMR pin, the PULSE_HI bit in the TIMER_CONFIG register is set or cleared. If the PULSE_HI bit is cleared, the measurement is initiated by a falling edge, the content of the counter register is captured to the pulse width buffer on the rising edge, and to the period buffer on the next falling edge. When the PULSE_HI bit is set, the measurement is initiated by a rising edge, the counter value is captured to the pulse width buffer on the falling edge, and to the period buffer on the next rising edge. 10-24 ADSP-BF52x Blackfin Processor Hardware Reference In WDTH_CAP mode, these three events always occur at the same time: 1. The TIMER_PERIOD register is updated from the period buffer. 2. The TIMER_WIDTH register is updated from the width buffer. 3. The TIMIL bit gets set (if enabled) but does not generate an error. The PERIOD_CNT bit in the TIMER_CONFIG register controls the point in time at which this set of transactions is executed. Taken together, these three events are called a measurement report. The TOVF_ERR bit does not get set at a measurement report. A measurement report occurs, at most, once per input signal period. The current timer counter value is always copied to the width buffer and period buffer registers at the trailing and leading edges of the input signal, respectively, but these values are not visible to software. A measurement report event samples the captured values into visible registers and sets the timer interrupt to signal that TIMER_PERIOD and TIMER_WIDTH are ready to be read. When the PERIOD_CNT bit is set, the measurement report occurs just after the period buffer captures its value (at a leading edge). When the PERIOD_CNT bit is cleared, the measurement report occurs just after the width buffer captures its value (at a trailing edge). If the PERIOD_CNT bit is set and a leading edge occurred (see Figure 10-11), then the TIMER_PERIOD and TIMER_WIDTH registers report the pulse period and pulse width measured in the period that just ended. If the PERIOD_CNT bit is cleared and a trailing edge occurred (see Figure 10-12), then the TIMER_WIDTH register reports the pulse width measured in the pulse that just ended, but the TIMER_PERIOD register reports the pulse period measured at the end of the previous period. If the PERIOD_CNT bit is cleared and the first trailing edge occurred, then the first period value has not yet been measured at the first measurement report, so the period value is not valid. Reading the TIMER_PERIOD value in this case returns "0", as shown in Figure 10-12. To measure the pulse width of a waveform that has only one leading edge and one trailing edge, ADSP-BF52x Blackfin Processor Hardware Reference 10-25 SCLK TMR PIN, PULSE_HI = 0 TMR PIN, PULSE_HI = 1 TIMER_COUNTER X 1 TIMER_PERIOD BUFFER X 0 TIMER_WIDTH BUFFER X 0 TIMER_PERIOD X 0 4 8 TIMER_WIDTH X 0 2 3 2 3 4 1 2 3 4 5 6 7 8 4 2 1 8 3 TIMIL TOVF_ERR TIMEN STARTS COUNTING MEASUREMENT REPORT MEASUREMENT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 10-11. Example of Period Capture Measurement Report Timing (WDTH_CAP mode, PERIOD_CNT = 1) 10-26 ADSP-BF52x Blackfin Processor Hardware Reference SCLK TMR PIN, PULSE_HI = 0 TMR PIN, PULSE_HI = 1 X 1 X TIMER_COUNTER 0 2 3 4 5 6 7 8 1 2 8 3 4 1 2 3 4 TIMER_PERIOD BUFFER X 0 3 1 2 TIMER_WIDTH BUFFER TIMER_PERIOD X 0 0 8 4 TIMER_WIDTH X 0 3 1 2 TIMIL TOVF_ERR TIMEN STARTS MEASUREMENT COUNTING REPORT MEASUREMENT REPORT MEASUREMENT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 10-12. Example of Width Capture Measurement Report Timing (WDTH_CAP mode, PERIOD_CNT = 0) set PERIOD_CNT = 0. If PERIOD_CNT = 1 for this case, no period value is captured in the period buffer. Instead, an error report interrupt is generated (if enabled) when the counter range is exceeded and the counter wraps ADSP-BF52x Blackfin Processor Hardware Reference 10-27 around. In this case, both TIMER_WIDTH and TIMER_PERIOD read "0" (because no measurement report occurred to copy the value captured in the width buffer to TIMER_WIDTH). See the first interrupt in Figure 10-13. When using mode described measure the width of the pulse, it=is0recommended to above tothe timer a single disable PERIOD_CNT after taking the interrupt that ends the measurement interval. If desired, the timer can then be reenabled as appropriate in preparation for another measurement. This procedure prevents the timer from free-running after the width measurement, and from logging errors generated by the timer count overflowing. A timer interrupt (if enabled) is generated if the TIMER_COUNTER register wraps around from 0xFFFF FFFF to "0" in the absence of a leading edge. At that point, the TOVF_ERR bit in the TIMER_STATUS register and the ERR_TYP bits in the TIMER_CONFIG register are set, indicating a count overflow due to a period greater than the counter’s range. This is called an error report. When a timer generates an interrupt in WDTH_CAP mode, either an error has occurred (an error report) or a new measurement is ready to be read (a measurement report), but never both at the same time. The TIMER_PERIOD and TIMER_WIDTH registers are never updated at the time an error is signaled. Refer to Figure 10-13 and Figure 10-14 for more information. 10-28 ADSP-BF52x Blackfin Processor Hardware Reference SCLK TMR PIN, PULSE_HI = 0 TMR PIN, PULSE_HI = 1 0xFFFF 0xFFFF 0xFFFF 0xFFFF FFFC FFFD FFFE FFFF TIMER_COUNTER X 1 TIMER_PERIOD BUFFER X 0 TIMER_WIDTH BUFFER X 0 TIMER_PERIOD X 0 0 4 TIMER_WIDTH X 0 0 2 2 3 0 1 2 3 5 4 0 2 4 2 TIMIL TOVF_ERR TIMEN STARTS COUNTING ERROR REPORT MEASUREMENT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 10-13. Example Timing for Period Overflow Followed by Period Capture (WDTH_CAP mode, PERIOD_CNT = 1) ADSP-BF52x Blackfin Processor Hardware Reference 10-29 SCLK TMR pin, PULSE_HI = 0 TMR pin, PULSE_HI = 1 TIMER_COUNTER X 1 2 0xFFFF 0xFFFF 0xFFFF 0xFFFF FFFC FFFD FFFE FFFF 3 0 1 2 3 4 1 2 TIMER_PERIOD BUFFER X 4 0 0 TIMER_WIDTH BUFFER X 0 3 3 TIMER_PERIOD X 0 0 0 TIMER_WIDTH X 0 3 3 TIMIL TOVF_ERR TIMEN STARTS COUNTING MEASUREMENT REPORT ERROR REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 10-14. Example Timing for Width Capture Followed by Period Overflow (WDTH_CAP mode, PERIOD_CNT = 0) 10-30 ADSP-BF52x Blackfin Processor Hardware Reference Both TIMIL and TOVF_ERR are sticky bits, and software must explicitly clear them. If the timer overflowed and PERIOD_CNT = 1, neither the TIMER_PERIOD nor the TIMER_WIDTH register were updated. If the timer overflowed and PERIOD_CNT = 0, the TIMER_PERIOD and TIMER_WIDTH registers were updated only if a trailing edge was detected at a previous measurement report. Software can count the number of error report interrupts between measurement report interrupts to measure input signal periods longer than 0xFFFF FFFF. Each error report interrupt adds a full 232 SCLK counts to the total for the period, but the width is ambiguous. For example, in Figure 10-13 the period is 0x1 0000 0004 but the pulse width could be either 0x0 0000 0002 or 0x1 0000 0002. The waveform applied to the TMR pin is not required to have a 50% duty cycle, but the minimum TMR pin low time is one SCLK period and the minimum TMR pin high time is one SCLK period. This implies the maximum TMR pin input frequency is SCLK/2 with a 50% duty cycle. Under these conditions, the WDTH_CAP mode timer would measure Period = 2 and Pulse Width = 1. Autobaud Mode On some devices, in WDTH_CAP mode, some of the timers can provide autobaud detection for the Universal Asynchronous Receiver/Transmitter (UART) interface(s). The TIN_SEL bit in the TIMER_CONFIG register causes the timer to sample the TACI pin instead of the TMR pin when enabled for WDTH_CAP mode. Autobaud detection can be used for initial bit rate negotiations as well as for detection of bit rate drifts while the interface is in operation. External Event (EXT_CLK) Mode Use the EXT_CLK mode (sometimes referred to as the counter mode) to count external events—that is, signal edges on the TMR pin (which is an ADSP-BF52x Blackfin Processor Hardware Reference 10-31 input in this mode). Figure 10-15 shows a flow diagram for EXT_CLK mode. The timer works as a counter clocked by an external source, which can also be asynchronous to the system clock. The current count in TIMER_COUNTER represents the number of leading edge events detected. Setting the TMODE field to b#11 in the TIMER_CONFIG register enables this mode. The TIMER_PERIOD register is programmed with the value of the maximum timer external count. The waveform applied to the TMR pin is not required to have a 50% duty cycle, but the minimum TMR low time is one SCLK period, and the minimum TMR high time is one SCLK period. This implies the maximum TMR pin input frequency is SCLK/2. Period may be programmed to any value from 1 to (232 – 1), inclusive. DATA BUS TIMER_PERIOD RESET CLOCK TIMER_COUNTER EQUAL? PULSE_HI LEADING EDGE DETECT TMR pin Y INTERRUPT TIMER_ENABLE Figure 10-15. Timer Flow Diagram, EXT_CLK Mode 10-32 ADSP-BF52x Blackfin Processor Hardware Reference After the timer has been enabled, it resets the TIMER_COUNTER register to 0x0 and then waits for the first leading edge on the TMR pin. This edge causes the TIMER_COUNTER register to be incremented to the value 0x1. Every subsequent leading edge increments the count register. After reaching the period value, the TIMIL bit is set, and an interrupt is generated. The next leading edge reloads the TIMER_COUNTER register again with 0x1. The timer continues counting until it is disabled. The PULSE_HI bit determines whether the leading edge is rising (PULSE_HI set) or falling (PULSE_HI cleared). The configuration bits TIN_SEL and PERIOD_CNT have no effect in this mode. The TOVF_ERR and ERR_TYP bits are set if the TIMER_COUNTER register wraps around from 0xFFFF FFFF to "0" or if Period = "0" at startup or when the TIMER_COUNTER register rolls over (from Count = Period to Count = 0x1). The TIMER_WIDTH register is unused. Programming Model The architecture of the timer block enables any of the timers within this block to work individually or synchronously along with others as a group of timers. Regardless of the operating mode, the programming model is always straightforward. Because of the error checking mechanism, always follow this order when enabling timers: 1. Set timer mode. 2. Write TIMER_WIDTH and TIMER_PERIOD registers as applicable. 3. Enable timer. If this order is not followed, the plausibility check may fail because of undefined width and period values, or writes to TIMER_WIDTH and TIMER_PERIOD may result in an error condition, because the registers are read-only in some modes. The timer may not start as expected. ADSP-BF52x Blackfin Processor Hardware Reference 10-33 If in PWM_OUT mode the PWM patterns of the second period differ from the patterns of the first one, the initialization sequence above might become: 1. Set timer mode to PWM_OUT. 2. Write first TIMER_WIDTH and TIMER_PERIOD value pair. 3. Enable timer. 4. Immediately write second TIMER_WIDTH and TIMER_PERIOD value pair. Hardware ensures that the buffered width and period values become active when the first period expires. Once started, timers require minimal interaction with software, which is usually performed by an interrupt service routine. In PWM_OUT mode software must update the pulse width and/or settings as required. In WDTH_CAP mode it must store captured values for further processing. In any case, the service routine should clear the TIMIL bits of the timers it controls. Timer Registers The timer peripheral module provides general-purpose timer functionality. It consists of multiple identical timer units. Each timer provides four registers: • • TIMER_WIDTH[31:0] • TIMER_PERIOD[31:0] • 10-34 TIMER_CONFIG[15:0] – timer configuration register TIMER_COUNTER[31:0] – timer pulse width register – timer period register – timer counter register ADSP-BF52x Blackfin Processor Hardware Reference Additionally, three registers are shared between the timers within a block: • TIMER_ENABLE[15:0] • TIMER_DISABLE[15:0] • TIMER_STATUS[31:0] – timer enable register – timer disable register – timer status register The size of accesses is enforced. A 32-bit access to a TIMER_CONFIG register or a 16-bit access to a TIMER_WIDTH, TIMER_PERIOD, or TIMER_COUNTER register results in a memory-mapped register (MMR) error. Both 16- and 32-bit accesses are allowed for the TIMER_ENABLE, TIMER_DISABLE, and TIMER_STATUS registers. On a 32-bit read of one of the 16-bit registers, the upper word returns all 0s. Timer Enable Register (TIMER_ENABLE) Figure 10-16 shows an example of the TIMER_ENABLE register for a product with eight timers. The register allows simultaneous enabling of multiple timers so that they can run synchronously. For each timer there is a single W1S control bit. Writing a "1" enables the corresponding timer; writing a "0" has no effect. The bits can be set individually or in any combination. A read of the TIMER_ENABLE register shows the status of the enable for the corresponding timer. A "1" indicates that the timer is enabled. All unused bits return "0" when read. ADSP-BF52x Blackfin Processor Hardware Reference 10-35 Timer Enable Register (TIMER_ENABLE) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 TIMEN7 (Timer7 Enable) 1 - Enable timer Read as 1 when enabled TIMEN0 (Timer0 Enable) 1 - Enable timer Read as 1 when enabled TIMEN6 (Timer6 Enable) 1 - Enable timer Read as 1 when enabled TIMEN1 (Timer1 Enable) 1 - Enable timer Read as 1 when enabled TIMEN5 (Timer5 Enable) 1 - Enable timer Read as 1 when enabled TIMEN4 (Timer4 Enable) 1 - Enable timer Read as 1 when enabled TIMEN2 (Timer2 Enable) 1 - Enable timer Read as 1 when enabled TIMEN3 (Timer3 Enable) 1 - Enable timer Read as 1 when enabled This diagram shows an example configuration for eight timers. Different products have different numbers of timers. Figure 10-16. Timer Enable Register T imer Disable Register (TIMER_DISABLE) Figure 10-17 shows an example of the TIMER_DISABLE register for a product with eight timers. The register allows simultaneous disabling of multiple timers. For each timer there is a single W1C control bit. Writing a "1" disables the corresponding timer; writing a "0" has no effect. The bits can be cleared individually or in any combination. A read of the TIMER_DISABLE register returns a value identical to a read of the TIMER_ENABLE register. A "1" indicates that the timer is enabled. All unused bits return "0" when read. 10-36 ADSP-BF52x Blackfin Processor Hardware Reference Timer Disable Register (TIMER_DISABLE) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 TIMDIS7 (Timer7 Disable) 1 - Disable timer Read as 1 if this timer is enabled TIMDIS6 (Timer6 Disable) 1 - Disable timer Read as 1 if this timer is enabled TIMDIS0 (Timer0 Disable) 1 - Disable timer Read as 1 if this timer is enabled TIMDIS1 (Timer1 Disable) 1 - Disable timer Read as 1 if this timer is enabled TIMDIS5 (Timer5 Disable) 1 - Disable timer Read as 1 if this timer is enabled TIMDIS4 (Timer4 Disable) 1 - Disable timer Read as 1 if this timer is enabled TIMDIS2 (Timer2 Disable) 1 - Disable timer Read as 1 if this timer is enabled TIMDIS3 (Timer3 Disable) 1 - Disable timer Read as 1 if this timer is enabled This diagram shows an example configuration for eight timers. Different products have different numbers of timers. Figure 10-17. Timer Disable Register In PWM_OUT mode, a write of a "1" to TIMER_DISABLE does not stop the corresponding timer immediately. Rather, the timer continues running and stops cleanly at the end of the current period (if PERIOD_CNT = 1) or pulse (if PERIOD_CNT = 0). If necessary, the processor can force a timer in PWM_OUT mode to stop immediately by first writing a "1" to the corresponding bit in TIMER_DISABLE, and then writing a "1" to the corresponding TRUN bit in TIMER_STATUS. See “Stopping the Timer in PWM_OUT Mode” on page 10-21. In WDTH_CAP and EXT_CLK modes, a write of a "1" to TIMER_DISABLE stops the corresponding timer immediately. Timer Status Register (TIMER_STATUS) The TIMER_STATUS register indicates the status of the timers and is used to check the status of multiple timers with a single read. Status bits are sticky and W1C. The TRUN bits can clear themselves, which they do when a PWM_OUT mode timer stops at the end of a period. During a TIMER_STATUS ADSP-BF52x Blackfin Processor Hardware Reference 10-37 register read access, all reserved or unused bits return a "0". Figure 10-18 on page 10-39 shows an example of the TIMER_STATUS register for a product with eight timers. For detailed behavior and usage of the TRUN bit see “Stopping the Timer in PWM_OUT Mode” on page 10-21. Writing the TRUN bits has no effect in other modes or when a timer has not been enabled. Writing the TRUN bits to "1" in PWM_OUT mode has no effect on a timer that has not first been disabled. Error conditions are explained in “Illegal States” on page 10-7. 10-38 ADSP-BF52x Blackfin Processor Hardware Reference Timer Status Register (TIMER_STATUS) All bits are W1C 31 30 29 28 27 26 0 0 0 0 0 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 0000 TRUN7 (Timer7 Slave Enable Status) Read as 1 if timer running, W1C to abort in PWM_OUT mode TRUN6 (Timer6 Slave Enable Status) Read as 1 if timer running, W1C to abort in PWM_OUT mode TRUN5 (Timer5 Slave Enable Status) TIMIL4 (Timer4 Interrupt) Indicates an interrupt request when IRQ_ENA is set TIMIL5 (Timer5 Interrupt) Indicates an interrupt request when IRQ_ENA is set TIMIL6 (Timer6 Interrupt) Indicates an interrupt request when IRQ_ENA is set TIMIL7 (Timer7 Interrupt) Indicates an interrupt request when IRQ_ENA is set TOVF_ERR4 (Timer4 Counter Overflow) Indicates that an error or an overflow occurred TOVF_ERR5 (Timer5 Counter Overflow) Indicates that an error or an overflow occurred Read as 1 if timer running, W1C to abort in PWM_OUT mode TRUN4 (Timer4 Slave Enable Status) Read as 1 if timer running, W1C to abort in PWM_OUT mode TOVF_ERR7 (Timer7 Counter Overflow) Indicates that an error or an overflow occurred TOVF_ERR6 (Timer6 Counter Overflow) Indicates that an error or an overflow occurred 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRUN3 (Timer3 Slave Enable Status) Read as 1 if timer running, W1C to abort in PWM_OUT mode TRUN2 (Timer2 Slave Enable Status) Read as 1 if timer running, W1C to abort in PWM_OUT mode TRUN1 (Timer1 Slave Enable Status) Read as 1 if timer running, W1C to abort in PWM_OUT mode TRUN0 (Timer0 Slave Enable Status) Read as 1 if timer running, W1C to abort in PWM_OUT mode TIMIL0 (Timer0 Interrupt) Indicates an interrupt request when IRQ_ENA is set TIMIL1 (Timer1 Interrupt) Indicates an interrupt request when IRQ_ENA is set TIMIL2 (Timer2 Interrupt) Indicates an interrupt request when IRQ_ENA is set TIMIL3 (Timer3 Interrupt) Indicates an interrupt request when IRQ_ENA is set TOVF_ERR0 (Timer0 Counter Overflow) Indicates that an error or an overflow occurred TOVF_ERR1 (Timer1 Counter Overflow) Indicates that an error or an overflow occurred TOVF_ERR3 (Timer3 Counter Overflow) Indicates that an error or an overflow occurred TOVF_ERR2 (Timer2 Counter Overflow) Indicates that an error or an overflow occurred This diagram shows an example configuration for eight timers. Different products have different numbers of timers, therefore some of the bits may not be applicable to your device. Figure 10-18. Timer Status Register ADSP-BF52x Blackfin Processor Hardware Reference 10-39 T imer Configuration Register (TIMER_CONFIG) The operating mode for each timer is specified by its TIMER_CONFIG register. The TIMER_CONFIG register, shown in Figure 10-19, may be written only when the timer is not running. After disabling the timer in PWM_OUT mode, make sure the timer has stopped running by checking its TRUN bit in TIMER_STATUS before attempting to reprogram TIMER_CONFIG. The TIMER_CONFIG registers may be read at any time. The ERR_TYP field is read-only. It is cleared at reset and when the timer is enabled. Each time TOVF_ERR is set, ERR_TYP[1:0] is loaded with a code that identifies the type of error that was detected. This value is held until the next error or timer enable occurs. For an overview of error conditions, see Table 10-1 on page 10-9. The TIMER_CONFIG register also controls the behavior of the TMR pin, which becomes an output in PWM_OUT mode (TMODE = 01) when the OUT_DIS bit is cleared. operating PPI in When the theand the GP output modes with internal frame bits for the timers involved syncs, CLK_SEL TIN_SEL must be set to "1". 10-40 ADSP-BF52x Blackfin Processor Hardware Reference Timer Configuration Register (TIMER_CONFIG) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 TMODE[1:0] (Timer Mode) 00 - Reset state - unused 01 - PWM_OUT mode 10 - WDTH_CAP mode 11 - EXT_CLK mode ERR_TYP[1:0] (Error Type) - RO 00 - No error 01 - Counter overflow error 10 - Period register programming error 11 - Pulse width register programming error EMU_RUN (Emulation Behavior Select) 0 - Timer counter stops during emulation 1 - Timer counter runs during emulation TOGGLE_HI (PWM_OUT PULSE_HI Toggle Mode) 0 - The effective state of PULSE_HI is the programmed state 1 - The effective state of PULSE_HI alternates each period CLK_ SEL (Timer Clock Select) 0 - Use system clock SCLK for counter 1 - Use PWM_CLK to clock counter OUT_DIS (Output Pad Disable) 0 - Enable TMR pad in PWM_OUT mode 1 - Disable pad in PWM_OUT mode PULSE_HI 0 - Negative action pulse 1 - Positive action pulse PERIOD_CNT (Period Count) 0 - Count to end of width 1 - Count to end of period IRQ_ENA (Interrupt Request Enable) 0 - Interrupt request disable 1 - Interrupt request enable TIN_ SEL (Timer Input Select) PWM_OUT Mode 0 - Clock from TACLK input if CLK_SEL = 1 1 - Clock from TMRCLK input if CLK_SEL = 1 WDTH_CAP Mode 0 - Sample TMR pin input 1 - Sample TACI input Figure 10-19. Timer Configuration Register T imer Counter Register (TIMER_COUNTER) This read-only register retains its state when disabled. When enabled, the TIMER_COUNTER register is reinitialized by hardware based on configuration and mode. The TIMER_COUNTER register, shown in Figure 10-20, may be read at any time (whether the timer is running or stopped), and it returns an atomic 32-bit value. Depending on the operating mode, the incrementing counter can be clocked by four different sources: SCLK, the TMR pin, the alternative timer clock pin TACLK, or the common TMRCLK pin, which is most likely used as the PPI clock (PPI_CLK). ADSP-BF52x Blackfin Processor Hardware Reference 10-41 While the processor core is being accessed by an external emulator debugger, all code execution stops. By default, the TIMER_COUNTER register also halts its counting during an emulation access in order to remain synchronized with the software. While stopped, the count does not advance—in PWM_OUT mode, the TMR pin waveform is “stretched”; in WDTH_CAP mode, measured values are incorrect; in EXT_CLK mode, input events on the TMR pin may be missed. All other timer functions such as register reads and writes, interrupts previously asserted (unless cleared), and the loading of TIMER_PERIOD and TIMER_WIDTH in WDTH_CAP mode remain active during an emulation stop. Some applications may require the timer to continue counting asynchronously to the emulation-halted processor core. Set the EMU_RUN bit in TIMER_CONFIG to enable this behavior. 10-42 ADSP-BF52x Blackfin Processor Hardware Reference Timer Counter Register (TIMER_COUNTER) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 0001 Timer Counter[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Timer Counter[15:0] Figure 10-20. Timer Counter Register T imer Period (TIMER_PERIOD) and Timer Width (TIMER_WIDTH) Registers a running, When totimer is enabled andregister andand the software writes new values the the register, TIMER_PERIOD TIMER_WIDTH the writes are buffered and do not update the registers until the end of the current period (when TIMER_COUNTER equals TIMER_WIDTH). Usage of the TIMER_PERIOD register, shown in Figure 10-21, and the TIMER_WIDTH register, shown in Figure 10-22, varies depending on the mode of the timer: • In PWM_OUT mode, both the TIMER_PERIOD and TIMER_WIDTH register values can be updated “on-the-fly” since the values change simultaneously. • In WDTH_CAP mode, the timer period and timer pulse width buffer values are captured at the appropriate time. The TIMER_PERIOD and TIMER_WIDTH registers are then updated simultaneously from their respective buffers. Both registers are read-only in this mode. • In EXT_CLK mode, the TIMER_PERIOD register is writable and can be updated “on-the-fly.” The TIMER_WIDTH register is not used. ADSP-BF52x Blackfin Processor Hardware Reference 10-43 If new values are not written to the TIMER_PERIOD register or the TIMER_WIDTH register, the value from the previous period is reused. Writes to the 32-bit TIMER_PERIOD register and TIMER_WIDTH register are atomic; it is not possible for the high word to be written without the low word also being written. Values written to the TIMER_PERIOD registers or TIMER_WIDTH registers are always stored in the buffer registers. Reads from the TIMER_PERIOD or TIMER_WIDTH registers always return the current, active value of period or pulse width. Written values are not read back until they become active. When the timer is enabled, they do not become active until after the TIMER_PERIOD and TIMER_WIDTH registers are updated from their respective buffers at the end of the current period. See Figure 10-1 on page 10-3. When the timer is disabled, writes to the buffer registers are immediately copied through to the TIMER_PERIOD or TIMER_WIDTH register so that they will be ready for use in the first timer period. For example, to change the values for the TIMER_PERIOD and/or TIMER_WIDTH registers in order to use a different setting for each of the first three timer periods after the timer is enabled, the procedure to follow is: 1. Program the first set of register values. 2. Enable the timer. 3. Immediately program the second set of register values. 4. Wait for the first timer interrupt. 5. Program the third set of register values. Each new setting is then programmed when a timer interrupt is received. m with very small periods (less counts), In may notode enough time between updatesthan 10the buffer there be from PWM_OUT registers to write both the TIMER_PERIOD register and the TIMER_WIDTH register. The next period may use one old value and one new value. In order to prevent “pulse width period” errors, 10-44 ADSP-BF52x Blackfin Processor Hardware Reference write the TIMER_WIDTH register before the TIMER_PERIOD register when decreasing the values, and write the TIMER_PERIOD register before the TIMER_WIDTH register when increasing the value. Timer Period Register (TIMER_PERIOD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 0000 Timer Period[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Timer Period[15:0] Figure 10-21. Timer Period Register Timer Width Register (TIMER_WIDTH) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 0000 Timer Width[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Timer Width[15:0] Figure 10-22. Timer Width Register ADSP-BF52x Blackfin Processor Hardware Reference 10-45 S ummary Table 10-2 summarizes control bit and register usage in each timer mode. Table 10-2. Control Bit and Register Usage Chart Bit / Register PWM_OUT Mode WDTH_CAP Mode EXT_CLK Mode TIMER_ENABLE 1 - Enable timer 0 - No effect 1 - Enable timer 0 - No effect 1 - Enable timer 0 - No effect TIMER_DISABLE 1 - Disable timer at end 1 - Disable timer of period 0 - No effect 0 - No effect 1 - Disable timer 0 - No effect TMODE b#01 b#11 PULSE_HI 1 - Generate high width 1 - Measure high width 1 - Count rising edges 0 - Generate low width 0 - Measure low width 0 - Count falling edges PERIOD_CNT 1 - Generate PWM 0 - Single width pulse 1 - Interrupt after mea- Unused suring period 0 - Interrupt after measuring width IRQ_ENA 1 - Enable interrupt 0 - Disable interrupt 1 - Enable interrupt 0 - Disable interrupt TIN_SEL Depends on CLK_SEL: 1 - Select TACI input 0 - Select TMR pin If CLK_SEL = 1, input 1 - Count TMRCLK clocks 0 - Count TACLK clocks b#10 1 - Enable interrupt 0 - Disable interrupt Unused If CLK_SEL = 0, Unused OUT_DIS 1 - Disable TMR pin 0 - Enable TMR pin Unused Unused CLK_SEL 1 - PWM_CLK clocks timer 0 - SCLK clocks timer Unused Unused 10-46 ADSP-BF52x Blackfin Processor Hardware Reference Table 10-2. Control Bit and Register Usage Chart (Continued) Bit / Register PWM_OUT Mode WDTH_CAP Mode EXT_CLK Mode TOGGLE_HI 1 - One waveform period every two counter periods 0 - One waveform period every one counter period Unused Unused ERR_TYP Reports b#00, b#01, b#10, or b#11, as appropriate Reports b#00 or b#01, Reports b#00, b#01, or as appropriate b#10, as appropriate EMU_RUN 0 - Halt during emulation 1 - Count during emulation 0 - Halt during emulation 1 - Count during emulation TMR Pin Depends on OUT_DIS: 1 - Three-state 0 - Output Depends on TIN_SEL: Input 1 - Unused 0 - Input Period R/W: Period value RO: Period value R/W: Period value Width R/W: Width value RO: Width value Unused Counter RO: Counts up on SCLK or PWM_CLK RO: Counts up on SCLK RO: Counts up on TMR pin event TRUN Read: Timer slave enable status Write: 1 - Stop timer if disabled 0 - No effect Read: Timer slave enable status Write: 1 - No effect 0 - No effect Read: Timer slave enable status Write: 1 - No effect 0 - No effect ADSP-BF52x Blackfin Processor Hardware Reference 0 - Halt during emulation 1 - Count during emulation 10-47 Table 10-2. Control Bit and Register Usage Chart (Continued) Bit / Register PWM_OUT Mode WDTH_CAP Mode EXT_CLK Mode TOVF_ERR Set at startup or rollover if period = 0 or 1 Set at rollover if width >= Period Set if counter wraps Set if counter wraps Set if counter wraps or set at startup or rollover if period = 0 IRQ Depends on IRQ_ENA: 1 - Set when TOVF_ERR set or when counter equals period and PERIOD_CNT = 1 or when counter equals width and PERIOD_CNT = 0 0 - Not set Depends on IRQ_ENA: 1 - Set when TOVF_ERR set or when counter captures period and PERIOD_CNT = 1 or when counter captures width and PERIOD_CNT = 0 0 - Not set Depends on IRQ_ENA: 1 - Set when counter equals period or TOVF_ERR set 0 - Not set P rogramming Examples Listing 10-1 configures the port control registers in a way that enables TMR pins associated with Port G. This example assumes TMR1-7 are connected to Port G bits 5–11. Listing 10-1. Port Setup timer_port_setup: [--sp] = (r7:7, p5:5); p5.h = hi(PORTG_FER); p5.l = lo(PORTG_FER); r7.l = PG5|PG6|PG7|PG8|PG9|PG10|PG11; w[p5] = r7; p5.l = lo(PORTG_MUX); r7.l = PFTE; 10-48 ADSP-BF52x Blackfin Processor Hardware Reference w[p5] = r7; (r7:7, p5:5) = [sp++]; rts; timer_port_setup.end: Listing 10-2 generates signals on the TMR4 and TMR5 outputs. By default, timer 5 generates a continuous PWM signal with a duty cycle of 50% (period = 0x40 SCLKs, width = 0x20 SCLKs) while the PWM signal generated by timer 4 has the same period but 25% duty cycle (width = 0x10 SCLKs). If the preprocessor constant SINGLE_PULSE is defined, every TMR pin outputs only a single high pulse of 0x20 (timer 4) and 0x10 SCLKs (timer 5) duration. In any case the timers are started synchronously and the rising edges are aligned. That is, the pulses are left aligned. Listing 10-2. Signal Generation // #define SINGLE_PULSE timer45_signal_generation: [--sp] = (r7:7, p5:5); p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); #ifdef SINGLE_PULSE r7.l = PULSE_HI | PWM_OUT; #else r7.l = PERIOD_CNT | PULSE_HI | PWM_OUT; #endif w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; w[p5 + TIMER4_CONFIG - TIMER_ENABLE] = r7; r7 = 0x10 (z); [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r7; r7 = 0x20 (z); ADSP-BF52x Blackfin Processor Hardware Reference 10-49 [p5 + TIMER4_WIDTH - TIMER_ENABLE] = r7; #ifndef SINGLE_PULSE r7 = 0x40 (z); [p5 + TIMER5_PERIOD - TIMER_ENABLE] = r7; [p5 + TIMER4_PERIOD - TIMER_ENABLE] = r7; #endif r7.l = TIMEN5 | TIMEN4; w[p5] = r7; (r7:7, p5:5) = [sp++]; rts; timer45_signal_generation.end: All subsequent examples use interrupts. Thus, Listing 10-3 illustrates how interrupts are generated and how interrupt service routines can be registered. In this example, the timer 5 interrupt is assigned to the IVG12 interrupt channel of the CEC controller. Listing 10-3. Interrupt Setup timer5_interrupt_setup: [--sp] = (r7:7, p5:5); p5.h = hi(IMASK); p5.l = lo(IMASK); /* register interrupt service routine */ r7.h = hi(isr_timer5); r7.l = lo(isr_timer5); [p5 + EVT12 - IMASK] = r7; /* unmask IVG12 in CEC */ r7 = [p5]; bitset(r7, bitpos(EVT_IVG12)); [p5] = r7; /* assign timer 5 IRQ (= IRQ37 in this example) to IVG12 */ p5.h = hi(SIC_IAR4); p5.l = lo(SIC_IAR4); /*SIC_IAR register mapping is processor dependent*/ 10-50 ADSP-BF52x Blackfin Processor Hardware Reference r7.h = 0xFF5F; r7.l = 0xFFFF; [p5] = r7; /* enable timer 5 IRQ */ p5.h = hi(SIC_IMASK1); p5.l = lo(SIC_IMASK1); /*SIC_IMASK register mapping is processor dependent*/ r7 = [p5]; bitset(r7, 5); [p5] = r7; /* enable interrupt nesting */ (r7:7, p5:5) = [sp++]; [--sp] = reti; rts; timer5_interrupt_setup.end: The example shown in Listing 10-4 does not drive the TMR pin. It generates periodic interrupt requests every 0x1000 SCLK cycles. If the preprocessor constant SINGLE_PULSE was defined, timer 5 requests an interrupt only once. Unlike in a real application, the purpose of the interrupt service routine shown in this example is just the clearing of the interrupt request and counting interrupt occurrences. Listing 10-4. Periodic Interrupt Requests // #define SINGLE_PULSE timer5_interrupt_generation: [--sp] = (r7:7, p5:5); p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); #ifdef SINGLE_PULSE r7.l = EMU_RUN | IRQ_ENA | OUT_DIS | PWM_OUT; #else r7.l = EMU_RUN | IRQ_ENA | PERIOD_CNT | OUT_DIS | PWM_OUT; #endif ADSP-BF52x Blackfin Processor Hardware Reference 10-51 w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; r7 = 0x1000 (z); #ifndef SINGLE_PULSE [p5 + TIMER5_PERIOD - TIMER_ENABLE] = r7; r7 = 0x1 (z); #endif [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r7; r7.l = TIMEN5; w[p5] = r7; (r7:7, p5:5) = [sp++]; r0 = 0 (z); rts; timer5_interrupt_generation.end: isr_timer5: [--sp] = astat; [--sp] = (r7:7, p5:5); p5.h = hi(TIMER_STATUS); p5.l = lo(TIMER_STATUS); r7.h = hi(TIMIL5); r7.l = lo(TIMIL5); [p5] = r7; r0+= 1; ssync; (r7:7, p5:5) = [sp++]; astat = [sp++]; rti; isr_timer5.end: Listing 10-5 illustrates how two timers can generate two non-overlapping clock pulses as typically required for break-before-make scenarios. Both timers are running in PWM_OUT mode with PERIOD_CNT = 1 and PULSE_HI = 1. 10-52 ADSP-BF52x Blackfin Processor Hardware Reference Figure 10-23 explains how the signal waveform represented by the period P and the pulse width W translates to timer period and width values. Table 10-3 summarizes the register writes. Table 10-3. Register Writes for Non-Overlapping Clock Pulses Register Before Enable After At IRQ1 At IRQ2 P/2 - W/2 W/2 W/2 P/2 - W-2 Enable TIMER5_PERIOD P/2 TIMER5_WIDTH P/2 - W/2 W/2 TIMER4_PERIOD P P/2 TIMER4_WIDTH P - W/2 ENABLE IRQ1 IRQ2 IRQ3 TMR5 TMR4 P/2 - W/2 W/2 W/2 W/2 P/2 P/2 W/2 P/2 P/2 P - W/2 P W Figure 10-23. Non-Overlapping Clock Pulses Since hardware only updates the written period and width values at the end of periods, software can write new values immediately after the timers have been enabled. Note that both timers’ period expires at exactly the same times with the exception of the first timer 5 interrupt (at IRQ1) which is not visible to timer 4. ADSP-BF52x Blackfin Processor Hardware Reference 10-53 Listing 10-5. Non-Overlapping Clock Pulses #define P 0x1000 /* signal period */ #define W 0x0600 /* signal pulse width */ #define N 4 /* number of pulses before disable */ timer45_toggle_hi: [--sp] = (r7:1, p5:5); p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); /* config timers */ r7.l = IRQ_ENA | PERIOD_CNT | TOGGLE_HI | PULSE_HI | PWM_OUT; w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; r7.l = PERIOD_CNT | TOGGLE_HI | PULSE_HI | PWM_OUT; w[p5 + TIMER4_CONFIG - TIMER_ENABLE] = r7; /* calculate timers widths and period */ r0.l = lo(P); r0.h = hi(P); r1.l = lo(W); r1.h = hi(W); r2 = r1 >> 1; /* W/2 */ r3 = r0 >> 1; /* P/2 */ r4 = r3 - r2; /* P/2 - W/2 */ r5 = r0 - r2; /* P - W/2 */ /* write values for initial period */ [p5 + TIMER4_PERIOD - TIMER_ENABLE] = r0; [p5 + TIMER4_WIDTH - TIMER_ENABLE] = r5; [p5 + TIMER5_PERIOD - TIMER_ENABLE] = r3; [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r4; /* start timers */ r7.l = TIMEN5 | TIMEN4 ; w[p5 + TIMER_ENABLE - TIMER_ENABLE] = r7; /* write values for second period */ [p5 + TIMER4_PERIOD - TIMER_ENABLE] = r3; [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r2; 10-54 ADSP-BF52x Blackfin Processor Hardware Reference /* r0 functions as signal period counter */ r0.h = hi(N * 2 - 1); r0.l = lo(N * 2 - 1); (r7:1, p5:5) = [sp++]; rts; timer45_toggle_hi.end: isr_timer5: [--sp] = astat; [--sp] = (r7:5, p5:5); p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); /* clear interrupt request */ r7.h = hi(TIMIL5); r7.l = lo(TIMIL5); [p5 + TIMER_STATUS - TIMER_ENABLE] = r7; /* toggle width values (width = period - width) */ r7 = [p5 + TIMER5_PERIOD - TIMER_ENABLE]; r6 = [p5 + TIMER5_WIDTH - TIMER_ENABLE]; r5 = r7 - r6; [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r5; r5 = [p5 + TIMER4_WIDTH - TIMER_ENABLE]; r7 = r7 - r5; CC = r7 < 0; if CC r7 = r6; [p5 + TIMER4_WIDTH - TIMER_ENABLE] = r7; /* disable after a certain number of periods */ r0+= -1; CC = r0 == 0; r5.l = 0; r7.l = TIMDIS5 | TIMDIS4; if !CC r7 = r5; w[p5 + TIMER_DISABLE - TIMER_ENABLE] = r7; (r7:5, p5:5) = [sp++]; astat = [sp++]; ADSP-BF52x Blackfin Processor Hardware Reference 10-55 rti; isr_timer5.end: Listing 10-5 generates N pulses on both timer output pins. Disabling the timers does not corrupt the generated pulse pattern anyhow. Listing 10-6 configures timer 5 in WDTH_CAP mode. If looped back externally, this code might be used to receive N PWM patterns generated by one of the other timers. Ensure that the PWM generator and consumer both use the same PERIOD_CNT and PULSE_HI settings. Listing 10-6. Timer Configured in WDTH_CAP Mode .section L1_data_a; .align 4; #define N 1024 .var buffReceive[N*2]; .section L1_code; timer5_capture: [--sp] = (r7:7, p5:5); /* setup DAG2 */ r7.h = hi(buffReceive); r7.l = lo(buffReceive); i2 = r7; b2 = r7; l2 = length(buffReceive)*4; /* config timer for high pulses capture */ p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); r7.l = EMU_RUN|IRQ_ENA|PERIOD_CNT|PULSE_HI|WDTH_CAP; w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; r7.l = TIMEN5; w[p5 + TIMER_ENABLE - TIMER_ ENABLE] = r7; (r7:7, p5:5) = [sp++]; rts; 10-56 ADSP-BF52x Blackfin Processor Hardware Reference timer5_capture.end: isr_timer5: [--sp] = astat; [--sp] = (r7:7, p5:5); /* clear interrupt request first */ p5.h = hi(TIMER_STATUS); p5.l = lo(TIMER_STATUS); r7.h = hi(TIMIL5); r7.l = lo(TIMIL5); [p5] = r7; r7 = [p5 + TIMER5_PERIOD - TIMER_STATUS]; [i2++] = r7; r7 = [p5 + TIMER5_WIDTH - TIMER_STATUS]; [i2++] = r7; ssync; (r7:7, p5:5) = [sp++]; astat = [sp++]; rti; isr_timer5.end: Unique Behavior for the ADSP-BF52x Processor The ADSP-BF52x processor features one general-purpose timer module that contains eight identical 32-bit timers. Each timer can be individually configured to operate in various modes. Although the timers operate completely independently of each other, all of them can be started and stopped simultaneously for synchronous operation. ADSP-BF52x Blackfin Processor Hardware Reference 10-57 I nterface Overview Figure 10-24 shows the ADSP-BF52x specific block diagram of the general-purpose timer module. BLACKFIN SIC CONTROLLER IRQ 32 IRQ 33 IRQ 34 IRQ 35 IRQ 36 IRQ 37 IRQ 38 IRQ 39 PAB GP TIMERS TIMER_STATUS TIMER_ENABLE TIMER 0 TMR0 TACI0 TACLK0 TIMER 1 TMR1 TACI1 TACLK1 TIMER 2 TMR2 TACI2 TACLK2 TIMER 3 TMR3 TACI3 TACLK3 TIMER 4 TACLK4 TMR4 TACI4 TIMER 5 TACLK5 TMR5 TIMER 6 TMR6 TACLK6 TMR7 TACLK7 TACI7 TIMER 7 TIMER_DISABLE PJ2(PPICLK) PJ3 PF6 PF4 PG5 PF7 PF5 PJ6 PG6(UART1 RX) PH9 PG7(UART1 RX) PG8(UART 0 RX) PG9 CLKBUF PG10 PG11 USB CLK COUNTER0 TO PORT CONTROL Figure 10-24. Timer Block Diagram External Interface The TMRCLK input is common to all eight timers. The PPI unit is clocked by the same pin; therefore any of the timers can be clocked by PPI_CLK. 10-58 ADSP-BF52x Blackfin Processor Hardware Reference Since timer 0 and timer 1 are often used in conjunction with the PPI, they are internally looped back to the PPI module for frame sync generation. The timer signals TMR0 and TMR1 are multiplexed with the PPI frame syncs when the frame syncs are applied externally. PPI modes requiring only one frame sync free up TMR1. For details, see Chapter 15, “Parallel Peripheral Interface”. timer 0 and If the PPI frame syncs are appliedbeexternally,other purposestimer 1 are still fully functional and can used for not involving the TMRx pins. Timer 0 and timer 1 must not drive their TMR0 and TMR1 pins. If operating in PWM_OUT mode, the OUT_DIS bit in the TIMER0_CONFIG and TIMER1_CONFIG registers must be set. ADSP-BF52x Blackfin Processor Hardware Reference 10-59 10-60 ADSP-BF52x Blackfin Processor Hardware Reference 1 1 CORE TIMER This chapter describes the core timer. Following an overview, functional description, and consolidated register definitions, the chapter concludes with a programming example. Specific Information for the ADSP-BF52x For details regarding the number of core timers for the ADSP-BF52x product, please refer to the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. For Core Timer interrupt vector assignments, refer to Table 5-3 on page 5-18 in Chapter 5, “System Interrupts”. For a list of MMR addresses for each Core Timer, refer to Appendix A, “System MMR Assignments”. Core timer behavior for the ADSP-BF52x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Behavior for the ADSP-BF52x Processor” on page 11-9 Overview and Features The core timer is a programmable 32-bit interval timer which can generate periodic interrupts. Unlike other peripherals, the core timer resides ADSP-BF52x Blackfin Processor Hardware Reference 11-1 inside the Blackfin core and runs at the core clock ( CCLK) rate. Core timer features include: • 32-bit timer with 8-bit prescaler • Operates at core clock (CCLK) rate • Dedicated high-priority interrupt channel • Single-shot or continuous operation Timer Overview Figure 11-1 provides a block diagram of the core timer. CORE REGISTER ACCESS BUS (RAB) 32 CCLK TPERIOD TIMER ENABLE AND PRESCALE LOGIC TINT TCNTL TMREN TSCALE COUNT REGISTER LOAD LOGIC TIMER INTERRUPT DEC TCOUNT ZERO Figure 11-1. Core Timer Block Diagram External Interfaces The core timer does not directly interact with any pins of the chip. 11-2 ADSP-BF52x Blackfin Processor Hardware Reference I nternal Interfaces The core timer is accessed through the 32-bit register access bus (RAB). The module is clocked by the core clock CCLK. The timer’s dedicated interrupt request is a higher priority than requests from all other peripherals. D escription of Operation The software should initialize the TCOUNT register before the timer is enabled. The TCOUNT register can be written directly, but writes to the TPERIOD register are also passed through to TCOUNT. When the timer is enabled by setting the TMREN bit in the core timer control register (TCNTL), the TCOUNT register is decremented once every time the prescaler TSCALE expires, that is, every TSCALE + 1 number of CCLK clock cycles. When the value of the TCOUNT register reaches 0, an interrupt is generated and the TINT bit is set in the TCNTL register. If the TAUTORLD bit in the TCNTL register is set, then the TCOUNT register is reloaded with the contents of the TPERIOD register and the count begins again. If the TAUTORLD bit is not set, the timer stops operation. The core timer can be put into low power mode by clearing the TMPWR bit in the TCNTL register. Before using the timer, set the TMPWR bit. This restores clocks to the timer unit. When TMPWR is set, the core timer may then be enabled by setting the TMREN bit in the TCNTL register. Hardware behavior is undefined if TMREN is set when TMPWR = 0. Interrupt Processing The timer’s dedicated interrupt request is a higher priority than requests from all other peripherals. The request goes directly to the core event controller (CEC) and does not pass through the system interrupt control- ADSP-BF52x Blackfin Processor Hardware Reference 11-3 ler (SIC). Therefore, the interrupt processing is also completely in the CCLK domain. edge-sensitive The core timer interruptasrequestasisthe interrupt is and cleared by hardware automatically soon serviced. The TINT bit in the TCNTL register indicates that an interrupt has been generated. Note that this is not a W1C bit. Write a 0 to clear it. However, the write is optional. It is not required to clear interrupt requests. The core time module doesn’t provide any further interrupt enable bit. When the timer is enabled, interrupts can be masked in the CEC controller. Core Timer Registers The core timer includes four core memory-mapped registers, the timer control register (TCNTL), the timer count register (TCOUNT), the timer period register (TPERIOD), and the timer scale register (TSCALE). As with all core MMRs, these registers are always accessed by 32-bit read and write operations. 11-4 ADSP-BF52x Blackfin Processor Hardware Reference C ore Timer Control Register (TCNTL) The TCNTL register, shown in Figure 11-2, functions as control and status register. Core Timer Control Register (TCNTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 X X X X X X X 0 X X X X X X X X X X X X X 2 1 0 0 0 0 TINT Sticky status bit 0 - Timer has not generated an interrupt 1 - Timer has generated an interrupt TAUTORLD 0 - Disable auto-reload feature. When TCOUNT reaches zero, the timer generates an interrupt and halts 1 - Enable auto-reload feature. When TCOUNT reaches zero and the timer generates an interrupt, TCOUNT is automatically reloaded with the contents of TPERIOD and the timer continues to count Reset = Undefined TMPWR 0 - Puts the timer in low power mode 1 - Active state. Timer can be enabled using the TMREN bit TMREN Meaningful only when TMPWR = 1 0 - Disable timer 1 - Enable timer Figure 11-2. Core Timer Control Register C ore Timer Count Register (TCOUNT) The TCOUNT register, shown in Figure 11-3, decrements once every TSCALE + 1 clock cycles. When the value of TCOUNT reaches 0, an interrupt is generated and the TINT bit of the TCNTL register is set. Values written to the TPERIOD register are automatically copied to the TCOUNT register. Nevertheless, the TCOUNT register can be written directly. In auto reload mode the value written to TCOUNT may differ from the TPERIOD value to let the initial period be shorter or longer than following periods. To do this, write to TPERIOD first and overwrite TCOUNT afterward. ADSP-BF52x Blackfin Processor Hardware Reference 11-5 Writes to TCOUNT are ignored once the timer is running. Core Timer Count Register (TCOUNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Reset = Undefined Count Value[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Count Value[15:0] Figure 11-3. Core Timer Count Register Core Timer Period Register (TPERIOD) The TPERIOD register is shown in Figure 11-4. When auto-reload is enabled, the TCOUNT register is reloaded with the value of the TPERIOD register whenever TCOUNT reaches 0. Writes to TPERIOD are ignored when the timer is running. Core Timer Period Register (TPERIOD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Reset = Undefined Period Value[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Period Value[15:0] Figure 11-4. Core Timer Period Register 11-6 ADSP-BF52x Blackfin Processor Hardware Reference C ore Timer Scale Register (TSCALE) The TSCALE register is shown in Figure 11-5. The register stores the scaling value that is one less than the number of cycles between decrements of TCOUNT. For example, if the value in the TSCALE register is 0, the counter register decrements once every CCLK clock cycle. If TSCALE is 1, the counter decrements once every two cycles. Core Timer Scale Register (T SCALE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 X X X X X X X X X X X X X X X X X X X X X 2 1 0 X X Reset = Undefined X Scale Value[7:0] Figure 11-5. Core Timer Scale Register Programming Examples Listing 11-1 configures the core timer in auto-reload mode. Assuming a CCLK of 500 MHz, the resulting period is 1 second. The initial period is twice as long as the others. Listing 11-1. Core Timer Configuration #include <defBF527.h>/*ADSP-BF527 product is used as an example*/ .section L1_code; .global _main; _main: /* Register service routine at EVT6 and unmask interrupt */ p1.l = lo(IMASK); p1.h = hi(IMASK); ADSP-BF52x Blackfin Processor Hardware Reference 11-7 r0.l = lo(isr_core_timer); r0.h = hi(isr_core_timer); [p1 + EVT6 - IMASK] = r0; r0 = [p1]; bitset(r0, bitpos(EVT_IVTMR)); [p1] = r0; /* Prescaler = 50, Period = 10,000,000, First Period = 20,000,000 */ p1.l = lo(TCNTL); p1.h = hi(TCNTL); r0 = 50 (z); [p1 + TSCALE - TCNTL] = r0; r0.l = lo(10000000); r0.h = hi(10000000); [p1 + TPERIOD - TCNTL] = r0; r0 <<= 1; [p1 + TCOUNT - TCNTL] = r0; /* R6 counts interrupts */ r6 = 0 (z); /* start in auto-reload mode */ r0 = TAUTORLD | TMPWR | TMREN (z); [p1] = r0; _main.forever: jump _main.forever; _main.end: /* interrupt service routine simple increments R6 */ isr_core_timer: [--sp] = astat; r6+= 1; astat = [sp++]; rti; isr_core_timer.end: 11-8 ADSP-BF52x Blackfin Processor Hardware Reference U nique Behavior for the ADSP-BF52x Processor None. ADSP-BF52x Blackfin Processor Hardware Reference 11-9 11-10 ADSP-BF52x Blackfin Processor Hardware Reference 1 2 WATCHDOG TIMER This chapter describes the watchdog timer. Following an overview, functional description, and consolidated register definitions, the chapter concludes with programming examples. Specific Information for the ADSP-BF52x For details regarding the number of watchdog timers for the ADSP-BF52x product, please refer to the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. For Watchdog Timer interrupt vector assignments, refer to Table 5-3 on page 5-18 in Chapter 5, “System Interrupts”. For a list of MMR addresses for each Watchdog Timer, refer to Appendix A, “System MMR Assignments”. Watchdog timer behavior for the ADSP-BF52x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Information for the ADSP-BF52x Processor” on page 12-11 Overview and Features The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system reliability by generating an event to the processor core if the watchdog expires before being updated by software. ADSP-BF52x Blackfin Processor Hardware Reference 12-1 Watchdog timer key features include: • 32-bit watchdog timer • 8-bit disable bit pattern • System reset on expire option • NMI on expire option • General-purpose interrupt option Typically, the watchdog timer is used to supervise stability of the system software. When used in this way, software reloads the watchdog timer in a regular manner so that the downward counting timer never expires (never becomes 0). An expiring timer then indicates that system software might be out of control. At this point a special error handler may recover the system. For safety, however, it is often better to reset and reboot the system directly by hardware control. Especially in slave boot configurations, a processor reset cannot automatically force the Blackfin device to be rebooted. In this case, the processor may reset without booting again and may negotiate with the host device by the time program execution starts. Alternatively, a watchdog event can cause an NMI event. The NMI service routine may request the host device reset and/or reboot the Blackfin processor. The watchdog timer is often programmed to let the processor wake up from sleep mode after a programmable period of time. does not For easier debugging, the watchdog timer emulationdecrement (even if enabled) when the processor is in mode. 12-2 ADSP-BF52x Blackfin Processor Hardware Reference I nterface Overview Figure 12-1 provides a block diagram of the watchdog timer. PAB 16 WDEN WDOG_CNT WDOG_CTL 32 WDRO RELOAD WDEV WRITE READ SCLK WDOG_STAT RESET EXPIRE EVENT CONTROL NMI IRQ Figure 12-1. Watchdog Timer Block Diagram External Interface The watchdog timer does not directly interact with any pins of the chip. Internal Interface The watchdog timer is clocked by the system clock SCLK. Its registers are accessed through the 16-bit peripheral access bus (PAB). The 32-bit registers WDOG_CNT and WDOG_STAT must always be accessed by 32-bit read/write operations. Hardware ensures that those accesses are atomic. When the counter expires, one of three event requests can be generated. Either a reset or an NMI request is issued to the core event controller ADSP-BF52x Blackfin Processor Hardware Reference 12-3 (CEC) or a general-purpose interrupt request is passed to the system interrupt controller (SIC). Description of Operation If enabled, the 32-bit watchdog timer counts downward every SCLK cycle. If it becomes 0, one of three event requests can be issued to either the CEC or the SIC. Depending on how the WDEV bit field in the WDOG_CTL register is programmed, the event that is generated may be a reset, a non-maskable interrupt, or a general-purpose interrupt. The counter value can be read through the 32-bit WDOG_STAT register. The WDOG_STAT register cannot, however, be written directly. Rather, software writes the watchdog period value into the 32-bit WDOG_CNT register before the watchdog is enabled. Once the watchdog is started, the period value cannot be altered. To start the watchdog timer: 1. Set the count value for the watchdog timer by writing the count value into the watchdog count register (WDOG_CNT). Since the watchdog timer is not enabled yet, the write to the WDOG_CNT registers automatically pre-loads the WDOG_STAT register as well. 2. In the watchdog control register (WDOG_CTL), select the event to be generated upon timeout. 3. Enable the watchdog timer in WDOG_CTL. The watchdog timer then begins counting down, decrementing the value in the WDOG_STAT register. If software does not service the watchdog in time, WDOG_STAT continues decrementing until it reaches 0. Then, the programmed event is generated. The counter stops decrementing and remains at zero. Additionally, the WDRO latch bit in the WDOG_CTL register is set and can be interrogated by software in case event generation is not enabled. 12-4 ADSP-BF52x Blackfin Processor Hardware Reference When the watchdog is programmed to generate a reset, it resets the processor core and peripherals. If the NOBOOT bit in the SYSCR register was set by the time the watchdog resets the part, the chip is not rebooted. This is recommended behavior in slave boot configurations. The reset handler may evaluate the RESET_WDOG bit in the software reset register SWRST to detect a reset caused by the watchdog. For details, see the System Reset and Booting chapter. To prevent the watchdog from expiring, software services the watchdog by performing dummy writes to the WDOG_STAT register. The values written are ignored, but the write commands cause the WDOG_STAT register to be reloaded from the WDOG_CNT register. If the watchdog is enabled with a zero value loaded to the counter and the WDRO bit was cleared, the WDRO bit of the watchdog control register is set immediately and the counter remains at zero without further decrements. If, however, the WDRO bit was set by the time the watchdog is enabled, the counter decrements to 0xFFFF FFFF and continues operation. Software can disable the watchdog timer only by writing a 0xAD value to the WDEN field in the WDOG_CTL register. Register Definitions The watchdog timer is controlled by three registers. Watchdog Count (WDOG_CNT) Register The WDOG_CNT register, shown in Figure 12-2, holds the 32-bit unsigned count value. The WDOG_CNT register must always be accessed with 32-bit read/writes. A valid write to the WDOG_CNT register also preloads the watchdog counter. For added safety, the WDOG_CNT register can be updated only when the ADSP-BF52x Blackfin Processor Hardware Reference 12-5 watchdog timer is disabled. A write to the WDOG_CNT register while the timer is enabled does not modify the contents of this register. Watchdog Count Register (WDOG_CNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 0000 Watchdog Count[31:16] 0 0 0 0 0 Watchdog Count[15:0] Figure 12-2. Watchdog Count Register Watchdog Status (WDOG_STAT) Register The 32-bit WDOG_STAT register, shown in Figure 12-3, contains the current count value of the watchdog timer. Reads to WDOG_STAT return the current count value. Values cannot be stored directly in WDOG_STAT, but are instead copied from WDOG_CNT. This can happen in two ways. • While the watchdog timer is disabled, writing the WDOG_CNT register pre-loads the WDOG_STAT register. • While the watchdog timer is enabled, but not rolled over yet, writes to the WDOG_STAT register load it with the value in WDOG_CNT. watchdog Enabling therom timer does not automatically reload f . WDOG_STAT 12-6 WDOG_CNT ADSP-BF52x Blackfin Processor Hardware Reference The WDOG_STAT register is a 32-bit unsigned system MMR that must be accessed with 32-bit reads and writes. Watchdog Status Register (WDOG_STAT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 0000 Watchdog Status[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Watchdog Status[15:0] Figure 12-3. Watchdog Status Register Watchdog Control (WDOG_CTL) Register The WDOG_CTL register, shown in Figure 12-4, is a 16-bit system MMR used to control the watchdog timer. The watchdog event (WDEV[1:0]) bit field is used to select the event that is generated when the watchdog timer expires. Note that if the general-purpose interrupt option is selected, the SIC_IMASK register that holds the watchdog timer mask bit should be appropriately configured to unmask that interrupt. If the generation of watchdog events is disabled, the watchdog timer operates as described, except that no event is generated when the watchdog timer expires. The watchdog enable (WDEN[7:0]) bit field is used to enable and disable the watchdog timer. Writing any value other than the disable key (0xAD) into this field enables the watchdog timer. This multibit disable key minimizes the chance of inadvertently disabling the watchdog timer. Software can determine whether the watchdog has expired by interrogating the WDRO status bit of the WDOG_CTL register. This is a sticky bit that is ADSP-BF52x Blackfin Processor Hardware Reference 12-7 set whenever the watchdog timer count reaches 0. It can be cleared only by writing a “1” to the bit when the watchdog has been disabled first. Watchdog Control Register (WDOG_CTL) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 0 WDRO - W1C 0 - Watchdog timer has not expired 1 - Watchdog timer has expired Reset = 0x0AD0 WDEV[1:0] 00 - Generate reset event 01 - Generate NMI 10 - Generate GP interrupt 11 - Disable event generation WDEN[7:0] 0xAD - Counter disabled All other values - Counter enabled Figure 12-4. Watchdog Control Register P rogramming Examples Listing 12-1 shows how to configure the watchdog timer so that it resets the chip when it expires. At startup, the code evaluates whether the recent reset event has been caused by the watchdog. Additionally, the example sets the NOBOOT bit to prevent the memory from being rebooted. Listing 12-1. Watchdog Timer Configuration #include <defBF527.h>/*ADSP-BF527 product is used as an example*/ #define WDOGPERIOD 0x00200000 .section L1_code; .global _reset; _reset: ... /* optionally, test whether reset was caused by watchdog */ 12-8 ADSP-BF52x Blackfin Processor Hardware Reference p0.h=hi(SWRST); p0.l=lo(SWRST); r6 = w[p0] (z); CC = bittst(r6, bitpos(RESET_WDOG)); if !CC jump _reset.no_watchdog_reset; /* optionally, warn at system level or host device here */ _reset.no_watchdog_reset: /* optionally, set NOBOOT bit to avoid reboot in case */ p0.h=hi(SYSCR); p0.l=lo(SYSCR); r0 = w[p0](z); bitset(r0,bitpos(NOBOOT)); w[p0] = r0; /* start watchdog timer, reset if expires */ p0.h = hi(WDOG_CNT); p0.l = lo(WDOG_CNT); r0.h = hi(WDOGPERIOD); r0.l = lo(WDOGPERIOD); [p0] = r0; p0.l = lo(WDOG_CTL); r0.l = WDEN | WDEV_RESET; w[p0] = r0; ... jump _main; _reset.end: The subroutine shown in Listing 12-2 can be called by software to service the watchdog. Note that the value written to the WDOG_STAT register does not matter. ADSP-BF52x Blackfin Processor Hardware Reference 12-9 Listing 12-2. Service Watchdog service_watchdog: [--sp] = p5; p5.h = hi(WDOG_STAT); p5.l = lo(WDOG_STAT); [p5] = r0; p5 = [sp++]; rts; service_watchdog.end: Listing 12-3 is an interrupt service routine that restarts the watchdog. Note that the watchdog must be disabled first. Listing 12-3. Watchdog Restarted by Interrupt Service Routine isr_watchdog: [--sp] = astat; [--sp] = (p5:5, r7:7); p5.h = hi(WDOG_CTL); p5.l = lo(WDOG_CTL); r7.l = WDDIS; w[p5] = r7; bitset(r7, bitpos(WDRO)); w[p5] = r7; r7 = [p5 + WDOG_CNT - WDOG_CTL]; [p5 + WDOG_CNT - WDOG_CTL] = r7; r7.l = WDEN | WDEV_GPI; w[p5] = r7; (p5:5, r7:7) = [sp++]; astat = [sp++]; rti; isr_watchdog.end: 12-10 ADSP-BF52x Blackfin Processor Hardware Reference U nique Information for the ADSP-BF52x Processor None. ADSP-BF52x Blackfin Processor Hardware Reference 12-11 12-12 ADSP-BF52x Blackfin Processor Hardware Reference 1 3 GENERAL-PURPOSE COUNTER This chapter describes the general-purpose up/down counter. The counter provides support for manually controlled rotary controllers, such as the volume wheel on a radio device. This unit also supports industrial encoders. Following the overview and list of key features is a description of the operating modes. This chapter concludes with a programming model, consolidated register definitions, and programming examples. Specific Information for the ADSP-BF52x For details regarding the number of GP counters for the ADSP-BF52x product, please refer to the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. For GP counter interrupt vector assignments, refer to Table 5-3 on page 5-18 in Chapter 5, “System Interrupts”. To determine how each of the GP counters is multiplexed with other functional pins, refer to Table 9-2 on page 9-5 through Table 9-5 on page 9-9 in Chapter 9, “General-Purpose Ports”. For a list of MMR addresses for each GP counter, refer to Appendix A, “System MMR Assignments”. GP counter behavior for the ADSP-BF52x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Behavior for the ADSP-BF52x Processor” on page 13-38 ADSP-BF52x Blackfin Processor Hardware Reference 13-1 O verview The purpose of this interface is to convert pulses from incremental position encoders into data that is representative of the actual position. This is done by integrating (counting) pulses on one or two inputs. Since integration provides relative position, some devices also feature a zero position input (zero marker) that can be used to establish a reference point to verify that the acquired position does not drift over time. In addition, the incremental position information can be used to determine speed, if the time intervals are measured. The GP counter provides flexible ways to establish position information. When used in conjunction with the GP timer block, the GP counter allows for the acquisition of coherent position/time-stamp information that enables speed calculation. Features The GP counter includes the following features: • 32-bit up/down counter • Quadrature encoder mode (Gray code) • Binary encoder mode • Alternative frequency-direction mode • Timed direction and up/down counting modes • Zero marker/push button support • Capture event timing in association with general purpose timer • Boundary comparison and boundary setting features 13-2 ADSP-BF52x Blackfin Processor Hardware Reference • Input pin noise filtering (debouncing) • Flexible error detection/signaling I nterface Overview A block diagram of the GP counter is shown in Figure 13-1. There are two input pins, the count up and direction (CUD) pin and the count down and gate (CDG) pin, that accept various forms of incremental inputs and are processed by the 32-bit counter. The third input, count zero marker (CZM), is the zero marker input. The module interfaces to the processor by way of the peripheral access bus (PAB) and can optionally generate an interrupt request through the IRQ line. There is also an output that can be used by the timer module to generate time-stamps on certain events. CUD CDG PROGRAMMABLE NOISE FILTERING 32-BIT QUADRATURE COUNTER CZM CONTROL BLOCK AND PROCESSOR INTERFACE IRQ BOUNDARY DETECTION LOGIC AND EVENT GENERATION TO GP TIMER OUTPUT PAB BUS Figure 13-1. Block Diagram of the GP Counter Interface ADSP-BF52x Blackfin Processor Hardware Reference 13-3 D escription of Operation The GP counter has five modes of operation that are described in this section. With the exception of the timed direction mode, the GP counter can operate with the GP timer block to capture additional timing information (time-stamps) associated with events detected by this block. The third input (CZM) may be used as a zero marker or to sense the pressing of a push button. Refer to “Zero Marker (Push Button) Operation” on page 13-9 for more details. The three input pins may be filtered (debounced) before being evaluated by the GP counter. Refer to “Input Noise Filtering (Debouncing)” on page 13-8 for more details. The GP counter also features a flexible boundary comparison. In all of the operating modes, the counter can be compared to an upper and lower limit. A variety of actions can be taken when these limits are reached. Refer to “Boundary Comparison Modes” on page 13-10 for more details. Quadrature Encoder Mode In this mode, the CUD:CDG inputs expect a quadrature-encoded signal that is interpreted as a 2-bit Gray code. The order of transitions of the CUD and CDG inputs determines whether the counter increments or decrements. The CNT_COUNTER register contains the number of transitions that have occurred. Refer to Table 13-1 for more details. Optionally, an interrupt is generated if both inputs change within one SCLK cycle. Such transitions are not allowed by Gray coding. Therefore, 13-4 ADSP-BF52x Blackfin Processor Hardware Reference the CNT_COUNTER register remains unchanged and an error condition is signaled. Table 13-1. Quadrature Events and Counting Mechanism CNT_COUNTER Register Value –4 –3 –2 –1 0 +1 +2 +3 +4 CDG:CUD Inputs 00 01 11 10 00 01 11 10 00 It is possible to reverse the count direction of the Gray coded signal. This can be achieved by enabling the polarity inverter of either the CUD pin or the CDG pin. Inverting both pins will not alter the behavior. This feature can be enabled with the CDGINV and CUDINV bits in the CNT_CONFIG register. As an example, if the CDG:CUD inputs are 00 respectively and the next transition is to 01, this would normally increment the counter as is shown in Table 13-1 on page 13-5. If the CUD polarity is inverted this generates a received input of 01 followed by 00. This will result in a decrement of the counter, altering the behavior of the connected hardware. Binary Encoder Mode This mode is almost identical to the previous mode, with the exception that the CUD:CDG inputs expect a binary-encoded signal. The order of transitions of the CUD and CDG inputs determines whether the counter increments or decrements. The CNT_COUNTER register contains the number of transitions that have occurred. Refer to Table 13-2. Optionally, an interrupt is generated if the detected code steps by more than 1 (in binary arithmetic) within one SCLK cycle. Such transitions are ADSP-BF52x Blackfin Processor Hardware Reference 13-5 considered erroneous. Therefore, the CNT_COUNTER register remains unchanged and an error condition is signaled. Table 13-2. Binary Events and Counting Mechanism CNT_COUNTER Register Value –4 –3 –2 –1 0 +1 +2 +3 +4 CDG:CUD Inputs 00 01 10 11 00 01 10 11 00 Reversing the CUD and CDG pin polarity has a different effect for the binary encoder mode than for the quadrature encoder mode. Inverting the polarity of the CUD pin only, or inverting both the CUD and CDG pins, will result in reversing the count direction. Up/Down Counter Mode In this mode, the counter is incremented or decremented at every active edge of the input pins. If an active edge is detected at the CUD input, the counter increments. The active edge can be selected by the CUDINV bit in the CNT_CONFIG register. If this bit is cleared, a rising edge will increment the counter. If this bit is set, a falling edge will increment the counter. If an active edge is detected at the CDG input, the counter decrements. The active edge can be selected by the CDGINV bit in the CNT_CONFIG register. If this bit is cleared, a rising edge will decrement the counter. If this bit is set, a falling edge will decrement the counter. If simultaneous edges occur on pin CDG and pin CUD, the counter remains unchanged and both up-count and down-count events are signaled in the CNT_STATUS register. 13-6 ADSP-BF52x Blackfin Processor Hardware Reference D irection Counter Mode In this mode, the counter is incremented or decremented at every active edge of the CDG input pin. The state of the CUD input determines whether the counter increments or decrements. The polarity can be selected by the CUDINV bit in the CNT_CONFIG register. If this bit is cleared, a high CUD input will increment, a low input will decrement. If this bit is set, the polarity is inverted. If an active edge is detected at the CDG input, the counter value changes by one in the selected direction. The active edge can be selected by the CDGINV bit in the CNT_CONFIG register. If this bit is cleared, a rising edge will decrement the counter. If this bit is set, a falling edge will decrement the counter. Timed Direction Mode In this mode, the counter is incremented or decremented at each SCLK cycle. The state of the CUD input determines whether the counter increments or decrements. The polarity can be selected by the CUDINV bit in the CNT_CONFIG register. If this bit is cleared, a high CUD input will increment the counter, a low input will decrement it. If this bit is set, the polarity is inverted. The CDG pin can be used to gate the clock. The polarity can be selected by the CDGINV bit in the CNT_CONFIG register. If this bit is cleared, a high CDG input will enable the counter, a low input will stop it. If this bit is set, the polarity is inverted. Functional Description The following sections describe the various functions in more detail. ADSP-BF52x Blackfin Processor Hardware Reference 13-7 I nput Noise Filtering (Debouncing) In all modes, the three input pins can be filtered to present clean signals to the GP counter logic. This filtering can be enabled or disabled by the DEBE bit in the CNT_CONFIG register. Figure 13-2 shows the filtering operation for the CUD pin. t filter NOISY EDGES CUD CUD FILTERED Figure 13-2. Programmable Noise Filtering The filtering mechanism is implemented using counters for each pin. The counter for each pin is initialized from the DPRESCALE field of the CNT_DEBOUNCE register. When a transition is detected on a pin, the corresponding counter starts counting up to the programmed number of SCLK cycles. The state of the pin is latched after time tfilter and passed on to the GP counter logic. The 5-bit DPRESCALE field in the CNT_DEBOUNCE register programs the desired number of cycles and therefore the debouncing time. The number of SCLK cycles for each pin can be selected in 18 steps ranging from 1 × 128 SCLK periods to 131072 × 128 SCLK periods (see Figure 13-9 on page 13-25). The time tfilter is determined, given SCLK and the DPRESCALE value contained in the CNT_DEBOUNCE register, by the following formula: DPRESCALE t filter = 128 2 SCLK 13-8 ADSP-BF52x Blackfin Processor Hardware Reference where DPRESCALE can contain values from 0 (minimum filtering) to 17 (maximum filtering). Assuming an SCLK frequency of 133 MHz, the filter time range is shown by the following equations: DPRESCALE = 0b0000 t filter = 128 *1*7.5ns = 960 ns = (approx.) 1 s = 0b10001 t filter = 128 131072 *7.5ns = 125829 s = (approx.) 126ms DPRESCALE Zero Marker (Push Button) Operation The CZM input pin can be used to sense the zero marker output of a rotary device or to detect the pressing of a push button. There are four programming schemes which are functional in all counter modes: • Push button mode–This mode is enabled by setting the CZMIE bit in the CNT_IMASK register. An active edge at the CZM input will set the CZMII bit in the CNT_STATUS register. If enabled at the system interrupt controller, this will generate an interrupt request. The active edge is selected by the CZMINV bit in the CNT_CONFIG register (rising edge if cleared, falling edge if set to one). • Zero-marker-zeros-counter mode–This mode is enabled by setting the ZMZC bit in the CNT_CONFIG register. An active level at the CZM input clears the CNT_COUNTER register and holds it until the CZM pin is deactivated. In addition, if enabled by the CZMZIE bit in the CNT_IMASK register, it will set the CZMZII bit in the CNT_STATUS register. If enabled by the peripheral interrupt controller, this will generate an interrupt request. The active level is selected by the CZMINV bit in the CNT_CONFIG register (active high if cleared, active low if set to one). ADSP-BF52x Blackfin Processor Hardware Reference 13-9 • Zero-marker-error mode–This mode is used to detect discrepancies between counter value and the zero marker output of certain rotary encoder devices. It is enabled by setting the CZMEIE bit in the CNT_IMASK register. When an active edge is detected at the CZM input pin, the four LSBs of the CNT_COUNTER register are compared to zero. If they are not zero, a mismatch is signaled by way of the CZMEII bit in the CNT_STATUS register. If enabled by the peripheral interrupt controller, this will generate an interrupt request. The active edge is selected by the CZMINV bit in the CNT_CONFIG register: (rising edge if cleared, falling edge if set to one). • Zero-once mode–This mode is used to perform an initial reset of the counter value when an active zero marker is detected. After that, the zero marker is ignored (the counter is not reset anymore). This mode is enabled by setting the W1ZMONCE bit in the CNT_COMMAND register. The CNT_COUNTER register and the W1ZMONCE bit are cleared on the next active edge on the CZM pin. Thus, the W1ZMONCE bit can be read to check whether the event has already occurred, if desired. The active edge of the CZM pin is selected by the CZMINV bit in the CNT_CONFIG register (rising edge if cleared, falling edge if set to one). Boundary Comparison Modes The GP counter includes two boundary registers, CNT_MIN (lower) and CNT_MAX (upper). The counter value is compared to the lower and upper boundary. Depending on which mode is selected, different actions are taken if the count value reaches either of the boundary values. There are four boundary modes: • 13-10 Boundary-compare mode–The two boundary registers are simply compared to the CNT_COUNTER register. If, after incrementing, CNT_COUNTER equals CNT_MAX then the MAXCII bit in the CNT_STATUS register is set. If the MAXCIE bit in the CNT_IMASK register is set, an ADSP-BF52x Blackfin Processor Hardware Reference interrupt request is generated. Similarly if, after decrementing, CNT_COUNTER equals CNT_MIN then the MINCII status bit is set. If the MINCIE bit in the CNT_IMASK register is set, an interrupt request is generated. The MAXCII and MINCII bits are not set if the CNT_MAX and CNT_MIN registers are updated by software. • Boundary-zero mode–This mode is similar to the boundary-compare mode. In addition to setting the status bits and requesting interrupts, the counter value in the CNT_COUNTER register is also set to zero. • Boundary auto-extend mode–In this mode, the boundary registers are modified by hardware whenever the counter value reaches either of them. The CNT_MAX register is loaded with the current CNT_COUNTER value if the latter increments beyond the CNT_MAX value. Similarly, the CNT_MIN register is loaded with the CNT_COUNTER value if the latter decrements below the CNT_MIN value. This mode may be used to keep track of the widest angle the wheel ever reported, even if the software did not serve interrupts. At startup, the application software should set both boundary registers to the initial CNT_COUNTER value. The MAXCII and MINCII status bits are still set when the counter value matches the boundary register. • Boundary-capture mode–In this mode, the CNT_COUNTER value is latched into the CNT_MIN register at one detected edge of the CZM input pin, and latched into CNT_MAX at the opposite edge. If the CZMINV bit in the CNT_CONFIG register is cleared, a rising edge captures into CNT_MIN and a falling edge into CNT_MAX. If the CZMINV bit is set, the edges are inverted. The MAXCII and MINCII status bits report the capture event. The comparison is performed with signed arithmetic. The boundary registers and the counter value are all treated as signed integer values. ADSP-BF52x Blackfin Processor Hardware Reference 13-11 C ontrol and Signaling Events Eleven events can be signaled to the processor using status information and optional interrupt requests. The interrupts are enabled by the respective bits in the CNT_IMASK register. Dedicated bits in the CNT_STATUS register report events. When an interrupt from the GP counter is acknowledged, the application software is responsible for correct interpretation of the events. It is recommended to logically AND the content of the CNT_IMASK and CNT_STATUS registers to identify pending interrupts. Interrupt requests are cleared by write-one-to-clear (W1C) operations to the CNT_STATUS register. Hardware does not clear the status bits automatically, unless the counter module is disabled. Illegal Gray/Binary Code Events When the illegal transitions described in “Quadrature Encoder Mode” on page 13-4 or “Binary Encoder Mode” on page 13-5 occur, the ICII bit in the CNT_STATUS register is set. If enabled by the ICIE bit in the CNT_IMASK register, an interrupt request is generated. The ICIE bit should only be set in the quadrature encoder or binary encoder modes. Up/Down Count Events The UCII bit in the CNT_STATUS register indicates whether the counter has been incremented. Similarly, the DCII bit reports decrements. The two events are independent. For instance, if the counter first increments by one and then decrements by two, both bits remain set, even though the resulting counter value shows a decrement by one. In up/down counter mode, hardware may detect simultaneous active edges on the CUD and CDG inputs. In that case, the CNT_COUNTER remains unchanged, but both the UCII and DCII bits are set. Interrupt requests for these events may be enabled through the UCIE and DCIE bits. This feature should be used carefully when the counter is 13-12 ADSP-BF52x Blackfin Processor Hardware Reference clocked at high rates. This is especially critical when the counter operates in DIR_TMR mode, as interrupts would be generated every SCLK cycle. These events can also be used for additional push buttons, if GP counter features are not needed. When up/down counter mode is enabled, these count events can be used to report interrupts from push buttons that connect to the CUD and CDG inputs. Zero-Count Events The CZEROII status bit indicates that the CNT_COUNTER has reached a value equal to 0x0000 0000 after an increment or decrement. This bit is not set when the counter value is set to zero by a write to CNT_COUNTER or by setting the W1LCNT_ZERO bit in the CNT_COMMAND register. If enabled by the CZEROIE bit, an interrupt request is generated. Overflow Events There are two status bits that indicate whether the signed counter register has overflowed from a positive to a negative value or vice versa. The COV31II bit reports that the 32-bit CNT_COUNT register has either incremented from 0x7FFF FFFF to 0x8000 0000, or decremented from 0x8000 0000 to 0x7FFF FFFF. If enabled by the COV31IE bit, an interrupt request is generated. Similarly, in applications where only the lower 16 bits of the counter are of interest, the COV15II status bit reports counter transitions from 0xXXXX 7FFF to 0xXXXX 8000, or from 0xXXXX 8000 to 0xXXXX 7FFF. If enabled by the COV15IE bit, an interrupt request is generated. Boundary Match Events The MINCII and MAXCII status bits report boundary events as described in “Boundary Comparison Modes” on page 13-10. These bits are not set if ADSP-BF52x Blackfin Processor Hardware Reference 13-13 the CNT_COUNTER, CNT_MAX or CNT_MIN registers are updated by software or the CNT_COMMAND register is written to. The MINCIE and MAXCIE bits in the CNT_IMASK register enable interrupt generation on boundary events. Zero Marker Events There are three status bits CZMII, CZMEII and CZMZII associated with zero marker events, as described in “Zero Marker (Push Button) Operation” on page 13-9. Each of these events can optionally generate an interrupt request, if enabled by the corresponding CZMIE, CZMEIE and CZMZIE bits in the CNT_IMASK register. Capturing Timing Information To calculate speed, many applications may wish to measure the time between two count events—in addition to accurately counting encoder pulses. For more accuracy, particularly at very low speeds, it is also necessary to obtain the time that has elapsed since the last count event. This additional information allows for estimating how much the GP counter has advanced since the last counter event. For this purpose, the GP counter has an internal signal that connects to the alternate capture input (TACIx) of one of the GP timers. It is functional in all modes, with the exception of the timed direction mode. Refer to the "Internal Interfaces" section of Chapter 9, “General-Purpose Ports” for information regarding which GP timer(s) are associated with which GP counter module(s) for your device. In order to use the timing measurements, the associated GP timer must be used in the WDTH_CAP mode. The alternate capture input is selected by setting the TIN_SEL bit in the GP timer's TIMER_CONFIG register. For more information about the GP timers and their operating modes, refer to the General-Purpose Timer chapter. 13-14 ADSP-BF52x Blackfin Processor Hardware Reference C apturing Time Interval Between Successive Counter Events When the only timing information of interest is the interval between successive count events, the associated timer should be programmed in WDTH_CAP mode with PULSE_HI = 1, PERIOD_CNT = 1 and TIN_SEL = 1. Typically, this information is sufficient if the speed of GP counter events is known not to reach very low values. Figure 13-3 shows the operation of the GP counter and the GP timer in this mode. TO generates a pulse every time a count event occurs. The GP timer will update its TIMER_PERIOD register with the period (measured from rising edge to rising edge) of the TO signal. The TIMER_PERIOD register is updated at every rising edge of the TO signal and contains the number of system clock (SCLK) cycles that have elapsed since the previous rising edge. Incidentally, the TIMER_WIDTH register is also updated at the same time, but is generally of no interest in this mode of operation. If no reads of the CNT_COUNTER register occur between counter events, the TIMER_WIDTH register only contains the width of the TO pulse. If a read of CNT_COUNTER has occurred between events, the TIMER_WIDTH register will contain the time between the read of CNT_COUNTER and the next event. ADSP-BF52x Blackfin Processor Hardware Reference 13-15 This mode can also be used with PULSE_HI = 0. In this case, the period of TO is measured between falling edges. It will result in the same values as in the previous case, only the latching occurs one SCLK cycle later. SCLK CUD CDG TIMER_PERIOD TO CNT_COUNTER TIMER_COUNTER 1 1 2 2 3 1 2 3 4 3 5 6 7 1 2 4 3 1 2 5 3 4 1 2 TIMER_PERIOD BUFFER 10 3 7 3 4 TIMER_WIDTH BUFFER 1 1 1 1 1 TIMER_PERIOD 10 3 7 3 4 TIMER_WIDTH 1 1 1 1 1 Measurement reports available Figure 13-3. Operation with GP Timer Module Capturing Counter Interval and CNT_COUNTER Read Timing It is possible to also capture the time elapsed since the last count event. In this mode, the associated timer should be programmed in WDTH_CAP mode with PULSE_HI = 0, PERIOD_CNT = 0 and TIN_SEL = 1. Typically, this additional information is used to estimate the advancement of the GP counter 13-16 ADSP-BF52x Blackfin Processor Hardware Reference since the last count event, when the speed is very low. Figure 13-4 shows the operation of the GP counter module and the GP timer module in this mode. TO generates a pulse every time a count event occurs. In addition, when the processor reads the CNT_COUNTER register, the TO signal presents a pulse which is extended (high) until the next count event. The GP timer will update its TIMER_PERIOD register with the period (measured from falling edge to falling edge, because PULSE_HI = 0) of the TO signal. The TIMER_WIDTH register is updated with the pulse width (the portion where TO is low, again because PULSE_HI = 0). Both registers are updated at every rising edge of the TO signal (because PERIOD_CNT = 0). Therefore, the TIMER_PERIOD register contains the period between the last two count events and the TIMER_WIDTH register contains the time since the last count event and the read of the CNT_COUNTER register, both measured in number of SCLK cycles. The result is that when reading the CNT_COUNTER register, the two time measurements are also latched and the user has a coherent triplet of information to calculate speed and position. apply use terms Restrictionsthe userto the takeof thetoTO signal in at veryof speed. Therefore, must care not operate high count events. For instance, if CNT_COUNTER is incremented/decremented every SCLK cycle (timed direction mode), the TO signal is incorrect. ADSP-BF52x Blackfin Processor Hardware Reference 13-17 SCLK CUD CDG CNT_COUNTER READ TIMER_PERIOD TO CNT_COUNTER TIMER_COUNTER TIMER_PERIOD BUFFER 1 12 2 1 2 1 12 X 3 2 3 1 4 2 3 1 2 3 2 3 5 4 5 6 7 3 8 6 1 2 8 TIMER_WIDTH BUFFER 11 1 2 2 4 1 TIMER_PERIOD x 12 2 3 3 8 TIMER_WIDTH 11 1 2 2 4 1 Measurement report of interest due to read of CNT_COUNTER Figure 13-4. Capturing Counter Interval P rogramming Model In a typical application, the user will initialize the GP counter for the desired mode, without enabling it. Normally the events of interest will be processed using interrupts rather than polling the status bit. In that case, 13-18 ADSP-BF52x Blackfin Processor Hardware Reference clear all status bits and activate the generation of interrupt requests with the CNT_IMASK register. Set up the system interrupt controller and core interrupts. If timing information is required, set up the relevant GP timer in WDTH_CAP mode with the settings described in the “Capturing Timing Information” on page 13-14. Then, enable the interrupts and the peripheral itself. Registers The GP counter interface has eight memory-mapped registers (MMRs) that regulate its operation. Descriptions and bit diagrams for MMRs is provided in the sections that follow. Counter Module Register Overview Refer to Table 13-3 for an overview of all MMRs associated with the GP counter interface. Table 13-3. Counter Module Register Overview Register Name Width PAB Operation Reset Value CNT_CONFIG 16 bits R/W 0x0000 CNT_IMASK 16 bits R/W 0x0000 CNT_STATUS 16 bits R/W1C 0x0000 CNT_COMMAND 16 bits R/W1A 0x0000 CNT_DEBOUNCE 16 bits R/W 0x0000 CNT_COUNTER 32 bits R/W (16/32 bits) 0x0000 0000 CNT_MAX 32 bits R/W (16/32 bits) 0x0000 0000 CNT_MIN 32 bits R/W (16/32 bits) 0x0000 0000 ADSP-BF52x Blackfin Processor Hardware Reference 13-19 C ounter Configuration Register (CNT_CONFIG) This register is used to configure counter modes and input pins, as well as to enable the peripheral. It can be accessed at any time with 16-bit read and write operations. Counter Configuration (CNT_CONFIG) Register 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 INPDIS (CUD and CDG Input Disable) 0 = Enabled 1 = Disabled Reset = 0x0000 CNTE (Counter Enable) 0 = Disabled 1 = Enabled DEBE (Debounce Enable) BNDMODE (Boundary Register Mode) 00: BND_COMP 01: BIN_ENC 10: BND_CAPT 11: BND_AEXT 0 = Disabled 1 = Enabled ZMZC (CZM Zeroes Counter Enable) Level sensitive - active CZM pin zeroes CNT_COUNTER CNTMODE (Counter Operating Mode) 000: QUAD_ENC - quadrature encoder mode 001: BIN_ENC - binary encoder mode 010: UD_CNT - up/down counter mode 011: Reserved 100: DIR_CNT - direction counter mode 101: DIR_TMR - direction timer mode 110: Reserved 111: Reserved CDGINV (CDG Pin Polarity Invert) 0 = Active high, rising edge 1 = Active low, falling edge CUDINV (CUD Pin Polarity Invert) 0 = Active high, rising edge 1 = Active low, falling edge CZMINV (CZM Pin Polarity Invert) 0 = Active high, rising edge 1 = Active low, falling edge Figure 13-5. Counter Configuration Register Counter Interrupt Mask Register (CNT_IMASK) This register is used to enable interrupt request generation from each of the eleven events. It can be accessed at any time with 16-bit read and write 13-20 ADSP-BF52x Blackfin Processor Hardware Reference operations. For explanations of the register bits, refer to the “Control and Signaling Events” on page 13-12. Counter Interrupt Mask (CNT_IMASK) Register 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 ICIE (Illegal Gray/binary code interrupt enable) CZMZIE (Counter zeroed by zero marker interrupt enable) UCIE (Upcount interrupt enable) CZMEIE (Zero marker error interrupt enable) DCIE (Downcount interrupt enable) CZMIE (CZM pin interrupt enable/push-button interrupt) MINCIE (Min count interrupt enable) CZEROIE (CNT_COUNTER counts to zero interrupt enable MAXCIE (Max count interrupt enable) COV15IE (Bit 15 overflow interrupt enable) COV31IE (Bit 31 overflow interrupt enable) For all bits: 0 = Interrupt disabled 1 = Interrupt enabled Figure 13-6. Counter Interrupt Mask Register Counter Status Register (CNT_STATUS) This register provides status information for each of the eleven events where 0 = no interrupt pending and 1 = interrupt pending. When an event is detected, the corresponding bit in this register is set. It remains set until either software writes a “1” to the bit (write-1-to-clear) or the GP counter ADSP-BF52x Blackfin Processor Hardware Reference 13-21 is disabled. For explanations of the register bits, refer to the “Control and Signaling Events” on page 13-12. Counter Status (CNT_STATUS) Register 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 CZMZIE (Counter zeroed by zero marker) (W1C) CZMEII (Zero marker error interrupt) (W1C) CZMII (CZM pin interrupt/ Push-button interrupt) (W1C) CZEROII (CNT_COUNTER counts to zero interrupt) (W1C) COV15II (Bit 15 overflow interrupt) (W1C) For all bits: 0 = No Interrupt pending 1 = Interrupt pending Reset = 0x0000 ICII (Illegal Gray/binary code interrupt) (W1C) UCII (Upcount interrupt) (W1C) DCII (Downcount interrupt) (W1C) MINCII (Min interrupt) (W1C) MAXCII (Max interrupt) (W1C) COV31II (Bit 31 overflow interrupt) (W1C) Figure 13-7. Counter Status Register Counter Command Register (CNT_COMMAND) The CNT_COMMAND register (shown in Figure 13-8 on page 13-24) configures the GP counter, enabling operations such as zeroing a counter register and copying or swapping boundary registers. These actions are taken by writing a “one” to the appropriate bit. Read operations from this register will not return meaningful values, with the exception of the W1ZONCE bit, where a “1” indicates that the bit has been set by software before, but no zero marker event has been detected on the CZM pin yet. Refer to the “Zero Marker (Push Button) Operation” on page 13-9 for more details. The CNT_COUNTER, CNT_MIN and CNT_MAX registers can be initialized to zero by writing a “one” to the W1LCNT_ZERO, W1LMIN_ZERO and W1LMAX_ZERO 13-22 ADSP-BF52x Blackfin Processor Hardware Reference fields. In addition to clearing registers, CNT_COMMAND allows the boundary registers to be modified in a number of ways. The current counter value in CNT_COUNT can be captured and loaded into either of the two boundary registers CNT_MAX and CNT_MIN to create new boundary limits. This is performed by setting the W1LMAX_CNT and W1LMIN_CNT bits. Alternatively, the counter can be loaded from CNT_MAX or CNT_MIN via the W1LCNT_MAX and W1LCNT_MIN bits. It is also possible to transfer the current CNT_MAX value into CNT_MIN (or vice versa) through the W1LMIN_MAX and W1LMAX_MIN bits. The final supported operation is the ability to only have the zero marker clear the CNT_COUNT register once, as described in “Zero Marker (Push Button) Operation” on page 13-9. It is possible for multiple actions to be performed simultaneously by setting multiple bits in the CNT_COMMAND register. However, there are restrictions. The bits associated with each command have been grouped together such that all bits that involve a write to the CNT_COUNTER register are located within bits 3:0 of the CNT_COMMAND register. All commands that involve a write to the CNT_MIN register are located within bits 7:4 of the CNT_COMMAND register, and all commands that involve a write to the CNT_MAX register are located within bits 11:8 of the CNT_COMMAND register. be A maximum of three commands canNoteissued( at any one time, command. that , excluding the W1ZMONCE W1LCNT_MAX W1LCNT_MIN and W1LCNT_ZERO) have to be used exclusively. Never ADSP-BF52x Blackfin Processor Hardware Reference 13-23 set more than one of them at the same time. The same rule applies for (W1LMAX_MIN, W1LMAX_CNT and W1LMAX_ZERO) and for (W1LMIN_MAX, W1LMIN_CNT, and W1LMIN_ZERO). Counter Command (CNT_COMMAND) Register 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W1ZMONCE (Write one to enable single Zero marker clear CNT_COUNT action (W1A/R) W1LMAX_MIN (Write one to copy former CNT_MIN to new CNT_MAX) (W1A) W1LMAX_CNT (Write one to capture CNT_COUNTER to CNT_MAX Register) (W1A) W1LMAX_ZERO (Write one to zero CNT_MAX Register) (W1A) W1LMIN_MAX (Write one to copy former CNT_MAX to new CNT_MIN (W1A) Reset = 0x0000 W1LCNT_ZERO (Write one to zero CNT_COUNTER) (W1A) W1LCNT_MIN (Write one to zero CNT_COUNTER (W1A) W1LCNT_MAX (Write one to load CNT_COUNTER from CNT_MAX) (W1A) W1LMIN_ZERO (Write one to zero CNT_MIN Register) (W1A) W1LMIN_CNT (Write one to capture CNT_COUNTER to CNT_MIN Register) (W1A) Figure 13-8. Counter Command Register Counter Debounce Register (CNT_DEBOUNCE) This register is used to select the noise filtering characteristic of the three input pins (see “Input Noise Filtering (Debouncing)” on page 13-8). Bits 13-24 ADSP-BF52x Blackfin Processor Hardware Reference [4:0] determine the filter time. The register can be accessed at any time with 16-bit read and write operations. DPRESCALE t filter = 128 2 SCLK Counter Debounce (CNT_DEBOUNCE) Register 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 DPRESCALE (DEBOUNCE DELAY) 00000: 1 x 128 SCLK cycles 00001: 2 x 128 SCLK cycles 00010: 4 x 128 SCLK cycles 00011: 8 x 128 SCLK cycles 00100: 16 x 128 SCLK cycles 00101: 32 x 128 SCLK cycles 00110: 64 x 128 SCLK cycles 00111: 128 x 128 SCLK cycles 01000: 256 x 128 SCLK cycles 01001: 512 x 128 SCLK cycles 01010: 1024 x 128 SCLK cycles 01011: 2048 x 128 SCLK cycles 01100: 4096 x 128 SCLK cycles 01101: 8192 x 128 SCLK cycles 01110: 16384 x 128 SCLK cycles 01111: 32768 x 128 SCLK cycles 10000: 65536 x 128 SCLK cycles 10001: 131072 x 128 SCLK cycles Others: Reserved Figure 13-9. Counter Debounce Register Counter Count Value Register (CNT_COUNTER) This register holds the 32-bit, twos-complement, count value. It can be read and written at any time. Hardware ensures that reads and write are atomic, by providing respective shadow registers. This register can be ADSP-BF52x Blackfin Processor Hardware Reference 13-25 accessed with either 32-bit or 16-bit operations. This allows use of the GP counter as a 16-bit counter if sufficient for the application. Counter Count Value (CNT_COUNTER) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 Reset = 0x0000 0000 Count Value 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Count Value Figure 13-10. Counter Count Value Register Counter Boundary Registers (CNT_MIN and CNT_MAX) These registers hold the 32-bit, twos-complement, lower and upper boundary values. They can be read and written at any time. Hardware ensures that reads and write are atomic, by providing respective shadow registers. This register can be accessed with either 32-bit or 16-bit operations. This allows for using the GP counter as a 16-bit counter if sufficient for the application. 13-26 ADSP-BF52x Blackfin Processor Hardware Reference Counter Maximal Count (CNT_MAX) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 Reset = 0x0000 0000 CNT_MAX (Counter Max) 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 CNT_MAX (Counter Max) Figure 13-11. Counter Maximal Count Register Counter Minimal Count (CNT_MIN) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 Reset = 0x0000 0000 0 CNT_MIN[ 31:16] (Counter Min) 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 CNT_MIN[15:0] (Counter Min) Figure 13-12. Counter Minimal Count Register P rogramming Examples Listing 13-1 illustrates how to initialize the GP counter for various modes. The required interrupts are first unmasked. The GP counter is then con- ADSP-BF52x Blackfin Processor Hardware Reference 13-27 figured for the required mode of operation. Note that at this point we do not yet enable the counter. Finally, some GP counter MMRs are cleared, as well as any interrupts that may be pending in the CNT_STATUS register. Listing 13-1. Initializing the GP Counter /* Setup Counter Interrupts */ P5.H = hi(CNT_IMASK); P5.L = lo(CNT_IMASK); R5 = nCZMZIE /* Counter zeroed by zero marker interrupt */ | CZMEIE /* Zero marker error interrupt */ | CZMIE /* CZM pin interrupt (push-button) */ | CZEROIE /* Counts to zero interrupt */ | nCOV15IE /* Counter bit 15 overflow interrupt */ | nCOV31IE /* Counter bit 31 overflow interrupt */ | MAXCIE /* Max count interrupt */ | MINCIE /* Min count interrupt */ | DCIE /* Downcount interrupt */ | UCIE /* Upcount interrupt */ | ICIE (z); /* Illegal gray/binary code interrupt */ w[P5] = R5; /* Configure the GP Counter mode of operation */ P5.H = hi(CNT_CONFIG); P5.L = lo(CNT_CONFIG); R5 = nINPDIS /* Enable CUD and CDG inputs */ | BNDMODE_COMP /* Boundary compare mode */ | nZMZC /* Disable Zero Counter Enable */ | CNTMODE_QUADENC /* Quadrature Encoder Mode */ | CZMINV /* Polarity of CUD pin */ | nCDGINV /* Polarity of CDG Pin */ | nDEBE /* Disable the debounce */ | nCNTE (z); 13-28 /* Polarity of CZM pin */ | nCUDINV /* Disable the counter */ ADSP-BF52x Blackfin Processor Hardware Reference w[P5] = R5; /* Zero the CNT_COUNT, CNT_MIN and CNT_MAX registers This is optional as after reset they are default to zero */ P5.H = hi(CNT_COMMAND); P5.L = lo(CNT_COMMAND); R5 = W1LCNT_ZERO | W1LMIN_ZERO | W1LMAX_ZERO (z); w[P5] = R5; /* Clear any identified interrupts */ P5.H = hi(CNT_STATUS); P5.L = lo(CNT_STATUS); R5.L = ICII /* Illegal Gray/Binary Code Interrupt Identifier */ | UCII /* Up count Interrupt Identifier */ | DCII /* Down count Interrupt Identifier */ | MINCII /* Min Count Interrupt Identifier */ | MAXCII /* Max Count Interrupt Identifier */ | COV31II /* Bit 31 Overflow Interrupt Identifier */ | COV15II /* Bit 15 Overflow Interrupt Identifier */ | CZEROII /* Count to Zero Interrupt Identifier */ | CZMII /* CZM Pin Interrupt Identifier */ | CZMEII /* CZM Error Interrupt Identifier */ | CZMZII; /* CZM Zeroes Counter Interrupt Identifier */ w[P5] = R5; Listing 13-2 illustrates how to set up the peripheral and core interrupts for the GP counter. This example assumes the counter interrupts are generated on IRQ27, which is assumed to be mapped to the IVG11 interrupt. Finally, the system and peripheral interrupts are unmasked, and then the GP counter is enabled. This example can be easily tailored to processors with different SIC register mappings. ADSP-BF52x Blackfin Processor Hardware Reference 13-29 Listing 13-2. Setting Up the Interrupts for the GP Counter /* Assign the CNT interrupt to IVG11 */ P5.H = hi(SIC_IAR3); P5.L = lo(SIC_IAR3); R6.H = hi(0xFFFF4FFF); R6.L = lo(0xFFFF4FFF); R7.H = hi(0x00000000); R7.L = lo(0x00000000); R5 = [P5]; R5 = R5 & R6; /* zero the counter interrupt field */ R5 = R5 | R7; /* set Counter interrupt to required priority */ [P5] = R5; /* Set up the interrupt vector for the counter */ R5.H = hi(_IVG11_handler); R5.L = lo(_IVG11_handler); P5.H = hi(EVT11); P5.L = lo(EVT11); [P5] = R5; /* Unmask IVG11 interrupt in the IMASK register */ P5.H = hi(IMASK); P5.L = lo(IMASK); R5 = [P5]; bitset(R5, bitpos(EVT_IVG11)); [P5] = R5; /* Unmask interrupt 27 generated by the counter */ P5.H = hi(SIC_IMASK0); P5.L = lo(SIC_IMASK0); R5 = [P5]; bitset(R5, bitpos(IRQ_CNT)); [P5] = R5; 13-30 ADSP-BF52x Blackfin Processor Hardware Reference /* Enable the counter */ P5.H = hi(CNT_CONFIG); P5.L = lo(CNT_CONFIG); R5 = w[P5](z); bitset(R5, bitpos(CNTE)); w[P5] = R5.L; Using the same assumptions from the previous example, Listing 13-3 illustrates a sample interrupt handler that is responsible for servicing the GP counter interrupts. On entry to the handler, the SIC_ISR0 register is interrogated to determine if the counter is waiting for an interrupt to be serviced. If so, the handler responsible for processing all counter interrupts is called. Listing 13-3. Sample Interrupt Handler for GP Counter Interrupts _IVG11_handler: /* Stack management */ [--SP] = RETS; [--SP] = ASTAT; [--SP] = (R7:0, P5:0); /* Was it a counter interrupt? */ P5.H = hi(SIC_ISR0); P5.L = lo(SIC_ISR0); R5 = [P5]; CC = bittst(R5, bitpos(IRQ_CNT)); IF !CC JUMP _IVG11_handler.completed; CALL _IVG11_handler.counter; _IVG11_handler.completed: SSYNC; ADSP-BF52x Blackfin Processor Hardware Reference 13-31 /* Restore from stack */ (R7:0, P5:0) = [SP++]; ASTAT = [SP++]; RETS = [SP++]; RTI; /* Exit the interrupt service routine */ _IVG11_handler.end: _IVG11_handler.counter: /* Stack management */ [--SP] = RETS; [--SP] = (R7:0, P5:0); /* Determine what counter interrupts we wish to service */ R5 = w[P5](z); P5.H = hi(CNT_IMASK); P5.L = lo(CNT_IMASK); R5 = w[P5](z); P5.H = hi(CNT_STATUS); P5.L = lo(CNT_STATUS); R6 = w[P5](z); R5 = R5 & R6; /* Interrupt handlers for all GP counter interrupts */ _IVG11_handler.counter.illegal_code: CC = bittst(R5, bitpos(ICII)); IF !CC JUMP _IVG11_handler.counter.up_count; /* Clear the serviced request */ R6 = ICII (z); w[P5] = R6; /* insert illegal code handler here */ 13-32 ADSP-BF52x Blackfin Processor Hardware Reference _IVG11_handler.counter.illegal_code.end: _IVG11_handler.counter.up_count: CC = bittst(R5, bitpos(UCII)); IF !CC JUMP _IVG11_handler.counter.down_count; /* Clear the serviced request */ R6 = UCII (z); w[P5] = R6; /* insert up count handler here */ _IVG11_handler.counter.up_count.end: _IVG11_handler.counter.down_count: CC = bittst(R5, bitpos(DCII)); IF !CC JUMP _IVG11_handler.counter.min_count; /* Clear the serviced request */ R6 = DCII (z); w[P5] = R6; /* insert down count handler here */ _IVG11_handler.counter.down_count.end: _IVG11_handler.counter.min_count: CC = bittst(R5, bitpos(MINCII)); IF !CC JUMP _IVG11_handler.counter.max_count; /* Clear the serviced request */ R6 = MINCII (z); w[P5] = R6; ADSP-BF52x Blackfin Processor Hardware Reference 13-33 /* insert min count handler here */ _IVG11_handler.counter.min_count.end: _IVG11_handler.counter.max_count: CC = bittst(R5, bitpos(MAXCII)); IF !CC JUMP _IVG11_handler.counter.b31_overflow; /* Clear the serviced request */ R6 = MAXCII (z); w[P5] = R6; /* insert max count handler here */ _IVG11_handler.counter.max_count.end: _IVG11_handler.counter.b31_overflow: CC = bittst(R5, bitpos(COV31II)); IF !CC JUMP _IVG11_handler.counter.b15_overflow; /* Clear the serviced request */ R6 = COV31II (z); w[P5] = R6; /* insert bit 31 overflow handler here */ _IVG11_handler.counter.b31_overflow.end: _IVG11_handler.counter.b15_overflow: CC = bittst(R5, bitpos(COV15II)); IF !CC JUMP _IVG11_handler.counter.count_to_zero; 13-34 ADSP-BF52x Blackfin Processor Hardware Reference /* Clear the serviced request */ R6 = COV15II (z); w[P5] = R6; /* insert bit 15 overflow handler here */ _IVG11_handler.counter.b15_overflow.end: _IVG11_handler.counter.count_to_zero: CC = bittst(R5, bitpos(CZEROII)); IF !CC JUMP _IVG11_handler.counter.czm; /* Clear the serviced request */ R6 = CZEROII (z); w[P5] = R6; /* insert count to zero handler here */ _IVG11_handler.counter.count_to_zero.end: _IVG11_handler.counter.czm: CC = bittst(R5, bitpos(CZMII)); IF !CC JUMP _IVG11_handler.counter.czm_error; /* Clear the serviced request */ R6 = CZMII (z); w[P5] = R6; /* insert czm handler here */ _IVG11_handler.counter.czm.end: _IVG11_handler.counter.czm_error: CC = bittst(R5, bitpos(CZMEII)); ADSP-BF52x Blackfin Processor Hardware Reference 13-35 IF !CC JUMP _IVG11_handler.counter.czm_zeroes_counter; /* Clear the serviced request */ R6 = CZMEII (z); w[P5] = R6; /* insert czm error handler here */ _IVG11_handler.counter.czm_error.end: _IVG11_handler.counter.czm_zeroes_counter: CC = bittst(R5, bitpos(CZMZII)); IF !CC JUMP _IVG11_handler.counter.all_serviced; /* Clear the serviced request */ R6 = CZMZII (z); w[P5] = R6; /* insert czm zeroes counter handler here */ _IVG11_handler.counter.czm_zeroes_counter.end: _IVG11_handler.counter.all_serviced: /* Restore from stack */ (R7:0, P5:0) = [SP++]; RETS = [SP++]; RTS; _IVG11_handler.counter.end: Listing 13-4 shows how to set up timer 7 (as an example) to capture the period of counter events. Refer to the "Internal Interfaces" section of Chapter 9, “General-Purpose Ports” for information regarding which GP timer(s) are associated with which GP counter module(s) for your device. 13-36 ADSP-BF52x Blackfin Processor Hardware Reference The timer is configured for WDTH_CAP mode, and the period between the last two successive counter events is read from within the up count interrupt handler that was provided in Listing 13-3 on page 13-31. Listing 13-4. Setting Up Timer 7 for Counter Event Period Capture /* configure the timer for WDTH_CAP mode */ P5.H = hi(TIMER7_CONFIG); P5.l = lo(TIMER7_CONFIG); R5 = PULSE_HI | PERIOD_CNT | TIN_SEL | WDTH_CAP (z); w[P5] = R5.l; /* Enable Timer 7 P5.H = hi(TIMER_ENABLE0); P5.L = lo(TIMER_ENABLE0); R5 = TIMEN7 (z); w[P5] = R5.L; ... _IVG11_handler.counter.up_count: CC = bittst(R5, bitpos(UCII)); IF !CC JUMP _IVG11_handler.counter.down_count; /* Clear the serviced request */ R6 = UCII (z); w[P5] = R6; /* insert up count handler here */ /* Read the period between the last two successive events */ P5.H = hi(TIMER7_PERIOD); P5.L = lo(TIMER7_PERIOD); R5 = [P5]; ADSP-BF52x Blackfin Processor Hardware Reference 13-37 P5.H = hi(_event_period); P5.L = lo(_event_period); [P5] = R5; _IVG11_handler.counter.up_count.end: Unique Behavior for the ADSP-BF52x Processor None 13-38 ADSP-BF52x Blackfin Processor Hardware Reference 1 4 REAL-TIME CLOCK This chapter describes the real-time clock (RTC). Following an overview and list of key features is a description of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Specific Information for the ADSP-BF52x For RTC interrupt vector assignments, refer to Table 5-3 on page 5-18 in Chapter 5, “System Interrupts”. For a list of MMR addresses for the RTC, refer to Appendix A, “System MMR Assignments”. RTC behavior for the ADSP-BF52x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Information for the ADSP-BF52x Processor” on page 14-27 Overview The RTC provides a set of digital watch features to the processor, including time of day, alarm, and stopwatch countdown. It is typically used to implement either a real-time watch or a life counter, which counts the elapsed time since the last system reset. The RTC watch features are clocked by a 32.768 kHz crystal external to the processor. The RTC uses dedicated power supply pins and is indepen- ADSP-BF52x Blackfin Processor Hardware Reference 14-1 dent of any reset, which enables it to maintain functionality even when the rest of the processor is powered down. The RTC input clock is divided down to a 1 Hz signal by a prescaler, which can be bypassed. When bypassed, the RTC is clocked at the 32.768 kHz crystal rate. In normal operation, the prescaler is enabled. The primary function of the RTC is to maintain an accurate day count and time of day. The RTC accomplishes this by means of four counters: • 60 second counter • 60 minute counter • 24 hour counter • 32768 day counter The RTC increments the 60 second counter once per second and increments the other three counters when appropriate. The 32768 day counter is incremented each day at midnight (0 hours, 0 minutes, 0 seconds). Interrupts can be issued periodically, either every second, every minute, every hour, or every day. Each of these interrupts can be independently controlled. The RTC provides two alarm features, programmed with the RTC_ALARM register. The first is a time of day alarm (hour, minute, and second). When the alarm interrupt is enabled, the RTC generates an interrupt each day at the time specified. The second alarm feature allows the application to specify a day as well as a time. When the day alarm interrupt is enabled, the RTC generates an interrupt on the day and time specified. The alarm interrupt and day alarm interrupt can be enabled or disabled independently. The RTC provides a stopwatch function that acts as a countdown timer. The application can program a second count into the RTC stopwatch count register (RTC_SWCNT). When the stopwatch interrupt is enabled and 14-2 ADSP-BF52x Blackfin Processor Hardware Reference the specified number of seconds have elapsed, the RTC generates an interrupt. Interface Overview The RTC external interface consists of two clock pins, which together with the external components form the reference clock circuit for the RTC. The RTC interfaces internally to the processor system through the peripheral access bus (PAB), and through the interrupt interface to the system interrupt controller (SIC). ADSP-BF52x Blackfin Processor Hardware Reference 14-3 The RTC has dedicated power supply pins that power the clock functions at all times, including when the core power supply is turned off. Figure 14-1 provides a block diagram of the RTC. RTC_PREN HOURS EVENT 24 HOURS EVENT DAYS COUNTER HOURS COUNTER 9 Y SECONDS EVENT SECONDS COUNTER 6 1 Hz TICK PRESCALE COUNTER RTXI 32.768 kHz 1 0 6 Y Y EQUAL? EQUAL? 9 MINUTES COUNTER 5 Y EQUAL? MINUTES EVENT 5 EQUAL? 6 6 WRITE RTC_SWCNT RTC_ALARM REGISTER DAY ALARM EVENT ALARM EVENT STOPWATCH ENABLE STOPWATCH COUNTER 16 EQUAL 0? SET RST Y STOPWATCH EVENT Figure 14-1. RTC Block Diagram Description of Operation The following sections describe the operation of the RTC. 14-4 ADSP-BF52x Blackfin Processor Hardware Reference R TC Clock Requirements The RTC timer is clocked by a 32.768 kHz crystal external to the processor. The RTC system memory mapped registers (MMRs) are clocked by this crystal. When the prescaler is disabled, the RTC MMRs are clocked at the 32.768 kHz crystal frequency. When the prescaler is enabled, the RTC MMRs are clocked at the 1 Hz rate. There is no way to disable the RTC counters using software. If a given system does not require the RTC functionality, then it may be disabled with hardware tie offs. Tie the RTXI and RTCGND pins to EGND, tie the RTCVDD pin to EVDD, and leave the RTXO pin unconnected. Additionally, writing RTC_PREN to “0” saves a small amount of power. Prescaler Enable The single active bit of the RTC prescaler enable register (RTC_PREN) is written using a synchronization path. Clearing of the bit is synchronized to the 32.768 kHz clock. This faster synchronization allows the module to be put into high speed mode (bypassing the prescaler) without waiting the full one second for the write to complete that would be necessary if the module were already running with the prescaler enabled. When this bit is cleared, the prescaler is disabled, and the RTC runs at the 32.768 kHz crystal frequency. When setting the RTC_PREN bit, the first positive edge of the 1 Hz clock occurs 1 to 2 cycles of the 32.768 kHz clock after the prescaler is enabled. The write complete status/interrupt works as usual when enabling or disabling the prescale counter. The new RTC clock rate is in effect before the write complete status is set. In order for the RTC to operate at the proper rate, software must set the prescaler enable bit after initial powerup. When this bit is set, the prescaler is enabled, and the RTC runs at a frequency of 1 Hz. ADSP-BF52x Blackfin Processor Hardware Reference 14-5 Write RTC_PREN and then wait for the write complete event before programming the other registers. It is safe to write RTC_PREN to “1” every time the processor boots. The first time sets the bit, and subsequent writes have no effect, as no state is changed. clearing bit in reg Do not disable the prescaler by there are the writes theRTC MMRs ister without making sure that no to RTC_PREN in progress. Do not switch between fast and slow mode during normal operation by setting and clearing this bit, as this disrupts the accurate tracking of real time by the counters. To avoid these potential errors, initialize the RTC during startup using RTC_PREN and do not dynamically alter the state of the prescaler during normal operation. Running without the prescaler enabled is provided primarily as a test mode. All functionality works, just 32,768 times as fast. Typical software should never program RTC_PREN to “0”. The only reason to do so is to synchronize the 1 Hz tick to a more precise external event, as the 1 Hz tick predictably occurs a few RTXI cycles after a 0-to-1 transition of RTC_PREN. Use the following sequence to achieve synchronization to within 100 ms. 1. Write RTC_PREN to “0”. 2. Wait for the write to complete. 3. Wait for the external event. 4. Write RTC_PREN to “1”. 5. Wait for the write to complete. 6. Reprogram the time into RTC_STAT. 14-6 ADSP-BF52x Blackfin Processor Hardware Reference R TC Programming Model The RTC programming model consists of a set of system MMRs. Software can configure the RTC and can determine the status of the RTC through reads and writes to these registers. The RTC interrupt control register (RTC_ICTL) and the RTC interrupt status register (RTC_ISTAT) provide RTC interrupt management capability. Note that software cannot disable the RTC counting function. However, all RTC interrupts can be disabled, or masked. At reset, all interrupts are disabled. The RTC state can be read via the system MMR status registers at any time. The primary RTC functionality, shown in Figure 14-1 on page 14-4, consists of registers and counters that are powered by an independent RTC supply (VDDRTC). This logic is never reset; it comes up in an indeterminate state when VDDRTC is first powered on. The RTC also contains logic powered by the same internal Vdd as the processor core and other peripherals. This logic contains some control functionality, holding registers for PAB write data, and prefetched PAB read data shadow registers for each of the five VDDRTC-powered registers. This logic is reset by the same system reset and clocked by the same SCLK as the other peripherals. Figure 14-2 shows the connections between the VDDRTC-powered RTC MMRs and their corresponding VDDINT-powered write holding registers and read shadow registers. In the figure, “REG” means each of the RTC_STAT, RTC_ALARM, RTC_SWCNT, RTC_ICTL, and RTC_PREN registers. The RTC_ISTAT register connects only to the PAB. The rising edge of the 1 Hz RTC clock is the “1 Hz tick”. Software can synchronize to the 1 Hz tick by waiting for the seconds event flag to set or by waiting for the seconds interrupt (if enabled). ADSP-BF52x Blackfin Processor Hardware Reference 14-7 1 Hz TICK REG POWERED BY VDDRTC CLOCKED BY 1 Hz TICK POWERED BY VDDINT CLOCKED BY SCLK N REG WRITE HOLDING N REG READ SHADOW 16/32 16/32 RST REG WRITE PENDING RTC_ISTAT 16 16 MMR WRITE TO REG PAB SET 5 WRITE PENDING STATUS FALLING EDGE DETECT WRITE COMPLETE EVENT Figure 14-2. RTC Register Architecture R egister Writes Writes to all RTC MMRs except RTC_ISTAT are saved in write holding registers and then are synchronized to the RTC 1 Hz clock. The write pending status bit in RTC_ISTAT indicates the progress of the write. The write pending status bit is set when a write is initiated and is cleared when all writes are complete. The falling edge of the write pending status bit causes the write complete flag in RTC_ISTAT to be set. This flag can be configured in RTC_ICTL to cause an interrupt. Software does not have to wait for writes to one RTC MMR to complete before writing to another RTC 14-8 ADSP-BF52x Blackfin Processor Hardware Reference MMR. The write pending status bit is set if any writes are in progress, and the write complete flag is set only when all writes are complete. writes peripherals are Anystop in progress whenby entering deepreset are aborted. Do not (for example, sleep mode) or SCLK remove internal Vdd power until all RTC writes have completed. not attempt same register without Do the previous another write to theSubsequent writes to thewaiting for write to complete. same register are ignored if the previous write is not complete. before complete Reading a registerithat has been writtenold value.the write check the flag in s set will return the Always RTC_ISTAT write pending status bit in RTC_ISTAT before attempting a read or write. Write Latency Writes to the RTC MMRs are synchronized to the 1 Hz RTC clock. When setting the time of day, do not factor in the delay when writing to the RTC MMRs. The most accurate method of setting the RTC is to monitor the seconds (1 Hz) event flag or to program an interrupt for this event and then write the current time to RTC_STAT in the interrupt service routine (ISR). The new value is inserted ahead of the incrementer. Hardware adds one second to the written value (with appropriate carries into minutes, hours and days) and loads the incremented value at the next 1 Hz tick, when it represents the then-current time. Writes posted at any time are properly synchronized to the 1 Hz clock. Writes complete at the rising edge of the 1 Hz clock. A write posted just before the 1 Hz tick may not be completed until the 1 Hz tick one second later. Any write posted in the first 990 ms after a 1 Hz tick completes on the next 1 Hz tick, but the simplest, most predictable and recommended technique is to only post writes to RTC_STAT, RTC_ALARM, RTC_SWCNT, RTC_ICTL, or RTC_PREN immediately after a seconds interrupt or event. All five registers may be written in the same second. ADSP-BF52x Blackfin Processor Hardware Reference 14-9 W1C bits in the RTC_ISTAT register take effect immediately. R egister Reads There is no latency when reading RTC MMRs, as the values come from the read shadow registers. These shadow registers are updated and ready for reading by the time any RTC interrupts or event flags for that second are asserted. Once the internal Vdd logic completes its initialization sequence after SCLK starts, there is no point in time when it is unsafe to read the RTC MMRs for synchronization reasons. They always return coherent values, although the values may be indeterminate. Deep Sleep When the dynamic power management mode is set to deep sleep, all clocks in the system (except RTXI and the RTC 1 Hz tick) are stopped. In this state, the VDDRTC-powered counters continue to increment. The internal Vdd shadow registers are not updated, but neither can they be read. During deep sleep mode, all bits in RTC_ISTAT are cleared. Events that occur during deep sleep are not recorded in RTC_ISTAT. The internal Vdd RTC control logic generates a virtual 1 Hz tick within one RTXI period (30.52 s) after SCLK restarts. This loads all shadow registers with up-to-date values and sets the seconds event flag. Other event flags may also be set. When the system wakes up from deep sleep, whether by an RTC event or a hardware reset, all of the RTC events that occurred during that second (and only that second) are reported in RTC_ISTAT. When the system wakes up from deep sleep mode, software does not need to W1C the bits in RTC_ISTAT. All W1C bits are already cleared by hardware. The seconds event flag is set when the RTC internal Vdd logic has completed its restart sequence. Software should wait until the seconds event flag is set and then may begin reading or writing any RTC register. 14-10 ADSP-BF52x Blackfin Processor Hardware Reference E vent Flags the registers power-up The indeterminate values incorrect value isatwritten intocan causethe event flags to set before the each of registers. By catching the 1 Hz clock edge, the write to RTC_STAT can occur a full second before the write to RTC_ALARM. This would cause an extra second of delay between the validity of RTC_STAT and RTC_ALARM, if the value of the RTC_ALARM out of reset is the same as the value written to RTC_STAT. Therefore, wait for the writes to complete on these registers before using the flags and interrupts associated with their values. The following is a list of flags along with the conditions under which they are valid: • Seconds (1 Hz) event flag Always set on the positive edge of the 1 Hz clock and after shadow registers have updated after waking from deep sleep. This is valid as long as the RTC 1 Hz clock is running. Use this flag or interrupt to validate the other flags. • Write complete and write pending status Always valid. • Minutes event flag Valid only after the second field in RTC_STAT is valid. Use the write complete and write pending status flags or interrupts to validate the RTC_STAT value before using this flag value or enabling the interrupt. • Hours event flag Valid only after the minute field in RTC_STAT is valid. Use the write complete and write pending status flags or interrupts to validate the RTC_STAT value before using this flag value or enabling the interrupt. ADSP-BF52x Blackfin Processor Hardware Reference 14-11 • 24 Hours event flag Valid only after the hour field in RTC_STAT is valid. Use the write complete and write pending status flags or interrupts to validate the RTC_STAT value before using this flag value or enabling the interrupt. • Stopwatch event flag Valid only after the RTC_SWCNT register is valid. Use the write complete and write pending status flags or interrupts to validate the RTC_SWCNT value before using this flag value or enabling the interrupt. • Alarm event and day alarm event flags Valid only after the RTC_STAT and RTC_ALARM registers are valid. Use the write complete and write pending status flags or interrupts to validate the RTC_STAT and RTC_ALARM values before using this flag value or enabling its interrupt. Writes posted together at the beginning of the same second take effect together at the next 1 Hz tick. The following sequence is safe and does not result in any spurious interrupts from a previous state. 1. Wait for 1 Hz tick. 2. Write 1s to clear the RTC_ISTAT flags for alarm, day alarm, stopwatch, and/or per interval. 3. Write new values for RTC_STAT, RTC_ALARM, and/or RTC_SWCNT. 4. Write new value for RTC_ICTL with alarm, day alarm, stopwatch, and/or per interval interrupts enabled. 5. Wait for 1 Hz tick. 6. New values have now taken effect simultaneously. 14-12 ADSP-BF52x Blackfin Processor Hardware Reference S etting Time of Day The RTC_STAT register is used to read or write the current time. Reads return a 32-bit value that always reflects the current state of the days, hours, minutes, and seconds counters. Reads and writes must be 32-bit transactions; attempted 16-bit transactions result in an MMR error. Reads always return a coherent 32-bit value. The hours, minutes, and seconds fields are usually set to match the real time of day. The day counter value is incremented every day at midnight to record how many days have elapsed since it was last modified. Its value does not correspond to a particular calendar day. The 15-bit day counter provides a range of 89 years, 260 or 261 days (depending on leap years) before it overflows. After the 1 Hz tick, program RTC_STAT with the current time. At the next 1 Hz tick, RTC_STAT takes on the new, incremented value. For example: 1. Wait for 1 Hz tick. 2. Read RTC_STAT, get 10:45:30. 3. Write RTC_STAT to current time, 13:10:59. 4. Read RTC_STAT, still get old time 10:45:30. 5. Wait for 1 Hz tick. 6. Read RTC_STAT, get new current time, 13:11:00. Using the Stopwatch The RTC_SWCNT register contains the countdown value for the stopwatch. The stopwatch counts down seconds from the programmed value and generates an interrupt (if enabled) when the count reaches “0”. The counter stops counting at this point and does not resume counting until a new value is written to RTC_SWCNT. Once running, the counter may be overwritten with a new value. This allows the stopwatch to be used as a watchdog timer with a precision of one second. ADSP-BF52x Blackfin Processor Hardware Reference 14-13 The stopwatch can be programmed to any value between 0 and (216 – 1) seconds, which is a range of 18 hours, 12 minutes, and 15 seconds. Typically, software should wait for a 1 Hz tick, then write RTC_SWCNT. One second later, RTC_SWCNT changes to the new value and begins decrementing. Because the register write occupies nearly one second, the time from writing a value of N until the stopwatch interrupt is nearly N + 1 seconds. To produce an exact delay, software can compensate by writing N – 1 to get a delay of nearly N seconds. This implies that you cannot achieve a delay of 1 second with the stopwatch. Writing a value of “1” immediately after a 1 Hz tick results in a stopwatch interrupt nearly two seconds later. To wait one second, software should just wait for the next 1 Hz tick. The RTC_SWCNT register is not reset. After initial powerup, it may be running. When the stopwatch is not used, writing it to “0” to force it to stop saves a small amount of power. Interrupts The RTC can provide interrupts at several programmable intervals: • Per second, minute, hour, and day—based on increments to the respective counters in RTC_STAT • On countdown from a programmable value—value in RTC_SWCNT transitions to “0” or is written with “0” by software (whether it was previously running or already stopped with a count of “0”) • Daily at a specific time—all fields of RTC_ALARM must match RTC_STAT except the day field • On a specific day and time—all fields of RTC_ALARM register must match RTC_STAT The RTC can be programmed to provide an interrupt at the completion of all pending writes to any of the 1 Hz registers (RTC_STAT, RTC_ALARM, RTC_SWCNT, RTC_ICTL, and RTC_PREN). The eight RTC interrupt events can 14-14 ADSP-BF52x Blackfin Processor Hardware Reference be individually masked or enabled by the RTC_ICTL register. The seconds interrupt is generated on each 1 Hz clock tick, if enabled. The minutes interrupt is generated at the 1 Hz clock tick that advances the seconds counter from 59 to 0. The hour interrupt is generated at the 1 Hz clock tick that advances the minute counter from 59 to 0. The 24 hour interrupt occurs once per 24 hour period at the 1 Hz clock tick that advances the time to midnight (00:00:00). Any of these interrupts can generate a wakeup request to the processor, if enabled. All implemented bits are read/write. This register is only partially cleared at reset, so some events may appear to be enabled initially. However, the RTC interrupt and the RTC wakeup to the PLL are handled specially and are masked (forced low) until after the first write to the RTC_ICTL register is complete. Therefore, all interrupts act as if they were disabled at system reset (as if all bits of RTC_ICTL were zero), even though some bits of RTC_ICTL may read as nonzero. If no RTC interrupts are needed immediately after reset, it is recommended to write RTC_ICTL to 0x0000 so that later read-modify-write accesses function as intended. Interrupt status can be determined by reading the RTC_ISTAT register. All bits in RTC_ISTAT are sticky. Once set by the corresponding event, each bit remains set until cleared by a software write to this register. Event flags are always set; they are not masked by the interrupt enable bits in RTC_ICTL. Values are cleared by writing a “1” to the respective bit location, except for the write pending status bit, which is read-only. Writes of “0” to any bit of the register have no effect. This register is cleared at reset and during deep sleep. The RTC interrupt is set whenever an event latched into the RTC_ISTAT register is enabled in the RTC_ICTL register. The pending RTC interrupt is cleared whenever all enabled and set bits in RTC_ISTAT are cleared, or when all bits in RTC_ICTL corresponding to pending events are cleared. As shown in Figure 14-3, the RTC generates an interrupt request (IRQ) to the processor core for event handling and wakeup from a sleep state. ADSP-BF52x Blackfin Processor Hardware Reference 14-15 The RTC generates a separate signal for wakeup from a deep sleep or from an internal Vdd power-off state. The deep sleep wakeup signal is asserted at the 1 Hz tick when any RTC interval event enabled in RTC_ICTL occurs. The assertion of the deep sleep wakeup signal causes the processor core clock (CCLK) and the system clock (SCLK) to restart. Any enabled event that asserts the RTC deep sleep wakeup signal also causes the RTC IRQ to assert once SCLK restarts. DAY, HOURS, SECONDS, STOPWATCH 24 HOURS, MINUTES, ALARM, EVENTS WAKE FROM POWER OFF RTC_ICTL 7 1 Hz TICK 7 7 POWERED BY RTC VDD POWERED BY INTERNAL VDD VOLTAGE REGULATOR POWERED BY EXTERNAL VDD WRITE COMPLETE EVENT 7 7 WAKE FROM DEEP SLEEP PLL ICTL READ SHADOW RTC_ISTAT 7 WRITE COMPLETE ENABLE 7 7 RTC IRQ SYSTEM INTERRUPT CONTROLLER PROCESSOR CORE Figure 14-3. RTC Interrupt Structure State Transitions Summary Table 14-1 shows how each RTC MMR is affected by the system states. The phase locked loop (PLL) states are defined in the Dynamic Power Management chapter. “No power” means none of the processor power supply pins are connected to a source of energy. “Off” means the processor 14-16 ADSP-BF52x Blackfin Processor Hardware Reference core, peripherals, and memory are not powered (internal Vdd is off), while the RTC is still powered and running. External Vdd may still be powered. Registers described as “as written” are holding the last value software wrote to the register. If the register has not been written since VDDRTC power was applied, then the state is indeterminate (for all bits of RTC_STAT, RTC_ALARM, and RTC_SWCNT, and for some bits of RTC_ISTAT, RTC_PREN, and RTC_ICTL). Table 14-1. Effect of States on RTC MMRs RTC Vdd IVdd System State RTC_ICTL RTC_ISTAT RTC_STAT RTC_SWCNT RTC_ALARM RTC_PREN Off Off No power X X X X On On Reset As written 0 Counting As written On On Full on As written Events Counting As written On On Sleep As written Events Counting As written On On Active As written Events Counting As written On On Deep sleep As written 0 Counting As written On Off Off As written X Counting As written Table 14-2 summarizes software’s responsibilities with respect to the RTC at various system state transition events. Table 14-2. RTC System State Transition Events At This Event: Execute This Sequence: Power on from no power Write RTC_PREN = 1. Wait for write complete. Write RTC_STAT to current time. Write RTC_ALARM, if needed. Write RTC_SWCNT. Write RTC_ISTAT to clear any pending RTC events. Write RTC_ICTL to enable any desired RTC interrupts or to disable all RTC interrupts. ADSP-BF52x Blackfin Processor Hardware Reference 14-17 Table 14-2. RTC System State Transition Events (Continued) At This Event: Execute This Sequence: Full on after reset Wait for seconds event, or write RTC_PREN = 1 and wait for or write complete. Full on after power on from off Write RTC_ISTAT to clear any pending RTC events. Write RTC_ICTL to enable any desired RTC interrupts or to disable all RTC interrupts. Read RTC MMRs as required. Wake from deep sleep Wait for seconds event flag to set. Write RTC_ISTAT to acknowledge RTC deep sleep wakeup. Read RTC MMRs as required. The PLL state is now active. Transition to full on as needed. Wake from sleep If wakeup came from RTC, seconds event flag will be set. In this case, write RTC_ISTAT to acknowledge RTC wakeup IRQ. Always, read RTC MMRs as required. Before going to sleep If wakeup by RTC is desired: Write RTC_ALARM and/or RTC_SWCNT as needed to schedule a wakeup event. Write RTC_ICTL to enable the desired RTC interrupt sources for wakeup. Wait for write complete. Enable RTC for wakeup in the system interrupt wakeup enable register (SIC_IWR). Before going to deep sleep Write RTC_ALARM and/or RTC_SWCNT as needed to schedule a wakeup event. Write RTC_ICTL to enable the desired RTC event sources for deep sleep wakeup. Wait for write complete. Before going to off Write RTC_ALARM and/or RTC_SWCNT as needed to schedule a wakeup event. Write RTC_ICTL to enable any desired RTC event sources for powerup wakeup. Wait for write complete. Set the wake bit in the voltage regulator control register (VR_CTL). 14-18 ADSP-BF52x Blackfin Processor Hardware Reference R egister Definitions The following sections contain the register definitions. Figure 14-4 through Figure 14-9 on page 14-22 illustrate the registers. Table 14-3 shows the functions of the RTC registers. Table 14-3. RTC Register Mapping Register Name Function Notes RTC_STAT RTC status register Holds time of day RTC_ICTL RTC interrupt con- Bits 14:7 are reserved trol register RTC_ISTAT RTC interrupt status register Bits 13:7 are reserved RTC_SWCNT RTC stopwatch count register Undefined at reset RTC_ALARM RTC alarm register Undefined at reset RTC_PREN Prescaler enable reg- Always set PREN = 1 for 1 Hz ticks ister ADSP-BF52x Blackfin Processor Hardware Reference 14-19 R TC Status (RTC_STAT) Register RTC Status Register (RTC_STAT) 31 30 29 28 27 26 25 24 X X X X X X X X 23 22 X X 21 20 X 19 18 17 16 X X X X X Reset = Undefined Hours[4] (0–23) Day Counter[14:0] (0–32767) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Seconds[5:0] (0–59) Minutes[5:0] (0–59) Hours[3:0] (0–23) Figure 14-4. RTC Status Register RTC Interrupt Control (RTC_ICTL) Register RTC Interrupt Control Register (RTC_ICTL) 0 – Interrupt disabled, 1 – Interrupt enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 X X X X X X X 0 0 0 0 0 Reset = 0x00XX Write Complete Interrupt Enable Stopwatch Interrupt Enable Day Alarm Interrupt Enable (Day, Hour, Minute, Second) Alarm Interrupt Enable (Hour, Minute, Second) 24 Hours Interrupt Enable Seconds (1Hz) Interrupt Enable Hours Interrupt Enable Minutes Interrupt Enable Figure 14-5. RTC Interrupt Control Register 14-20 ADSP-BF52x Blackfin Processor Hardware Reference R TC Interrupt Status (RTC_ISTAT) Register RTC Interrupt Status Register (RTC_ISTAT) All bits are write-1-to-clear, except bit 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 Stopwatch Event Flag 0 – No event 1 – Event occurred Write Complete 0 – Writes (if any) not yet complete 1 – All pending writes complete Alarm Event Flag 0 – No event 1 – Event occurred Write Pending Status (RO) 0 – No writes pending 1 – At least one write pending Seconds (1 Hz) Event Flag 0 – No event 1 – Event occurred Day Alarm Event Flag 0 – No event 1 – Event occurred Minutes Event Flag 0 – No event 1 – Event occurred 24 Hours Event Flag 0 – No event 1 – Event occurred Hours Event Flag 0 – No event 1 – Event occurred Figure 14-6. RTC Interrupt Status Register RTC Stopwatch Count (RTC_SWCNT) Register RTC Stopwatch Count Register (RTC_SWCNT) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Reset = Undefined Stopwatch Count[15:0] (0 to 65,535) Figure 14-7. RTC Stopwatch Count Register ADSP-BF52x Blackfin Processor Hardware Reference 14-21 R TC Alarm (RTC_ALARM) Register RTC Alarm Register (RTC_ALARM) 31 30 29 28 27 26 25 24 X X X X X X X 23 22 X X 21 20 X X 19 18 17 16 X X X X X Reset = Undefined Hours[4] (0 to 23) Day[14:0] (0 to 32767) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Seconds[5:0] (0 to 59) Minutes[5:0] (0 to 59) Hours[3:0] (0 to 23) Figure 14-8. RTC Alarm Register RTC Prescaler Enable (RTC_PREN) Register RTC Prescaler Enable Register (RTC_PREN) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0 0 Reset = Undefined PREN (Prescaler Enable) Figure 14-9. RTC Prescaler Enable Register Programming Examples The following RTC code examples show how to enable the RTC prescaler, how to set up a stopwatch event to take the RTC out of deep sleep 14-22 ADSP-BF52x Blackfin Processor Hardware Reference mode, and how to use the RTC alarm to exit hibernate state. Each of these code examples assumes that the appropriate header file is included in the source code (for instance, #include <defBF525.h> for ADSP-BF525 projects). Enable RTC Prescaler Listing 14-1 properly enables the prescaler and clears any pending interrupts. Listing 14-1. Enabling the RTC Prescaler RTC_Initialization: P0.H = HI(RTC_PREN); P0.L = LO(RTC_PREN); R0=PREN(Z); /* enable prescaler for 1 Hz ticks */ W[P0] = R0.L; P0.L = LO(RTC_ISTAT); R0 = 0x807F(Z); W[P0] = R0.L; /* clear any pending interrupts */ R0 = WRITE_COMPLETE(Z); Poll_WC: /* mask for WRITE-COMPLETE bit */ R1 = W[P0](Z); R1 = R1 & R0; /* wait for Write Complete */ CC = AZ; IF CC JUMP Poll_WC; RTS; RTC Stopwatch For Exiting Deep Sleep Mode Listing 14-2 sets up the RTC to utilize the stopwatch feature to come out of deep sleep mode. This code assumes that the _RTC_Interrupt label is properly registered as the ISR destination for the real-time clock event, the ADSP-BF52x Blackfin Processor Hardware Reference 14-23 RTC interrupt is enabled in both IMASK and SIC_IMASK, and that the RTC prescaler has already been enabled properly. Listing 14-2. RTC Stopwatch Interrupt to Exit Deep Sleep /* RTC Wake-Up Interrupt To Be Used With Deep Sleep Code */ _RTC_Interrupt: P0.H = HI(PLL_CTL); P0.L = LO(PLL_CTL); R0 = W[P0](Z); BITCLR (R0, BITPOS(BYPASS)); W[P0] = R0; IDLE; /* If BYPASS Set, Must Clear It */ /* Must go to IDLE for PLL changes to be effected */ R0 = 0x807F(Z); P0.H = HI(RTC_ISTAT); P0.L = LO(RTC_ISTAT); W[P0] = R7; /* clear pending RTC IRQs */ R0 = WRITE_COMPLETE(Z); Poll_WC_IRQ: /* mask for WRITE-COMPLETE bit */ R1 = W[P0](Z); R1 = R1 & R0; /* wait for Write Complete */ CC = AZ; IF CC JUMP Poll_WC_IRQ; RTI; Deep_Sleep_Code: P0.H = HI(RTC_SWCNT); P0.L = LO(RTC_SWCNT); R1 = 0x0010(Z); W[P0] = R1.L; /* set stop-watch to 16 seconds */ /* will produce ~15 second delay */ P0.L = LO(RTC_ICTL); 14-24 ADSP-BF52x Blackfin Processor Hardware Reference R1 = STOPWATCH(Z); W[P0] = R1.L; /* enable Stop-Watch interrupt */ P0.L = LO(RTC_ISTAT); R1 = 0x807F(Z); W[P0] = R1.L; /* clear any pending RTC interrupts */ R0 = WRITE_COMPLETE(Z); Poll_WC1: /* mask for WRITE-COMPLETE bit */ R1 = W[P0](Z); R1 = R1 & R0; /* wait for Write Complete */ CC = AZ; IF CC JUMP Poll_WC1; /* RTC now running with correct stop-watch count and interrupts */ P0.H = HI(PLL_CTL); P0.L = LO(PLL_CTL); R0 = W[P0](Z); BITSET (R0, BITPOS(PDWN)); /* set PDWN To Go To Deep Sleep */ W[P0] = R0.L; /* Issue Command for Deep Sleep */ CLI R0; /* Perform PLL Programming Sequence */ IDLE; STI R0; /* In Deep Sleep When Idle Exits */ RTS; RTC Alarm to Come Out of Hibernate State Listing 14-3 sets up the RTC to utilize the alarm feature to come out of hibernate state. This code assumes that the prescaler has already been properly enabled. ADSP-BF52x Blackfin Processor Hardware Reference 14-25 Listing 14-3. Setting RTC Alarm to Exit Hibernate State Hibernate_Code: P0.H = HI(RTC_ALARM); P0.L = LO(RTC_ALARM); R0 = 0x0010(Z); /* set alarm to 16 seconds from now */ W[P0] = R0.L; P0.L = LO(RTC_STAT); R0 = 0; /* Clear RTC Status to Start Counting at 0 */ W[P0] = R0.L; P0.L = LO(RTC_ICTL); R0 = ALARM(Z); W[P0] = R0.L; /* enable Alarm interrupt */ P0.L = LO(RTC_ISTAT); R0 = 0x807F(Z); W[P0] = R0.L; /* clear any pending RTC interrupts */ R0 = WRITE_COMPLETE(Z); Poll_WC1: R1 = W[P0](Z); R1 = R1 & R0; /* wait for Write Complete */ CC = AZ; IF CC JUMP Poll_WC1; /* RTC now running with correct RTC status */ GoToHibernate: P0.H = HI(VR_CTL); P0.L = LO(VR_CTL); R0 = W[P0](Z); BITCLR(R0, 0); /* Clear FREQ (bits 0 and 1) to */ BITCLR(R0, 1); /* go to Hibernate State BITSET(R0, BITPOS(WAKE)); 14-26 /* Enable RTC Wakeup */ */ ADSP-BF52x Blackfin Processor Hardware Reference W[P0] = R0.L; CLI R0; /* Use PLL programming sequence to */ IDLE; /* make VR_CTL changes take effect */ RTS; /* Should Never Execute This */ Unique Information for the ADSP-BF52x Processor None. ADSP-BF52x Blackfin Processor Hardware Reference 14-27 14-28 ADSP-BF52x Blackfin Processor Hardware Reference 1 5 PARALLEL PERIPHERAL INTERFACE This chapter describes the parallel peripheral interface (PPI). Following an overview and a list of key features are a description of operation and functional modes of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Specific Information for the ADSP-BF52x For details regarding the number of PPIs for the ADSP-BF52x product, please refer to the ADSP-BF522/523/524/525/526/527 Embedded Processor Data Sheet. For PPI DMA channel assignments, refer to Table 6-7 on page 6-106 in Chapter 6, “Direct Memory Access”. For PPI interrupt vector assignments, refer to Table 5-3 on page 5-18 in Chapter 5, “System Interrupts”. To determine how each of the PPIs is multiplexed with other functional pins, refer to Table 9-2 on page 9-5 through Table 9-5 on page 9-9 in Chapter 9, “General-Purpose Ports”. For a list of MMR addresses for each PPI, refer to Appendix A, “System MMR Assignments”. PPI behavior for the ADSP-BF52x that differs from the general information in this chapter can be found in the section “Unique Behavior for the ADSP-BF52x Processor” on page 15-39 ADSP-BF52x Blackfin Processor Hardware Reference 15-1 O verview The PPI is a half-duplex, bidirectional port accommodating up to 16 bits of data. It has a dedicated clock pin and three multiplexed frame sync pins. The highest system throughput is achieved with 8-bit data, since two 8-bit data samples can be packed as a single 16-bit word. In such a case, the earlier sample is placed in the 8 least significant bits (LSBs). Features The PPI includes these features: • Half duplex, bidirectional parallel port • Supports up to 16 bits of data • Programmable clock and frame sync polarities • ITU-R 656 support • Interrupt generation on overflow and underrun Typical peripheral devices that can be interfaced to the PPI port: • A/D converters • D/A converters • LCD panels • CMOS sensors • Video encoders • Video decoders 15-2 ADSP-BF52x Blackfin Processor Hardware Reference I nterface Overview Figure 15-1 shows a block diagram of the PPI. PPI_CONTROL PPI_CLK PPI_COUNT PPI_STATUS PAB DATA BUS PPI_DELAY DMA CONTROLLER PPI_FRAME DAB 16 BITS * 16-DEEP FIFO FS1 PACK/ UNPACK GATE SYNC FS2 FS3 Figure 15-1. PPI Block Diagram The PPI_CLK pin accepts an external clock input. It cannot source a clock internally. not there may be When the beforeis data free-running, or transmitted.additional latency cycles gets received In RX and PPI_CLK TX modes, there may be at least 2 cycles latency before valid data is received or transmitted. The PPI_CLK not only supplies the PPI module itself, but it also can clock one or more GP Timers to work synchronously with the PPI. Depending on PPI operation mode, the PPI_CLK can either equal or invert the TMRCLK input. For more information, see Chapter 10, “General-Purpose Timers”. ADSP-BF52x Blackfin Processor Hardware Reference 15-3 D escription of Operation Table 15-1 shows all the possible modes of operation for the PPI. Table 15-1. PPI Possible Operating Modes PPI Mode # of Syncs PORT_DIR PORT_CFG XFR_TYPE POLC POLS FLD_ SEL RX mode, 0 frame 0 syncs, external trigger 0 11 11 0 or 1 0 or 1 0 RX mode, 0 frame 0 syncs, internal trigger 0 11 11 0 or 1 0 or 1 1 RX mode, 1 external frame sync 1 0 00 11 0 or 1 0 or 1 0 RX mode, 2 or 3 3 external frame syncs 0 10 11 0 or 1 0 or 1 0 3 RX mode, 2 or 3 internal frame syncs 0 01 11 0 or 1 0 or 1 0 RX mode, ITU-R 656, active field only embedded 0 00 00 0 or 1 0 0 or 1 RX mode, ITU-R embed656, vertical blank- ded ing only 0 00 10 0 or 1 0 0 RX mode, ITU-R 656, entire field embedded 0 00 01 0 or 1 0 0 TX mode, 0 frame syncs 0 1 00 00 0 or 1 0 or 1 0 TX mode, 1 internal or external frame sync 1 1 00 11 0 or 1 0 or 1 0 TX mode, 2 external frame syncs 2 1 01 11 0 or 1 0 or 1 0 15-4 ADSP-BF52x Blackfin Processor Hardware Reference Table 15-1. PPI Possible Operating Modes (Continued) PPI Mode # of Syncs PORT_DIR PORT_CFG XFR_TYPE POLC POLS FLD_ SEL T X mode, 2 or 3 3 internal frame syncs, FS3 sync’d to FS1 assertion 1 01 11 0 or 1 0 or 1 0 TX mode, 2 or 3 3 internal frame syncs, FS3 sync’d to FS2 assertion 1 11 11 0 or 1 0 or 1 0 F unctional Description The following sections describe the function of the PPI. ITU-R 656 Modes The PPI supports three input modes for ITU-R 656-framed data. These modes are described in this section. Although the PPI does not explicitly support an ITU-R 656 output mode, recommendations for using the PPI for this situation are provided as well. ITU-R 656 Background According to the ITU-R 656 recommendation (formerly known as CCIR-656), a digital video stream has the characteristics shown in Figure 15-2, and Figure 15-3 for 525/60 (NTSC) and 625/50 (PAL) systems. The processor supports only the bit-parallel mode of ITU-R 656. Both 8- and 10-bit video element widths are supported. In this mode, the horizontal (H), vertical (V), and field (F) signals are sent as an embedded part of the video datastream in a series of bytes that form a control word. The start of active video (SAV) and end of active video (EAV) signals indicate the beginning and end of data elements to read in on each line. SAV occurs on a 1-to-0 transition of H, and EAV begins on a ADSP-BF52x Blackfin Processor Hardware Reference 15-5 0-to-1 transition of H. An entire field of video is comprised of active video + horizontal blanking (the space between an EAV and SAV code) and vertical blanking (the space where V = 1). A field of video commences on a transition of the F bit. The “odd field” is denoted by a value of F = 0, whereas F = 1 denotes an even field. Progressive video makes no distinction between field 1 and field 2, whereas interlaced video requires each field to be handled uniquely, because alternate rows of each field combine to create the actual video image. END OF ACTIVE VIDEO EAV CODE (H = 1) F F 0 0 0 0 4 X Y START OF ACTIVE VIDEO SAV CODE (H = 0) HORIZONTAL BLANKING 8 0 1 0 8 0 1 0 8 0 268 (280 FOR PAL) START OF NEXT LINE 1 0 F F 0 0 0 0 XCYC YB R 4 YC B YC R Y CY R F F DIGITAL VIDEO STREAM 1440 1716 (1728 FOR PAL) Figure 15-2. ITU-R 656 8-Bit Parallel Data Stream for NTSC (PAL) Systems 15-6 ADSP-BF52x Blackfin Processor Hardware Reference LINE # 1 LINE 4 VERTICAL BLANKING HORIZONTAL BLANKING 1 1 1 0 4-19, 264-265 0 1 1 0 0 0 1 0 1 0 1 0 LINE NUMBER F V H (EAV) H (SAV) 0 1 1 0 23-310 0 0 1 0 313-335, 624-625 1 1 1 0 336-623 283 1 0 1 0 LINE 3 SAV 1 LINE 1 VERTICAL BLANKING FI ELD 1 HORIZONTAL BLANKING 23 FIELD 1 ACTIVE VIDEO VERTICAL BLANKING 311 LINE 313 336 FI ELD 2 FIELD 2 ACTIVE VIDEO VERTICAL BLANKING EAV H (SAV) 1-22, 311-312 FI ELD 2 FIELD 2 ACTIVE VIDEO EAV H (EAV) LINE 266 VERTICAL BLANKING 525 V 283-525 264 F 20-263 FIELD 1 ACTIVE VIDEO LINE NUMBER 1-3, 266-282 FI ELD 1 20 624 625 LINE 625 SAV Figure 15-3. Typical Video Frame Partitioning for NTSC/PAL Systems for ITU-R BT.656-4 The SAV and EAV codes are shown in more detail in Table 15-2. Note there is a defined preamble of three bytes (0xFF, 0x00, 0x00), followed by the XY status word, which, aside from the F (field), V (vertical blanking) and H (horizontal blanking) bits, contains four protection bits for single-bit error detection and correction. Note F and V are only allowed to change as part of EAV sequences (that is, transition from H = 0 to H = 1). The bit definitions are as follows: • F = 0 for field 1 • F = 1 for field 2 ADSP-BF52x Blackfin Processor Hardware Reference 15-7 • V = 1 during vertical blanking • V = 0 when not in vertical blanking • H = 0 at SAV • H = 1 at EAV • P3 = V XOR H • P2 = F XOR H • P1 = F XOR V • P0 = F XOR V XOR H In many applications, video streams other than the standard NTSC/PAL formats (for example, CIF, QCIF) can be employed. Because of this, the processor interface is flexible enough to accommodate different row and field lengths. In general, as long as the incoming video has the proper EAV/SAV codes, the PPI can read it in. In other words, a CIF image could be formatted to be “656-compliant,” where EAV and SAV values define the range of the image for each line, and the V and F codes can be used to delimit fields and frames. Table 15-2. Control Byte Sequences for 8-bit and 10-bit ITU-R 656 Video 8-bit Data 10-bit Data D9 (MSB) 15-8 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Control Byte D7 0 Preamble D8 0 0 0 0 0 0 0 0 0 1 F V H P3 P2 P1 P0 0 0 ADSP-BF52x Blackfin Processor Hardware Reference I TU-R 656 Input Modes Figure 15-4 shows a general illustration of data movement in the ITU-R 656 input modes. In the figure, the clock CLK is either provided by the video source or supplied externally by the system. ITU-R 656 INPUT MODE '656 COMPATIBLE VIDEOSOURCE PPI 8- OR 10-BIT DATA WITH EMBEDDED CONTROL PPIx PPI_CLK CLK Figure 15-4. ITU-R 656 Input Modes There are three submodes supported for ITU-R 656 inputs: entire field, active video only, and vertical blanking interval only. Figure 15-5 shows these three submodes. BLANKING BLANKING BLANKING FIELD 1 ACTIVE VIDEO FIELD 1 ACTIVE VIDEO FIELD 1 ACTIVE VIDEO BLANKING BLANKING BLANKING FIELD 2 ACTIVE VIDEO FIELD 2 ACTIVE VIDEO FIELD 2 ACTIVE VIDEO BLANKING BLANKING BLANKING ENTIRE FIELD SENT ACTIVE VIDEO ONLY SENT BLANKING ONLY SENT Figure 15-5. ITU-R 656 Input Submodes Entire Field In this mode, the entire incoming bitstream is read in through the PPI. This includes active video as well as control byte sequences and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to field 1 occurs, ADSP-BF52x Blackfin Processor Hardware Reference 15-9 but does not include the first EAV code that contains the F = 0 assignment. transferred in after Note the first line preamble. However,enabling the PPI will be missing its first 4-byte subsequent lines and frames should have all control codes intact. One side benefit of this mode is that it enables a “loopback” feature through which a frame or two of data can be read in through the PPI and subsequently output to a compatible video display device. Of course, this requires multiplexing on the PPI pins, but it enables a convenient way to verify that 656 data can be read into and written out from the PPI. Active Video Only This mode is used when only the active video portion of a field is of interest, and not any of the blanking intervals. The PPI ignores (does not read in) all data between EAV and SAV, as well as all data present when V = 1. In this mode, the control byte sequences are not stored to memory; they are filtered out by the PPI. After synchronizing to the start of field 1, the PPI ignores incoming samples until it sees an SAV. the number (active In this mode, the user specifiesin the of totalMR. plus vertical blanking) lines per frame M PPI_FRAME Vertical Blanking Interval (VBI) only In this mode, data transfer is only active while V = 1 is in the control byte sequence. This indicates that the video source is in the midst of the vertical blanking interval (VBI), which is sometimes used for ancillary data transmission. The ITU-R 656 recommendation specifies the format for these ancillary data packets, but the PPI is not equipped to decode the packets themselves. This task must be handled in software. Horizontal blanking data is logged where it coincides with the rows of the VBI. Control byte sequence information is always logged. The user specifies the number of total lines (active plus vertical blanking) per frame in the PPI_FRAME MMR. 15-10 ADSP-BF52x Blackfin Processor Hardware Reference Note the VBI is split into two regions within each field. From the PPI’s standpoint, it considers these two separate regions as one contiguous space. However, keep in mind that frame synchronization begins at the start of field 1, which doesn’t necessarily correspond to the start of vertical blanking. For instance, in 525/60 systems, the start of field 1 (F = 0) corresponds to line 4 of the VBI. I TU-R 656 Output Mode The PPI does not explicitly provide functionality for framing an ITU-R 656 output stream with proper preambles and blanking intervals. However, with the TX mode with 0 frame syncs, this process can be supported manually. Essentially, this mode provides a streaming operation from memory out through the PPI. Data and control codes can be set up in memory prior to sending out the video stream. With the 2D DMA engine, this could be performed in a number of ways. For instance, one line of blanking (H + V) could be stored in a buffer and sent out N times by the DMA controller when appropriate, before proceeding to DMA active video. Alternatively, one entire field (with control codes and blanking) can be set up statically in a buffer while the DMA engine transfers only the active video region into the buffer, on a frame-by-frame basis. Frame Synchronization in ITU-R 656 Modes Synchronization in ITU-R 656 modes always occurs at the falling edge of F, the field indicator. This corresponds to the start of field 1. Consequently, up to two fields might be ignored (for example, if field 1 just started before the PPI-to-camera channel was established) before data is received into the PPI. Because all H and V signaling is embedded in the datastream in ITU-R 656 modes, the PPI_COUNT register is not necessary. However, the PPI_FRAME register is used in order to check for synchronization errors. The user programs this MMR for the number of lines expected in each frame of video, and the PPI keeps track of the number of EAV-to-SAV transitions that ADSP-BF52x Blackfin Processor Hardware Reference 15-11 occur from the start of a frame until it decodes the end-of-frame condition (transition from F = 1 to F = 0). At this time, the actual number of lines processed is compared against the value in PPI_FRAME. If there is a mismatch, the FT_ERR bit in the PPI_STATUS register is asserted. For instance, if an SAV transition is missed, the current field will only have NUM_ROWS – 1 rows, but resynchronization will reoccur at the start of the next frame. Upon completing reception of an entire field, the field status bit is toggled in the PPI_STATUS register. This way, an interrupt service routine (ISR) can discern which field was just read in. General-Purpose PPI Modes The general-purpose PPI modes are intended to suit a wide variety of data capture and transmission applications. Table 15-3 summarizes these modes. If a particular mode shows a given PPI_FSx frame sync not being used, this implies that the pin is available for its alternate, multiplexed functions. Table 15-3. General-Purpose PPI Modes GP PPI Mode PPI_FS1 Direction PPI_FS2 Direction PPI_FS3 Direction Data Direction RX mode, 0 frame syncs, external trigger Input Not used Not used Input RX mode, 0 frame syncs, internal trigger Not used Not used Not used Input RX mode, 1 external frame sync Input Not used Not used Input RX mode, 2 or 3 external frame syncs Input Input Input (if used) Input RX mode, 2 or 3 internal frame syncs Output Output Output (if used) Input TX mode, 0 frame syncs Not used Not used Not used Output TX mode, 1 external frame sync Input Not used Not used Output 15-12 ADSP-BF52x Blackfin Processor Hardware Reference Table 15-3. General-Purpose PPI Modes (Continued) GP PPI Mode PPI_FS1 Direction PPI_FS2 Direction PPI_FS3 Direction Data Direction T X mode, 2 external frame syncs Input Input Not used Output TX mode, 1 internal frame sync Output Not used Not used Output Output Output (if used) Output TX mode, 2 or 3 internal frame syncs Output Figure 15-6 illustrates the general flow of the general purpose PPI modes. The top of the diagram shows an example of RX mode with one external frame sync. After the PPI receives the hardware frame sync pulse (PPI_FS1), it delays for the duration of the PPI_CLK cycles programmed into PPI_DELAY. The DMA controller then transfers in the number of samples specified by PPI_COUNT. Every sample that arrives after this, but before the next PPI_FS1 frame sync arrives, is ignored and not transferred onto the DMA bus. frame sync arrives before the If the next samples have been read in, the sample specified reinitialcounter PPI_FS1 PPI_COUNT izes to 0 and starts to count up to PPI_COUNT again. This situation can cause the DMA channel configuration to lose synchronization with the PPI transfer process. The bottom of Figure 15-6 shows an example of TX mode, one internal frame sync. After PPI_FS1 is asserted, there is a latency of one PPI_CLK cycle, and then there is a delay for the number of PPI_CLK cycles programmed into PPI_DELAY. Next, the DMA controller transfers out the ADSP-BF52x Blackfin Processor Hardware Reference 15-13 number of samples specified by PPI_COUNT. No further DMA takes place until the next PPI_FS1 sync and programmed delay occur. frame sync arrives before If the next samples have been transferred out,the specified priority the sync has PPI_FS1 PPI_COUNT and starts a new line transfer sequence. This situation can cause the DMA channel configuration to lose synchronization with the PPI transfer process. FRAME SYNC (PPI_FS1) PROG DELAY (PPI_DELAY) PPI_COUNT SAMPLES IGNORED INPUT FRAME SYNC (PPI_FS1) 1 CYCLE DELAY PROG DELAY (PPI_DELAY) PPI_COUNT OUTPUT Figure 15-6. General Flow for GP Modes (Assumes Positive Assertion of PPI_FS1) Data Input (RX) Modes The PPI supports several modes for data input. These modes differ chiefly by the way the data is framed. Refer to Table 15-1 on page 15-4 for information on how to configure the PPI for each mode. 15-14 ADSP-BF52x Blackfin Processor Hardware Reference No Frame Syncs These modes cover the set of applications where periodic frame syncs are not generated to frame the incoming data. There are two options for starting the data transfer, both configured by the PPI_CONTROL register. • External trigger: An external source sends a single frame sync (tied to PPI_FS1) at the start of the transaction, when FLD_SEL = 0 and PORT_CFG = b#11. • Internal trigger: Software initiates the process by setting PORT_EN = 1 with FLD_SEL = 1 and PORT_CFG = b#11. All subsequent data manipulation is handled via DMA. For example, an arrangement could be set up between alternating 1K byte memory buffers. When one fills up, DMA continues with the second buffer, at the same time that another DMA operation is clearing the first memory buffer for reuse. clock domain synchronization in with Due tothere may be a delay of at least twoRX modescycles no frame syncs, between PPI_CLK when the mode is enabled and when valid data is received. Therefore, detection of the start of valid data should be managed by software. ADSP-BF52x Blackfin Processor Hardware Reference 15-15 1, 2, or 3 External Frame Syncs The frame syncs are level-sensitive signals. The 1-sync mode is intended for analog-to-digital converter (ADC) applications. The top part of Figure 15-7 shows a typical illustration of the system setup for this mode. A/D CONVERTER PPI PPI_FS1 FRAMESYNC DATA 8–16 BITS DATA PPIx PPI_CLK CLK VIDEO SOURCE PPI HSYNC PPI_FS1 VSYNC PPI_FS2 FIELD PPI_FS3 DATA CLK 8–16 BITS DATA PPIx PPI_CLK Figure 15-7. RX Mode, External Frame Syncs The 3-sync mode shown at the bottom of Figure 15-7 supports video applications that use hardware signaling (HSYNC, VSYNC, FIELD) in accordance with the ITU-R 601 recommendation. The mapping for the frame syncs in this mode is PPI_FS1 = HSYNC, PPI_FS2 = VSYNC, PPI_FS3 = FIELD. Please refer to “Frame Synchronization in GP Modes” on page 15-20 for more information about frame syncs in this mode. A 2-sync mode is supported by not enabling the PPI_FS3 pin. See the Product Specific Implementation section for information on how this is achieved on this processor. 2 or 3 Internal Frame Syncs This mode can be useful for interfacing to video sources that can be slaved to a master processor. In other words, the processor controls when to read from the video source by asserting PPI_FS1 and PPI_FS2, and then reading 15-16 ADSP-BF52x Blackfin Processor Hardware Reference data into the PPI. The PPI_FS3 frame sync provides an indication of which field is currently being transferred, but since it is an output, it can simply be left floating if not used. Figure 15-8 shows a sample application for this mode. IMAGE SOURCE PPI PPI_FS1 HSYNC PPI_FS2 PPIx PPI_CLK VSYNC 8–16 BITS DATA DATA CLK Figure 15-8. RX Mode, Internal Frame Syncs Data Output (TX) Modes The PPI supports several modes for data output. These modes differ chiefly by the way the data is framed. Refer to Table 15-1 on page 15-4 for information on how to configure the PPI for each mode. No Frame Syncs In this mode, data blocks specified by the DMA controller are sent out through the PPI with no framing. That is, once the DMA channel is configured and enabled, and the PPI is configured and enabled, data transfers ADSP-BF52x Blackfin Processor Hardware Reference 15-17 will take place immediately, synchronized to PPI_CLK. See Figure 15-9 for an illustration of this mode. is delay of > In thisormode, thereyclesa (for 8-bitup to 16 cycles (for the8-bit data) 32 c data) between enabling PPI SCLK SCLK and transmission of valid data. Furthermore, DMA must be configured to transmit at least 16 samples (for > 8-bit data) or 32 samples (for 8-bit data). PPIx 8- TO 16-BIT DATA PPI_CLK RECEIVER CLK Figure 15-9. TX Mode, 0 Frame Syncs 1 or 2 External Frame Syncs In these modes, an external receiver can frame data sent from the PPI. Both 1-sync and 2-sync modes are supported. The top diagram in 15-18 ADSP-BF52x Blackfin Processor Hardware Reference Figure 15-10 shows the 1-sync case, while the bottom diagram illustrates the 2-sync mode. of 1.5 c plus the value There is a mandatory delay, between assertionycles,the external frame programmed in of PPI_CLK PPI_DELAY sync(s) and the transfer of valid data out through the PPI. DATA RECEIVER PPI PPI_FS1 FRAMESYNC PPIx DATA 8–16 BITS DATA PPI_CLK CLK DATA RECEIVER PPI FRAMESYNC1 PPI_FS1 FRAMESYNC2 PPI_FS2 DATA CLK 8–16 BITS DATA PPIx PPI_CLK Figure 15-10. TX Mode, 1 or 2 External Frame Syncs 1, 2, or 3 Internal Frame Syncs The 1-sync mode is intended for interfacing to digital-to-analog converters (DACs) with a single frame sync. The top part of Figure 15-11 shows an example of this type of connection. The 3-sync mode is useful for connecting to video and graphics displays, as shown in the bottom part of Figure 15-11. A 2-sync mode is implicitly supported by leaving PPI_FS3 unconnected in this case. ADSP-BF52x Blackfin Processor Hardware Reference 15-19 D/A CONVERTER PPI FRAMESYNC PPI_FS1 1 FRAME SYNC PPIx 8–16 BITS DATA DATA CLK PPI_CLK PPI VIDEO DISPLAY PPI_FS1 PPI_FS2 3 FRAME SYNCS HSYNC VSYNC PPI_FS3 FIELD PPIx 8–16 BITS DATA CLK PPI_CLK Figure 15-11. PPI GP Output F rame Synchronization in GP Modes Frame synchronization in general purpose modes operates differently in modes with internal frame syncs than in modes with external frame syncs. Modes With Internal Frame Syncs In modes with internal frame syncs, PPI_FS1 and PPI_FS2 link directly to the pulsewidth modulation (PWM) circuits of general purpose timers. See the Chapter 10, “General-Purpose Timers” for information on how this is achieved on this processor. This allows for arbitrary pulse widths and periods to be programmed for these signals using the existing TIMERx registers. This capability accommodates a wide range of timing needs. Note these PWM circuits are clocked by PPI_CLK, not by SCLK (as during conventional timer PWM operation). If PPI_FS2 is not used in the configured PPI mode, its corresponding timer operates as it normally would, unrestricted in functionality. The state of PPI_FS3 depends completely on the 15-20 ADSP-BF52x Blackfin Processor Hardware Reference state of PPI_FS1 and/or PPI_FS2, so PPI_FS3 has no inherent programmability. To programmode: frame sync PPI_FS1 and/or PPI_FS2 for operation in an internal 1. Configure and enable DMA for the PPI. See “DMA Operation” on page 15-23. 2. Configure the width and period for each frame sync signal via the appropriate TIMER_WIDTH and TIMER_PERIOD registers. 3. Set up the appropriate TIMER_CONFIG register(s) for PWM_OUT mode. This includes setting CLK_SEL to 1 and TIN_SEL to 1 for each timer involved. 4. Write to PPI_CONTROL to configure and enable the PPI. 5. Write to TIMER_ENABLE to enable the appropriate timer(s). to guarantee proper frame sync polarity It is important peripherals. To do this, make sure that ifbetween the PPI and timer = b#10 or b#11, the PULSE_HI bit is cleared in the appropriate TIMER_CONFIG register(s). Likewise, if PPI_CONTROL[15:14] = b#00 or b#01, the PULSE_HI bit should be set in the appropriate TIMER_CONFIG register(s). PPI_CONTROL[15:14] To switch to another PPI mode not involving internal frame syncs: 1. Disable the PPI (using PPI_CONTROL). 2. Disable the appropriate timer(s) (using TIMER_DISABLE). Modes With External Frame Syncs In RX modes with external frame syncs, the PPI_FS1 and PPI_FS2 pins become edge-sensitive inputs. In such modes the timers associated with the PPI_FS1 and PPI_FS2 pins can still be used for a purpose not involving the actual pin. However, timer access to a TMRx pin is disabled when the ADSP-BF52x Blackfin Processor Hardware Reference 15-21 PPI is using that pin for a PPI_FSx frame sync input function. For modes that do not require PPI_FS2, the associated timer is not restricted in functionality and can be operated as if the PPI were not being used (that is, the TMR1 pin becomes available for timer use as well). For more information on configuring and using the timers, please refer to the General-Purpose Timers chapter. with the start frame detec In RX modewhere a3 external aframe syncs,followed byofan assertion of tion occurs ssertion is PPI_FS2 while PPI_FS3 is low. This happens at the start of field 1. Note that PPI_FS3 only needs to be low when PPI_FS1 is asserted, not when PPI_FS2 asserts. Also, PPI_FS3 is only used to synchronize to the start of the very first frame after the PPI is enabled. It is subsequently ignored. PPI_FS1 In TX modes with external frame syncs, the PPI_FS1 and PPI_FS2 pins are treated as edge-sensitive inputs. In this mode, it is not necessary to configure the timer(s) associated with the frame sync(s) as input(s), or to enable them via the TIMER_ENABLE register. Additionally, the actual timers themselves are available for use, even though the timer pin(s) are taken over by the PPI. In this case, there is no requirement that the timebase (configured by TIN_SEL in TIMERx_CONFIG) be PPI_CLK. However, if using a timer whose pin is connected to an external frame sync, be sure to disable the pin via the OUT_DIS bit in TIMER_CONFIG. Then the timer itself can be configured and enabled for non-PPI use without affecting PPI operation in this mode. For more information, see the General-Purpose Timers chapter. Programming Model The following sections describe the PPI programming model. 15-22 ADSP-BF52x Blackfin Processor Hardware Reference D MA Operation The PPI must be used with the processor’s DMA engine. This section discusses how the two interact. For additional information about the DMA engine, including explanations of DMA registers and DMA operations, please refer to the Direct Memory Access chapter. The PPI DMA channel can be configured for either transmit or receive operation, and it has a maximum throughput of (PPI_CLK) × (16 bits/transfer). In modes where data lengths are greater than eight bits, only one element can be clocked in per PPI_CLK cycle, and this results in reduced bandwidth (since no packing is possible). The highest throughput is achieved with 8-bit data and PACK_EN = 1 (packing mode enabled). Note for 16-bit packing mode, there must be an even number of data elements. Configuring the PPI’s DMA channel is a necessary step toward using the PPI interface. It is the DMA engine that generates interrupts upon completion of a row, frame, or partial-frame transfer. It is also the DMA engine that coordinates the origination or destination point for the data that is transferred through the PPI. The processor’s 2D DMA capability allows the processor to be interrupted at the end of a line or after a frame of video has been transferred, as well as if a DMA error occurs. In fact, the specification of the DMA_XCOUNT and DMA_YCOUNT MMRs allows for flexible data interrupt points. For example, assume the DMA registers XMODIFY = YMODIFY = 1. Then, if a data frame ADSP-BF52x Blackfin Processor Hardware Reference 15-23 contains 320 x 240 bytes (240 rows of 320 bytes each), these conditions hold: • Setting XCOUNT = 320, YCOUNT = 240, and DI_SEL = 1 (the DI_SEL bit is located in DMA_CONFIG) interrupts on every row transferred, for the entire frame. • Setting XCOUNT = 320, YCOUNT = 240, and DI_SEL = 0 interrupts only on the completion of the frame (when 240 rows of 320 bytes have been transferred). • Setting XCOUNT = 38,400 (320 x 120), YCOUNT = 2, and DI_SEL = 1 causes an interrupt when half of the frame has been transferred, and again when the whole frame has been transferred. The general procedure for setting up DMA operation with the PPI follows. 1. Configure DMA registers as appropriate for desired DMA operating mode. 2. Enable the DMA channel for operation. 3. Configure appropriate PPI registers. 4. Enable the PPI by writing a 1 to bit 0 in PPI_CONTROL. 5. If internally generated frame syncs are used, write to the TIMER_ENABLE register to enable the timers linked to the PPI frame syncs. Figure 15-12 shows a flow diagram detailing the steps on how to configure the PPI for the various modes of operation. 15-24 ADSP-BF52x Blackfin Processor Hardware Reference START Y PROGRAM Y_COUNT AND Y_MODIFY 2D DMA? N Enable necessary PPI pins through PORT_MUX and PORT_FER registers Y GP? Y FS? PROGRAM PPI_DELAY N N EXTERNAL TRIGGER? Y Y INTERNAL FS? N PROGRAM PPI_FRAME PROGRAM TIMER(S) LINKED WITH FS N PROGRAM PPI_COUNT WRITE DMA_CONFIG TO ENABLE DMA WRITE PPI_CONTROL TO ENABLE PPI Y INTERNAL FS? WRITE TIMER_ENABLE TO ENABLE TIMERS N END Figure 15-12. PPI Flow Diagram ADSP-BF52x Blackfin Processor Hardware Reference 15-25 P PI Registers The PPI has five memory-mapped registers (MMRs) that regulate its operation. These registers are the PPI control register (PPI_CONTROL), the PPI status register (PPI_STATUS), the delay count register (PPI_DELAY), the transfer count register (PPI_COUNT), and the lines per frame register (PPI_FRAME). Descriptions and bit diagrams for each of these MMRs are provided in the following sections. P PI Control Register (PPI_CONTROL) The PPI_CONTROL register configures the PPI for operating mode, control signal polarities, and data width of the port. See Figure 15-13 for a bit diagram of this MMR. The POLC and POLS bits allow for selective signal inversion of the PPI_CLK and PPI_FS1/PPI_FS2 signals, respectively. This provides a mechanism to connect to data sources and receivers with a wide array of control signal polarities. Often, the remote data source/receiver also offers configurable signal polarities, so the POLC and POLS bits simply add increased flexibility. The DLEN[2:0] field is programmed to specify the width of the PPI port in any mode. Note any width from 8 to 16 bits is supported, with the exception of a 9-bit port width. Any pins unused by the PPI as a result of the DLEN setting are free for use in their other functions. 656 modes, field should configured In ITU-Rgreater than athe port width. Ifnotis,bethe PPI will for anything 10-bit it DLEN reserve extra pins, making them unusable by other peripherals. The SKIP_EN bit, when set, enables the selective skipping of data elements being read in through the PPI. By ignoring data elements, the PPI is able to conserve DMA bandwidth. 15-26 ADSP-BF52x Blackfin Processor Hardware Reference PPI Control Register (PPI_CONTROL) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POLS 0 - PPI_FS1 and PPI_FS2 are treated as rising edge asserted 1 - PPI_FS1 and PPI_FS2 are treated as falling edge asserted POLC 0 - PPI samples data on rising edge and drives data on falling edge of PPI_CLK 1 - PPI samples data on falling edge and drives data on rising edge of PPI_CLK DLEN[2:0] (Data Length) 000 - 8 bits 001 - 10 bits 010 - 11 bits 011 - 12 bits 100 - 13 bits 101 - 14 bits 110 - 15 bits 111 - 16 bits SKIP_EO (Skip Even Odd) In ITU-R 656 and GP Input modes: 0 - Skip odd-numbered elements 1 - Skip even-numbered elements SKIP_EN (Skip Enable) In ITU-R 656 and GP Input modes: 0 - Skipping disabled 1 - Skipping enabled PACK_EN (Packing Mode Enable) 0 - Disabled 1 - Output mode, unpacking enabled; Input mode, packing enabled Reset = 0x0000 PORT_EN (Enable) 0 - PPI disabled 1 - PPI enabled PORT_DIR (Direction) 0 - PPI in Receive mode (input) 1 - PPI in Transmit mode (output) XFR_TYPE[1:0] (Transfer Type) In Input mode: 00 - ITU-R 656, Active Field Only 01 - ITU-R 656, Entire Field 10 - ITU-R 656, Vertical Blanking Only 11 - Non-ITU-R 656 mode In Output mode: 00, 01, 10 - Sync-less Output mode 11 - Output mode with 1, 2, or 3 frame syncs PORT_CFG[1:0] (Port Configuration) In non-ITU-R 656 Input modes (PORT_DIR = 0, XFR_TYPE = 11): 00 - 1 external frame sync 01 - 2 or 3 internal frame syncs 10 - 2 or 3 external frame syncs 11 - 0 frame syncs, triggered In Output modes with frame syncs (PORT_DIR = 1, XFR_TYPE = 11): 00 - 1 frame sync 01 - 2 or 3 frame syncs 10 - Reserved 11 - Sync PPI_FS3 to assertion of PPI_FS2 rather than of PPI_FS1. FLD_SEL (Active Field Select) In ITU-R 656 modes, when XFR_TYPE = 00: 0 - Field 1 1 - Fields 1 and 2 In RX mode with external frame sync, when PORT_CFG = 11: 0 - External trigger 1 - Internal trigger Figure 15-13. PPI Control Register ADSP-BF52x Blackfin Processor Hardware Reference 15-27 When the SKIP_EN bit is set, the SKIP_EO bit allows the PPI to ignore either the odd or the even elements in an input datastream. This is useful, for instance, when reading in a color video signal in YCbCr format (Cb, Y, Cr, Y, Cb, Y, Cr, Y...). Skipping every other element allows the PPI to only read in the luma (Y) or chroma (Cr or Cb) values. This could also be useful when synchronizing two processors to the same incoming video stream. One processor could handle luma processing and the other (whose SKIP_EO bit is set differently from the first processor’s) could handle chroma processing. This skipping feature is valid in ITU-R 656 modes and RX modes with external frame syncs. The PACK_EN bit only has meaning when the PPI port width (selected by DLEN[2:0]) is eight bits. Every PPI_CLK-initiated event on the DMA bus (that is, an input or output operation) handles 16-bit entities. In other words, an input port width of ten bits still results in a 16-bit input word for every PPI_CLK; the upper 6 bits are 0s. Likewise, a port width of eight bits also results in a 16-bit input word, with the upper eight bits all 0s. In the case of 8-bit data, it is usually more efficient to pack this information so that there are two bytes of data for every 16-bit word. This is the function of the PACK_EN bit. When set, it enables packing for all RX modes. 15-28 ADSP-BF52x Blackfin Processor Hardware Reference Consider this data transported into the PPI via DMA: 0xCE, 0xFA, 0xFE, 0xCA.... • With PACK_EN set: This is read into the PPI, configured for an 8-bit port width: 0xCE, 0xFA, 0xFE, 0xCA... • This is transferred onto the DMA bus: 0xFACE, 0xCAFE,... • With PACK_EN cleared: This is read into the PPI: 0xCE, 0xFA, 0xFE, 0xCA,... • This is transferred onto the DMA bus: 0x00CE, 0x00FA, 0x00FE, 0x00CA,... For TX modes, setting PACK_EN enables unpacking of bytes. Consider this data in memory, to be transported out through the PPI via DMA: 0xFACE CAFE.... ADSP-BF52x Blackfin Processor Hardware Reference 15-29 (0xFA and 0xCA are the two most significant bits (MSBs) of their respective 16-bit words) • With PACK_EN set: This is DMAed to the PPI: 0xFACE, 0xCAFE,... • This is transferred out through the PPI, configured for an 8-bit port width (note LSBs are transferred first): 0xCE, 0xFA, 0xFE, 0xCA,... • With PACK_EN cleared: This is DMAed to the PPI: 0xFACE, 0xCAFE,... • This is transferred out through the PPI, configured for an 8-bit port width: 0xCE, 0xFE,... The FLD_SEL bit is used primarily in the active field only ITU-R 656 mode. The FLD_SEL bit determines whether to transfer in only field 1 of each video frame, or both fields 1 and 2. Thus, it allows a savings in DMA bandwidth by transferring only every other field of active video. The PORT_CFG[1:0] field is used to configure the operating mode of the PPI. It operates in conjunction with the PORT_DIR bit, which sets the direction of data transfer for the port. The XFR_TYPE[1:0] field is also used to configure operating mode and is discussed below. See Table 15-1 on page 15-4 for the possible operating modes for the PPI. The XFR_TYPE[1:0] field configures the PPI for various modes of operation. Refer to Table 15-1 on page 15-4 to see how XFR_TYPE[1:0] interacts with other bits in PPI_CONTROL to determine the PPI operating mode. 15-30 ADSP-BF52x Blackfin Processor Hardware Reference The PORT_EN bit, when set, enables the PPI for operation. an input port, When configured asenabled until thethe PPI does not start data transfer after being appropriate synchronization signals are received. If configured as an output port, transfer (including the appropriate synchronization signals) begins as soon as the frame syncs (timer units) are enabled, so all frame syncs must be configured before this happens. Refer to the section “Frame Synchronization in GP Modes” on page 15-20 for more information. PPI Status Register (PPI_STATUS) The PPI_STATUS register, shown in Figure 15-14, contains bits that provide information about the current operating state of the PPI. The ERR_DET bit is a sticky bit that denotes whether or not an error was detected in the ITU-R 656 control word preamble. The bit is valid only in ADSP-BF52x Blackfin Processor Hardware Reference 15-31 ITU-R 656 modes. If ERR_DET = 1, an error was detected in the preamble. If ERR_DET = 0, no error was detected in the preamble. PPI Status Register (PPI_STATUS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 LT_ERR_OVR (Horizontal Tracking Overflow Error) - W1C ERR_NCOR (Error Not Corrected) - W1C Used only in ITU-R 656 modes 0 - No uncorrected preamble error has occurred 1 - Preamble error detected but not corrected Used only in ITU-R 656 modes 0 - No horizontal tracking overflow error 1 - PPI_COUNT expired before receiving SAV code LT_ERR_UNDR (Horizontal Tracking Underflow Error) - W1C ERR_DET (Error Detected) - W1C 0 - No horizontal tracking underflow error 1 - PPI_FS1 (or SAV code) received before PPI_COUNT expired for that line Used only in ITU-R 656 modes 0 - No preamble error detected 1 - Preamble error detected FLD (Field Indicator) 0 - Field 1 1 - Field 2 UNDR (FIFO Underrun) - W1C 0 - No interrupt 1 - FIFO Underrun Error interrupt occurred OVR (FIFO Overflow) - W1C 0 - No interrupt 1 - FIFO Overflow Error interrupt occurred FT_ERR (Frame Track Error) - W1C 0 - No interrupt 1 - Frame Track Error interrupt occurred Figure 15-14. PPI Status Register The ERR_NCOR bit is sticky and is relevant only in ITU-R 656 modes. If ERR_NCOR = 0 and ERR_DET = 1, all preamble errors that have occurred have been corrected. If ERR_NCOR = 1, an error in the preamble was detected but not corrected. This situation generates a PPI error interrupt, unless this condition is masked off in the SIC_IMASK register. The FT_ERR bit is sticky and indicates, when set, that a frame track error has occurred. In this condition, the programmed number of lines per 15-32 ADSP-BF52x Blackfin Processor Hardware Reference frame in PPI_FRAME does not match up with the “frame start detect” condition (see the information note on page 15-36). A frame track error generates a PPI error interrupt, unless this condition is masked off in the SIC_IMASK register. The FLD bit is set or cleared at the same time as the change in state of F (in ITU-R 656 modes) or PPI_FS3 (in other RX modes). It is valid for input modes only. The state of FLD reflects the current state of the F or PPI_FS3 signals. In other words, the FLD bit always reflects the current video field being processed by the PPI. The OVR bit is sticky and indicates, when set, that the PPI FIFO has overflowed and can accept no more data. A FIFO overflow error generates a PPI error interrupt, unless this condition is masked off in the SIC_IMASK register. FIFO is bits wide and ThebitPPI sticky and16indicates, whenhas 16 entries. FIFO has is set, that the PPI The UNDR underrun and is data-starved. A FIFO underrun error generates a PPI error interrupt, unless this condition is masked off in the SIC_IMASK register. The LT_ERR_OVR and LT_ERR_UNDR bits are sticky and indicate, when set, that a line track error has occurred. These bits are valid for RX modes with recurring frame syncs only. If one of these bits is set, the programmed number of samples in PPI_COUNT did not match up with the actual number of samples counted between assertions of PPI_FS1 (for general-purpose modes) or start of active video (SAV) codes (for ITU-R 656 modes). If the PPI error interrupt is enabled in the SIC_IMASK register, an interrupt request is generated when one of these bits is set. The LT_ERR_OVR flag signifies that a horizontal tracking overflow has occurred, where the value in PPI_COUNT was reached before a new SAV code was received. This flag does not apply for non ITU-R 656 modes; in this case, once the value in PPI_COUNT is reached, the PPI simply stops counting until receiving the next PPI_FS1 frame sync. ADSP-BF52x Blackfin Processor Hardware Reference 15-33 The LT_ERR_UNDR flag signifies that a horizontal tracking underflow has occurred, where a new SAV code or PPI_FS1 assertion occurred before the value in PPI_COUNT was reached. PPI Delay Count Register (PPI_DELAY) The PPI_DELAY register, shown in Figure 15-15, can be used in all configurations except ITU-R 656 modes and GP modes with 0 frame syncs. It contains a count of how many PPI_CLK cycles to delay after assertion of PPI_FS1 before starting to read in or write out data. at one frame sync, Note in TX modes usingwhatleastspecified in the there is aregister. one-cycle delay beyond is PPI_DELAY PPI Delay Count Register (PPI_DELAY) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 PPI_DELAY[15:0] Number of PPI_CLK cycles to delay after assertion of PPI_FS1 before latching in or sending out data Figure 15-15. PPI Delay Count Register PPI Transfer Count Register (PPI_COUNT) The PPI_COUNT register, shown in Figure 15-16, is used in all modes except “RX mode with 0 frame syncs, external trigger” and “TX mode with 0 frame syncs.” For RX modes, this register holds the number of samples to read into the PPI per line, minus one. For TX modes, it holds the number of samples to write out through the PPI per line, minus one. The register itself does not actually decrement with each transfer. Thus, at the beginning of a new line of data, there is no need to rewrite the value of 15-34 ADSP-BF52x Blackfin Processor Hardware Reference this register. For example, to receive or transmit 100 samples through the PPI, set PPI_COUNT to 99. the Take care tos ensure that withnumber of samples programmed into i in keeping the number of samples expected durPPI_COUNT ing the “horizontal” interval specified by PPI_FS1. PPI Transfer Count Register (PPI_COUNT) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 PPI_COUNT[15:0] In RX modes, holds one less than the number of samples to read in to the PPI per line. In TX modes, holds one less than the number of samples to write out through the PPI per line. Figure 15-16. PPI Transfer Count Register PPI Lines Per Frame Register (PPI_FRAME) The PPI_FRAME register, shown in Figure 15-17, is used in all TX and RX modes with two or three frame syncs. For ITU-R 656 modes, this register holds the number of lines expected per frame of data, where a frame is defined as field 1 and field 2 combined, designated by the F indicator in the ITU-R stream. Here, a line is defined as a complete ITU-R 656 SAV-EAV cycle. For non ITU-R 656 modes with external frame syncs, a frame is defined as the data bounded between PPI_FS2 assertions, regardless of the state of PPI_FS3. A line is defined as a complete PPI_FS1 cycle. In these modes, PPI_FS3 is used only to determine the original “frame start” each time the PPI is enabled. It is ignored on every subsequent field and frame, and its state (high or low) is not important except during the original frame start. ADSP-BF52x Blackfin Processor Hardware Reference 15-35 If the start of a new frame (or field, for ITU-R 656 mode) is detected before the number of lines specified by PPI_FRAME have been transferred, a frame track error results, and the FT_ERR bit in PPI_STATUS is set. However, the PPI still automatically reinitializes to count to the value programmed in PPI_FRAME, and data transfer continues. 656 modes, a frame start detect In ITU-R, the field indicator. This occurs athappens onofthe falling edge of the start field 1. F In RX mode with three external frame syncs, a frame start detect refers to a condition where a PPI_FS2 assertion is followed by an assertion of PPI_FS1 while PPI_FS3 is low. This occurs at the start of field 1. Note that PPI_FS3 only needs to be low when PPI_FS1 is asserted, not when PPI_FS2 asserts. Also, PPI_FS3 is only used to synchronize to the start of the very first frame after the PPI is enabled. It is subsequently ignored. When using RX mode with three external frame syncs, and only two syncs are needed, configure the PPI for 3-frame-sync operation and provide an external pull-down to GND for the PPI_FS3 pin. PPI Lines Per Frame Register (PPI_FRAME) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0000 PPI_FRAME[15:0] Holds the number of lines expected per frame of data Figure 15-17. PPI Lines Per Frame Register 15-36 ADSP-BF52x Blackfin Processor Hardware Reference P rogramming Examples The PPI can be configured to receive data from a video source in several RX modes. The following programming examples (Listing 15-1 through Listing 15-5) describe the ITU-R 656 entire field input mode. Listing 15-1. Configure DMA Registers config_dma: /*Assumes PPI is mapped to DMA channel 0.*/ /* DMA0_START_ADDR */ R0.L = rx_buffer; R0.H = rx_buffer; P0.L = lo(DMA0_START_ADDR); P0.H = hi(DMA0_START_ADDR); [P0] = R0; /* DMA0_CONFIG */ R0.L = DI_EN | WNR; P0.L = lo(DMA0_CONFIG); P0.H = hi(DMA0_CONFIG); W[P0] = R0.L; /* DMA0_X_COUNT */ R0.L = 256; P0.L = lo(DMA0_X_COUNT); P0.H = hi(DMA0_X_COUNT); W[P0] = R0.L; /* DMA0_X_MODIFY */ R0.L = 0x0001; P0.L = lo(DMA0_X_MODIFY); P0.H = hi(DMA0_X_MODIFY); W[P0] = R0.L; ADSP-BF52x Blackfin Processor Hardware Reference 15-37 ssync; config_dma.END: RTS; Listing 15-2. Configure PPI Registers config_ppi: /* PPI_CONTROL */ P0.L = lo(PPI_CONTROL); P0.H = hi(PPI_CONTROL); R0.L = 0x0004; W[P0] = R0.L; ssync; config_ppi.END: RTS; Listing 15-3. Enable DMA /* DMA0_CONFIG */ P0.L = lo(DMA0_CONFIG); P0.H = hi(DMA0_CONFIG); R0.L = W[P0]; bitset(R0,0); W[P0] = R0.L; ssync; Listing 15-4. Enable PPI /* PPI_CONTROL */ P0.L = lo(PPI_CONTROL); P0.H = hi(PPI_CONTROL); R0.L = W[P0]; bitset(R0,0); 15-38 ADSP-BF52x Blackfin Processor Hardware Reference W[P0] = R0.L; ssync; Listing 15-5. Clear DMA Completion Interrupt /* DMA0_IRQ_STATUS */ P2.L = lo(DMA0_IRQ_STATUS); P2.H = hi(DMA0_IRQ_STATUS); R2.L = W[P2]; BITSET(R2,0); W[P2] = R2.L; ssync; Unique Behavior for the ADSP-BF52x Processor None. ADSP-BF52x Blackfin Processor Hardware Reference 15-39 15-40 ADSP-BF52x Blackfin Processor Hardware Reference 1 6 SECURITY This chapter describes the security features and functionality of the ADSP-BF52x Blackfin processor. Following an overview and a list of key features are a description of operation and functional modes of operation. This chapter includes the following sections: • “Overview” on page 16-1 • “Features” on page 16-4 • “Description of Operation” on page 16-6 • “Programming Model” on page 16-32 • “Security Registers” on page 16-45 The intention of the chapter is to describe security features of the ADSP-BF52x Blackfin processor and how they can be used to facilitate a secure system. It is beyond the scope of this chapter to fully describe various ways to implement secure systems or to describe security protocols and primitives in any great detail. O verview LockboxTM Secure Technology for Analog Devices Blackfin processors is comprised of a mix of hardware and software mechanisms designed to prevent unauthorized accesses and allow trusted code to execute on the ADSP-BF52x Blackfin Processor Hardware Reference 16-1 processor. Throughout the rest of this chapter, the terms Blackfin Lockbox secure technology and Lockbox will be used interchangeably. security features is completely The developer’s decision to useare enabled by default. The developtional. No security features oper can choose to not implement security features in the application if it is so desired. The Blackfin will always power up/boot in Open Mode when no security features or restrictions are enabled. Blackfin Lockbox secure technology allows users to: • safeguard as little as a single function, a complete system, or anything in-between. • uniquely identify each processor by a Unique Chip ID. • utilize secure key storage provided by non-volatile, write-protectable One Time Programmable (OTP) memory. • perform digital signature authentication using elliptic curve cryptography (ECC) and secure one-way hash (SHA-1) algorithms implemented in firmware. • keep secret information in secure OTP Memory. • use any encryption algorithm to protect code or other assets. ensure data integrity through digital signature authentication. • safeguard confidentiality by encrypting any or all of the system from core IP (code security) to data integrity. 16-2 ADSP-BF52x Blackfin Processor Hardware Reference These features in combination provide the following benefits. • Authenticity/Origin verification—Lockbox secure technology allows verification of a code image against its associated digital signature, and provides for a process to identify entities and data origins. • Integrity—Developers can use a digital signature authentication process to ensure that the message or the content of the storage media has not been altered in any way. If either the message or digital signature was altered, Lockbox fails during the authentication process. • Confidentiality—Cryptographic encryption/decryption supports situations that require the ability to prevent unauthorized users from seeing and using designated files and streams. Methods for ensuring confidentiality are supported by the secure processing environment (Secure Mode) and secure memory. • Renewability—System components can be updated to enhance security. The Unique Chip ID enables end users to identify each Blackfin processor and hence each OEM device in which the processor resides. This Lockbox feature can be used in support of revocation and renewability of licenses in case of security violations in digital rights management systems. For example: ADSP-BF52x Blackfin Processor Hardware Reference 16-3 • Unique Chip ID—In combination with a trusted DRM agent (sourced by the OEM), this feature enables developers to implement renewability in DRM systems. • Unique Chip ID—Provides capability to identify each OEM device and “blacklist” devices to remove them from a system. • Prevention of mass copying—Lockbox supports cryptographic encryption/decryption algorithms for situations when confidentiality is required. The Unique Chip ID can also be utilized to “bind” the processor to one specific boot source/device and can be used to facilitate antitheft schemes and prevent OEM device cloning. The ADSP-BF52x Blackfin processors featuring Lockbox secure technology provide security features that enable applications to use secure protocols consisting of code authentication and execution of code within a secure environment. Together these features protect secure memory spaces and restrict control of security features to authenticated developer code. F eatures Lockbox is comprised of a combination of hardware and software elements. These elements are: • OTP Memory An array of non-volatile write-protectable memory that can be programmed by the developer only one time. Half of the array is public (accessible in any mode) and the other half is private (only accessible in Secure Mode). For more information on OTP memory, refer to Chapter 4, “One-Time Programmable Memory”. • Secured System Switches 16-4 ADSP-BF52x Blackfin Processor Hardware Reference Programmable bitfields in the Secured System Switches MMR to disable and enable different methods of memory access in support of a secured environment. Some of these protection mechanisms include disabling DMA access to L1 memory and disabling ADI JTAG instructions from the ICE port. • Secure Mode Control This involves the Secure State Machine hardware required to support a transition from an unsecured state of operation (Open Mode), through an authentication state (Secure Entry Mode), and finally to a secured state (Secure Mode) where secrets are accessible. • Firmware Code that resides in the on-chip ROM and performs digital signature authentication. Having the code that performs the digital signature authentication in ROM ensures integrity of the code. • User callable cryptographic ciphers In addition to the control code that resides in the on-chip ROM used for authentication, the SHA-1 cryptographic function is user-callable. The API is documented in “Programming Model” on page 16-32. • Unique Chip ID Each ADSP-BF52x Blackfin processor has a 128-bit unique chip identification value stored in public OTP memory. The Unique Chip ID is programmed and write protected before a processor leaves the Analog Devices factory. It is always located at the same OTP page address. Unique Chip value can read The 128-bit the developer IDend user. Abetotal ofbut cannotofbeOTP modified by or 64K bits memory is available to the developer if additional user-defined ID values are desired. These IDs can be stored in either public or priADSP-BF52x Blackfin Processor Hardware Reference 16-5 vate areas of OTP memory depending on application requirements. Refer to Chapter 4, “One-Time Programmable Memory” for details. Description of Operation Blackfin Lockbox technology is based upon the concept of authentication of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and access protected assets. Digital signatures are created using a public-key signature algorithm, the Elliptic Curve Cryptography (ECC) public-key cipher, and a secure one-way hash algorithm, SHA-1. A public-key algorithm actually uses two different keys; the public key and the private key (called a key pair). The private key is known only to its owner and is not stored on-chip, while the public key can be available to anyone and is stored in the public OTP memory region on-chip. Public-key algorithms, such as ECC, are designed so that if one key is used for encryption, the other is necessary for decryption. Furthermore, the encryption key cannot be reasonably calculated from the decryption key. In a digital signature authentication scheme like Lockbox, the private key is used to generate the signature and the corresponding public key is used to validate the signature. Each ADSP-BF52x Blackfin processor has an on-chip ROM that contains firmware with the Elliptic Curve Cryptography (ECC) and SHA-1 algorithms. These are called to verify the digital signatures (ECDSA1). JTAG emulation and test features are disabled in hardware, and certain memory access restrictions are enabled during verification of the digital signature. Once the signature is authenticated, the access restrictions are still in effect and can only be controlled by the authenticated user code. 1 16-6 ECDSA implementation on the ADSP-BF52x Blackfin products only supports the Koblitz curve. ADSP-BF52x Blackfin Processor Hardware Reference S ecure State Machine The ADSP-BF52x processor includes a Secure State Machine to handle the different protection configurations of the processor depending on the security situation. The machine states are “Open Mode”, “Secure Entry Mode”, and “Secure Mode” (See Figure 16-1). The following sections describe these machine states. The state of the Secure State Machine can be identified by reading bits in the SECURE_STATUS[1:0] register. The bit values in the upper right of the states shown in Figure 16-1 correspond to the bit values in SECURE_STATUS[1:0]. For more information on the SECURE_STATUS register, see “Security Registers” on page 16-45. POWER UP OR RESET OPEN MODE (00) ENTRY HARDWARE TRIGGER AUTHENTICATION FAILURE SECURE ENTRY MODE (01) SOFTWARE TRIGGER (SECURE MODE BIT = 1) SECURE MODE (10) SOFTWARE TRIGGER (SECURE MODE BIT = 0) Figure 16-1. Secure State Machine Modes ADSP-BF52x Blackfin Processor Hardware Reference 16-7 O pen Mode This is the default operating state of the processor, in which no restrictions are present except restricted access to the Private OTP memory area. The processor powers up and boots in Open Mode. This is the default state upon power up and after processor reset. No Lockbox security features or protection mechanisms are enabled in this state. The state flow illustrated in Figure 16-1 shows that the Secure State Machine can only transition from Open Mode into Secure Entry Mode, and there is no direct path from Open Mode into Secure Mode. Secure Entry Mode The on-chip ROM firmware performs the authentication process in this operating state. This mode is entered when NMI is active, and the program counter (PC) is vectored to the first address of the authentication firmware in the on-chip ROM. The program counter is monitored to ensure that it remains within the address range allocated to the Authentication firmware code. If the program counter vectors outside of the address range of the authorization code, authentication fails and the state returns to Open Mode. Any errors caught by firmware or hardware monitor will result in authentication failure and an abortion of the authentication process with the firmware exiting Secure Entry Mode and transitioning back to Open Mode. If authentication is successful, the firmware initiates the transition from Secure Entry Mode to Secure Mode. In Secure Entry Mode, no DMA access is allowed to certain regions of internal SRAM, and JTAG emulation is disabled. The user should disable cache prior to initiating authentication. Interrupts are disabled by firmware prior to entry into Secure Mode. Interrupts are either re-enabled by dropping the interrupt level from NMI via the SESR arguments, or they are reenabled after authentication in the authenticated code after entry into Secure Mode. In addition, only the public area of OTP memory is accessible in this mode. For more information on memory access restric- 16-8 ADSP-BF52x Blackfin Processor Hardware Reference tions within Secure Entry Mode, see “Secure Entry Service Routine (SESR) API” on page 16-32. State flow, illustrated in Figure 16-1, shows that the Secure State Machine can only transition from Secure Entry Mode to Secure Mode upon successful digital signature authentication. A transition from Secure Entry Mode back into Open Mode can occur if digital signature authentication fails or if the authentication process is aborted due to an error observed by the firmware. Such errors include illegal memory boundary conditions or jumps outside of the firmware range (for example, servicing an interrupt). Secure Mode Secure operating state in which trusted, authenticated code is allowed unrestricted access to the processor resources, execution of authenticated code occurs, decryption of sensitive information, etc. This is the only mode that allows access (reads and writes) to the private OTP memory space where secure data, such as secret keys, can be stored. Hence, the private area of OTP memory can be used to store confidential, secret information that only authorized authenticated code can access. Therefore, this is the only operating state in which users can securely run their own Blackfin implementation of any cryptographic cipher in which secret keys are used. Only the code (or message) digitally signed by a trusted source and successfully passed through Lockbox’s authentication process can gain access to Secure Mode. State flow illustrated in Figure 16-1 shows that the Secure State Machine can only transition from Secure Mode back into Open Mode, and there is no direct path from Secure Mode into Secure Entry Mode. Exit from ADSP-BF52x Blackfin Processor Hardware Reference 16-9 Secure Mode is implemented through software control by writing a “0” value to the SECURE0 bit within the SECURE_CONTROL register. reset or power cycling will the processor Assertion ofOpen Mode regardless of thealso returnoperation whento the default state of the reset or power cycle event occurred. See special handling of hardware reset in “Reset Handling in Secure Mode” on page 16-21. Access to private OTP memory is restricted in Open Mode and Secure Entry Mode regardless of whether or not other security features are enabled or disabled. 16-10 ADSP-BF52x Blackfin Processor Hardware Reference S ecureMode Control Figure 16-2 describes the inputs that control the secure state machine flow. All secure system switches (SYSSWT) are deactivated. The SYSSWT register is not accessible. OTP secrets are read/write protected. Hardware monitor has detected the proper entry of Authentication firmware. NMI must be active. POWER UP OR RESET OPEN MODE (00) ENTRY HARDWARE TRIGGER AUTHENTICATION FAILURE SECURE ENTRY MODE (01) SOFTWARE TRIGGER (SECURE MODE BIT = 1) SECURE MODE Exit of firmware will reset the securitySM. Used if authentication fails. All SYSSWT are activated. Most SYSSWT are not accessible including the OTP secrets enable bit (OTPSEN). Firmware has written the SECURE0 bit. (10) SOFTWARE TRIGGER (SECURE MODE BIT = 0) The SYSSWT register is fully accessible. Initially the SYSSWT values (secured system switches) are activated. Writing 0 to the SECURE0 bit will reset the securitySM. Used to exit Secure mode. Figure 16-2. Secure Mode Control ADSP-BF52x Blackfin Processor Hardware Reference 16-11 Hardware supports transition from an Open Mode of operation, through a Secure Entry Mode, to a Secure Mode where secrets are accessible. Open Mode is characterized by being the default mode of processor upon power up/reset/boot, holding all secured system switches deactivated and protecting the private OTP memory area from access. The processor is open with all features being available with no restrictions (except for the private area of OTP memory). Secure Entry Mode is characterized by executing firmware out of internal ROM memory to authenticate information loaded into on-chip memory. All secured system switches are activated. However, private OTP Memory is not accessible yet. Secure Mode is entered only after a successful digital signature authentication process from Secure Entry Mode. It provides access to the private OTP memory area and makes secured system switches accessible to user (authenticated) code. This is the mode of operation in which to perform sensitive decryption or execution of trusted, authenticated code. Authentication can only be requested and initiated while the processor is operating in Open Mode. If authentication is requested while the processor is operating in Secure Mode, the Secure State Machine will not transition into Secure Entry Mode. Instead, the Secure State Machine will remain in Secure Mode. Mode Please note that Open Mode, Secure Entry Mode and SecureMode are states which pertain to the Secure State Machine. User and Supervisor Mode are modes of operation which pertain to the core. The use of the term “mode” should not be confused and are not necessarily mutually exclusive. In Open Mode, the processor can operate in either User or Supervisor Mode. Since the firmware is entered when the NMI is being handled, Secure Entry Mode must start in Supervisor Mode. Finally, authenticated code executing in Secure Mode must be either operating at NMI interrupt level or the interrupt level that triggered the NMI. 16-12 ADSP-BF52x Blackfin Processor Hardware Reference S ecurity Features The following sections provide a functional description of the Security features. Protection relies on the on-chip ROM code that includes Elliptic Curve Cryptography (ECC) and SHA-1 algorithms, applied towards verification of code authenticity using a digital signature. A processor has emulation and test features disabled in hardware as well as certain memory access restrictions upon entry into Secure Entry Mode (where authentication is performed) and maintained into Secure Mode. These functions can be controlled only by authenticated user application software executing in Secure Mode. User code must request authentication by complying with two criteria: (1) asserting a Non-Maskable Interrupt (NMI) and (2) vector the Program Counter (PC) to the first executable address in the Secure Entry Service Routine (SESR) in firmware which resides in on-chip boot ROM. During the authentication process, JTAG emulation is disabled, memory protection restrictions are enabled and interrupts are masked. The user has the option to pass arguments to the security firmware to control certain functionality during the authentication process. Refer to “Secure Entry Service Routine (SESR) API” on page 16-32. D igital Signature Authentication Digital signatures are created off-chip (typically on a host computer) using the ECC algorithm and SHA-1, both of which are available in the public domain. In digital signature authentication, the private key generates the signature (off-chip), and the corresponding public key validates the signature (on-chip). The private key is known only to its owner and is not stored on-chip, while the public key can be available to anyone and is stored on-chip in OTP memory. ADSP-BF52x Blackfin Processor Hardware Reference 16-13 Lockbox uses standards-based cryptographic algorithms for digital signature authentication. ECDSA1 is implemented in the Blackfin ADSP-BF52x processors. Digital signature validation on ADSP-BF52x utilizes Elliptic Curve Cryptography2 (ECC) based on a binary field size of 163 bits and SHA-13 secure one-way hash (which produces a 160-bit message digest). In order to generate public/private key pairs or prepare digital signatures and apply them to application code, developers can use any method that complies with the Elliptic Curve Digital Signature Algorithm (ECDSA) specified in FIPS 186-2 with Change Notice 1 dated October 5, 2001, Digital Signature Standard (DSS). ECDSA is described in ANSI X9.62-1998. The Lockbox implementation in the ADSP-BF52x processors supports the following Koblitz curve, which is recommended in FIPS 186-2 for US Federal Government use: m: 163 (degree of binary field) a: 1 b: 1 (a and b are the constants in the elliptic curve equation: y2 + xy = x3 + ax + b) Xg: 2FE13C0537BBC11ACAA07D793DE4E6D5E5C94EEE8 Yg: 289070FB05D38FF58321F2E800536D538CCDAA3D9 (Xg and Yg define the base point G) r: 4000000000000000000020108A2E0CC0D99F8A5EF (r is the order of the base point G) T: 4 (T is the normal basis type) p(t): t163 + t7 + t6 + t3 + 1 (pt(t) is the field polynomial) The following steps summarize the Digital Signature Authentication process. Steps 1 to 3 correspond to the off-chip creation of a digital signature 1 ECDSA implementation on these Blackfin products only supports the Koblitz curve. These implementations are based on the Elliptic Curve Digital Signature Algorithm (ECDSA) specified in FIPS 186-2 with Change Notice 1 dated October 5, 2001, Digital Signature Standard (DSS) (http://csrc.nist.gov/cryptval/dss.htm), and specified in ANSI X9.62-1998. 3 SHA-1 is based on the publicly available standard for FIPS 180-2 (Secure Hash Signature Standard [SHS]) (FIPS PUB 180-2), http://csrc.nist.gov/CryptoToolkit/tkhash.html). 2 16-14 ADSP-BF52x Blackfin Processor Hardware Reference of a file or message. Steps 4 to 6 correspond to the on-chip digital signature authentication. These steps are preceded by generation of a key pair (Private Key and Public Key) and the programming of the Public Key in the Public OTP Memory. 1. A one-way hash of the file (message to be authenticated) is produced using SHA-1 off-chip (for example, using a host PC). 2. The hash is encrypted through ECC off-chip with the private key, thereby signing the file and completing the generation of the digital signature. 3. The file and the signed hash are stored on an external device such as Flash memory or a host device. 4. Upon transfer to the Blackfin processor’s internal memory, a one-way hash of the file is calculated on-chip through SHA-1 (residing in the Blackfin on-chip boot ROM). 5. Using the ECC algorithm (residing in the Blackfin on-chip boot ROM), the Blackfin decrypts the signed hash with the user's public key stored in the Blackfin processor OTP memory. 6. The two hash results are then compared. If the signed hash matches the calculated hash, the signature is valid and the file is intact. If the digital signature authentication process is successful, the Blackfin processor transitions from Secure Entry Mode to Secure Mode. At this time, all of the access restrictions mentioned will be in place. JTAG will be disabled and certain portions of on-chip SRAM memory are restricted from DMA access. The restrictions can be controlled once in Secure Mode by having the authenticated code modify the Secure System Switches (SECURE_SYSSWT) appropriate for use by the developer’s application. when an application Encryption/decryption. is only necessarynecessary to work with requires confidentiality It is not always encrypted code to ensure code security. Authentication alone can ADSP-BF52x Blackfin Processor Hardware Reference 16-15 be used when confidentiality is not required when ensuring tamper-proof code image and/or non-repudiation in a system. Thus, authentication safeguards code integrity. Since the digital signature uniquely describes its corresponding code/message, the code/message itself does not have to be encrypted if confidentiality is not required. If the code/message is modified, either intentionally or inadvertently, authentication fails since the integrity of the code message has been compromised. D igital Signature Authentication Performance Measurement Authentication can be performed at any point during processor operation in Open Mode. It can be performed immediately upon boot or it can be performed any time after boot. The algorithms used in the Lockbox firmware are highly optimized Blackfin code running from the on-chip boot ROM in the system clock domain. Firmware execution time for the digital signature authentication process is on the order of 40 million core clock cycles, depending upon the size of the digitally signed application code. This must be considered when architecting an application in order to allow a sufficient window of time in which authentication can proceed without requiring servicing of interrupts in the system. The time it takes for authentication is dependent on several factors. These include the size of the message to be authenticated. This affects the amount of calculations done in the secure hash function (SHA-1). It also affects the DMA time required to move the message out of L1 data memory and place it into L1 code memory. P rotection Features In order to establish a secure processing environment and protect the security of applications that establish trust and reach the privileged mode of 16-16 ADSP-BF52x Blackfin Processor Hardware Reference operation, Lockbox implements access restrictions. These restrictions include disabling JTAG emulation and disabling DMA access to portions of on-chip SRAM memory. The memory access restrictions implemented in hardware on the Blackfin processor are not applied to off-chip memory. Therefore, external memory is always considered insecure and caching external memory while operating in Secure Mode represents a security risk. Protection features include the following: • Secure State Machine for implementing privileged states of operation in which access restrictions may be imposed to protect code and data. • Disable DMA access to L1 memory • These restrictions to memory areas are configurable (see “Secure System Switch Register, Bits 15:0” on page 16-47) • Protection of L1 regions of memory with DMA access controlled when in Secure Mode • Disable ADI JTAG emulation from ICE port • Divert hardware reset to NMI during Secure Mode operation to prevent “reset attack” • Provide software control over hardware protection features accessible to trusted code operating in Secure Mode • OTP memory for storage of customer programmable cipher keys, unique chip ID or a customer ID • OTP write protection to protect programmed OTP memory locations from future tampering • Private/Secret OTP memory region accessible only in Secure Mode ADSP-BF52x Blackfin Processor Hardware Reference 16-17 • Store private key(s) for decryption of data or other validation • A privileged mode (including firmware execution out of on-chip ROM) to perform code authentication 16-18 ADSP-BF52x Blackfin Processor Hardware Reference Protection mechanisms are summarized Table 16-1 for each state of the Secure State Machine along with the Secure System Switch register (SECURE_SYSSWT) that provides control over the protection feature. Table 16-1. Secure State Machine Secure State Machine SECURE_SYSSWT Description Protected Memory Range Open Mode (0x00000000) The switches are involuntarily set with all controls OFF (unrestricted access) No protection mechanisms or restrictions enabled No restrictions1 Secure Entry (0x000704D9) EMUDABL Emulation Disable Emulation disabled L1IDABLE L1 Instruction Memory Disable 0xFFA00000— 0xFFA07FFF SRAM 32 KB L1DADABL L1 Data Bank A Memory Disable 0xFF800000— 0xFF807FFF SRAM and SRAM/Cache 32 KB L1DBDABL L1 Data Bank B Memory Disable 0xFF900000— 0xFF901FFF SRAM 8 KB ADSP-BF52x Blackfin Processor Hardware Reference 16-19 Table 16-1. Secure State Machine (Continued) Secure State Machine SECURE_SYSSWT Description Protected Memory Range Secure Mode (0x000704D9) EMUDABL Emulation Disable User Configurable RSTDABL RESET Disable User Configurable L1IDABLE L1 Instruction Memory Disable 0xFFA00000— 0xFFA07FFF SRAM 0-32 KB L1DADABL L1 Data Bank A Memory Disable 0xFF800000— 0xFF807FFF SRAM and SRAM/Cache 0-32 KB L1DBDABL L1 Data Bank B Memory Disable 0xFF900000— 0xFF901FFF SRAM 0-32 KB 1 Private OTP is only accessible when operating in Secure Mode with OTPSEN bit set in SECURE_SYSSWT register On-chip SRAM memory protection takes the form of DMA access restrictions only. There is no need to protect the on-chip SRAM from processor core access because, while operating in Secure Mode, the developer’s authenticated code has full control over the processor core and execution of all core software instructions. It is the responsibility of the developer to take steps to avoid surrendering control of the Program Sequencer and the core to untrusted code execution. Operating in Secure Mode Entering Secure Mode Upon successful digital signature authentication, the Secure State Machine transitions into Secure Mode. The same default protection fea- 16-20 ADSP-BF52x Blackfin Processor Hardware Reference tures enabled in Secure Entry Mode are carried forward into Secure Mode. This includes JTAG emulation being disabled, and DMA access restrictions to memory and interrupts being masked. It is the responsibility of the authenticated code to manipulate or remove these restrictions as desired. Exiting Secure Mode Secure Mode provides a secure operating environment to execute sensitive code, run cryptographic ciphers, and process sensitive data. Upon exiting Secure Mode, the authenticated code should remove any sensitive code and data from memory because this sensitive information will still be accessible in Open Mode if it is not removed prior to exiting Secure Mode. Exit from Secure Mode is implemented through software control by writing a “0” value to the SECURE0 bit within the SECURE_CONTROL register. Refer to “Security Registers” on page 16-45 and “Clearing Private Data” on page 16-22 for more information. Reset Handling in Secure Mode Hardware Reset Hardware reset is diverted to NMI when operating in Secure Mode only. When operating outside of Secure Mode, hardware reset behaves normally. This protection feature is configurable via the RSTDABL bit within the SECURE_SYSSWT register when operating within Secure Mode. This is a protection feature to prevent malicious entities from attempting to assert hardware reset while sensitive code or data is present in the processor’s on-chip SRAM or in the processor’s registers. A “reset attack” could take the following form: If hardware reset were left unprotected and reset was asserted while sensitive information were present on-chip, the processor would return to the default state of Open Mode with no protection features enabled and a malicious entity could gain access to the ADSP-BF52x Blackfin Processor Hardware Reference 16-21 on-chip memory and registers, for example via JTAG emulation. In such a scenario assets intended to be protected could be compromised. By diverting hardware reset to NMI while the processor operates in Secure Mode, servicing of hardware reset can be controlled and delayed in order to first implement a memory clean-up routine in software to purge sensitive information from internal memory and registers prior to servicing reset. At the completion of the memory clean-up, the processor can then be reset via software command and safely returned to Open Mode with no sensitive information available to be compromised. By default, the SESR loads the address of a memory clean-up routine stored in the on-chip boot ROM into the NMI EVT2 prior to transitioning from Secure Entry Mode into Secure Mode. See “Clearing Private Data” on page 16-22 for more information. Clearing Private Data As part of the SESR firmware, there is a small routine stored in the on-chip boot ROM that clears the internal L1 data memory, generates a RESET event, and puts the processor into idle. Note that this firmware memory clear routine does not clear the contents of L1 Instruction memory or Data, Pointer, and DAG registers within the computational units. It is recommended that the user sets this routine as the new EVT2 NMI vector once the user’s authenticated application code is executing. This will prevent a malicious user from trying to reset the processor while it is operating in Secure Mode and then view the contents of internal memory when the processor returns to Open Mode after servicing RESET. running in Secure It is recommended that user softwareprior to clearing the Mode should also perform RAM clean-up SECURE0 Secure Mode bit and exiting Secure Mode via normal code execution within user’s secure function. If sensitive code/data remains in on-chip RAM after exiting Secure Mode without wiping memory and register contents or cycling power to the processor, it is visible and accessible in Open Mode. 16-22 ADSP-BF52x Blackfin Processor Hardware Reference The memory clear routine in the on-chip boot ROM executes a watchdog RESET to reset the processor at the completion of the memory clear. The code also performs a clear of the OTP_DATA0-3 registers which are used to hold data from OTP access reads (i.e. which could contain secret key or other sensitive data left by user code execution). If a custom memory cleanup routine is part of an authenticated message, the user can use that routine instead of the one provided with the Lockbox firmware. The user can simply update EVT2 in the event vector table to point to the start of the custom memory cleanup routine while operating in Secure Mode. their It is strongly recommended thatif developers substitute of L1own custom memory clear routines they require clearing instruction as the ROM memory clear routine will only clear the contents of L1 Data (Bank A and B) memory. The ROM memory clear routine will not protect instruction code from being exposed after reset is serviced or when the Secure State Machine transitions to Open Mode via other means. Due to the fact that hardware reset is configured by default to be redirected to NMI when the processor is operating in Secure Mode, it is recommended that the user implements a watchdog reset within the EVT2 NMI ISR in order to reset the processor. A Watchdog reset is implemented by writing a value 2'b00 in WDOG_CTL[2:1] and causes a complete core reset. The watchdog reset will not be redirected to the NMI pin as in the case of the external hardware reset and it will properly reset the processor. For more details of watchdog reset, refer to “Software Resets” in Chapter 17, System Reset and Booting. This “reset attack” protection scheme needs to protect only against hardware reset. Since it can be applied externally, the system developer typically has no control over reset in an embedded system. While operating in Secure Mode, the developer’s authenticated code has full control over the processor core and execution of all software instructions, so there is no need to protect against soft reset instructions. It is not recommended ADSP-BF52x Blackfin Processor Hardware Reference 16-23 that the user’s secure application code implement a soft reset without first deleting sensitive information from memory and registers. Public Key Requirements A valid ECC public key must be a non-zero value and meet the following criteria: Given the public key value shown here: 369368AF243193D001E39CE76BB1D5DA08A9BC0A6 15F7A90C841D4F1E1B005E70F167F6EF7CD2E251B format in 32-bit little endian as follows: 8A9BC0A6 BB1D5DA0 1E39CE76 43193D00 69368AF2 00000003 CD2E251B 167F6EF7 B005E70F 41D4F1E1 16-24 ADSP-BF52x Blackfin Processor Hardware Reference 5F7A90C8 00000001 The values should be stored in OTP pages 0x10, 0x11, 0x12 as follows, where 'L' denotes lower half of page (OTP page bits 63:0), 'H' denotes upper or high half of page (OTP page bits 127:64): page: 0x010L: 0xbb1d5da08a9bc0a6, page: 0x010H: 0x43193d001e39ce76, page: 0x011L: 0x0000000369368af2, page: 0x011H: 0x167f6ef7cd2e251b, page: 0x012L: 0x41d4f1e1b005e70f, page: 0x012H: 0x000000015f7a90c8, The general format takes the form of twelve (12) 32-bit words: Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 ADSP-BF52x Blackfin Processor Hardware Reference 16-25 Word 7 Word 8 Word 9 Word 10 Word 11 Word 12 Stored into OTP pages in the following order (where 'L' denotes lower half of page, 'H' denotes upper or high half of page): page: 0x010L:Word 2 Word 1 page: 0x010H:Word 4 Word 3 page: 0x011L:Word 6 Word 5 page: 0x011H:Word 8 Word 7 page: 0x012L:Word 10 Word 9 page: 0x012H:Word 12 Word 11 Storing Public Cipher Key in Public OTP In order to make use of security features, the user must first store an ECC public key in the Blackfin processor public region of OTP memory pages 0x10, 0x11, and 0x12 as specified in the Firmware’s Secure Entry Service Routine (SESR) API and the OTP memory map (see “Secure Entry Service Routine (SESR) API” on page 16-32). If no ECC public key is stored in this area of OTP, digital signature authentication cannot be successfully 16-26 ADSP-BF52x Blackfin Processor Hardware Reference completed and no Lockbox security features can be enabled. For more information see Chapter 4, “One-Time Programmable Memory”. Cryptographic Ciphers Lockbox uses SHA-1 and ECC to implement ECDSA as part of the authentication process to enter into Secure Mode. These ciphers reside in the firmware in the on-chip boot ROM. The SHA-1 cipher is user-callable in Open Mode or in Secure Mode. The API is documented in “Programming Model” on page 16-32. Note that ECC is not user-callable and is only executed as part of firmware during the authentication process. Keys Although Lockbox uses an ECC public key for digital signature authentication and has private OTP memory to store private keys for other cryptographic algorithms, Lockbox does not implement key management. Lockbox does not implement key generation, nor does it implement key exchanges natively in the Blackfin hardware. In order to use Lockbox, an ECDSA key pair must be generated. The private key is used off-chip (typically on a host PC) to sign the message. The public key is placed in the public OTP memory where it is used to authenticate the signed message. Lockbox is only part of a full cryptosystem. It is the responsibility of the user to develop the other parts of the cryptosystem necessary for the intended application. Debug Functionality The processor is fully compatible with the IEEE 1149.1 standard, also known as the Joint Test Action Group (JTAG) standard. Full details of the JTAG standard can be found in the document IEEE Standard Test Access Port and Boundary-Scan Architecture, ISBN 1-55937-350-4. ADSP-BF52x Blackfin Processor Hardware Reference 16-27 ADSP-BF52x debug functionality has some modified behavior dependent upon the access privileges associated with the state of the Secure State Machine operating mode. This is to ensure that sensitive information and processing performed within Secure Entry Mode and Secure Mode will not be compromised via JTAG. Furthermore, public JTAG instructions necessary for system test and debug (such as boundary scan and bypass mode) remain in effect regardless of the state of the Secure State Machine and are not hindered by the ADSP-BF52x Secure Mode operation. This makes it possible for developers to debug their systems without interference from the Blackfin processor or its security features. In compliance with the JTAG standard, ADSP-BF52x processors provide an Instruction Register (IR) that interprets 5-bit instruction codes to select the test mode that performs the desired test operation. The instruction register is five bits wide and accommodates up to 32 boundary-scan instructions. The instruction register holds both public and private instructions. The JTAG standard requires some of the public instructions; other public instructions are optional. Private instructions are reserved for the manufacturer’s use. All supported public and private JTAG instructions remain operational when operating in Open Mode. All supported public JTAG features remain operational and all private JTAG features are disabled when operating in Secure Entry Mode and Secure Mode. Refer to Appendix B, “Test Features” for more information about supported JTAG instructions By default, JTAG emulation is disabled when the processor enters Secure Entry Mode or Secure Mode. There is only one way to enter Secure Mode—through successful authentication of user code based on digital signature validation. Once the digital signature authentication process results in success, the user’s trusted, authenticated code is given full control over the processor, including access to Secured System Switches register (SECURE_SYSSWT) that enables/disables various protection mechanisms, including JTAG emulation. The Secured System Switch register provides a setting that allows authenticated code to enable JTAG emula- 16-28 ADSP-BF52x Blackfin Processor Hardware Reference tion either in a one-time secure session setting or in a “sticky” persistent manner that allows emulation to be enabled by default the next time the processor enters Secure Mode. These settings are cleared when reset is asserted or if processor core power is cycled. See the EMUOVR and EMUDABL bits in the SECURE_SYSSWT Secure System Switches Register in “Secure System Switch Register, Bits 15:0” on page 16-47. Two bits within the SECURE_SYSSWT Secure System Switches register control JTAG emulation; they are Emulation Disable (EMUDABL) and Emulation Override (EMUOVR). To enable JTAG emulation for the current session while operating within Secure Mode, SECURE_SYSSWT bit 0 (EMUDABL) must be set to 0. To enable JTAG emulation to remain “sticky” and persistently enabled for the current session and for all subsequent entries into Secure Mode until cleared by the user or until cleared via RESET or cycling power to the processor, SECURE_SYSSWT bit 0 (EMUDABL) must be set to 0 and SECURE_SYSSWT bit 14 (EMUOVR) must be set to 1 simultaneously. See “Secure System Switch Register, Bits 15:0” on page 16-47 for details. The bit is only directly writable when in Secure Mode. can be written to a 0 at any time. RESET will clear EMUOVR. EMUOVR can be cleared by the user at any time and in any mode, including Open Mode, Secure Entry Mode, and Secure Mode. You do not have to operate in Secure Mode in order to clear EMUOVR. EMUDABL EMUOVR The EMUDABL bit is writable only directly when in Secure Mode. EMUOVR can be written to a 0 at any time. This means if you are in Secure Mode and wish to remove the privilege of emulation override, you are allowed to clear EMUOVR. Or if you are operating in Open Mode and wish to remove emulation override, you can clear EMUOVR. In the case of Secure Entry Mode, writing the EMUOVR bit to a 0 immediately blocks emulation (and the EMUDABL bit would read 0 immediately). While Operating in Secure Entry Mode, the value of EMUDABL is the not of EMUOVR, i.e., EMUDABL = ~EMUOVR. While operating in Secure Mode, you can read or write the ADSP-BF52x Blackfin Processor Hardware Reference 16-29 bit, which has no immediate affect since EMUDABL is in control at that point. EMUOVR Upon setting EMUDABL = 0 and EMUOVR = 1, JTAG emulation remains active and enabled for the current session during Secure Mode operation and for all subsequent entries into Secure Mode until EMUOVR is cleared (set to 0) or until RESET or power cycle clears this setting. This is also known as “sticky” emulation setting. If “sticky” emulation is enabled (EMUDABL = 0 and EMUOVR = 1), JTAG emulation is active and enabled in all modes, that is, Secure Entry, Secure Mode, as well as Open Mode. The Secure State Machine can cycle through all modes of operation, and JTAG emulation will remain active and enabled in every mode with these settings in place until cleared by the user application code, or until RESET or power cycle clears the setting. For example, a user creates code to be authenticated with a valid digital signature. The code and digital signature are loaded onto the Blackfin processor in Open Mode, Authentication is requested (JTAG emulation is disabled by default during Authentication in Secure Entry Mode), and the Authentication process is successful. The processor enters Secure Mode (JTAG emulation still is disabled by default) and control is given to the authenticated code. Authenticated code sets bits within the Secure System Switches to enable JTAG Emulation and sets the “sticky” bit to allow JTAG emulation to be enabled by default the next time the processor transitions into Secure Mode as well. Debug within Secure Mode can occur using emulation now. If a different set of trusted code must be loaded into the processor, the user can do so now without leaving Secure Mode, or the user can choose to exit Secure Mode and return back to Open Mode in order to authenticate another set of code or load test/problematic code. A new set of code and digital signature now can be loaded and authenticated. Upon entry into Secure Mode, JTAG emulation will be enabled by default due to the sticky bit setting in the Secure System Switches. Debug can be performed within Secure Mode without changes to problematic code. 16-30 ADSP-BF52x Blackfin Processor Hardware Reference One possible usage scenario for persistent (sticky) emulation might be as follows: a “final” production code that must run in Secure Mode is prepared. There seems to be an issue with the code, but emulation prevents working with it. You would take advantage of the EMUOVR bit within the SECURE_SYSSWT register by first performing a simple authentication of code that sets the EMUOVR bit in order to enable JTAG emulation within Secure Mode. From there you exit Secure Mode (write a value of “1” to the SECURE0 bit in the SECURE_CONTROL register, but do not invoke any processor reset), and call the routine to debug. You would then set a breakpoint just after authentication. That way you can now step through your code using JTAG emulation and operate in Secure Mode. enables Digitally signed user code, whichtreated aseither single session or in sticky JTAG emulation, must be confidential by users the same manner as private keys. If this code is allowed to fall outside of developer control or become public, it can be used to compromise a developer’s security. In summation, to enable JTAG emulation during Secure Mode, the user must successfully perform the Authentication process at least one time, and then program the Secured System Switches while operating in Secure Mode to enable emulation. P rogramming Examples Listing 16-1. Assembly Code – Enable (“Sticky”) Persistent JTAG Emulation for Secure Mode Debug #include <defBF527.h> .section L1_code; .align 4; .global _secure_function; _secure_function: /* required nops to account for SESR PC vector target+4 for overlay ID accommodation*/ ADSP-BF52x Blackfin Processor Hardware Reference 16-31 nop; nop; P0.H = ((SECURE_SYSSWT) >> 16); P0.L = ((SECURE_SYSSWT) & 0xFFFF); R0 = [P0]; BITCLR(R0,0); [P0] = R0; SSYNC; _secure_function .END: Listing 16-2. C Code – Enable JTAG Emulation for Secure Mode Debug (single session) #include <cdefBF527.h> #define ENABLE_JTAG_MASK 0xFFFFFFFE void secure_function(void) { /* Enable JTAG */ *pSECURE_SYSSWT = ( *pSECURE_SYSSWT & ENABLE_JTAG_MASK ); ssync(); return; } Programming Model Secure Entry Service Routine (SESR) API This section describes the procedure to use Lockbox to authenticate a message. Memory configuration, input arguments and return codes are also described here. 16-32 ADSP-BF52x Blackfin Processor Hardware Reference In this chapter, the term “message” was widely used to describe the entity being digitally signed off-chip, and later authenticated on-chip by the SESR security firmware. “Message”, “secure function” (SF), and “secure application” are used interchangeably in this section and mean the same thing. S tarting Authentication For an application to establish trust and reach the privileged mode of operation (for example, enter Secure Mode), the Secure State Machine has to transition from Open Mode, through Secure Entry Mode, to Secure Mode. In order to transition from Open Mode to Secure Entry Mode, NMI must be asserted and the program counter (PC) must vector to the beginning address of the firmware (SESR) at location 0xFFA1 4000. This can be achieved by loading the beginning address of the SESR (0xFFA1 4000) as the NMI handler in the event vector table (EVT2). Then in supervisor mode, issue a raise 2; instruction. Similarly, NMI hardware pin may be asserted instead of issuing a software raise; instruction. Once the program counter vectors to the SESR, while NMI assertion is sensed by the hardware, the Secure State Machine transitions into Secure Entry Mode. Before actually going into Secure Entry Mode, the user will have to set up the memory environment. This includes specifying the arguments (described in this section) and moving the message to be authenticated into L1 data memory. ADSP-BF52x Blackfin Processor Hardware Reference 16-33 M emory Configuration Figure 16-3 illustrates the Secure Entry Mode default memory configuration upon initiating authentication and entering the SESR. 0xEF000000 0xFF800000 0xFF900000 Argument buffers for SF and SESR Data Content for SF (Optional) ECC Data buffers and variables. (Reserved) Boot Code Digital Signature Data variables and buffers used by authentication code (Reserved) 0xEF001000 Message (Code and optional data content to be authenticated, a.k.a. SF) Authentication code 0xFF901900 SHA-1 Data Content for SF (Optional) Elliptical Curve Cipher 0xFF804000 0xFF904000 OTP Access Library Unprotected User Data Boot ROM Unused/Protected 0xFF808000 0xFF908000 L1 Data Bank A L1 Data Bank B Figure 16-3. Memory Configuration for Authentication 16-34 ADSP-BF52x Blackfin Processor Hardware Reference M essage Placement The message must be placed in L1A for authentication. If the message (for example, code) is put into L1A for authentication, it must be DMA’d to L1 code space, where it can execute. It is the user’s responsibility to provide the message in L1A memory for the SESR. If authentication is successful, the SESR then moves the message via DMA to the final destination according to the SESR arguments. No further action is required by the developer to perform this DMA as it is executed by the firmware. Digital Signature The digital signature is a pair of 163-bit integers. Each integer is padded to the nearest 32-bit word, resulting in 192 bits for each integer, resulting in a total size of 384 bits. The authentication firmware always expects the digital signature to be followed by the message. For example, if the message is placed in L1A data memory, and the digital signature starts at address 0xFF80 0000, the message must immediately follow the digital signature and be located at address 0xFF80 0030. The message and digital signature must be stored together contiguously in memory with the message always immediately following the digital signature. Message Size Constraints The maximum size of any message to be authenticated is limited by the size of on-chip memory in the Blackfin processor. When the Secure State Machine enters into Secure Entry Mode (authentication), certain portions of on-chip SRAM memory are protected from DMA accesses. These protected memory regions include L1A (32 KB) and L1B data memory (8 KB each and 32 KB of L1 code memory). This means that the maximum allowable message/code size that can be authenticated is 32 KB less 48 bytes for the digital signature when placed in L1A data memory. ADSP-BF52x Blackfin Processor Hardware Reference 16-35 M emory Usage In data bank B of the L1 memory, the arguments for both the SESR and the secure function are stored beginning at address 0xFF90 0000. In addition, a portion of the L1B data memory is reserved for the firmware for scratch space. All memory above address 0xFF90 1900 is reserved for authentication. The user can either allocate this area of memory solely for Lockbox or save any data elsewhere in memory prior to starting authentication. user information residing in the scratch space reserved area AnyData Bank B will be overwritten during the authentication of L1 process. Memory Protection This Secure Entry Mode default memory configuration with both protected and unprotected regions of on-chip SRAM is implemented in order to allow developers to initiate digital signature authentication at any time during Open Mode processor operation. If an application is already running on the processor, the unprotected memory regions can be used for placement of data buffers. When authentication occurs, access to these data buffers is not restricted, thus the application can be given higher precedence over the authentication process if necessary. The Secure Entry Mode default memory protection configuration put into place upon initiating authentication cannot be modified by the developer. This is to ensure integrity of the secure processing environment during the authentication process and help prevent malicious tampering. Secure Function and Secure Entry Service Routine Arguments Prior to initiating the authentication, the arguments for both the SESR and the message (also known as Secure Function or SF) must be set up. 16-36 ADSP-BF52x Blackfin Processor Hardware Reference The arguments are stored in argument buffers stored in L1B data memory. Specifically, the arguments for the Secure Function are stored at the top of L1B data memory, at address 0xFF90 0000. There are 24 bytes allocated for the arguments for the secure function. Following the argument buffer for the Secure Function is the argument buffer for the SESR, at address 0xFF90 0018. For security reasons this authentication protocol accesses fixed locations for arguments. When the user starts executing the Secure Function, it receives two arguments. The first argument (R0) contains the address of the Secure Function argument buffer. The second argument (R1) holds the IMASK value before shut off interrupts. Secure Function Arguments When the message is successfully authenticated, the Program Counter will vector to the Secure Function with the first argument (R0) containing a pointer to top of L1B data memory. The second argument (R1) of the secure function is the IMASK value. This value is obtained when the SESR successfully authenticates the message. Before the message is transferred via DMA to its final target run location, interrupts are shut off so tampering cannot occur between the time of successful authentication and execution of the secure function. The prototype for the secure function is: void secure_function(tSecureFunctionArgs *, unsigned short imask); The 24-byte Secure Function argument buffer is for the convenience of the user to be able to pass arguments to the Secure Function prior to starting authentication. It is the responsibility of the user’s Secure Function to re-enable interrupts by using the saved IMASK value or by using a new IMASK value. The 24-byte Secure Function argument buffer can be used in any aligned fashion. For example, it can be used to store six 32-bit words or twelve 16-bit words, or any combination of data types such as integers, shorts and characters, as long as the accesses are aligned. ADSP-BF52x Blackfin Processor Hardware Reference 16-37 S ecure Entry Service Routine Arguments The argument buffer for the SESR is shown in Listing 16-3. Listing 16-3. Argument Buffer for SESR /* SESR argument structure. Expected to reside at address 0xFF900018 */ typedef struct SESR_args { unsigned short usFlags;/* security firmware flags*/ unsigned short usIRQMask;/* interrupt mask*/ unsigned long ulMessageSize;/* message length in bytes*/ unsigned long ulSFEntryPoint;/* entry point of secure function*/ unsigned long ulMessagePtr;/* pointer to the buffer containing the digital signature and message */ unsigned long ulReserved1;/* reserved*/ unsigned long ulReserved2;/* reserved*/ } tSESR_args; usFlags The first argument, usFlags, is a 16-bit flag that signals authentication what to do. Figure Figure 16-4 shows the meaning of the bits. Bit 0 tells the authentication firmware whether or not to drop the interrupt level. To execute raise 2;, the Blackfin processor must operate in supervisor mode, in other words, operate at one of the interrupt levels. NMI must be asserted when authentication is initiated. The caller/user has the option to deassert NMI and drop back down to a lower interrupt 16-38 ADSP-BF52x Blackfin Processor Hardware Reference level (the interrupt level in effect when NMI was asserted to initiate authentication) or continue authentication at NMI level. 15 14 13 12 11 10 x x x x x x 9 8 7 6 5 x x x x x 4 x0 3 2 1 0 x x x x Reserved Public Key Index 0 - ADI key 1 - Customer Key Reduce Execution Level (REL) 0 - Continue execution at NMI level 1 - Drop execution level Reserved Reserved Figure 16-4. Bit Fields for Flags Argument By lowering the interrupt level at which the authentication firmware executes, other interrupts can be serviced. Be aware that if another interrupt is serviced and the PC vectors out of the authentication firmware during authentication, the authentication process fails and returns an error code. Bit 8 tells the firmware which public key is used for authentication. The OTP memory holds two public keys. One is programmed by Analog Devices for failure analysis purposes only, and the other is programmed by the developer. uslRQMask The usIRQMask argument is a 16-bit user-defined bitmask to be loaded into the lower 16 bits of the IMASK MMR if the execution level is to be lowered from NMI level. This argument allows the user to specify which, if any, interrupts will be allowed to be serviced should they occur during the time authentication occurs. Note that if any interrupt is serviced, the authentication process fails and returns an error code as mentioned above. ADSP-BF52x Blackfin Processor Hardware Reference 16-39 For more information regarding IMASK, please refer to the Blackfin Processor Programming Reference manual. ulMessageSize The ulMessageSize argument is a 32-bit non-negative integer that tells the SESR how big the message is, in bytes. The ulMessageSize must be a multiple of two, otherwise the SESR returns an error code. ulSFEntryPoint The ulSFEntryPoint argument is the final address that the message will be moved to and executed from L1 Instruction memory. Again, since the authentication firmware expects code as the first portion of the message, the address must be a multiple of four since instructions can be either 16-bit or 32-bit lengths. If the message consists of both code and data, it is the user’s responsibility to move the data to the proper area of data memory for subsequent use within the application. ulMessagePtr The ulMessagePtr argument holds the address where the digital signature and message are found in L1 Data memory. Secure Message Execution If the authentication of the digital signature is successful, the authentication firmware directly vectors the program counter to the Secure Function at its final target location, plus an offset of four bytes. The offset provides a location for the overlay ID if overlays are used with Lockbox. To return to the calling function, the authenticated message must execute rtn; if execution level was not signaled to be lowered in the authentication firmware. Otherwise, if the execution level was lowered, the Secure Function can return via rts;. 16-40 ADSP-BF52x Blackfin Processor Hardware Reference To prevent tampering, interrupts and the watchdog timer are shut off near the end of successful authentication. It is the user’s responsibility to re-enable the interrupts and the watchdog timer in the Secure Function if they are required in the user’s application while operating in Secure Mode. Return Codes If for any reason an error occurs, the SESR returns an error code, and bit 7 in the SECURE_STAT MMR sets to indicate that register R0 contains a valid error code. Table 16-2 lists a portion of the valid return codes. Table 16-2. List of Return Codes from SESR Return Codes Value Description SECFW_SUCCESS 0 Success SECFW_ERROR_INV_FLAGS –1 “Flags” argument to firmware is invalid SECFW_ERROR_INV_INTMASK –2 IRQ mask specified is invalid SECFW_ERROR_INV_CODESZ –3 Code size specified is either non-positive or odd SECFW_ERROR_OOB_CODE –6 The message (Secure function) is too big and surpasses the protected region in L1A SECFW_ERROR_BAD_EVT –10 One of the ISR specified in the Event Vector table points inside the authentication firmware. SECFW_ERROR_PUBKEY_ZERO –11 Invalid public key of (0,0) SECFW_ERROR_AUTH_FAILED –12 Invalid message/signature pair SECFW_ERROR_DMA –15 MDMA error occurred during DMA transfer or the message to the final target vector. SECFW_ERROR_DROPPING_INT_FAILED –17 Could not drop interrupt level from NMI. SECFW_ERROR_FUSE_READ_FAILED –18 Error occurred while reading OTP memory. ADSP-BF52x Blackfin Processor Hardware Reference 16-41 Table 16-2. List of Return Codes from SESR (Continued) Return Codes Value Description SECFW_ERROR_TGTVECT_NONALIGNED –19 Target vector is not 4 Byte aligned. SECFW_ERROR_SECURE0_WRITE_FAILED –20 Write to Secure0 bit failed. Secure State Machine might be blocking the write because ISR was taken. SECFW_ERROR_SM_NOT_ENTERED –21 Secure0 bit was written three times but secure mode was still not entered. SECFW_ERROR_BAD_TGT_ADDR –22 Target vector must be in L1 code space. SECFW_ERROR_SF_TOO_BIG –23 Message (Secure function) too big to fit at target location. In addition to the return codes listed in Table 16-2, a return value between –62 and –252 is also a valid error return code. These errors are from OTP accesses. To decipher the error from an OTP access, there is an offset that must be added to the error code. The macro OTP_READ_ERROR_OFFSET (defined in VisualDSP++ header files with a value of –285) is added to the return 16-42 ADSP-BF52x Blackfin Processor Hardware Reference value. The result is a bit mask. Figure 16-5 shows the definition of the bit fields. 7 6 5 0 4 3 2 1 0 OTP Read Error Where OTP error occurred 1 - Page 1 - low half 2 - Page 1 - high half 3 - Page 2 - low half 4 - Page 2 - high half 5 - Page 3 - low half 6 - Page 3 - high half Attempt to access invalid OTP space Double bit error detected Hamming Code Syndrome error ECC firmware error Figure 16-5. Bit Field Definition Return Value if OTP Error Occurred Secure Hash Algorithm (SHA-1) API The ADSP-BF52x processor includes a software implementation of the Secure Hash Algorithm (SHA-1) in the on-chip boot ROM. This implementation of the SHA-1 hash algorithm is C-callable. The following describes the application programming interface (API) for using SHA-1, including both data types and ROM routines. ADI_SHA1 Data Type typedef struct ADI_SHA1 { u8 *pInputMessage; u32 udMessageSize; u8 *pOutputDigest; u8 *pScratchBuffer; } ADI_SHA1; ADSP-BF52x Blackfin Processor Hardware Reference 16-43 The SHA1 hash routine, bfrom_Sha1Hash, when provided with a reference to an object of type ADI_SHA1, hashes the udMessageSize-long message referenced by pInputMessage, and stores the hash value (also referred to as message digest) in the buffer referenced by pOutputDigest. The elements in an object of type ADI_SHA1, are shown in Table 16-3. Table 16-3. Elements in an Object of Type ADI_SHA1 pInputMessage Pointer to the input buffer udMessageSize The size, in bytes, of the valid input data in pInputMessage. pOutputDigest Pinter to the output data buffer. After hashing, this buffer will contain the digest of the input message. The digest is 160-bits (SHA1_HASH_SIZE-bytes) long pScratchBuffer Pointer to a data buffer of size, SHA1_SCRATCH_BUFFER_SIZE-bytes, used by the SHA-1 module. bfrom_Sha1Init ROM Routine Entry address: Defined as BFROM_SHA1_INIT in the bfrom.h header file in the VisualDSP++ installation directory. Arguments: R0: Pointer to a buffer of size SHA1_SCRATCH_BUFFER_SIZE C prototype: void bfrom_Sha1Init (u8 *pScratchBuffer); This function initializes some data elements in pScratchBuffer. It is called first before making any calls to bfrom_Sha1Hash. bfrom_Sha1Hash ROM Routine Entry address: Defined as BFROM_SHA1_HASH in the bfrom.h header file in the VisualDSP++ installation directory. Arguments: 16-44 ADSP-BF52x Blackfin Processor Hardware Reference R0: Pointer to an object of type ADI_SHA1 C prototype: void bfrom_Sha1Hash (ADI_SHA1 *pSha1); This function performs the hash operation. Security Registers There are three registers for security mode control and status of the Secure State Machine states. These registers require privileged access depending upon the operating state of the processor. Table 16-4. Security Registers Register Description Size (Bits) Memory-Mapped Address SECURE_SYSSWT Secure System Switches 32 0xFFC03620 SECURE_CONTROL Secure Control 16 0xFFC03624 SECURE_STATUS Secure Status 16 0xFFC03628 ADSP-BF52x Blackfin Processor Hardware Reference 16-45 S ecure System Switch (SECURE_SYSSWT) Register The SECURE_SYSSWT register controls hardware that would otherwise allow a threat of attack to a secured system. Hardware is controlled voluntarily and involuntarily as follows. • During Open Mode the switches are involuntarily set with all controls off (unrestricted access, with exception of access to OTP protected “secrets” area). OTP secrets are always protected and can only be accessed upon entry into Secure Mode. • During Secure Entry Mode all switches are initially set with all controls on (restricted access) Two exceptions are the OTP secrets control (OTPSEN bit) is not accessible so access to the secrets OTP area remains restricted, and the RSTDABL bit remains deactivated (External Reset is allowed). • During Secure Mode operation all switches are voluntary (initially set) and under the control of authenticated code. Therefore, restricted access controls can be reconfigured by authenticated user code. This includes the activation of Reset Disable (RSTDABL) bit. The register, shown in Figure 16-6 and Figure 16-7 on page 16-48, is 32-bits wide and requires 32-bit access. Limited write access to a few bits 16-46 ADSP-BF52x Blackfin Processor Hardware Reference is allowed in Secure Entry mode, and full write access to all bits is allowed in Secure mode. No write access is allowed in Open Mode. Secure System Switch Register (SECURE_SYSSWT) Bits 15:0 15 14 13 12 11 10 0xFFC03620 0 0 0 0 0 0 9 0 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset = 0x0000 OTPSEN 0 - Disable 1 - Enable EMUDABL 0 - JTAG instructions executed 1 - JTAG instructions ignored EMUOVR 0 - EMUDABL bit is set 1 - EMUDABL bit is cleared RSTDABL 0 - External Resets generated 1 - External Resets redirected to NMI pin RESERVED DMA0OVR 0 - DMA0 accesses restricted by Memory Disable settings 1 - Unrestricted DMA0 accesses in all memory areas L1DBDABL 000 - All DMA accesses allowed 001 - 1K byte of memory has restricted non-core access 010 - 2K byte of memory has restricted non-core access 011 - 4K byte of memory has restricted non-core access 100 - 8K byte of memory has restricted non-core access 101 - 16K byte of memory has restricted non-core access 110 - 32K byte of memory has restricted DMA access 111 - Reserved L1IDABL 000 - All DMA accesses allowed 001 - 1K byte of memory restricted non-core access 010 - 2K byte of memory restricted non-core access 011 - 4K byte of memory restricted non-core access 100 - 8K byte of memory restricted non-core access 101 - 16K byte of memory restricted non-core access 110 - 32K byte of memory restricted DMA access 111 - Invalid (32K restricted access) L1DADABL 000 - All DMA accesses allowed 001 - 1K byte of memory has restricted non-core access 010 - 2K byte of memory has restricted non-core access 011 - 4K byte of memory has restricted non-core access 100 - 8K byte of memory has restricted non-core access 101 - 16K byte of memory has restricted non-core access 110 - 32K byte of memory has restricted DMA access 111 - Reserved Figure 16-6. Secure System Switch Register, Bits 15:0 ADSP-BF52x Blackfin Processor Hardware Reference 16-47 Secure System Switch Register (SECURE_SYSSWT) Bits 31:16 31 30 29 28 27 26 0xFFC03620 0 0 0 0 0 0 25 24 23 22 21 20 19 18 17 16 0 0 000 00000 Reset = 0x0000 Reserved Figure 16-7. Secure System Switch Register, Bits 31:16 Table 16-5. Secure System Switch Register Bit Position Bit Name Bit Description Reset = 0x0000 Secured Entry = 0x0007 04D9 Secure Mode = 0x0007 04DB 0 EMUDABL Emulation Disable. Upon Secured Entry the EMUDABL setting is based on the previous state of EMUOVR. Upon re-entering Open Mode, EMUDABL is cleared. This bit is always read accessible. This bit is write accessible only in Secure Mode. 0 - Analog Devices JTAG emulation instructions are recognized and executed. Once this bit is cleared while in Secure Mode it will not be set upon Secured Entry. This condition will remain until reset, at which time it is cleared. This feature is used in security debug. 1 - Analog Devices JTAG emulation instructions are ignored. Standard emulation commands such as bypass are allowed. 1 RSTDABL Reset Disable. This bit is not effected upon Secured Entry. This bit is set upon entering Secure Mode. Upon re-entering Open Mode, RSTDABL is cleared. This bit is always read accessible. This bit is write accessible only in Secure Mode. 0 - External Resets are generated and serviced normally. 1 - External Resets are redirected to the NMI pin. This avoids circumventing memory clean operations. 16-48 ADSP-BF52x Blackfin Processor Hardware Reference Table 16-5. Secure System Switch Register (Continued) Bit Position Bit Name Bit Description 4:2 L1IDABL L1 Instruction Memory Disable. Upon Secured Entry L1IDABL is set to 0x6. Upon re-entering Unsecure Mode, L1IDABL is cleared. These bits are always read accessible. These bits are write accessible only in Secure Mode. In the event a DMA access is performed to a restricted memory area a DMA memory access error will occur resulting in a DMA_ERR interrupt and a clearing of DMA_RUN. 000 - All DMA accesses are allowed to L1 Instruction areas. 001 - 1K byte of memory (0xFFA0 0000 - 0xFFA0 03FF) has restricted non core access 010 - 2K byte of memory (0xFFA0 0000 - 0xFFA0 07FF) has restricted non core access 011 - 4K byte of memory (0xFFA0 0000 - 0xFFA0 0FFF) has restricted non core access 100 - 8K byte of memory (0xFFA0 0000 - 0xFFA0 1FFF) has restricted non core access 101 - 16K byte of memory (0xFFA0 0000 - 0xFFA0 3FFF) has restricted non core access 110 - 32K byte of memory (0xFFA0 0000 - 0xFFA0 7FFF) has restricted DMA access. This is the initial setting upon entering Secured Entry. 111 - Reserved ADSP-BF52x Blackfin Processor Hardware Reference 16-49 Table 16-5. Secure System Switch Register (Continued) Bit Position Bit Name Bit Description 7:5 16-50 L1DADABL L1 Data Bank A Memory Disable. Upon Secured Entry L1DADABL is set to 0x6. Upon re-entering Open Mode, L1DADABL is cleared. These bits are always read accessible. These bits are write accessible only in Secure Mode. In the event a DMA access is performed to a restricted memory area a DMA memory access error will occur resulting in a DMA_ERR interrupt and a clearing of DMA_RUN. 000 - All DMA accesses are allowed to L1 data bank A areas. 001 - 1K byte of memory (0xFF80 0000 - 0xFF80 03FF) has restricted non core access 010 - 2K byte of memory (0xFF80 0000 - 0xFF80 07FF) has restricted non core access 011 - 4K byte of memory (0xFF80 0000 - 0xFF80 0FFF) has restricted non core access 100 - 8K byte of memory (0xFF80 0000 - 0xFF80 1FFF) has restricted non core access 101 - 16K byte of memory (0xFF80 0000 - 0xFF80 3FFF) has restricted non core access 110 - 32K byte of memory (0xFF80 0000 - 0xFF80 7FFF) has restricted DMA access. This is the initial setting upon entering Secured Entry. 111 - Reserved ADSP-BF52x Blackfin Processor Hardware Reference Table 16-5. Secure System Switch Register (Continued) Bit Position Bit Name Bit Description 10:8 L1DBDABL L1 Data Bank B Memory Disable. Upon Secured Entry L1DBDABL is set to 0x4 giving L1 Data Bank B 8 Kbyte of non core restricted access. Upon re-entering Open Mode, L1DBDABL is cleared. These bits are always read accessible. These bits are write accessible only in Secure Mode. In the event a DMA access is performed to a restricted memory area a DMA memory access error will occur resulting in a DMA_ERR interrupt and a clearing of DMA_RUN. 000 - All DMA accesses are allowed to L1 data bank B areas. This is the initial setting upon entering Secured Entry. 001 - 1K byte of memory (0xFF90 0000 - 0xFF90 03FF) has restricted non core access 010 - 2K byte of memory (0xFF90 0000 - 0xFF90 07FF) has restricted non core access 011 - 4K byte of memory (0xFF90 0000 - 0xFF90 0FFF) has restricted non core access 100 - 8K byte of memory (0xFF90 0000 - 0xFF90 1FFF) has restricted non core access. This is the initial setting upon entering Secured Entry. 101 - 16K byte of memory (0xFF90 0000 - 0xFF90 3FFF) has restricted non core access 110 - 32K byte of memory (0xFF90 0000 - 0xFF90 7FFF) has restricted DMA access. 111 - Reserved 11 DMA0OVR DMA0 Memory Access Override Entering Secured Entry or Secure Mode does not effect this bit. Upon re-entering Open Mode, DMA0OVR is cleared. This bit is always read accessible. This bit is write accessible in both Secured Entry and Secure Mode. Controls DMA0 access to L1 Instruction, L1 Data and memory other than L1 regions. When clear access restrictions are based on Memory Disable settings within this register. 0 - DMA0 accesses are restricted based on Memory Disable settings. 1 - Unrestricted DMA0 accesses are allowed to all memory areas. 12 Reserved Reserved bit. This reserved bit always returns a “0” value on a read access. Writing this bit with any value has no effect. 13 Reserved Reserved bit. This reserved bit always returns a “0” value on a read access. Writing this bit with any value has no effect. ADSP-BF52x Blackfin Processor Hardware Reference 16-51 Table 16-5. Secure System Switch Register (Continued) Bit Position Bit Name Bit Description 14 EMUOVR Emulation Override This bit is always read accessible. This bit may be written with a 1 in Secure Mode only. This bit can be cleared in any mode (Open Mode, Secured Entry and Secure mode). Controls the value of EMUDABL upon Secured Entry. 0 - Upon Secured Entry the EMUDABL bit is set. 1 - Upon Secured Entry the EMUDABL bit is cleared. This bit can only be set when EMUDABL (bit-0) is written with a “0” while this bit (bit-14) is simultaneously written with a 1. 15 OTPSEN OTP Secrets Enable. This bit can be read in all modes but is write accessible in Secure Mode only. 0 - Read and Programming access of the “secured” OTP Fuse area is restricted. Accesses will result in an access error (FERROR) 1 - Read and Programming access of the “secured” OTP Fuse area is allowed. If the corresponding program protection bit for an access is set, a program access is protected regardless of this bit's setting. 31:16 Reserved Reserved. To ensure upward compatibility with future implementations, write back the value that is read from these bits. S ecure Control (SECURE_CONTROL) Register The SECURE_CONTROL register is used during Secure Entry Mode authentication. This register is used to establish Secure Mode transition and can be 16-52 ADSP-BF52x Blackfin Processor Hardware Reference used at any time to exit from Secure Mode. The register, shown in Figure 16-8, is 16-bits wide and requires 16-bit access. Secure Control Register (SECURE_CONTROL) 15 14 13 12 11 10 0xFFC03624 0 0 0 0 0 0 9 0 8 0 7 6 0 0 5 0 4 3 2 1 0 0 0 0 0 0 Reserved Reset = 0x0000 S ECURE0 This is a write only bit. 0 - All SECURE bits are cleared. 1 - Initial 1 sets SECURE1 bit. Next 1 sets SECURE2 bit. Next 1 sets SECUE2 bit. S ECURE1 This is a read-only bit. 0 - SECURE0 has not been written with a 1 1 - SECURE0 is written with a 1 S ECURE2 This is a read-only bit. 0 - SECURE0 has not been written with a 1 while SECURE1 is set. 1 - SECURE0 is written with a 1 for a second time S ECURE3 This is a read-only bit. 0 - SECURE0 has not been written with a 1 while SECURE2 is set. 1 - SECURE0 is written with a 1 for a third time Figure 16-8. Secure Control Register ADSP-BF52x Blackfin Processor Hardware Reference 16-53 Table 16-6. Secure Control Register Bit Position Bit Name Bit Description Reset = 0x0000 0 SECURE0 SECURE 0 This is a write only bit. A read always returns “0”. A 1 value can only be written to SECURE0 when in Secured Entry. The purpose of this control bit is to require 3 successive writes with a value of 1 to SECURE0 in order to enter Secure Mode. 0 - When written with a “0” value, all SECURE bits within this register are cleared and Open Mode is entered. All SYSSWT bits are cleared with the exception of EMUOVR. If EMUOVR had been set by the user, it will remain set (until RESET is asserted or until it is written with a “0”). 1 - Initially when written with a 1 value SECURE1 is set. With a subsequent 1 written SECURE2 is set. A subsequent 1 written will set SECURE3. Upon a set of SECURE3 Secure Mode is entered. 1 SECURE1 SECURE 1 This is a read-only bit and indicates a successful write of SECURE0 with a data value of 1 0 - SECURE0 has not been written with a 1 value 1 - SECURE0 is written with a 1 value 2 SECURE2 SECURE 2 This is a read-only bit and indicates two successful writes of SECURE0 with a data value of 1 has occurred 0 - SECURE0 has not been written with a 1 value while SECURE1 was set. 1 - SECURE0 is written with a 1 value for a second time. 3 SECURE3 SECURE 3 This is a read-only bit and indicates three successful writes of SECURE0 with a data value of 1 has occurred. 0 - SECURE0 has not been written with a 1 value while SECURE2 was set 1 - SECURE0 is written with a 1 value for a third time. The part is currently in Secure Mode and the SYSSWT register is writable by Authenticated code. 16-54 ADSP-BF52x Blackfin Processor Hardware Reference bit is user accessible and is used to exit from Secure Mode. Bits SECURE1, SECURE2, and SECURE3 are not user accessible and are accessed only by the firmware during the digital signature validation process. SECURE0 Secure Status (SECURE_STATUS) Register The SECURE_STATUS register provides information about the current secure state. This information can be used during security mode control as well ADSP-BF52x Blackfin Processor Hardware Reference 16-55 as understanding why an authentication attempt has failed. The register, shown in Figure 16-9, is 16-bits wide and requires 16-bit access. Secure Status Register (SECURE_STATUS) 15 14 13 12 11 10 0xFFC03628 0 0 0 0 0 0 9 0 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset = 0x0000 SECMODE 00 - Open Mode 01 - Secured Entry 10 - Secure Mode 11 - Illegal Reserved NMI 0 - Currently NMI is not detected 1 - Currently NMI is detected AFVALID 0 - Authentication has not begun properly or is interrupted 1 - Authentication is valid AFEXIT 0 - No improper exit is made 1 - An improper exit is made SECSTAT 000 - Reset value 001 - Reserved 010 - Reserved 011 - Reserved 100 - Reserved 101 - Reserved 110 - Reserved 111 - Reserved Figure 16-9. Secure Status Register 16-56 ADSP-BF52x Blackfin Processor Hardware Reference Table 16-7. Secure Status Register Bit Position Bit Name Bit Description Reset = 0x0000 1:0 SECMODE Secure Mode Control State These are read-only bits that reflects the current Secure Mode Control's state. 00 - Open Mode 01 - Secured Entry 10 - Secure Mode 11 - Illegal 2 NMI This is a read-only bit that reflects the detection of NMI. 0 - Currently NMI is not detected. 1 - Currently NMI is detected. 3 AFVALID Authentication Firmware Valid This is a read-only bit that reflects the state of the hardware monitor logic. If execution of authentication has begun properly and has had uninterrupted operation the authentication is considered valid. A valid authentication is required for Secured Entry and Secure Mode operation. 0 - Authentication has not begun properly or is interrupted. 1 - Authentication is valid and is progressing properly and uninterrupted. 4 AFEXIT Authentication Firmware Exit This is a write one to clear status bit. In the event authentication has begun properly but has had an improper exit before completion, this bit is set. This can only occur on an exit from Secured Entry back to Open Mode. 0 - No improper exit is made while executing authentication firmware. 1 - An improper exit from authentication firmware is made. 7:5 SECSTAT Secure Status These are some read write bits which is defined later. These are intended to pass a status back to the handler in the event an authentication has failed. 000 - Reset value 001 - Reserved 010 - Reserved 011 - Reserved 100 - Reserved 101 - Reserved 110 - Reserved 111 - Reserved ADSP-BF52x Blackfin Processor Hardware Reference 16-57 Firmware ) is an Secure Authenticationand not anValid ( control/status.input to theoes State Machine output g AFVALID AFVALID active based on reaching the correct program counter address. 16-58 ADSP-BF52x Blackfin Processor Hardware Reference 1 7 SYSTEM RESET AND BOOTING This document contains material that is subject to change without notice. The content of the boot ROM as well as hardware behavior may change across silicon revisions. See the anomaly list for differences between silicon revisions. Overview When the RESET input signal releases, the processor starts fetching and executing instructions from the on-chip boot ROM at address 0xEF00 0000. The internal boot ROM includes a small boot kernel that loads application data from an external memory or host device. The application data is expected to be available in a well-defined format called the boot stream. A boot stream consists of multiple blocks of data and special commands that instruct the boot kernel how to initialize on-chip L1 memories as well as off-chip volatile memories. The boot kernel processes the boot stream block-by-block until it is instructed by a special command to terminate the procedure and jump to the application’s programmable start address, which traditionally is at 0xFFA0 0000 in on-chip L1 memory. This process is called “booting.” The processor features four dedicated input pins BMODE[3:0] that select the booting mode. The boot kernel evaluates the BMODE pins and performs ADSP-BF52x Blackfin Processor Hardware Reference 17-1 booting from respective sources. Table 17-1 describes the modes of the BMODE pins. Table 17-1. Booting Modes BMODE[3:0] Boot Source Description 0000 No boot – idle The processor does not boot. Rather, the boot kernel executes an IDLE instruction. 0001 Boot from 8-bit or 16-bit external flash memory The kernel boots from address 0x2000 0000 in asynchronous memory bank 0. The first byte of the boot stream contains further instructions whether the memory is eight or 16 bits wide. 0010 Boot from 16-bit asynchronous FIFO By using the handshaked memory DMA (HMDMA1) feature through the DMAR1 input, the kernel boots from address 0x2030 0000 in asynchronous memory bank 3. 0011 Boot from serial SPI memory After an initial device detection routine, the kernel boots from either 8-bit, 16-bit, 24-bit or 32-bit addressable SPI flash or EEPROM memory that connects to SPI_SEL1. 0100 Boot from SPI host In this slave mode, the kernel expects the boot stream to be applied to SPI by an external host device. 0101 Boot from serial TWI memory The kernel boots from TWI memory connected to TWI. Memory is expected to respond to the unique slave identifier of 0xA0. 0110 Boot from TWI host In this slave mode, the kernel expects the boot stream to be applied to TWI by an external host device. The Blackfin processor uses the slave identifier 0x5F. 17-2 ADSP-BF52x Blackfin Processor Hardware Reference Table 17-1. Booting Modes (Continued) BMODE[3:0] Boot Source Description 0111 Boot from UART0 host In this slave mode, the kernel expects the boot stream to be applied to UART0 by an external host device. Prior to providing the boot stream, the host device is expected to send a 0x40 (ASCII '@') character that is examined by the kernel to adjust the bit rate. 1000 Boot from UART1 host. Same as BMODE = 0111 but UART1 interface is used. 1001 Reserved 1010 Boot from SDRAM memory1 This mode provides a quick warm boot option. It requires the SDRAM controller to be programmed by the preboot routine based on OTP settings. The kernel starts booting from address 0x0000 0010. 1011 Boot from on-chip OTP memory This is the only stand-alone booting mode. It boots from the on-chip serial OTP memory. By default, the boot stream is expected to reside from OTP page 0x40 on. The start page can be altered by programming the OTP_START_PAGE field in OTP page PBS01H. 1100 Boot from 8-bit NAND flash using port F data interface. The boot kernel automatically detects whether an 8-bit small-page device or an 8-bit large-page device is connected to the NFC. The NAND flash may optionally contain further initialization code that enables some more advanced boot options. 1101 Boot from 8-bit NAND flash using the port H data interface. The boot kernel automatically detects whether an 8-bit small-page device or an 8-bit large-page device is connected to the NFC. The NAND flash may optionally contain further initialization code that enables some more advanced boot options. ADSP-BF52x Blackfin Processor Hardware Reference 17-3 Table 17-1. Booting Modes (Continued) BMODE[3:0] Boot Source Description 1110 Boot from 16-bit Host DMA The kernel initializes the Host DMA unit to 16-bit ACK mode. Boot stream parsing is up to the host device. An HIRQ command causes the kernel to issue a CALL to the address 0xFFA0 0000. 1111 Boot from 8-bit Host DMA The kernel initializes the Host DMA unit 8-bit INT mode. Boot stream parsing is up to the host device. An HIRQ command causes the kernel to issue a CALL to the address 0xFFA0 0000. 1 This chapter uses the term SDRAM as a synonym for off-chip synchronous dynamic memory. For the ADSP-BF522/523/524/525/526/527 products, this includes the Mobile SDRAM standard. R eset and Power-up There is a subroutine in the boot kernel known as "preboot", which is executed prior to the boot mode being processed. This preboot routine can customize default values of MMR registers, such as the PLL and SDRAM controller registers. Furthermore, the SPI and TWI master modes can be customized. The preboot behavior is controlled through OTP programming. To enable booting from volatile memories such as SDRAM, the SDRAM controller must be programmed before data can be loaded into the memory. Either the preboot or the initialization code mechanism can be used for this purpose. 17-4 ADSP-BF52x Blackfin Processor Hardware Reference Table 17-2 describes the six types of resets. Each type resets the core except for the System Software reset. Table 17-2. Resets Reset Source Result Hardware reset The RESET pin causes a hardware reset. Resets both the core and the peripherals, including the dynamic power management controller (DPMC). Resets bits [15:4] of the SYSCR register. For more information, see “System Reset Configuration (SYSCR) Register” on page 17-100. Wake up Wake-up event as enabled in the Behaves as hardware reset except the WURESET bit from hibernate VR_CTL register and reported by the in the SYSCR register is set. Booting can be perstate PLL_STAT register. formed conditionally on this event. System software reset Calling the bfrom_SysControl() routine with the SYSCTRL_SYSRESET option triggers a system reset. Resets only the peripherals, excluding the RTC (real time clock) block and most of the DPMC. The system software reset clears bits [15:13] and bits [11:4] of the SYSCR register, but not the WURESET bit. The core is not reset and a boot sequence is not triggered. Sequencing continues at the instruction after bfrom_SysControl() returns. Watchdog timer reset Programming the watchdog timer causes a watchdog timer reset. Resets both the core and the peripherals, excluding the RTC block and most of the DPMC. (Because of the partial reset to the DPMC, the watchdog timer reset is not functional when the processor is in Sleep or Deep Sleep modes.) The SWRST or the SYSCR register can be read to determine whether the reset source was the watchdog timer. ADSP-BF52x Blackfin Processor Hardware Reference 17-5 Table 17-2. Resets (Continued) Reset Source Result Core double-fault reset A core double fault occurs when an exception happens while the exception handler is executing. If the core enters a double-fault state, a reset can be caused by unmasking the DOUBLE_FAULT bit in the SWRST register. Resets both the core and the peripherals, excluding the RTC block and most of the DPMC. The SWRST or SYSCR registers can be read to determine whether the reset source was a core double-fault. Software reset This reset is caused by executing a Program executions vector to the 0xEF00 0000 RAISE 1 instruction or by setting address. The boot code executes an immediate the software reset (SYSRST) bit in system reset to ensure system consistency. the core debug control register (DBGCTL) through emulation software through the JTAG port. The DBGCTL register is not visible to the memory map. H ardware Reset The processor chip reset is an asynchronous reset event. The RESET input pin must be deasserted after a specified asserted hold time to perform a hardware reset. For more information, see the product data sheet. A hardware-initiated reset results in a system-wide reset that includes both core and peripherals. After the RESET pin is deasserted, the processor ensures that all asynchronous peripherals have recognized and completed a reset. After the reset, the processor transitions into the boot mode sequence configured by the state of the BMODE pins. The BMODE pins are dedicated mode control pins. No other functions are shared with these pins, and they may be permanently strapped by tying them directly to either VDDEXT or GND. The pins and the corresponding bits in the SYSCR register configure the boot mode that is employed after hardware reset or system software reset. See the Blackfin Processor Programming Reference for further information. 17-6 ADSP-BF52x Blackfin Processor Hardware Reference S oftware Resets A software reset may be initiated in three ways. • By the watchdog timer, if appropriately configured • Calling the bfrom_SysControl() API function residing in the on-chip ROM. For further information, see Chapter 18, “Dynamic Power Management”. • By the RAISE 1 instruction The watchdog timer resets both the core and the peripherals, as long as the processor is in Active or Full-On mode. A system software reset results in a reset of the peripherals without resetting the core and without initiating a booting sequence. In a system reset, ou tineorder tobeperformwhile executing the L1 memory (either ras must called from bfrom_SysControl() cache or as SRAM). When L1 instruction memory is configured as cache, make sure the system reset sequence is read into the cache. After either the watchdog or system software reset is initiated, the processor ensures that all asynchronous peripherals have recognized and completed a reset. For a reset generated by formatting the watchdog timer, the processor transitions into the boot mode sequence. The boot mode is configured by the state of the BMODE bit field in the SYSCR register. A software reset is initiated by executing the RAISE 1 instruction or setting the software reset (SYSRST) bit in the core debug control register (DBGCTL) (DBGCTL is not visible to the memory map) through emulation software through the JTAG port. A software reset only affects the state of the core. The boot kernel immediately issues a system reset to keep consistency with the system domain. ADSP-BF52x Blackfin Processor Hardware Reference 17-7 R eset Vector When reset releases, the processor starts fetching and executing instructions from address 0xEF00 0000. This is the address where the on-chip boot ROM resides. On a hardware reset, the boot kernel initializes the EVT1 register to 0xFFA0 0000. When the booting process completes, the boot kernel jumps to the location provided by the EVT1 vector register. With the exception of the HOSTDP boot modes, the content of the EVT1 register is overwritten by the TARGET ADDRESS field of the first block of the applied boot stream. If the BCODE field of the SYSCR register is set to 1 (no boot option), the EVT1 register is not modified by the boot kernel on software resets. Therefore, programs can control the reset vector for software resets through the EVT1 register. This process is illustrated by the flow chart in Figure 17-1. 17-8 ADSP-BF52x Blackfin Processor Hardware Reference The content of the EVT1 register may be undefined in emulator sessions. START at 0xEF00 0000 HARDWARE WAKEUP RESET ELSE Issue System Reset (SWRST = 0x0007) ELSE BCODE_QUICKBOOT BCODE PREPARE ALLBOOT (BFLAG_WAKEUP = 0) PREPARE QUICKBOOT (BFLAG_WAKEUP = 1) PREBOOT ELSE BCODE BOOT KERNEL BCODE_NOBOOT JUMP TO EVT1 VECTOR Figure 17-1. Global Boot Flow ADSP-BF52x Blackfin Processor Hardware Reference 17-9 S ervicing Reset Interrupts The processor services a reset event like other interrupts. The reset interrupt has top priority. Only emulation events have higher priority. When coming out of reset, the processor is in supervisor mode and has full access to all system resources. The boot kernel can be seen as part of the reset service routine. It runs at the top interrupt priority level. Even when the boot process has finished and the boot kernel passes control to the user application, the processor is still in the reset interrupt. To enter user mode, the reset service routine must initialize the RETI register and terminate with an RTI instruction. For a programming example, see “System Reset” on page 17-138. Listing 17-1 and Listing 17-2 on page 17-138 show code examples that handle the reset event. See the Blackfin Processor Programming Reference for details on user and supervisor modes. Systems that do not work in an operating system environment may not enter user mode. Typically, the interrupt level needs to be degraded down to IVG15. Listing 17-3 and Listing 17-4 on page 17-139 show how this is accomplished. running at reset interrupt priority, NMI Since the boot kernel is and exceptions are not serviced at boot events, hardware errors time. As soon as the reset service routine returns, the processor can service the events that occurred during the boot sequence. It is recommended that programs install NMI, hardware error, and exception handlers before leaving the reset service routine. This includes proper initialization of the respective event vector registers EVTx. 17-10 ADSP-BF52x Blackfin Processor Hardware Reference P reboot After reset, the boot kernel residing in the on-chip boot ROM does not immediately start processing the boot stream. First it calls a subroutine called preboot, as shown in Figure 17-2 on page 17-12 and Figure 17-3 on page 17-13. The preboot routine customizes the default values of several system MMR registers based on user-configurable OTP (one-time programmable) memory. The following modules can be customized in this way. • PLL and voltage regulator settings • SDRAM controller settings • Asynchronous EBIU settings Some OTP bits customize the boot process: • Bit rate of SPI and TWI master boot modes • TWI master boot addressing scheme • Activation of SPI fast read mode • Boot host wait (HWAIT) signal Further OTP bits let the user disable certain features of the processor: • Individual boot modes (for security reasons) Finally, certain bits are already preset in the factory: • USB voltage trim • Individual boot modes ADSP-BF52x Blackfin Processor Hardware Reference 17-11 PREBOOT N = 0x18 Load Page N < 0xDC N PBS00L NO VALID >= 0xDC IDLE N=N+4 YES ELSE BCODE BCODE_NORMAL or SYSCTRL_PLLCTL = OTP_SET_PLL BCODE_FULLBOOT SYSCTRL_PLLDIV = OTP_SET_PLL BMODE >0 pPS->uwPllCtl = OTP_PLL_CTL pPS->uwPllDiv = OTP_PLL_DIV 0 OTP_SET_VR 1 SYSCTRL_PLLCTL = 0 SYSCTRL_PLLDIV = 0 0 HARDWARE RESET WAKEUP SYSCTRL_OTPVOLTAGE = 1 SYSCTRL_VRCTL = 1 SYSCTRL_VR_CTL = OTP_SET_VR pPS->uwVrCtl = VRCTL pPS->uwVrCtl = OTP_VRCTL SYSCTRL_WRITE = 1 CALL SysControl () TO PREBOOT PAGE 2 Figure 17-2. Preboot Flow 1 of 2 17-12 ADSP-BF52x Blackfin Processor Hardware Reference FROM PREBOOT PAGE 1 HWAIT Initialization FPS01 Processing Save SPI and TWI Boot Instructions 1 LOAD_PBS01H BMODE 0 OR DISABLED IDLE VALID 0 Manage NFC and OTP boot start page 1 LOAD_PBS02L Initialize SDRAM Controller 0 1 LOAD_PBS00H Initialize Async Controller 0 RETURN TO MAIN Figure 17-3. Preboot Flow 2 of 2 ADSP-BF52x Blackfin Processor Hardware Reference 17-13 F actory Page Settings (FPS) The content of the boot ROM is identical across all ADSP-BF52x Blackfin processors. The factory settings prevent the boot ROM from accidentally accessing resources that are not present on a given processor, which would result in unpredictable behavior and/or hardware errors. The boot kernel goes to a safe idle state when the user configures the BMODE pins to a boot mode that is not available on a specific part. For this purpose, the preboot routine always reads the FPS01L and FPS01H half pages from OTP memory. These half pages contain factory trim values for the USB PHY controller that are managed at preboot time, as required. In addition, the bfrom_SysControl() routine reads the half page FPS04H to apply factory trim values to the voltage regulator. Preboot Page Settings (PBS) Four OTP pages optionally enable the user to customize the behavior of the processor immediately after reset. These four pages (eight half pages) can be seen as one contiguous pre-boot settings (PBS) block. By default, the block spans OTP pages 0x18 to 0x1B. The OTP pages serve the following purposes: • PBS00L (by default, on half page 0x18L, see “Lower PBS00 Half Page” on page 17-106 for details) PLL and voltage regulator settings Boot customization Instruction whether to load further half pages • PBS00H (by default, on half page 0x18H, see “Upper PBS00 Half Page” on page 17-110 for details) 17-14 ADSP-BF52x Blackfin Processor Hardware Reference Asynchronous EBIU register settings • PBS01L (by default on half page 0x19L) Reserved • PBS01H (by default, on half page 0x19H, see “Upper PBS01 Half Page” on page 17-111 for details) Disabling of boot modes NFC controller register settings OTP boot start page • PBS02L (by default, on half page 0x1AL, see “Lower PBS02 Half Page” on page 17-114 for details) Synchronous EBIU register settings • PBS02H (by default, on half page 0x1AH, see “Upper PBS02 Half Page” on page 17-115 for details) Reserved in current silicon revision. Do not use. • PBS03L (by default, on half page 0x1BL, see “Reserved Half Pages” on page 17-115 for details) Reserved in current silicon revision. Do not use. • PBS03H (by default, on half page 0x1BH, see “Reserved Half Pages” on page 17-115 for details) Reserved in current silicon revision. Do not use. The preboot routine reads the main page PBS00L first. Since this page may instruct the preboot routine to alter the PLL settings, further pages may read more quickly. This page also instructs the preboot whether further OTP half pages have to be loaded and processed. By default, the PBS00L page reads all zeroes, and the preboot does not load further PBS pages. ADSP-BF52x Blackfin Processor Hardware Reference 17-15 A lternative PBS Pages Especially during the development cycle, the user may fail to write the proper value to OTP memory and may make multiple attempts to get things right. Therefore, the PBS00L page provides a mechanism to invalidate the entire PBS block (consisting of pages (0x18, 0x19, 0x1A and 0x1B) and to use pages 0x1C to 0x1F instead. To do so, set the two OTP_INVALID bits (bits 62 and 63 on the PBS00L page). If both bits are set, the preboot routine disregards potential error codes returned by the bfrom_OtpRead() routine and continues processing from page 0x1C on. The active PBS block now spans the pages 0x1C to 0x1F. If the user wants to invalidate the second set of OTP pages as well, setting bits 62 and 63 on page 0x1C (which is the new PBS00L half page) instructs the preboot routine to continue at page 0x20, and so on. Theoretically, this can be repeated up to page 0xD8L, if the pages are not required for other purposes. There are 49 chances to get things right, before a device may become useless. Note that every page that needs to be read by the preboot routine causes additional delay to the boot process. Programming PBS Pages Due to the need for error checking and correction (ECC), a 64-bit OTP half page must be written all at once. It is recommended that PBS pages be programmed only through the API function bfrom_OtpWrite(). anticipated that customizing the boot-related If it ispages for safety orthe user isreasons, it is recommended that all OTP security PBS blocks be locked at production time to protect these pages from being tampered with in the field. Reading OTP memory is subject to a potential failure rate. Since the preboot only accesses OTP memory through the bfrom_OtpRead() function, the ECC error correction is applied and the statistical failure rate is very low. However, the way the PBS00L page is tested for being invalid may at some point reduce the ECC 17-16 ADSP-BF52x Blackfin Processor Hardware Reference reliability. To keep failure rates at a minimum, it is a good idea to duplicate the content of pages 0x18–0x1B on pages 0x1C–0x1F. For production parts, the final block should be followed by its exact copy to maintain the lowest failure rates. Then, even the unlikely case where one of the OTP_INVALID bits is read incorrectly would not cause the boot to fail. Recovering From Misprogrammed PBS Pages The preboot mechanism provides a powerful method to customize the chip to the needs of the user. However, as a downside, there are chances that invalid values programmed to the PBS pages prevent the processor from operating within required operating conditions. There is specific risk when the PLL and the voltage regulator are programmed with meaningless values during the development cycle. In such cases, the boot mode BMODE = b#0000 helps. In this mode, the preboot routine does not attempt to read any of the user-programmable PBS pages, and the boot kernel does not try to boot any data. Rather, the processor is idled immediately after the FPS pages have been processed. Using the in-circuit emulator, the user then has the option to invalidate the actual PBS settings by overwriting both OTP_INVALID bits in the actual PBS00L with 1s. For safety reasons, none of the boot modes, except the emulator, can get control over the processor when in this state. Customizing Power Management When the processor awakes with default PLL and voltage regulator settings, the preboot mechanism can be used to alter these settings to custom values before the boot process takes place. This is done by programming the OTP half page PBS00L. If the OTP_SET_PLL bit is programmed to a 1, the value in the OTP_PLL_DIV bit field is copied into the PLL_DIV register, and the OTP_PLL_CTL bit field ADSP-BF52x Blackfin Processor Hardware Reference 17-17 is copied into the PLL_CTL register, followed by the required IDLE instruction (if the contents of PLL_CTL are being altered). If the OTP_SET_VR bit is programmed to a 1, the value in the OTP_VR_CTL bit field is copied into the VR_CTL register, followed by the required IDLE instruction (if the contents of VR_CTL are being altered). The preboot mechanism invokes the bfrom_SysControl() routine to alter the PLL and the voltage regulator. The bfrom_SysControl() routine not only performs custom instructions, it also applies correction values from factory OTP pages FPS01 and FPS04. See Chapter 18, “Dynamic Power Management” for details on the bfrom_SysControl() routine. Customizing Booting Options The OTP pages accessible by the preboot mechanism can also be used to customize some of the booting options. For example: • TWI master boot mode operating frequency • SPI master boot mode operating frequency • SPI master boot mode read operation mode • Start page for OTP boot mode • HWAIT signal behavior • Disabling of unwanted boot modes In TWI master boot mode, the OTP_TWI_PRESCALE and OTP_TWI_CLKDIV values in the preboot half page PBS00L control the respective prescale and clock divider values written to the TWI_CONTROL and TWI_CLKDIV registers. The table of values can be found in “TWI Master Boot Mode” on page 17-72. The bit field OTP_TWI_TYPE controls whether one, two, three or four address bytes are used to address the I2C memory device. By 17-18 ADSP-BF52x Blackfin Processor Hardware Reference default, two address bytes are used. The address bits embedded in the read command are not counted. In SPI master boot mode, the OTP_SPI_BAUD register in the preboot half page PBS00L controls the value written to the SPI_BAUD registers. By default, the clock divider value of 133 can be reduced in power-of-two steps. The table of values can be found in “SPI Master Boot Modes” on page 17-65. The OTP_SPI_BAUD bit instructs the boot kernel to use the 0x0B SPI read command instead of the normal 0x03 read command when accessing the SPI memory device. In OTP boot mode, the boot kernel normally assumes that the boot stream starts at OTP page 0x40L. The user can change this start page by programming the OTP_START_PAGE bit field in the preboot half page PBS01H. The boot host wait (HWAIT) signal is available in all boot modes. If the OTP_RESETOUT_HWAIT bit in the preboot half page PBS00L is set, the boot kernel does not toggle HWAIT. Rather, it simply drives it to simulate a reset output signal. If safety or security of an application is impacted by the existence of certain boot modes, the boot mode disable bits in preboot half page PBS01H can be used to disable unwanted boot modes. If a disabled boot mode is chosen by the BMODE pins, the boot kernel goes into a safe idle state and stops processing. The half page PBS01H is only loaded when the OTP_LOAD_PBS01H bit in the PBS00L page is set. Customizing the Asynchronous Port The preboot half page PBS00H contains instructions to customize the asynchronous portion of the EBIU controller. This half page is only loaded and processed when the OTP_LOAD_PBS00H bit in the PBS00L half page is programmed to a 1. ADSP-BF52x Blackfin Processor Hardware Reference 17-19 The OTP_EBIU_AMG field is copied into the EBIU_AMGCTL register. While the lower bit controls the CLKOUT signal, the upper three AMBEN bits control which of the four asynchronous banks are enabled. For the FIFO boot mode, the three AMBEN bits are overruled and are all always set. The preboot routine analyzes the three AMBEN bits and initializes the 16-bit portions (this routine is similar to the enabled banks in the EBIU_AMBCTL0 and EBIU_AMBCTL1 registers) with the value provided in the 16-bit OTP_EBIU_AMBCTL field. In this way, the bus timing of the asynchronous port can be customized prior to the boot process. Customizing the Synchronous Port Since many Blackfin applications require data and/or instruction code to be loaded into the SDRAM memory at boot time, the SDRAM controller must be initialized beforehand. This can be done by using either the “Initialization Code” on page 17-37 or the preboot mechanism described here. For the SDRAM boot mode, only the preboot mechanism is valid. If the OTP_LOAD_PBS02L bit in the PBS00L half page is programmed to a “1”, the preboot half page PBS02L is also loaded and processed to initialize the SDRAM controller. First, the preboot routine tests the SDRS bit in the EBIU_SDSTAT status register. To avoid reconfiguring an already enabled SDRAM controller, processing is bypassed if this bit is already set. The lower twelve bits of the OTP_EBIU_SDRCC refresh rate value are written to the EBIU_SDRCC register. Similarly, the lower six bits of the OTP_EBIU_SDBCTL value are written to the EBIU_SDBCTL bank control register. The entire 32-bit OTP_EBIU_SDGCTL word is copied to the EBIU_SDGCTL global SDRAM control register. To minimize access latencies during the boot process, an initial dummy access to the SDRAM is performed immediately after the SDRAM controller is set up. By default, a 32-bit dummy is read from address 0x0000 17-20 ADSP-BF52x Blackfin Processor Hardware Reference 0000. If the OTP_EBIU_POWERON_DUMMY_WRITE bit is programmed to a “1”, a 32-bit zero value is written to that address instead. This option takes less time but destroys the previous content of that memory location. Address 0x0000 0000 is rarely used for regular processing since it represents a target of NULL pointers. Basic Booting Process Once the preboot routine returns, the boot kernel residing in the on-chip boot ROM starts processing the boot stream. The boot stream is either read from memory or received from a host processor. A boot stream represents the application data and is formatted in a special manner. The application data is segmented into multiple blocks of data. Each block begins with a block header. The header contains control words such as the destination address and data length information. As Figure 17-4 on page 17-22 illustrates, the VisualDSP++ tools suite features a loader utility (elfloader.exe). The loader utility parses the input executable file (.DXE), segments the application data into multiple blocks, and creates the header information for each block. The output is stored in a loader file (.LDR). The loader file contains the boot stream and is made available to hardware by programming or burning it into non-volatile ADSP-BF52x Blackfin Processor Hardware Reference 17-21 external memory. Refer to the VisualDSP++ Loader Manual for information on switches for loader files. .ASM/.C/.CPP SOURCE FILES .DOJ(s) ASSEMBLER AND/OR COMPILER .DXE(s) LINKER LOADER .LDR TARGET SYSTEM B BOOTING UPON RESET EXTERNAL MEMORY Figure 17-4. Project Flow for a Standalone System Figure 17-5 on page 17-23 shows the parallel or serial boot stream contained in a flash memory device. In host boot scenarios, the non-volatile memory more likely connects to the host processor rather than directly to the Blackfin processor. After reset, the headers are read and parsed by the on-chip boot ROM, and processed block-by-block. Payload data is copied to destination addresses, either in on-chip L1 memory or off-chip SRAM/SDRAM. Booting into scratchpad memory (0xFFB0 0000–0xFFB0 0FFF) is not supported. If booting to scratchpad memory is attempted, the processor hangs within the on-chip boot ROM. Similarly, booting into the upper 16 bytes of L1 data bank A (0xFF80 7FF0– 0xFF80 7FFF by default) is not supported. These memory locations are used by the boot kernel for intermediate storage of block 17-22 ADSP-BF52x Blackfin Processor Hardware Reference header information. These memory regions cannot be initialized at boot time. After booting, they can be used by the application during runtime. When the BFLAG_INDIRECT flag for any block is set, as in TWI boot modes, the boot kernel uses another memory block in L1 data bank B (by default, 0xFF90 7E00–0xFF90 7FFF) for intermediate data storage. To avoid conflicts, the VisualDSP++ elfloader utility ensures this region is booted last. .LDR FILE FLASH/PROM B 16-BYTE HEADER FOR BLOCK 1 LI MEMORY BLOCK 1 BLOCK 1 BLOCK 3 16-BYTE HEADER FOR BLOCK 2 APPLICATION CODE/DATA BLOCK 2 16-BYTE HEADER FOR BLOCK 3 0xEF00 0000 ON-CHIP BOOT ROM BLOCK 3 SDRAM 16-BYTE HEADER FOR BLOCK n BLOCK 2 BLOCK n ... Figure 17-5. Booting Process The entire source code of the boot ROM is shipped with the VisualDSP++ tools installation. Refer to the source code for any additional questions not covered in this manual. Note that minor maintenance work may be done to the content of the boot ROM when silicon is updated. Block Headers A boot stream consists of multiple boot blocks, as shown in Figure 17-5 on page 17-23. Every block is headed by a 16-byte block header. How- ADSP-BF52x Blackfin Processor Hardware Reference 17-23 ever, every block does not necessarily have a payload, as shown in Figure 17-6 on page 17-24. The 16 bytes of the block header are functionally grouped into four 32-bit words, the BLOCK CODE, the TARGET ADDRESS, the BYTE COUNT, and the ARGUMENT fields. BLOCK 0 HEADER BLOCK 0 PAYLOAD 3 2 1 0 OFFSET 0X0000 BLOCK CODE BLOCK 1 HEADER 7 6 5 4 OFFSET 0X0004 TARGET ADDRESS 11 10 9 8 13 12 OFFSET 0X0008 BYTE COUNT BLOCK 2 HEADER 15 14 ARGUMENT OFFSET 0X000C BLOCK 2 PAYLOAD Figure 17-6. Boot Stream Headers 17-24 ADSP-BF52x Blackfin Processor Hardware Reference B lock Code The first 32-bit word is the BLOCK Block Code, 31–16 CODE. See Figure 17-7. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 101 011 01000000 HDRS GN Header Sign 17 16 0 0 HDRCHK Header XOR Checksum Block Code, 15–0 15 14 13 12 11 10 000 000 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 BFLAG_FINAL BFLAG_FIRST BFLAG_INDIRECT BFLAG_IGNORE DMACODE DMA Coding BFLAG_SAVE BFLAG_AUX BFLAG_INIT BFLAG_CALLBACK BFLAG_QUICKBOOT BFLAG_FILL Figure 17-7. Block Code, 31–0 DMA Code Field The DMA code (DMACODE) field instructs the boot kernel whether to use 8-bit, 16-bit or 32-bit DMA and how to program the source modifier of a memory DMA. Particularly in case of memory boot modes, this field is interrogated by the boot kernel to differentiate the 8-bit, 16-bit, and 32-bit cases. ADSP-BF52x Blackfin Processor Hardware Reference 17-25 The boot kernel tests this field only on the first block and ignores the field in further blocks (See Table 17-3). Table 17-3. Bus and DMA Width Coding DMA Code DMA Width Source DMA Modify Application 0 reserved1 1 8-bit 1 Default 8-bit boot from 8-bit source2 2 8-bit 2 Zero-padded 8-bit boot from 16-bit EBIU 3 8-bit 4 Zero-padded 8-bit boot from 32-bit EBIU3 4 8-bit 8 Zero-padded 8-bit boot from 64-bit EBIU4 5 8-bit 16 Zero-padded 8-bit boot from 128-bit EBIU4 6 16-bit 2 Default 16-bit boot from 16-bit source5 7 16-bit 4 Zero-padded 16-bit boot from 32-bit EBIU3 8 16-bit 8 Zero-padded 16-bit boot from 64-bit EBIU4 9 16-bit 16 Zero-padded 16-bit boot from 128-bit EBIU4 10 32-bit 4 Default 32-bit boot from 32-bit source3, 5 11 32-bit 8 Zero-padded 32-bit boot from 64-bit EBIU4 12 32-bit 16 Zero-padded 32-bit boot from 128-bit EBIU4 13 64-bit 8 Default 64-bit boot from 64-bit source4 14 64-bit 16 Zero-padded 64-bit boot from 128-bit EBIU4 15 128-bit 16 Default 128-bit boot from 128-bit source4 1 2 3 4 5 Reserved to differentiate from ADSP-BF53x boot streams. Used by all byte-wise serial boot modes. Applicable only to memory boot modes and OTP mode. This code is expected by OTP boot mode. Not supported by ADSP-BF52x Blackfin products. This is the only code supported by NAND flash boot. 17-26 ADSP-BF52x Blackfin Processor Hardware Reference Block Flags Field Table 17-4. Block Flags Bit Name Description 4 BFLAG_SAVE Saves the memory of this block to off-chip memory in case of power failure or a hibernate request. This flag is not used by the on-chip boot kernel. 5 BFLAG_AUX Nests special block types as required by special purpose second-stage loaders. This flag is not used by the on-chip boot kernel. 6 Reserved 7 Reserved 8 BFLAG_FILL Tells the boot kernel to not process any payload data. Instead the target memory (specified by the TARGET ADDRESS and BYTE COUNT fields) is filled with the 32-bit value provided by the ARGUMENT word. The fill operation is always performed by 32-bit DMA; therefore target address and byte count must be divisible by four. 9 BFLAG_QUICKBOOT Processes the block for full boot only. Does not process this block for a quick boot (warm boot). 10 BFLAG_CALLBACK Calls a subfunction that may reside in on-chip or off-chip ROM or is loaded by an initcode in advance. Often used with the BFLAG_INDIRECT switch. If BFLAG_CALLBACK is set for any block, an initcode must register the callback function first. The function is called when either the entire block is loaded or the intermediate storage memory is full. The callback function can do advanced processing such as CRC checksum. 11 BFLAG_INIT This flag causes the boot kernel to issue a CALL instruction to the target address of the boot block after the entire block is loaded. The initcode should return by an RTS instruction. It may or may not be overwritten by application data later in the boot process. If the code is loaded earlier or resides in ROM, the init block can be zero sized (no payload). ADSP-BF52x Blackfin Processor Hardware Reference 17-27 Table 17-4. Block Flags (Continued) Bit Name Description 12 BFLAG_IGNORE Indicates a block that is not booted into memory. It instructs the boot kernel to skip the number of bytes of the boot stream as specified by BYTE COUNT. In master boot modes, the boot kernel simply modifies its source address pointer. In this case the BYTE COUNT value can be seen as a 32-bit two’s-complement offset value to be added to the source address pointer. In slave boot modes, the boot kernel actively loads and changes the payload of the block. In slave modes the byte count must be a positive value. 13 BFLAG_INDIRECT Boots to an intermediate storage place, allowing for calling an optional callback function, before booting to the destination. This flag is used when the boot source does not have DMA support (TWI for example) and either the destination cannot be accessed by the core (L1 instruction SRAM) or cannot be efficiently accessed by the core (SDRAM or RAM). This flag is also used when CALLBACK requires access to data to calculate a checksum, or when performing tasks such as decryption or decompression. 14 BFLAG_FIRST This flag, which is only set on the first block of a DXE, tells the boot kernel about the special nature of the TARGET ADDRESS and the ARGUMENT fields. The TARGET ADDRESS field holds the start address of the application. The ARGUMENT field holds the offset to the next DXE. 15 BFLAG_FINAL This flag causes the boot kernel to pass control over to the application after the final block is processed. This flag is usually set on the last block of a DXE unless multiple DXEs are merged. The BFLAG_FIRST flag must not be combined with the BFLAG_FILL flag. The BFLAG_FIRST flag may be combined with the BFLAG_IGNORE flag to deposit special user data at the top of the boot stream. Note the special importance of the VisualDSP++ elfloader –readall switch. Header Checksum Field The header checksum (HDRCHK) field holds a simple XOR checksum of the other 31 bytes in the boot block header. The boot kernel jumps to the error routine if the result of an XOR operation across all 32 header bytes (including the HDRCHK value) differs from zero. The default error routine is 17-28 ADSP-BF52x Blackfin Processor Hardware Reference a simple IDLE; instruction. The user can overwrite the default error handler using the initcode mechanism. Header Sign Field The header signature (HDRSGN) byte always reads as 0xAD and is used to verify whether the block pointer actually points to a valid block. The HDRSGN byte can also be used as a boot stream version control. For the ADSP-BF54x, ADSP-BF52x and ADSP-BF51x Blackfin processors, the byte always reads 0xAD. The ADSP-BF53x boot streams always read 0xFF. The ADSP-BF561 boot streams always read 0xA0. T arget Address This 32-bit field holds the target address where the boot kernel loads the block payload data. When the BFLAG_FILL flag is set, the boot kernel fills the memory with the value stored in the ARGUMENT field starting at this address. If the BFLAG_INIT flag is set the kernel issues a CALL(TARGET ADDRESS) instruction after the optional payload is loaded. If the BFLAG_FIRST flag is set, the TARGET ADDRESS field contains the start address of the application to which the boot kernel jumps at the end of the boot process. This address will also be stored in the EVT1 register. By default the VisualDSP++ elfloader utility sets this value to 0xFFA0 0000 for compatibility with other Blackfin products. The target address should be divisible by four, because the boot kernel uses 32-bit DMA for certain operations. The target address must point to valid on-chip or off-chip memory locations. When booting to external memories, the memory controller must first be set up by either the preboot or the initcode mechanism. When booting through peripherals that do not support DMA transfers, such as the TWI or OTP boot mode, the BFLAG_INDIRECT flag must be set if the target address points to L1 instruction memory. For performance reasons this is also recommended when booting to off-chip memories. ADSP-BF52x Blackfin Processor Hardware Reference 17-29 For the TWI or OTP boot modes, the VisualDSP++ elfloader utility manages the BFLAG_INDIRECT flag automatically. Refer to the VisualDSP++ Loader and Utilities reference guide for manual control of the flag. not supported. The scratchpad Booting to scratchpada memory isthe boot kernel. The L1 data memmemory functions as stack for ory locations 0xFF80 7FF0 to 0xFF80 7FFF are used by the boot kernel and should not be overwritten by the application. The memory range used for intermediate storage as controlled by the BFLAG_INDIRECT switch should only be booted after the last BFLAG_INDIRECT bit is processed. By default the address range 0xFF90 7E00–0xFF90 7FFF is used for intermediate storage. For normal boot operation, the target address points to RAM memory. There are however a few exceptions where the target address can point to on-chip or off-chip ROM. For example a zero-sized BFLAG_INIT block would instruct the boot kernel to call a subroutine residing in ROM or flash memory. This method is used to activate the CRC32 feature. Byte Count This 32-bit field tells the boot kernel how many bytes to process. Normally, this is the size of the payload data of a boot block. If the BFLAG_FILL flag is set there is no payload. In this case the BYTE COUNT field uses the value in its ARGUMENT field to tell the boot kernel how many bytes to process. The byte count is a 32-bit value that should be divisible by four. Zero values are allowed in all block types. Most boot modes are based upon DMA operation which are only 16-bit words for Blackfin processors. The boot kernel may therefore start multiple DMA work units for large boot blocks. This enables a single block to fill to zero the entire SDRAM memory, for example, resulting in compact boot streams. The HWAIT signal may toggle for each work unit. 17-30 ADSP-BF52x Blackfin Processor Hardware Reference If the BFLAG_IGNORE flag is set, the byte count is used to redirect the boot source pointer to another memory location. In master boot modes, the byte count is a two’s-complement (signed long integer) value. In slave boot modes, the value must be positive. Argument This 32-bit field is a user variable for most block types. The value is accessible by the initcode or the callback routine and can therefore be used for optional instructions to these routines. When the CRC32 feature is activated, the ARGUMENT field holds the checksum over the payload of the block. When the BFLAG_FILL flag is set there is no payload. The argument contains the 32-bit fill value, which is most likely a zero. If the BFLAG_FIRST flag is set, the argument contains the relative next-DXE pointer for multi-DXE applications. For single-DXE applications the field points to the next free boot source address after the current DXE’s boot stream. Boot Host Wait (HWAIT) Feedback Strobe The HWAIT feedback strobe is a handshake signal that is used to hold off the host device from sending further data while the boot kernel is busy. On ADSP-BF52x processors this feature is implemented by a GPIO that is toggled by the boot kernel as required. The PG0 GPIO is used for this purpose. The signal polarity of the HWAIT strobe is programmable by an external resistor in the 10 k range. A pull-up resistor instructs the HWAIT signal to be active high. In this case the host is permitted to send header and footer data when HWAIT is low, ADSP-BF52x Blackfin Processor Hardware Reference 17-31 but should pause while HWAIT is high. This is the mode used in SPI slave boot on other Blackfin products. Similarly, a pull-down resistor programs active-low behavior. signal is implemented Note that the Blackfin processors. In theslightly differently than on ADSP-BF53x ADSP-BF52x procesHWAIT sors, the meaning of the pulling resistor is inverted and HWAIT is asserted by default during reset and preboot. After preboot, the boot kernel first senses the polarity on the respective HWAIT pin. Then it enables the output driver but keeps the signal in its asserted state. The signal is not released until the boot kernel is ready for data, or when a receive DMA is started. As soon as the DMA completes, HWAIT becomes active again. The boot host wait signal holds the host from booting in any slave boot mode and prevents it from being overrun with data. The HWAIT signal is, however, available in all boot modes with the exception of the NAND flash boot mode. In general the host device must interrogate the HWAIT signal before every word that is sent. This requirement can be relaxed for boot modes using on-chip peripherals that feature larger receive FIFOs. However, the host must not rely on the DMA FIFO since its content is cleared at the end of a DMA work unit. While the HWAIT signal is only used for boot purposes, it may also play a significant role after booting. In slave boot modes, for example, the host device does not necessarily know whether the Blackfin processor is in an active mode or a power-down mode. For example, the HWAIT signal can be used to signal when the processor is in hibernate mode. Using HWAIT as Reset Indicator While the HWAIT signal is mandatory in some boot modes, it is optional in others. When not required for booting, the behavior of the HWAIT signal 17-32 ADSP-BF52x Blackfin Processor Hardware Reference can be changed by programming the OTP_RESETOUT_HWAIT bit in OTP page PBS00L. If this bit is set, HWAIT does not toggle during the boot process. Rather, after page PBS00L is processed (and therefore the PLL has settled) the preboot routine first enables the HWAIT GPIO as an input and senses its state. Then HWAIT becomes an output and is driven to the invert of the state that is sensed. An external pulling resistor is required. If using a pull-up resistor, the HWAIT signal is driven low for the rest of the boot process (and beyond). If using a pull-down resistor, HWAIT is driven high. With a pull-down resistor, this feature can be used to simulate an active-low reset output. When the processor is reset, or in hibernate, the GPIO is in a high impedance state and HWAIT is pulled low by the resistor. As soon as the processor recovers and has settled the PLL again, the HWAIT is driven high and can alert external circuits. Boot Termination After the successful download of the application into the bootable memory, the boot kernel passes control to the user application. By default this is performed by jumping to the vector stored in the EVT1 register. The boot kernel provides options to execute an RTS instruction or a RAISE 1 instruction instead. The default behavior can be changed by an initcode routine. The EVT1 register is updated by the boot kernel when processing the BFLAG_FIRST block. See “Servicing Reset Interrupts” on page 17-10 to learn how the application can take control. Before the boot kernel passes program control to the application it does some housekeeping. Most of the registers that were used are changed back to their default state but some register values may differ for individual boot modes. DMA configuration registers and primary register control registers (UART0_LCR, SPI_CTL, HOST_CONTROL, etc.) are restored, while others are purposely not restored. For example SPI_BAUD, UART0_DLH and ADSP-BF52x Blackfin Processor Hardware Reference 17-33 remain unchanged so that settings obtained during the booting process are not lost. UART_DLL Single Block Boot Streams The simplest boot stream consists of a single block header and one contiguous block of instructions. With appropriate flag instructions the boot kernel loads the block to the target address and immediately terminates by executing the loaded block. Table 17-5 shows an example of a single block boot stream header that could be loaded from any serial boot mode. It places a 256-byte block of instructions at L1 instruction SRAM address 0xFFA0 0000. The flags BFLAG_FIRST and BFLAG_FINAL are both set at the same time. Advanced flags, such as BFLAG_IGNORE, BFLAG_INIT, BFLAG_CALLBACK and BFLAG_FILL, do not make sense in this context and should not be used. Table 17-5. Header for a Single Block Boot Stream Field Value Comments BLOCK CODE 0xAD33 C001 0xAD00 0000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | (DMACODE & 0x1) TARGET ADDRESS 0xFFA0 0000 Start address of block and application code BYTE COUNT 0x0000 0100 256 bytes of code ARGUMENT 0x0000 0100 Functions as next-DXE pointer in multi-DXE boot streams With the BFLAG_FIRST flag set, the ARGUMENT field functions as the next-DXE pointer. This is a relative pointer to the next free source address or to the next DXE start address in a multi-DXE stream. D irect Code Execution Applications may want to avoid long booting times and start code execution directly from 16-bit flash or SDRAM memory. This feature is called 17-34 ADSP-BF52x Blackfin Processor Hardware Reference direct code execution. This is a special case of boot termination that replaces the no-boot/bypass mode in the ADSP-BF53x Blackfin processors. An initial boot block header is needed for the processor to fetch and execute program code from the boot device as early as possible. The safety mechanisms of the block, such as the header signature and the XOR checksum, avoid unpredictable processor behavior due to the boot memory not being programmed with valid data yet. Rather than blindly executing code, the boot kernel first executes the preboot routine for system customization, then loads the first block header and checks it for consistency. If the block header is corrupted, the boot kernel goes into a safe idle state and does not start code execution. If the initial block header checks good, the boot kernel interrogates the block flags. If the block has the BFLAG_FINAL flag set, the boot kernel immediately terminates and jumps directly to the address stored in the EVT1 register. To cause the boot kernel to customize the EVT1 register in advance, the initial blocks must also have the BFLAG_FIRST flag set. The TARGET ADDRESS field is then copied to the EVT1 register. In this way, the TARGET ADDRESS field of the initial block defines the start address of the application. For example in BMODE = 0001, when the block header described in Table 17-6 on page 17-36 is placed at address 0x2000 0000, the boot kernel is instructed to issue a JUMP command to address 0x2000 0020. The development tools must be instructed to link the above block to address 0x2000 0000 and the application code to address 0x2000 0020. ADSP-BF52x Blackfin Processor Hardware Reference 17-35 An example shown in “Direct Code Execution” on page 17-148 illustrates how this is accomplished using the VisualDSP++ tools suite. Table 17-6. Initial Header for Direct Code Execution in BMODE = 0001 Field Value Comments BLOCK CODE 0xAD7B D006 0xAD00 0000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | BFLAG_IGNORE | (DMACODE & 0x6) TARGET ADDRESS 0x2000 0020 Start address of application code BYTE COUNT 0x0000 0010 Ignores 16 bytes to provide space for control data such as version code and build data. This is optional and can be zero. ARGUMENT 0x0000 0010 Functions as next-DXE pointer in multi-DXE boot streams Similarly for direct code execution in the SDRAM boot mode (BMODE = 1010), an initial block as shown in Table 17-7 has to be linked to address 0x0000 0010. Table 17-7. Initial Header for Direct Code Execution in BMODE = 1010 Field Value Comments BLOCK CODE 0xAD5B D006 0xAD000000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | BFLAG_IGNORE | (DMACODE & 0x6) TARGET ADDRESS 0x0000 0020 Start address of application code BYTE COUNT 0x0000 0000 No bubble for control data ARGUMENT 0x0000 0000 Functions as next-DXE pointer in multi-DXE boot streams For multi-DXE boot streams, Figure 17-11 on page 17-56 shows a linked list of initial blocks that represent different applications. 17-36 ADSP-BF52x Blackfin Processor Hardware Reference A dvanced Boot Techniques Initialization Code Initcode routines are subroutines that the boot kernel calls during the booting process. The user can customize and speed up the booting mechanisms using this feature. Traditionally, an initcode is used to set up system PLL, bit rates, wait states and the SDRAM controller. If executed early in the boot process, the boot time can be significantly reduced. After the payload data is loaded for a specific boot block, if the BFLAG_INIT flag is set, the boot kernel issues a CALL instruction to the target address of the block. On ADSP-BF52x Blackfin processors, initcode routines follow the C language calling convention so they can be coded in C language or assembly. The expected prototype is void initcode(ADI_BOOT_DATA* pBootStruct); The VisualDSP++ header files define the ADI_BOOT_INITCODE_FUNC type: typedef void ADI_BOOT_INITCODE_FUNC (ADI_BOOT_DATA* ) ; Optionally, the initcode routine can interrogate the formatting structure and customize its own behavior or even manipulate the regular boot process. A pointer to the structure is passed in the R0 register. Assembly coders must ensure that the routine returns to the boot kernel by a terminating RTS instruction. Initcodes can rely on the validity of the stack, which resides in scratchpad memory. The ADI_BOOT_DATA structure resides on the stack. Rules for register usage conform to the compiler conventions. See the VisualDSP++ C/C++ Compiler and Library Manual for more information. ADSP-BF52x Blackfin Processor Hardware Reference 17-37 In the simple case, initcodes consist of a single instruction section and are represented by a single block within the boot stream. This block has the BFLAG_INIT bit set. An init block can consist of multiple sections where multiple boot blocks represent the initcode within the boot stream. Only the last block has the BFLAG_INIT bit set. The VisualDSP++ elfloader utility ensures that the last of these blocks vectors to the initcode entry address. The utility instructs the on-chip boot ROM to execute a CALL instruction to the given target address. When the on-chip boot ROM detects a block with the BFLAG_INIT bit set, it boots the block into Blackfin memory and then executes it by issuing a CALL to its target address. For this reason, every initcode must be terminated by an RTS instruction to ensure that the processor vectors back to the on-chip boot ROM for the rest of the boot process. Sometimes initcode boot blocks have no payload and the BYTE COUNT field is set to zero. Then the only purpose of the block may be to instruct the boot kernel to issue the CALL instruction. Initcode routines can be very different in nature. They might reside in ROM or SRAM. They might be called once during the booting process or multiple times. They might be volatile and be overwritten by other boot blocks after executing, or they might be permanently available after boot time. The boot kernel has no knowledge of the nature of initcodes and has no restrictions in this regard. Refer to the VisualDSP++ Loader and Utilities Manual for how this feature is supported by the tools chain. It is the user’s responsibility to ensure that all code and data sections that are required by the initcode are present in memory by the time the initcode executes. Special attention is required if initcodes are written in C or C++ language. Ensure that the initcode does not contain calls to the runtime libraries. Do not assume that parts of the runtime environment, such as the heap are fully functional. Ensure that all runtime components are loaded and initialized before the initcode executes. 17-38 ADSP-BF52x Blackfin Processor Hardware Reference The VisualDSP++ elfloader utility provides two different mechanisms to support the initcode feature. • The -init initcode.dxe • The -initcall command line switch address/symbol command line switch If enabled by the VisualDSP++ elfloader -init initcode.DXE command line switch, the initcode is added to the beginning of the boot stream. Here, initcode.DXE refers to the user-provided custom initialization executable— a separate VisualDSP++ project. Figure 17-8 on page 17-40 shows a boot stream example that performs the following steps. 1. Boot initcode into L1 memory. 2. Execute initcode. 3. Initcode initializes the SDRAM controller and returns. 4. Overwrite initcode with final application code. 5. Boot data/code into SDRAM. 6. Continue program execution with block n. ADSP-BF52x Blackfin Processor Hardware Reference 17-39 Flash/PROM or SPI Device Header for Init Block L1 Memory Init Block Init Block Header for SDRAM Block SDRAM Block ........ App Code/Data Header for L1 Data Block L1 Data Block Header for L1 Code Block 0xEF00 0000 Blackfin Processor L1 Code Block On-Chip Boot ROM SDRAM Before Init Code Execution Flash/PROM or SPI Device After Init Code Execution Header for Init Block L1 Memory Init Block L1 Block Init Block Header for SDRAM Block SDRAM Block ........ App Code/Data Header for L1 Data Block L1 Data Block Header for L1 Code Block 0xEF00 0000 Blackfin Processor L1 Code Block On-Chip Boot ROM SDRAM Figure 17-8. Initialization Code Execution/Boot Although initcode.DXE files are built as VisualDSP++ projects, they differ from standard projects. Initcodes provide only a callable sub-function, so they look more like a library than an application. Nevertheless, unlike 17-40 ADSP-BF52x Blackfin Processor Hardware Reference library files (.DLB file extension), the symbol addresses have already been resolved by the linker. An initcode is always a heading for the regular application code. Consequently whether the initcode consists of one or multiple blocks, it is not terminated by a BFLAG_FINAL bit indicator—this would cause the boot ROM to terminate the boot process. It is advantageous to have a clear separation between the initcode and the application by using the -init switch. If this separation is not needed, the elfloader -initcall command-line switch might be preferred. It enables fractions of the application code to be traded as initcode during the boot process. See the VisualDSP++ Loader and Utilities Manual for further details. Initcode examples are shown in “Programming Examples” on page 17-138. Quick Boot In some booting scenarios, not all memories need to be re-initialized. For example in a wake-up from hibernate state, off-chip SRAM might not be impacted if it was powered while the processor was in hibernate state. Dynamic RAM might also not be impacted if it was put into self-refresh mode before the processor powered down. The ADSP-BF52x processor’s boot kernel can conditionally process boot blocks. The normal scenario is all boot, the shortened version is quick boot. It relies on the following primitives. • The SYSCR register is read to determine what kind of boot is expected from the boot kernel. Refer to Figure 17-39 on page 17-102. The WURESET bit is used to distinguish between cold boot and warm boot situations and to identify wake-up from hibernate situations. ADSP-BF52x Blackfin Processor Hardware Reference 17-41 The BCODE bit field in the SYSCR register can overrule the native decision of the boot kernel for a software boot. See the flowchart in Figure 17-1 on page 17-9. • The BFLAG_WAKEUP bit in the dFlag word of the ADI_BOOT_DATA structure indicates that the final decision was to perform a quick boot. If the boot kernel is called from the application, then the application can control the boot kernel behavior by setting the BFLAG_WAKEUP flag accordingly. See the dFlags variable on Figure 17-52 on page 17-120. • The BFLAG_QUICKBOOT flag in the BLOCK CODE word of the block header controls whether the current block is ignored for quick boot. If both the global BFLAG_WAKEUP and the block-specific BFLAG_QUICKBOOT flags are set, the boot kernel ignores those blocks. But since the BFLAG_INIT, BFLAG_CALLBACK, BFLAG_FINAL, and BFLAG_AUX flags are internally cleared and the BFLAG_IGNORE flag is toggled, through double negation, the “ignore the ignore block” command instructs the boot kernel to process the block. Although the BFLAG_INIT flag is suppressed in quick boot, the user may not want to combine the BFLAG_INIT flag with the BFLAG_QUICKBOOT flag. The initialization code can interrogate the BFLAG_WAKEUP flag and execute conditional instructions. For more information see “Quickboot With Restore From SDRAM” on page 17-145. Indirect Booting The processor’s boot kernel provides a control mechanism to let blocks either boot directly to their final destination or load to an intermediate 17-42 ADSP-BF52x Blackfin Processor Hardware Reference storage place, then copy the data to the final destination in a second step. This feature is motivated by the following requirements. • Some boot modes such as TWI do not use DMA. They load data by core instruction. The core cannot access some memories directly (for example L1 instruction SRAM), or is less efficient than the DMA in accessing some memories (for example, external SDRAM). • In some advanced booting scenarios, the core needs to access the boot data during the booting process, for example in processing decompression, decryption and checksum algorithms at boot time. The indirect booting option helps speed-up and simplify such scenarios. Software accesses off-chip memory less efficiently and cannot access data directly if it resides in L1 instruction SRAM. Indirect booting is not a global setting. Every boot block can control its own processing by the BFLAG_INDIRECT flag in the block header. In general a boot block may not fit into the temporary storage memory so the boot kernel processes the block in multiple steps. The larger the temporary buffer, the faster the boot process. By default the L1 data memory region between 0xFF90 7E00 and 0xFF90 7FFF is used for intermediate storage. Initialization code can alter this region by modifying the pTempBuffer and dTempByteCount variables in the ADI_BOOT_DATA structure. The default region is at the upper end of a physical memory block. When increasing the dTempByteCount value, pTempBuffer also has to change. Callback Routines Callback routines, like initialization codes, are user-defined subroutines called by the boot kernel at boot time. The BFLAG_CALLBACK flag in the block header controls whether the callback routine is called for a specific block. ADSP-BF52x Blackfin Processor Hardware Reference 17-43 There are several differences between initcodes and callback routines. While the BFLAG_INIT flag causes the boot kernel to issue a CALL instruction to the target address of the specific boot block, the BFLAG_CALLBACK flag causes the boot kernel to issue a CALL instruction to the address held by the pCallBackFunction pointer in the ADI_BOOT_DATA structure. While a boot stream can have multiple individual initcodes, it can have just one callback routine. In the standard boot scenario, the callback routine has to be registered by an initcode prior to the first block that has the BFLAG_CALLBACK flag set. The purpose of the callback routine is to apply standard processing to the block data. Typically, callback routines contain checksum, decryption, decompression, or hash algorithms. Checksum or hash words can be passed through the block header ARGUMENT field. Since callback routines require access to the payload data of the boot blocks, the block data must be loaded before it can be processed. Unlike initcodes, a callback usually resides permanently in memory. If the block is loaded to L1 instruction memory or off-chip memory, the BFLAG_CALLBACK flag is likely combined with the BFLAG_INDIRECT bit. The boot kernel performs these steps in the following order. 1. Data is loaded into the temporary buffer defined by the pTempBuffer variable. 2. The CALL to the pCallBackFunction is issued. 3. After the callback routine returns, the memory DMA copies data to the destination. If a block does not fit into the temporary buffer, for example when the BLOCK COUNT is greater than the dTempByteCount variable, the three steps are executed multiple times until all payload data is loaded and processed. The boot kernel passes the parameter dCbFlags to the callback routine to tell it that it is being invoked the first or the last time for a specific block. To store intermediate results across multiple calls the callback routine can 17-44 ADSP-BF52x Blackfin Processor Hardware Reference use the uwUserShort and dUserLong variables in the ADI_BOOT_DATA structure. Callback routines meet C language calling conventions for subroutines. The prototype is as follows. s32 CallBackFunction (ADI_BOOT_DATA* pBootStruct, ADI_BOOT_BUFFER* pCallbackStruct, s32 dCbFlags); The VisualDSP++ header file defines the ADI_BOOT_CALLBACK_FUNC type the following way: typedef s32 ADI_BOOT_CALLBACK_FUNC (ADI_BOOT_DATA*, ADI_BOOT_BUFFER*, s32 ) ; The pBootStruct argument is passed in R0 and points to the ADI_BOOT_DATA structure used by the boot kernel. These are handled by the pTempBuffer and dTempByteCount variables as well as the pHeader pointer to the ARGUMENT field. The callback routine may process the block further by modifying the pTempBuffer and dTempByteCount variables. The pCallbackStruct structure passed in R1 provides the address and length of the data buffer. When the BFLAG_INDIRECT flag is not set, the pCallbackStruct contains the target address and byte count of the boot block. If the BFLAG_INDIRECT flag is set, the pCallbackStruct contains a copy of the pTempBuffer. Depending on the size of the boot block and processing progress, the byte count provided by pCallbackStruct equals either dTempByteCount or the remainder of the byte count. When the BFLAG_INDIRECT flag is set along with the BFLAG_CALLBACK flag, memory DMA is invoked by the boot kernel after the callback routine returns. This memory DMA relies on the pCallbackStruct structure not the global pTempBuffer and dTempByteCount variables. The callback routine can control the source of the memory DMA by altering the content of the pCallbackStruct structure, as may be required if the callback routine performs data manipulation such as decompression. ADSP-BF52x Blackfin Processor Hardware Reference 17-45 The dCbFlags parameter passed in R2 tells the callback routine whether it is invoked the first time (CBFLAG_FIRST) or whether it is called the last time (CBFLAG_FINAL) for a specific block. The CBFLAG_DIRECT flag indicates that the BFLAG_INDIRECT bit is not active so that the callback routine will only be called once per block. When the CBFLAG_DIRECT flag is set, the CBFLAG_FIRST and CBFLAG_FINAL flags are also set. #define CBFLAG_FINAL 0x0008 #define CBFLAG_FIRST 0x0004 #define CBFLAG_DIRECT 0x0001 A callback routine also has a boolean return parameter in register R0. If the return value is non-zero, the subsequent memory DMA does not execute. When the CBFLAG_DIRECT flag is set, the return value has no effect. Error Handler While the default handler simply puts the processor into idle mode, an initcode routine can overwrite this pointer to create a customized error handler. The expected prototype is void ErrorFunction (ADI_BOOT_DATA* pBootStruct, void *pFailingAddress); Use an initcode to write the entry address of the error routine to the pErrorFunction pointer in the ADI_BOOT_DATA structure. The error handler has access to the boot structure and receives the instruction address that triggered the error. CRC Checksum Calculation The ADSP-BF52x Blackfin processors provide an initcode and a callback routine in ROM that can be used for CRC32 checksum generation during boot time. The checksum routine only verifies the payload data of the blocks. The block headers are already protected by the native XOR checksum mechanism. 17-46 ADSP-BF52x Blackfin Processor Hardware Reference Before boot blocks can be tagged with the BFLAG_CALLBACK flag to enable checksum calculation on the blocks, the boot stream must contain an initcode block with no payload data and with the CRC32 polynomial in the block header ARGUMENT word. The initcode registers a proper CRC32 wrapper to the pCallBackFunction pointer. The registration principle is similar to the XOR checksum example shown in “Programming Examples” on page 17-138. Load Functions With the exception of the Host DMA boot modes, all boot modes are processed by a common boot kernel algorithm. The major customization is done by a subroutine that must be registered to the pLoadFunction pointer in the ADI_BOOT_DATA structure. Its simple prototype is as follows. void LoadFunction (ADI_BOOT_DATA* pBootStruct); The VisualDSP++ header files define the following type: typedef void ADI_BOOT_LOAD_FUNC (ADI_BOOT_DATA* ) ; For a few scenarios some of the flags in the dFlags word of the ADI_BOOT_DATA structure, such as BFLAG_PERIPHERAL and BFLAG_SLAVE, slightly modify the boot kernel algorithm. The boot ROM contains several load functions. One performs a memory DMA for flash boot, others perform peripheral DMAs or load data from booting source by polling operation. The first is reused for fill operation and indirect booting as well. In second-stage boot schemes, the user can create customized load functions or reuse the original BFROM_PDMA routine and modify the pDmaControlRegister, pControlRegister and dControlValue values in the ADI_BOOT_DATA structure. The pDmaControlRegister points to the DMAx_CONFIG o r MDMA_Dx_CONFIG register. When the BFLAG_SLAVE flag is not set, the pControlRegister and dControlValue variables instruct the ADSP-BF52x Blackfin Processor Hardware Reference 17-47 peripheral DMA routine to write the control value to the control register every time the DMA is started. Load functions written by users must meet the following requirements. • Protect against dByteCount values of zero. • Multiple DMA work units are required if the dByteCount value is greater than 65536. • The pSource and pDestination pointers must be properly updated. In slave boot modes, the boot kernel uses the address of the dArgument field in the pHeader block as the destination for the required dummy DMAs when payload data is consumed from BFLAG_IGNORE blocks. If the load function requires access to the block's ARGUMENT word, it should be read early in the function. The most useful load functions BFROM_MDMA and BFROM_PDMA are accessible through the jump table. Others, do not have entries in the jump table. Their start address can be determined with the help of the hook routine when calling the respective BFROM_SPIBOOT, BFROM_OTPBOOT etc. functions. In this way they can be repurposed for runtime utilization. Calling the Boot Kernel at Runtime The boot kernel’s primary purpose is to boot data to memory after power-up and reset cycles. However some of the routines used by the boot kernel might be of general value to the application. The boot ROM supports reuse of these routines as C-callable subroutines. Programs such as second-stage boot kernels, boot managers, and firmware update tools may call the function in the ROM at runtime. This could load entirely different applications or a fraction of an application, such as a code overlay or a coefficient array. To call these boot kernel subroutines, the boot ROM provides an API at address 0xEF00 0000 in the form of a jump table. 17-48 ADSP-BF52x Blackfin Processor Hardware Reference When calling functions in the boot ROM, the user must ensure the presence of a valid stack following C language conventions. See the VisualDSP++ Compiler documentation for details. Debugging the Boot Process If the boot process fails, very little information can be gained by watching the chip from outside. In master boot modes, the interface signals can be observed. In slave boot modes only the HWAIT signal tells about the progress of the boot process. However, by using the emulator, there are many possibilities for debugging the boot process. The entire source code of the boot kernel is provided with the VisualDSP++ installation. This includes the project executable (DXE) file. The LOAD SYMBOLS feature of the VisualDSP++ IDDE helps to navigate the program. Note that the content of the ROM might differ between silicon revisions. Hardware breakpoints and single-stepping capabilities are also available. Table 17-8 shows program symbols that are of interest. Table 17-8. Boot Kernel Symbols for Debug Symbol Comment _bootrom.assert.default If the program counter halts at the IDLE instruction at the _bootrom.assert.default address, either the boot kernel or the preboot has detected an error condition and will not continue the boot process. A misformatted boot stream, or invalid PBS settings are the most likely causes of such an error. The RETS register points to the failing routine. When stepping a couple of instructions further, there is a way to ignore the error and to continue the boot process by clearing the >ASTAT register while the emulator steps over the subsequent IF CC JUMP 0 instruction. _bootrom.bootmenu If the emulator hits a hardware breakpoint at the _bootrom.bootmenu address, this indicates that the preboot returned properly. Otherwise the program may hang during preboot due to improper PBS settings or invalid boot modes. ADSP-BF52x Blackfin Processor Hardware Reference 17-49 Table 17-8. Boot Kernel Symbols for Debug (Continued) Symbol Comment _bootrom.bootkernel.entry If the emulator hits a hardware breakpoint at the _bootrom.bootkernel.entry label, this indicates that device detection or autobaud returned properly. _bootrom.bootkernel.breakpoint This is a good address to place a hardware breakpoint. The boot kernel loads a new block header at this breakpoint. The block header can be watched at address 0xFF80 7FF0 or wherever the pHeader points to. _bootrom.bootkernel.initcode All payload data of the current block is loaded by the time the program passes the _bootrom.bootkernel.initcode label. The boot kernel is about to interrogate the BFLAG_INIT flag. If set, the initcode can be debugged. _bootrom.bootkernel.exit Once the boot kernel arrives at the _bootrom.bootkernel exit label, it detects a BFLAG_FINAL flag. After some housekeeping, it jumps to the EVT1 vector. The boot kernel also generates a circular log file in scratch pad memory. While the pLogBuffer and the dLogByteCount variables describe the location and dimension of the log buffer, the pLogCurrent points to the next free location in the buffer. The log file is updated whenever the kernel passes the _bootrom.bootkernel.breakpoint label. 17-50 ADSP-BF52x Blackfin Processor Hardware Reference At each pass, nine 32-bit words are written to the log file, as follows. • block code word (dBlockCode) of the block header • target address (pTargetAddress) of the block header • byte count (dByteCount) of the block header • argument word (dArgument) of the block header • source pointer (pSource) of the boot stream • block count (dBlockCount) • internal copy of the dBlockCode word OR’ed with dFlags • content of the SEQSTAT register • 0xFFFF FFFA (-6) constant The ninth word is overwritten by the next entry set, so that 0xFFFF FFFA always marks the last entry in the log file. Most of the data structures used by the boot kernel reside on the stack in scratchpad memory. While executing the boot kernel routine (excluding subroutines), the P5 points to the ADI_BOOT_DATA structure. Type “(ADI_BOOT_DATA*) $P5” in the VisualDSP++ expression window to see the structure content. Boot Management Blackfin processor hardware platforms may be required to run different software at different times. An example might be a system with at least one application and one in-the-field firmware upgrade utility. Other systems may have multiple applications, one starting then terminating, to be replaced by another application. Conditional booting is called boot management. Some applications may self-manage their booting rules, while ADSP-BF52x Blackfin Processor Hardware Reference 17-51 others may have a separate application that controls the process, namely a boot manager. In a master boot mode where the on-chip boot kernel loads the boot stream from memory, the boot manager is a piece of Blackfin software which decides at runtime what application is booted next. This may simply be based on the state of a GPIO input pin interrogated by the boot manager, or it may be the conclusion of complex system behavior. Slave boot scenarios are different from master boot scenarios. In slave boot modes, the host masters boot management by setting the Blackfin processor to reset and then applying alternate boot data. Optionally, the host could alter the BMODE configuration pins, resulting in little impact to the Blackfin processor since the intelligence is provided by the host device. Booting a Different Application The boot ROM provides a set of user-callable functions that help to boot a new application (or a fraction of an application). Usually there is no need for the boot manager to deal with the format details of the boot stream. These functions are: • BFROM_MEMBOOT discussed in “Flash Boot Modes” on page 17-59 and “SDRAM Boot Mode” on page 17-63 • BFROM_TWIBOOT discussed in “TWI Master Boot Mode” on page 17-72 • BFROM_SPIBOOT discussed in “SPI Master Boot Modes” on page 17-65 • • BFROM_OTPBOOT discussed in “OTP Boot Mode” on page 17-80 BFROM_NANDBOOT discussed in “NAND Flash Boot Mode” on page 17-86 17-52 ADSP-BF52x Blackfin Processor Hardware Reference The user application, the boot manager application, or an initcode can call these functions to load the requested boot data. Using the BFLAG_RETURN flag the user can control whether the routine simply returns to the calling function or executes the loaded application immediately. These ROM functions expect the start address of the requested boot stream as an argument. For BFROM_MEMBOOT, this is a Blackfin memory address, for BFROM_TWIBOOT and BFROM_SPIBOOT it is a serial address. The SPI function can also accept the code for the GPIO pin that controls the device select strobe of the SPI memory. M ulti-DXE Boot Streams If the start addresses of all the boot streams are predefined, the boot manager needs only to call the ROM functions directly. However since the addresses tend to vary from build to build they may have to be calculated at runtime. In the world of the VisualDSP++ elfloader, a boot stream is always generated from a DXE file. It is therefore common to talk about multi-DXE or multi-application booting. When the elfloader utility accepts multiple DXE files on its command line, it generates a contiguous boot image by default. The second boot stream is appended immediately to the first one. Since the utility updates the ARGUMENT field of all BFLAG_FIRST blocks, the ARGUMENT field of a BFLAG_FIRST block is called next-DXE pointer (NDP). The next-DXE pointer of the first DXE boot stream points relatively to the start address of the second DXE boot stream. A multi-DXE boot image can be seen as a linked list of boot streams. The next-DXE pointer of the last DXE boot stream points relatively to the next free address. This is illustrated by an example shown in the next two figures. Figure 17-9 on page 17-54 shows a commented sketch as an example. Figure 17-10 on page 17-55 shows a screenshot of the Blackfin loader file viewer utility for the same example. The LdrViewer utility is not part of the VisualDSP++ tools suite. It is a third-party freeware product available on www.dolomitics.com. ADSP-BF52x Blackfin Processor Hardware Reference 17-53 0x2000 0000 BLOCK CODE = 0xAD95 5006 First block of initcode DXE BFLAG_FIRST | BFLAG_IGNORE TARGET ADDRESS = 0xFFA0 0000 Start address of application BYTE COUNT = 0x0000 0010 Size of optional bubble ARGUMENT = 0x0000 0120 Next DXE pointer Optional 16-byte bubble Bubble to be ignored by kernel BLOCK CODE = 0xADFC 0806 BFLAG_INIT (BFLAG_FINAL not set to continue boot processing) 0x2000 0010 0x2000 0020 TARGET ADDRESS = 0xFFA1 0000 Target address of initcode BYTE COUNT = 0x0000 0100 0x2000 0030 Size of initcode ARGUMENT = 0x0000 0000 Not used Payload of initcode 0x100 bytes Initcode 0x2000 0130 BLOCK CODE = 0xAD86 5006 First block of first application DXE BFLAG_FIRST | BFLAG_IGNORE TARGET ADDRESS = 0xFFA0 0000 Start address of application BYTE COUNT = 0x0000 0000 0x2000 0140 No bubble ARGUMENT = 0x0000 0220 Next DXE pointer BLOCK CODE = 0xADF6 0006 Normal data block TARGET ADDRESS = 0xFFA0 0000 Target address of block data BYTE COUNT = 0x0000 0200 0x2000 0150 Size of payload ARGUMENT = 0x0000 0000 Not used Payload of data/code block 0x200 bytes Loads L1 instruction SRAM BLOCK CODE = 0xADD5 8106 Last block of first application DXE BFLAG_FINAL | BFLAG_FILL TARGET ADDRESS = 0xFF80 0000 0x2000 0350 Fills L1 data bank 0 BYTE COUNT = 0x0000 8000 ARGUMENT = 0xA5A5 A5A5 0x2000 0360 32-bit fill value BLOCK CODE = 0xADB4 5006 First block of second application DXE BFLAG_FIRST|BFLAG_IGNORE TARGET ADDRESS = 0xFFA0 0000 Start address of application BYTE COUNT = 0x0000 0000 No bubble ARGUMENT = 0x0000 1000 Next DXE pointer Further boot stream of second application DXE (0x1000 bytes total) 0x2000 1370 Figure 17-9. Multi-DXE Boot Stream Example for Flash Boot 17-54 ADSP-BF52x Blackfin Processor Hardware Reference Figure 17-10. LdrViewer Screen Shot Boot management principles are not only applicable to multi-DXE boot streams. The same scheme, as shown in Figure 17-11 on page 17-56, can be applied to direct code executions of multiple applications. See “Direct Code Execution” on page 17-34 for more information. The example shows a linked list of initial block headers that instruct the boot kernel to ADSP-BF52x Blackfin Processor Hardware Reference 17-55 terminate immediately and to start code execution at the address provided by the TARGET ADDRESS field of the individual blocks. There is nothing in the boot ROM that prevents multi-DXE applications from mixing regular boot streams and direct code execution blocks. BLOCK CODE = 0xAD5A D006 TARGET ADDRESS = 0x2000 0100 BYTE COUNT = 0x0000 0010 ARGUMENT = 0x0000 0010 Optional 16-byte bubble BLOCK CODE = 0xAD5A D006 TARGET ADDRESS = 0x2001 0000 BYTE COUNT = 0x0000 0000 ARGUMENT = 0x0000 0000 BLOCK CODE = 0xAD59 D006 TARGET ADDRESS = 0x2002 0000 BYTE COUNT = 0x0000 0000 ARGUMENT = 0x0000 0000 Application 0 at 0x2000 0100 Application 1 at 0x2001 0000 Application 2 at 0x2002 0000 Figure 17-11. Multi-DXE Direct Code Execution Arrangement Example 17-56 ADSP-BF52x Blackfin Processor Hardware Reference D etermining Boot Stream Start Addresses The ROM functions BFROM_MEMBOOT, BFROM_TWIBOOT, BFROM_SPIBOOT, etc. not only allow the application to boot a subroutine residing at a given start address, they also assist in walking through linked multi-DXE streams. When the BFLAG_NEXTDXE bit in dFlags is set and these functions are called, the system does not boot but instead walks though the boot stream following the next-DXE pointers. The dBlockCount parameter can be used to specify the DXE of interest. The routines then return the start address of the requested DXE’s boot stream. Initialization Hook Routine When the ROM functions BFROM_MEMBOOT, BFROM_SPIBOOT, etc. are called, they create an instance of the ADI_BOOT_DATA structure on the stack and fill the items with default values. If the BFLAG_HOOK is set, the boot kernel invokes a callback routine which was passed as the fourth argument of the ROM routines, after the default values have been filled. The hook routine can be used to overwrite the default values. Every hook routine should fit the prototype: void hook (ADI_BOOT_DATA* pBS); The VisualDSP++ header files define the ADI_BOOT_HOOK_FUNC type the following way: typedef void ADI_BOOT_HOOK_FUNC (ADI_BOOT_DATA*); The hook function also gives access to the DMA load function used by the respective boot mode, which can be used for general purposes at runtime. For example, in the BFROM_SPIBOOT case, an instance of the load function: ADI_BOOT_LOAD_FUNC *pSpiLoadFunction; can be initialized by equipping the hook function with the instruction: pSpiLoadFunction = pBS->pLoadFunction; ADSP-BF52x Blackfin Processor Hardware Reference 17-57 S pecific Boot Modes This section discusses individual boot modes and the required hardware connections. The boot modes differ in terms of the booting source— for example whether data is loaded through the SPI or the parallel interface. Boot modes can also be grouped into slave boot modes and master boot modes. In slave boot modes, the Blackfin processor functions as a slave to any host device, which is typically another embedded processor, an FPGA device or even a desktop computer. Likely, the Blackfin processor RESET input is controlled by the host device. So, usually the host sets RESET first, then waits until the preboot routine terminates by sensing the HWAIT output, and finally provides the boot data. If a Blackfin processor, configured to operate in any of the slave boot modes, awakens from hibernate, it cannot boot by its own control. A feedback mechanism has to be implemented at the system level to inform the host device whether the processor is in hibernate state or not. The HWAIT strobe is an important primitive in such systems. In the master boot modes, the Blackfin processor usually does not need to be synchronized and can load the boot data by itself. Master modes typically read from memory. This can be parallel memory such as flash devices, or serial memory that is read through SPI or TWI interfaces. Memory boot modes should also be differentiated from peripheral boot modes. Boot modes that load boot streams through memory DMA are referred to as memory boot mode, reading data from regular memory. Peripheral modes load boot data through peripherals such as UART, TWI or SPI. With the exception of the FIFO boot, which is a hybrid, all memory boot modes are master modes. The boot source is typically non-volatile memory, such as a flash or EPROM device or even on-chip ROM. When supported by the system in warm boot scenarios, the boot source can also be SRAM or SDRAM. 17-58 ADSP-BF52x Blackfin Processor Hardware Reference Whether from the host (slave booting mode) or from memory (master booting mode), the boot source does not need to know about the structure of the boot stream. However in the case of Host DMA boot, the size (BYTE COUNT) of the boot stream should be known. This is because, having much more control over the Blackfin processor, the host must know what data is to be loaded to specific addresses. No Boot Mode When the BMODE pins are all tied low (BMODE = 0000), the Blackfin processor does not boot. Instead it processes factory-programmed OTP pages, then executes an IDLE instruction, preventing it from executing any instructions provided by the regular boot source. The purpose of this mode is to bring the processor up to a clean state after reset. This mode helps to recover from malicious OTP configuration since it prevents execution of the user-controllable portion of the preboot routine. When connecting an emulator and starting a debug session, the processor awakens from an idle due to the emulation interrupt and can be debugged in the normal manner. no boot mode is not bypass TheADSP-BF53x Blackfinthe same as the simulatemode featured by the processor. To that bypass mode feature using BMODE = 0001, see “Direct Code Execution” on page 17-34 and “Direct Code Execution” on page 17-148. Flash Boot Modes These booting modes are intended to boot from flash or EEPROM memories or even from battery-buffered SRAMs. The flash boot modes are ADSP-BF52x Blackfin Processor Hardware Reference 17-59 activated by BMODE = 0001. Although this is a single BMODE setting, the ADSP-BF52x Blackfin products support various configurations. • Boot from 8-bit asynchronous flash memory • Boot from 16-bit asynchronous flash memory By default, the boot kernel does not alter any EBIU registers. Therefore, traditional asynchronous flash is assumed and maximum wait states are applied. By programming OTP half pages PBS00L and PBS00H, the user has the option to instruct the preboot routine to alter the EBIU registers as desired. In this way, the EBIU can be preset to access the flash device in either page mode or burst mode. There are also options to customize bus settings, such as wait states and ARDY behavior. After the preboot routine returns and HWAIT is deasserted the first time, the boot kernel loads an initial burst of four 16-bit words. Then it interrogates the DMACODE field in the byte loaded from the 0x2000 0000 address. For flash mode, the DMA options shown in Table 17-9 are supported. Table 17-9. DMA Options DMACODE DMA Source Comment Width Modify 1 8 1 Not recommended Provides ADSP-BF533 style 8-bit boot from 16-bit flash memory 2 8 2 8-bit MDMA boots from 8-bit flash mapped to lower byte of address bus. 6 16 2 16-bit MDMA boots from 16-bit flash 10 32 4 32-bit MDMA boots from 16-bit flash The DMACODE field is filled by the elfloader utility based on boot mode, -width and -dmawidth settings. See the V isualDSP++ Loader and Utility Manual for details. 17-60 ADSP-BF52x Blackfin Processor Hardware Reference After the boot kernel has loaded and interpreted the first four 16-bit words, it continues loading the rest of the first block header and processes the boot stream. Hardware configurations for the individual modes are shown in Figure 17-12 and Figure 17-13. The chip select is always controlled by the AMS0 strobe. This maps the boot stream to the Blackfin processor’s address 0x2000 0000. BLACKFIN 8-BIT FLASH/PROM AMS0 AMS AOE OE AWE R/W or WR A[N+1:1] ADDR[N:0] D[7:0] DATA[7:0] Figure 17-12. 8-Bit Flash Interconnection 16-BIT FLASH/PROM BLACKFIN AMS0 AMS AOE OE AWE R/W or WR A[N+1:1] ADDR[N:0] D[15:0] DATA[15:0] Figure 17-13. 16-Bit Flash Interconnection ADSP-BF52x Blackfin Processor Hardware Reference 17-61 Some flash devices provide write protection mechanisms, which can be activated during the power-up and reset cycles of the Blackfin processor. In the absence of such mechanisms, a pull-up resistor on the AMS0 strobe prevents the chip select from floating when the state of the processor is unknown. The boot mode BMODE = 0001 can also be used to instruct the boot kernel to terminate immediately and directly execute code from the 16-bit flash memory instead. Code execution from 8-bit flash memory is not supported. See “Direct Code Execution” on page 17-34 for details. AMS0 1 0 1 0 1 0 1 AOE 1 0 1 0 1 0 1 ARE 1 1 010101010101010 1 0101010 1 0 1 0 1 0 1 AWE 1 ADDRESS 0003 DATA FFA0 0004 0005 0006 0000 1 0 0007 0548 RESET HWAIT 0 0008 0009 000A 000B 000C 000D 000E 0000 1 1 000F 0010 0011 0012 0006 AD9C 4000 FF80 0008 1 0 1 0000 1 0 0013 1 1 1 0 1 1 Figure 17-14. 16-bit Flash Mode Waveform 17-62 ADSP-BF52x Blackfin Processor Hardware Reference 0 S DRAM Boot Mode From the boot kernel perspective, the SDRAM boot mode is just another memory boot mode like flash boot. The only differences are that the boot stream is expected at address 0x0000 0010 and the initial eight bytes are loaded by two 32-bit loads. From the application point of view, SDRAM boot is a completely different scheme. Since SDRAM is volatile memory, BMODE = 1010 is not a valid setting when the processor and the memories have just been powered up. This mode can only be used as a dynamically applied BMODE setting to install warm boot scenarios. OTP programming is required to boot from SDRAM. Other boot modes can configure the SDRAM controller by execution of an initcode. But in the case of SDRAM boot, the initcode cannot be loaded without having the SDRAM controller already configured. SDRAM boot is meaningful when the Blackfin processor is in hibernate state or is completely shut off for power savings while the SDRAM is kept alive in self-refresh mode. Users who prefer to execute code out of SDRAM, rather than performing a boot from it, may refer to “Direct Code Execution” on page 17-34 for details. FIFO Boot Mode The FIFO boot mode (BMODE = 0010) boots the Blackfin processor from another processor or FPGA system, referred to as the host device. The host is decoupled from the Blackfin bus by an asynchronous FIFO memory. When compared to the glue-less Host DMA boot modes, the FIFO mode requires less intelligence from the host. The host device is only expected to handshake with the FIFO and to load the entire boot stream in 16-bit portions. There is no need for the host to know about the content and format of the boot stream. ADSP-BF52x Blackfin Processor Hardware Reference 17-63 The hardware configuration for the FIFO boot mode is shown in Figure 6-3 on page 6-40. The FIFO chip select connects to the AMS3 strobe. Data read requests go to the DMAR1 input on pin PG12. The host device controls the Blackfin processor's RESET input. As in all slave modes, the host device should not send requests to DMAR1 unless the HWAIT signal goes inactive. The host device may optionally rely on HWAIT edges to continue or discontinue transmission of boot data in an interrupt controlled manner. From the boot kernel perspective the FIFO boot mode (BMODE = 0010) is just another memory boot mode, the only exception being that the HMDMA1 block is enabled in advance. Activating this functionality makes the FIFO boot mode become a slave mode. The bits set in the HMDMA1_CONTROL register are REP and HMDMAEN. Since the ADSP-BF52x products do not support the SND bit as the ADSP-BF54x products do, the FIFO boot mode requires further precautions. In the FIFO boot mode, the DMACODE field in the boot block headers must always be 0x06, which instructs the boot kernel to perform 16-bit DMA. The boot kernel increments the applied addresses as if reading from flash memory. Regardless of the HMDMA settings, the source channel of the memory DMA prefetches four 32-bit words as soon as enabled. Only the transmit channel is stalled and triggered by the HMDMA module. In 16-bit DMA mode, these four early reads translate to eight 16-bit reads. The ADSP-BF52x boot kernel ensures that at least 16 valid data words are ready in the external FIFO—by first counting eight rising edges on the DMAR1 request input and then disabling the HMDMA module. When HMDMA is later re-enabled, the prefetch will find valid data and the MDMA can be started safely. This method requires that the host send 16 more request strobes after it has sent the complete boot stream to the FIFO. This is because the trans- 17-64 ADSP-BF52x Blackfin Processor Hardware Reference mit channel of the DMA still has to drain the FIFO, which must be protected from underflow at start. SPI Master Boot Modes The SPI boot mode (BMODE = 0011) boots from SPI memories connected to the SPISEL1 interface. 8-, 16-, 24-, and 32-bit address words are supported. Standard SPI memories are read using either the standard 0x03 SPI read command or the 0x0B SPI fast read command. other Blackfin Unlike have no specialprocessors, the ADSP-BF52x Blackfin processors support for DataFlash devices from Atmel. Nevertheless, DataFlash devices can be used for booting and are sold as standard 24-bit addressable SPI memories. They also support the fast read mode. If used for booting, DataFlash memory must be programmed in the power-of-2 page mode. For booting, the SPI memory is connected as shown in Figure 17-15. BLACKFIN (MASTER SPI DEVICE) SPI MEMORY (SLAVE SPI DEVICE) VDDEXT 10K 10K SPI SCK (PG2) SCK SPISEL1 (PG1) CS SPI MOSI (PG4) MOSI SPI MISO (PG3) MISO Figure 17-15. Blackfin to SPI Memory Connections The pull-up resistor on the MISO line is required for automatic device detection. The pull-up resistor on the SPISEL1 line ensures that the memory is in a known state when the Blackfin GPIO is in a high-impedance ADSP-BF52x Blackfin Processor Hardware Reference 17-65 state (for example, during reset). A pull-down resistor on the SPISCK line displays cleaner oscilloscope plots during debugging. For SPI master boot, the SPE, MSTR and SZ bits are set in the SPI_CTL register. For details see Chapter 22, “SPI-Compatible Port Controller”. With TIMOD = 2, the receive DMA mode is selected. Clearing both the CPOL and CPHA bits results in SPI mode 0. The boot kernel does not allow SPI hardware to control the SPISEL1 pin. Instead, this pin is toggled in GPIO mode by software. Initialization code is allowed to manipulate the uwSsel variable in the ADI_BOOT_DATA structure to extend the boot mechanism to a second SPI memory connected to another GPIO pin. By default, the boot kernel sets the SPI_BAUD register to a value of 133, resulting in a bit rate of SCLK/266. This default value can be altered by programming the 4-bit OTP_SPI_BAUD field in OTP page PBS00L to one of the values in Table 17-10. Table 17-10. Bit Rate OTP_SPI_BAUD SPI_BAUD Bit Rate b#0000 133 SCLK/(2x133) b#0001 Reserved b#0010 2 SCLK/(2x2) b#0011 4 SCLK/(2x4) b#0100 8 SCLK/(2x8) b#0101 16 SCLK/(2x16) b#0110 32 SCLK/(2x32) b#0111 64 SCLK/(2x64) Similarly, the boot kernel uses the standard 0x03 SPI read command, by default. Programming the OTP_SPI_FASTREAD bit in OTP page PBS00L enables the fast read mode where the boot kernel uses the 0x0B read command instead and transmits a dummy zero byte after the address bytes. 17-66 ADSP-BF52x Blackfin Processor Hardware Reference S PI Device Detection Routine Since BMODE = 0011 supports booting from various SPI memories, the boot kernel automatically detects what type of memory is connected. To determine whether the SPI memory device requires an 8-, 16-, 24- or 32-bit addressing scheme, the boot kernel performs a device detection sequence prior to booting. The MISO signal requires a pull-up resistor, since the routine relies on the fact that memories do not drive their data outputs unless the right number of address bytes are received. Initially, the boot kernel transmits a read command (either 0x03 or 0x0B) on the MOSI line, which is immediately followed by two zero bytes. Once the transmission is finished, the boot kernel interrogates the data received on the MISO line. If it does not equal 0xFF (usually a DMACODE value of 0x01 is expected), then an 8-bit addressable device is assumed. If the received value equals 0xFF, it is assumed that the memory device has not driven its data output yet and that the 0xFF value is due to the pull-up resistor. Thus, another zero byte is transmitted and the received data is tested again. If it differs from 0xFF, either a 16-bit addressable device (standard mode) or an 8-bit addressable device (fast read mode) is assumed. If the value still equals 0xFF, device detection continues. Device detection aborts immediately if a byte different than 0xFF is received. The boot kernel continues with normal boot operation and it re-issues a read command to read from address 0 again. The first block header is loaded by two read sequences, further block headers and block payload fields are loaded by separate read sequences. ADSP-BF52x Blackfin Processor Hardware Reference 17-67 Figure 17-16 illustrates how individual devices would behave. MOSI 0x03 |0x0B 0x00 0x00 MISO 0xFF 0xFF 0x01 MISO 0xFF 0xFF 0xFF 0x01 ... MISO 0xFF 0xFF 0xFF 0xFF 0x01 ... MISO 0xFF 0xFF 0xFF 0xFF 0xFF 0x01 MISO 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 ... STANDARD 8-BIT STANDARD 16-BIT, FAST READ 8-BIT STANDARD 24-BIT, FAST READ 16-BIT ... 0x01 STANDARD 32-BIT, FAST READ 24-BIT FAST READ 32-BIT Figure 17-16. SPI Device Detection Principle Figure 17-17 on page 17-69 shows the initial signaling when a 24-bit addressable SPI memory is connected in SPI master boot mode. After RESET releases and preboot has processed relevant OTP pages, a 0x03 command is transmitted to the MOSI output, followed by a number of 0x00 bytes. The 24-bit addressable memory device returns a first data byte at 17-68 ADSP-BF52x Blackfin Processor Hardware Reference the fourth zero byte. Then, the device detection has completed and the boot kernel re-issues a 0x00 address to load the boot stream. SPICLK SEL MOSI MISO HWAIT RESET Figure 17-17. Typical SPI Master Boot Waveforms SPI Slave Boot Mode For SPI slave mode boot (BMODE = 0100), the Blackfin processor is consuming boot data from an external SPI host device. The hardware configuration is shown in Figure 17-18. As in all slave boot modes, the host device controls the Blackfin processor RESET input. HOST (MASTER SPI DEVICE) SPICLK S_SEL VDDEXT BLACKFIN (SLAVE SPI DEVICE) SPI SCK (PG2) SPI SS (PG1) MOSI SPI MOSI (PG4) MISO SPI MISO (PG3) FLAG/INTERRUPT HWAIT (PG0) Figure 17-18. Connectio