# hw10 - 2 3 4 Y 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

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Electrical and Computer Engineering Department University of Maryland College Park, MD 20742-3285 Glenn L. Martin Institute of Technology d A. James Clark School of Engineering Dr. Charles B. Silio, Jr. Telephone 301-405-3668 Fax 301-314-9281 [email protected] ENEE 244 Homework Set 10 (Due: Class 22, Tues., Nov. 15, 2011) 1. Assume the gate propagation delay for each gate is 1 time unit, and draw the timing diagram for all of the gate outputs in response to the input signals (A, B, C) shown. 1 B C A 2 3 4 Y 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Time in units of gate delay B C 1 2 3 Y A 1

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2. Assume the gate propagation delay for each gate is 1 time unit, and draw the timing diagram for all of the gate outputs in response to the input signals (A and B) shown.
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Unformatted text preview: 2 3 4 Y 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Time in units of gate delay B A 1 A B 1 2 3 Y 2 3. Assume the gate propagation delay for each gate is 1 time unit, and draw the timing diagram for all of the gate outputs in response to the input signals (A and B) shown. Assume A(t) = B(t) = 0, t < 0. 1 1 1 1 1 Time in units of gate delay B A 1 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Y 3 2 1 A B Y Read all of Section 6.8 of Givone and read Sections 7.3.3–7.5.2; then work the following problems: 4. Prob. 6.22. 5. Prob. 6.23. 6. Prob. 6.27. 7. Prob. 6.28. 8. Prob. 6.30. 9. Prob. 7.7. 10. Prob. 7.12. 3...
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## This note was uploaded on 02/02/2012 for the course ELECTRICAL ENEE244 taught by Professor C.silio during the Fall '11 term at Maryland.

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hw10 - 2 3 4 Y 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

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