Unformatted text preview: (1) K v = 600 sec-1 (2) Phase margin ≥ 50 ◦ (3) Gain margin ≥ 10 db. (a) Design a series compensator G c ( s ) that will make the system satisfy the above speciﬁ-cations. (b) Repeat (a) with a phase-lead network and discuss the performance of the compensated system. Final Exam Schedule and Information Date: Monday, March 8, 2010 Time: 4:30 – 6:30 PM Place: EE 234 Materials: • The exam covers “everything” and is a closed-book exam. At least 20% of the exam material will come from the “compensator design” lectures. • You can bring in a SIMPLE calculator. • The exam format will be the same as previous tests, consisting of True/False questions, multiple-choice questions, and analytical problems, etc. • A formula sheet will be given at the exam for your reference....
View Full Document
- Spring '08
- Signal Processing, Gain margin, Phase margin