Chapter 05 - MSP430 ISA

Chapter 05 - MSP430 ISA - Chapter 5 MSP430 ISA The...

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Unformatted text preview: Chapter 5 MSP430 ISA The Instruction Set BYU CS/ECEn 124 Chapter 05 - MSP430 ISA 2 Where Are We? Problems Algorithms Language (Program) Machine (ISA) Architecture Micro-architecture Circuits Devices Programmable Computer Specific Manufacturer Specific The Gap BYU CS/ECEn 124 Chapter 05 - MSP430 ISA 3 Instruction Set Architecture The computer ISA defines all of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). MSP430 ISA BYU CS/ECEn 124 Chapter 05 - MSP430 ISA 4 MSP430 Instruction Set Architecture Implements RISC architecture with 27 instructions and 7 addressing modes. Orthogonal architecture with every instruction usable with every addressing mode. Sixteen 16-bit registers Single-cycle register operations. Reduces fetches to memory. Full access to program counter, status register, and stack pointer. 16-bit address bus (address space) allows direct access and branching throughout entire 64KB memory range. 16-bit, byte addressable (addressability) data bus allows direct manipulation of word-wide arguments. Word and byte addressing and instruction formats. MSP430 ISA BYU CS/ECEn 124 Chapter 05 - MSP430 ISA 5 MSP430 Registers R0 (PC) Program Counter This register always points to the next instruction to be fetched Each instruction occupies an even number of bytes. Therefore, the least significant bit (LSB) of the PC register is always zero. After fetch of an instruction, the PC register is incremented by 2, 4, or 6 to point to the next instruction. R1 (SP) Stack Pointer The MSP430 CPU stores the return address of routines or interrupts on the stack User programs store local data on the stack The SP can be incremented or decremented automatically with each stack access The stack grows down thru RAM and thus SP must be initialized with a valid RAM address SP always points to an even address, so its LSB is always zero MSP430 ISA BYU CS/ECEn 124 Chapter 05 - MSP430 ISA 6 MSP430 Registers R2 (SR/CG1) Status Register The status of the MSP430 CPU is contained in register R2 Only accessable through register addressing mode - all other addressing modes are reserved to support the constants generator MSP430 ISA Carry bit C Zero bit Z Negative bit N General interrupt enable GIE Turns off the CPU. CPUOFF Oscillator off OSCOFF Turns off the DCO dc generator. SCG0 Turns off the SMCLK. SCG1 Overflow bit V R3 (CG2) Constant Generator R4-R15 General Purpose registers Register As Constant Remarks R2 00...
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Chapter 05 - MSP430 ISA - Chapter 5 MSP430 ISA The...

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