Chapter 06 - MSP430 Micro-Architecture

Chapter 06 - MSP430 Micro-Architecture - Chapter 6 MSP430...

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Chapter 6 – MSP430 Micro-Architecture
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 2 Levels of Transformation Problems Algorithms Language (Program) Machine (ISA) Architecture Microarchitecture Circuits Devices Programmable Computer Specific Manufacturer Specific
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 3 Topics to Cover… MSP430 Micro-Architecture Instruction Cycle Review Fetch Cycle Source Addressing Modes Evaluate Source Operand Destination Addressing Modes Evaluate Destination Operand Execute Cycle Store Cycle Instruction Clock Cycles Digital I/O
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 4 MSP430 Modular Architecture MSP430 Micro-Architecture
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 5 Micro-Architecture Simulator Memory Address Register Arithmetic Logic Unit Program Counter Address Bus Data Bus Condition Codes Memory Port 1 Output Instruction Register Source Operand Destination Operand MSP430 Micro-Architecture
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 6 The Instruction Cycle INSTRUCTION FETCH Obtain the next instruction from memory DECODE Examine the instruction, and determine how to execute it SOURCE OPERAND FETCH Load source operand DESTINATION OPERAND FETCH Load destination operand EXECUTE Carry out the execution of the instruction STORE RESULT Store the result in the designated destination Not all instructions require all six phases Instruction Cycle
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 7 Fetching an Instruction PC Fetch Cycle PC can be  incremented  anytime during  the Fetch phase
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 8 Source Addressing Modes The MSP430 has four basic modes for the source address: Rs - Register x(Rs) - Indexed Register @Rs - Register Indirect @Rs+ - Indirect Auto-increment In combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) – Absolute, x(SR) #n – Immediate, @PC+ Source Addressing Modes
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 9 Register Addressing Mode Evaluate Source Operand
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 10 Source: Register Mode Rs Rs Evaluate Source Operand Select the generic  source register
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 11 Register-Indexed Addressing Mode Evaluate Source Operand
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 12 Source: Indexed Mode x(Rs) Rs PC PC PC incremented  at end of phase Evaluate Source Operand Use PC to obtain  index, use Rs for  base register
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 13 Symbolic Addressing Mode Evaluate Source Operand
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BYU CS/ECEn 124 Chapter 6 - MSP430 Micro-Architecture 14 Source: Symbolic Mode
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This document was uploaded on 02/06/2012.

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Chapter 06 - MSP430 Micro-Architecture - Chapter 6 MSP430...

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