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Unformatted text preview: Architecture of the MSP430 Processor 141 Peculiarities : There are tests for the conditions < and ≥ but not for ≤ nor > . It may be possible to choose the source and destination in a comparison to avoid this problem. Unfortunately the asymmetric addressing modes often prevent this, particularly if one value is immediate. Two tests may then be necessary. 5.4.5 Instruction Timing The number of MCLK cycles required for most instructions is limited by access to memory. This is a typical feature of a RISC-like CPU with a von Neumann architecture and also applies to the ARM7, for instance. Values for typical instructions are listed in Table 5.1 but there are several exceptions, including instructions that change the ﬂow of control and those where the destination is PC. The general principle for Format I instructions (two operands) is as follows. Most of these must read the instruction and two operands from memory and write the result back. The duration is set by the modes used to address memory for the operands.address memory for the operands....
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This document was uploaded on 02/06/2012.
- Winter '09