MSP430_Microcontroller_Basics_Chapter 5.4-5

MSP430_Microcontroller_Basics_Chapter 5.4-5 - 132 Chapter 5...

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132 Chapter 5 used in comparison, arithmetic, and logic operations and for masks to pick out bits 0–3. It is no accident that the most commonly tested bits in the status register are in these positions (Figure 5.3) and the same is true for registers in other modules. For example, direct (register) addressing of R3/CG2 returns the value 0, so mov.w R3,R5 clears R5. Similarly, mov.w @R2,R5 uses indirect addressing on R2/SR /CG1, which returns the value 8 and this will be stored in R5. These constants are combined with many of the 27 native instructions to provide a further 24 emulated instructions. They can be written in the same way as “real” instructions and the assembler converts them to native instructions with the appropriate constant from CG1 or CG2. A problem with this approach is that the constants can be used only as the source. The other operand is therefore a destination with restricted addressing modes, which can sometimes be a nuisance. Do not attempt to use any of the constant generators as a destination. This applies even in cases where the destination is not changed. It is tempting to try this for instructions such as comparison, but it is not allowed. Of course R2 may be used as a destination in register mode, when it acts as SR rather than CG1. Absolute addressing can de±nitely be used for the destination, which effectively uses CG1 as base. Neither mode works for CG2 as destination. 5.4 Instruction Set The instructions are thoroughly documented in the section “RISC 16-Bit CPU” of the family user’s guides. The MSP430 has 27 native instructions, and a further 24 emulated instructions are de±ned to make life easier for the programmer. These include common operations such as “clear,” which is implemented as an ordinary move with a value of 0 provided by the constant generator. I list all instructions for completeness but concentrate on the unusual features and traps for the unwary. The instruction set is orthogonal with few exceptions, meaning that all addressing modes can be used with all instructions and registers. I show the .w form for operations that can use either bytes or words. Aside : It sounds as though the MSP430 has fewer instructions than the PIC16 with 35, but trivial comparisons of radically different processors are always misleading. It might be more accurate to say that the PIC has 28 instructions with up to three addressing modes. For example, the operand for arithmetic and logic instructions can be a literal value, taken from a register whose address is given explicitly, or in a register whose address is speci±ed indirectly in FSR.
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Architecture of the MSP430 Processor 133 5.4.1 Movement Instructions There is only the one mov instruction to move data. It can address all of memory as either source or destination, including both registers in the CPU and the whole memory map.
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MSP430_Microcontroller_Basics_Chapter 5.4-5 - 132 Chapter 5...

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