MSP430_Microcontroller_Basics_Chapter 8.6-7

MSP430_Microcontroller_Basics_Chapter 8.6-7 - 330 Chapter 8...

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330 Chapter 8 by one interval of two cycles. (The frequency would be 877.7 Hz if this pattern were the exact output.) The two durations are clear on the oscilloscope trace. The signal sounds terrible and is quite unusable, even if its average frequency is mathematically correct. The signal contains so many harmonics that the ear does not focus on the desired tone of 440 Hz. In fact it sounds closer to the note C than A. For those who are interested, I plotted the power spectra of the signals from timer clocks of 1 KHz and 8 KHz in Figure 8.8(b). The plot for 1 KHz is better as an example of a spread-spectrum signal than an aid to tuning. I had to modify the program that used a 1 KHz clock because of a flaw in the design of Timer_A. This is documented as Bug TA12 in the errata to the data sheet for the F1121A. It affects Timer_A in all devices, as far as I know. The problem is that the next interrupt is lost if a capture/compare register TACCRn is incremented by only 1. There is nothing wrong in principle with doing this provided that the timer clock is slow compared with MCLK and there is a factor of 1000 between the frequencies in my program. However, the bug causes the next interrupt to be lost. A workaround is suggested in the errata. The moral of this is to check the errata if something strange seems to be happening: It may not be your program. Example 8.21 You might like to try this out and hear how the sound changes as a function of the frequency of the timer clock. 8.6 Output in the Up Mode: Edge-Aligned Pulse-Width Modulation The period of Timer_A is set by TACCR0 in the Up mode, rather than cycling through its natural range of 0x0000–0xFFFF. This offers precise control of the period but the capabilities of channel 0 are greatly restricted. The major advantage of the Up mode is that periodic outputs can be produced completely automatically in hardware, without any intervention from software after Timer_A has been con±gured. Thus the MSP430 can be left undisturbed in LPM3 if ACLK is used for Timer_A. This contrasts with the Continuous mode, where a new Compare value must be calculated in an ISR after each match has occurred. Because of the special nature of TACCR0, the notation TACCRn implies n 1 throughout this section. www.newnespress.com
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Timers 331 4 TAR TAIFG CCIFG0 CCIFG1 OUT0 (Toggle, 4) OUT1 (Reset/Set, 7) OUT1 (Set/Reset, 3) reset set set reset toggle period 0123401234 Figure 8.9: Sketch of output from channels 0 and 1 of Timer_A in an Up mode. Channel 0 is in the Toggle mode with TACCR0 = 4. The output from channel 1 is shown for both Reset/Set and Set/Reset modes with TACCR1 = 2. Figure 8.9 shows the behavior of TAR in the Up mode with possible outputs from a normal channel (1) and the special channel 0. I have chosen TACCR0 = 4 and TACCR1 = 2. These are the main features: TAR counts from 0 up to the value in TACCR0, which is 4 here, and returns to 0 to start a new cycle on the next clock transition. The period is therefore TACCR0 + 1 = 5 counts.
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MSP430_Microcontroller_Basics_Chapter 8.6-7 - 330 Chapter 8...

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