MSP430_Microcontroller_Basics_Chapter 10.7

MSP430_Microcontroller_Basics_Chapter 10.7 - 534 Chapter 10...

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534 Chapter 10 transmission. The results were strange because of the problems that I mentioned in the section “Digital Input and Output: Parallel Ports” on page 208. Enabling the pull resistor removes the full drive from the pin, so the sharp edges in Figure 10.10 become rounded because of the time required to charge the capacitances in the circuit. Another curious effect is that USIOE ceases to have any influence. Nor is the line pulled up when idle, so the experiment was not a success. I mention this only because pull-ups work well with I²C, as we see in the next sections. 10.7 Inter-integrated Circuit Bus The I²C bus was introduced by Philips (now NXP) Semiconductors. It was widely adopted and has become even more popular since its patents expired in 2006. It is a true bus, unlike SPI, with a speci±cation and user manual that can be downloaded from NXP. Revision 03 of the user manual is document UM10204, dated June 19, 2007. It is clearly written and a lot easier to read than you might expect. The I²C bus uses only two, bidirectional lines: Serial data (SDA). Serial clock (SCL). Of course there must be a connection for ground as well. It is often called the two-wire interface . Thus I²C provides the full functionality of a bus while using fewer lines than SPI. Inevitably there are penalties. The ±rst is that it is slow, only 100 kbit/sec in standard mode, because of the electrical arrangements needed to avoid damage if two nodes attempt to transmit simultaneously. Second, a protocol must be observed: You cannot merely transmit the data and nothing more, as in SPI. More hardware is needed than a simple shift register and transmissions must be controlled by logic such as a state machine. This may be implemented either in hardware, as in the USCI_B, or in software for the USI. Transfers on the bus take place between a master and a slave. Each slave has a unique address, which is usually 7 bits long. The master starts the transfer, provides the clock, addresses a particular slave, manages the transfer, and ±nally terminates it. There may be more than one master on the bus although only one can be in control at a time. I do not describe multimaster buses in any detail because most systems with I²C have only a single master and a few slaves—sometimes just one. SPI would be simpler in this case but I²C saves pins. www.newnespress.com
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Communication 535 10.7.1 Hardware for I²C The electronic interface to the I²C bus is shown in Figure 10.11 for a master and two slaves. A full-featured slave has the same hardware as a master but most are simpler and cannot drive the clock line SCL. On the other hand, slaves must always be able to drive SDA even if they receive only data as in a DAC, for instance. Digital outputs are normally driven actively for both their binary values, either to V SS for logic 0 or to V CC for logic 1. This was described in the section “Digital Outputs” on page 238. Problems clearly arise if two such outputs are connected together on a bus and attempt to drive it to different values. The I²C bus avoids this by using active devices to
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MSP430_Microcontroller_Basics_Chapter 10.7 - 534 Chapter 10...

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