MSP430x2xx Family User's Guide - Watchdog Timer+

MSP430x2xx Family User's Guide - Watchdog Timer+ - Chapter...

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10-1 Watchdog Timer+ Watchdog Timer+ The watchdog timer+ (WDT+) is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the WDT+ The WDT+ is implemented in all MSP430x2xx devices. Topic Page 10.1 Watchdog Timer+ Introduction 10-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Watchdog Timer+ Operation 10-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Watchdog Timer+ Registers 10-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 10
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Watchdog Timer+ Introduction 10-2 Watchdog Timer+ 10.1 Watchdog Timer+ Introduction The primary function of the watchdog timer+ (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Features of the watchdog timer+ module include: - Four software-selectable time intervals - Watchdog mode - Interval mode - Access to WDT+ control register is password protected - Control of RST /NMI pin function - Selectable clock source - Can be stopped to conserve power - Clock fail-safe feature The WDT+ block diagram is shown in Figure 10−1. Note: Watchdog Timer+ Powers Up Active After a PUC, the WDT+ module is automatically configured in the watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK. The user must setup or halt the WDT+ prior to the expiration of the initial reset interval.
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Watchdog Timer+ Introduction 10-3 Watchdog Timer+ Figure 10−1. Watchdog Timer+ Block Diagram WDTQn Y 0 1 2 3 Q6 Q9 Q13 Q15 16−bit Counter CLK A B 1 1 AE N PUC SMCLK ACLK Clear Password Compare 0 0 0 0 1 1 1 1 WDTCNTCL WDTTMSEL WDTNMI WDTNMIES WDTIS1 WDTSSEL WDTIS0 WDTHOLD EQU EQU Write Enable Low Byte R / W MDB LSB MSB WDTCTL (Asyn) Int. Flag Pulse Generator SMCLK Active MCLK Active ACLK Active 16−bit Fail-Safe Logic Clock Request Logic MCLK
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Watchdog Timer+ Operation 10-4 Watchdog Timer+ 10.2 Watchdog Timer+ Operation The WDT+ module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST /NMI pin. WDTCTL is a 16-bit, password-protected, read/write register. Any read or write access must use word instructions and write accesses must include the write password 05Ah in the upper byte. Any write to WDTCTL with any value other than 05Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of timer mode. Any read of WDTCTL reads 069h in the upper byte. The WDT+ counter clock should be slower or equal than the system (MCLK) frequency.
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MSP430x2xx Family User's Guide - Watchdog Timer+ - Chapter...

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