slau049f - MSP430x1xx Family User's Guide (Chapter 3)

slau049f - MSP430x1xx Family User's Guide (Chapter 3) -...

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3-1 RISC 16-Bit CPU RISC 16ĆBit CPU This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic Page 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 CPU Registers 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Addressing Modes 3-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Instruction Set 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 3
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CPU Introduction 3-2 RISC 16-Bit CPU 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: - RISC architecture with 27 instructions and 7 addressing modes. - Orthogonal architecture with every instruction usable with every addressing mode. - Full register access including program counter, status registers, and stack pointer. - Single-cycle register operations. - Large 16-bit register file reduces fetches to memory. - 16-bit address bus allows direct access and branching throughout entire memory range. - 16-bit data bus allows direct manipulation of word-wide arguments. - Constant generator provides six most used immediate values and reduces code size. - Direct memory-to-memory transfers without intermediate register holding. - Word and byte addressing and instruction formats. The block diagram of the CPU is shown in Figure 3-1.
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CPU Introduction 3-3 RISC 16-Bit CPU Figure 3-1. CPU Block Diagram 0 15 MDB - Memory Data Bus Memory Address Bus - MAB 16 Zero, Z Carry, C Overflow, V Negative, N 16-bit ALU dst src R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R3/CG2 Constant Generator R2/SR/CG1 Status R1/SP Stack Pointer R0/PC Program Counter 0 0 16 MCLK
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CPU Registers 3-4 RISC 16-Bit CPU 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the 64-KB address space are performed on word boundaries, and the PC is aligned to even addresses. Figure 3-2 shows the program counter. Figure 3-2. Program Counter 0 15 0 Program Counter Bits 15 to 1 1 The PC can be addressed with all instructions and addressing modes. A few examples: MOV #LABEL,PC ; Branch to address LABEL MOV LABEL,PC ; Branch to address contained in LABEL MOV @R14,PC ; Branch indirect to address in R14
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CPU Registers 3-5 RISC 16-Bit CPU 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes. Figure 3-3 shows the SP. The SP is initialized into RAM by the user, and is aligned to even addresses.
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slau049f - MSP430x1xx Family User's Guide (Chapter 3) -...

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