Chapter 05 - MSP430 ISA

Chapter 05 - MSP430 ISA - Chapter 5 – MSP430 ISA The...

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Unformatted text preview: Chapter 5 – MSP430 ISA The Instruction Set BYU CS/ECEn Chapter 05 - MSP430 ISA 2 Topics to Cover… n MSP430 ISA n Instruction Formats n Double Operand Instructions n Single Operand Instructions n Jump Instructions n Addressing Modes n Instruction Disassembly n Emulated Instructions BYU CS/ECEn Chapter 05 - MSP430 ISA 3 Problem Machine More concrete, machine-dependent; error prone, harder to write, read, debug, maintain Abstract, machine-independent; easier to write, read, debug, maintain Assembler 415E 0001 410F 532F 5F0E 4EE1 0000 415E 0001 531E 410F 532F 5F0E 415D 0001 410F 532F 5F0D 4EED 0000 415F 0001 531F 410E 532E 5F0E 41EE 0000 Machine language instructions Instruction = Many cycles Levels of Transformation Compiler MOV.B 0x0001(SP),R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B @R14,0x0000(SP) MOV.B 0x0001(SP),R14 INC.W R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B 0x0001(SP),R13 MOV.W SP,R15 INCD.W R15 ADD.W R15,R13 MOV.B @R14,0x0000(R13) MOV.B 0x0001(SP),R15 INC.W R15 MOV.W SP,R14 INCD.W R14 ADD.W R15,R14 MOV.B @SP,0x0000(R14) Assembly language instructions One statement = Many instructions Coder lampDoesntWork() { if(unPlugged) { plugin(); } else if(burnedOut) { replace(); } else { buyNewLamp(); } } High-level language statements One algorithm = Many statements Algorithm Problem solved by Algorithm Engineer Problem Problem BYU CS/ECEn Chapter 05 - MSP430 ISA 4 Instruction Set Architecture n The computer ISA defines all of the programmer-visible components and operations of the computer n Memory organization n address space -- how may locations can be addressed? n addressibility -- how many bits per location? n Register set n how many? what size? how are they used? n Instruction set n opcodes n data types n addressing modes n ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). MSP430 ISA BYU CS/ECEn Chapter 05 - MSP430 ISA 5 MSP430 ISA n RISC/CISC machine n 27 orthogonal instructions n 8 jump instructions n 7 single operand instructions n 12 double operand instructions n 7 addressing modes. n 8/16-bit instruction addressing formats. n Memory architecture n 16 16-bit registers n 16-bit Arithmetic Logic Unit (ALU). n 16-bit address bus (64K address space) n 16-bit data bus (8-bit addressability) n 8/16-bit peripherals MSP430 ISA BYU CS/ECEn Chapter 05 - MSP430 ISA 6 MSP430 Registers n R0 (PC) – Program Counter n This register always points to the next instruction to be fetched n Each instruction occupies an even number of bytes. Therefore, the least significant bit (LSB) of the PC register is always zero. n After fetch of an instruction, the PC register is incremented by 2, 4, or 6 to point to the next instruction....
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Chapter 05 - MSP430 ISA - Chapter 5 – MSP430 ISA The...

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