Lec summary module2

Lec summary module2 - ECE 362 Microprocessor System Design...

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Unformatted text preview: ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 1 Lecture Summary Module 2-A Bus Timing Analysis introduction bus signal definitions o bus clock o address bus o data bus o read/write o ready generic CPU-memory interface circuit (see notes), 9S12 bus signal preview generic CPU timing parameters (read/write) o common to both read and write cycles & t CY & t AD & t AH o read cycle & t RS & t RH o write cycle & t DD & t WH & t WZ generic memory timing parameters (input/output) o read cycle & t AA & t CE & t OE & t OH & t OZ o write cycle & t IS & t IH & t AW & t CW & t WP ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 2 CLK R/W OE ADDR CE DATA CLK R/W WE ADDR CE DATA practice drawing successive synchronous read cycles practice drawing successive synchronous write cycles ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 3 critical path assessment read cycle (see diagram on next page) o t AA o t CE o t OE reason why write paths usually not critical (but, should check anyway!) timing margin o definition o what is meant by the term nominal o why needed o typical/safe margin o consequence of insufficient margin potential consequences of excessive float delay homework practice: draw read cycle followed by write cycle ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 4 CLK R/W OE ADDR CE DATA t CY t AD t AH t RS t RH t OH t OZ t OE t AA t CE Successive Synchronous Read Cycles read timing margin where SRAM thinks read occurs 0 20 40 60 80 100 120 140 160 180 200 Description Parameter Value Address access time t AA 80 ns min Chip enable access time t CE 80 ns min Output enable access time t OE 20 ns min Output hold from OE/CE negation or address change t OH 10 ns min Output float delay following t OH t OZ 10 ns max Input (write) data setup time t IS 30 ns min Input (write) data hold time t IH 20 ns min Write pulse width t WP 40 ns min Address valid prior to memory write t AW 90 ns min Chip enable valid prior to memory write t CW 80 ns min Description Parameter Value Bus clock period t CY 200 ns Address generation delay t AD 30 ns Address hold time t AH 20 ns Read setup time t RS 30 ns Read hold time t RH 20 ns Write data generation delay t DD 80 ns Write hold time t WH 30 ns Write float delay (after t WH ) t WZ 10 ns CLK R/W WE ADDR CE DATA t CY t AH where write to memory occurs t AD t IS t IH t DD t WH t WZ t WP t AW t CW Successive Synchronous Write Cycles write timing margin 0 20 40 60 80 100 120 140 160 180 200 CPU Timing Parameters: Memory Timing Parameters: ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 5 Lecture Summary Module 2-B 9S12C Multiplexed Bus Expansion introduction o this is the hardest material covered in ECE 362 learn it, love it, live it o bus expansion = interfacing external memory and/or memory mapped I/O devices...
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Lec summary module2 - ECE 362 Microprocessor System Design...

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