Lec summary module3a

Lec summary module3a - ECE 362 Microprocessor System Design...

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Unformatted text preview: ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 1 Lecture Summary Module 3-A Analog-to-Digital (ATD) Converter analog-to-digital conversion process o sampling o quantizing o encoding design issues o sampling rate (bandwidth) o number of bits (resolution) o converter type sampling o sample-and-hold circuit (analog memory) o sampling aperture = shutter speed o sampling rate (Nyquist) o anti-aliasing (low pass) filter o aliasing example quantization o number of bits needed - resolution o assignment of fixed amplitude level o relative to reference voltages o quantization error = noise o SQNR = 20 log 10 (2 n / 1) o about 6 dB of dynamic range/bit converter types o with or without DTA converter o successive approximation most common s high resolution s linear conversion time (n) s based on BGaN game Example in which higher frequency sinusoid aliases to a lower frequency ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 2 9S12C32 ATD features/modes o 8 input channels o 8/10 bit resolution o 8 separate result registers o programmable sample time o fast conversion time (8 bits / 9 s) o program- or interrupt-driven modes o port PAD pins also usable as digital inputs o conversion may be externally triggered operating modes o conversion sequence: 1 to 8 conversions o 8 basic conversion modes s non-scan modes (program driven) s scan (continuous conversion interrupt driven) s sequence complete flag (SCF) can be used as polling or interrupt device flag s each channel also has a conversion complete flag (CCF) which may be polled s conversion sequence is initiated by writing to ATD control register (ATDCTL5) reference voltages o V RH (5 V) and V RL (0 V) o resolution (step size or one LSB change) = (V RH V RL )/2 n (n is number of bits) control registers (mappings provided in skeleton file) o ATDCTL2 s ADPU (bit 7) overall enable 0 ATD disabled 1 ATD enabled s AFFC (bit 6) fast flag clear mode (primarily useful for interrupt modes) 0 normal CCF flag clearing mode (must read status register first before reading result reg.) 1 fast CCF flag clearing mode (only need to read result reg - automatically clears CCF) s ASCIE (bit 1) sequence complete interrupt enable 0 ATD interrupt disabled 1 ATD interrupt enabled s ASCIF (bit 0) sequence complete interrupt device flag (read only bit) o ATDCTL3 s (bits 6-3) conversion sequence length s FIFO (bit 2) result register mode 0 non-FIFO (results map into result registers based on conversion sequence ) 1 FIFO mode (conversion results placed in consecutive result registers modulo 8) ECE 362 Microprocessor System Design and Interfacing 2011 by D. G. Meyer 3 o ATDCTL4 s S10BM (bit 7) 8/10 bit resolution mode selection 0 10-bit resolution 1 8 bit resolution s SMP (bits 6 & 5) sample time select (sampling aperture)...
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Lec summary module3a - ECE 362 Microprocessor System Design...

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