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Unformatted text preview: 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2 Microcontroller Interfacing 1 Module 2 Desired Outcome: "An ability to interface a microcontroller to various devices" Part A: Bus Timing Analysis Part B: 9S12C Multiplexed Bus Expansion Part C: General-Purpose I/O Ports General Part D: Buffered I/O Handling Part E: Interrupt Handling Part F: Buffered, Interrupt-Driven Printer InterruptDesign Example Part G: Clocks and Reset Generator (CRG) and Real Time Interrupt (RTI) Part H: External Microcontroller Interfaces 2 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-A Bus Timing Analysis 3 Instructional Objectives To learn the signals that typically comprise a microprocessor bus, their function, and their timing characteristics To learn how to interface memory components to a microprocessor bus To learn how to do bus timing analysis and identify critical paths as well as calculate timing margins 4 Outline Definitions of typical bus signals CPUCPU-Memory interface circuit Timing parameters Synchronous read cycle timing chart Synchronous write cycle timing chart Critical path assessment Timing margin Example application 5 Definitions of Typical Bus Signals BUS CLOCK (CLK) used to enable memory and I/O accesses (in conjunction with the R/W signal) in synchronous bus systems, one cycle of this clock usually corresponds to one "unit" of bus activity (e.g., a CPU read of a specific memory location or a CPU write to a specific I/O port) 6 Definitions of Typical Bus Signals ADDRESS BUS outputs memory or I/O location address during valid memory reference cycles high impedance state if processor relinquishes bus to a secondary bus master (like a DMA controller) 7 Definitions of Typical Bus Signals DATA BUS inputs data from memory or I/O location on read cycles, outputs data on write cycles high impedance state if processor relinquishes bus to a secondary bus master 8 Definitions of Typical Bus Signals Read/Write (R/W) (R/W indicates direction of data transfer on data bus (input for "read", output for "write") high impedance if processor relinquishes bus to a secondary bus master memory and I/O control signals OE (output enable) and WE (write enable) are usually provided directly by CPU 9 Definitions of Typical Bus Signals READY (RDY) in synchronous bus systems, asserted by the memory (or I/O device) being accessed to indicate the bus transaction requested by the CPU may be completed on the current bus cycle if negated, the CPU inserts wait negated, states allows the CPU to accommodate slower memory or I/O devices 10 CPUCPU-Memory Interface Circuit Address Decode PLD ABus CPU DBus R/W CLK CE Addr Memory Data OE WE 11 9S12C Bus Signals Looking ahead... 12 CPU Timing Parameters (Read/Write) Common to READ and WRITE cycles tCY (CPU bus cycle time) tAD (CPU address generation delay) tAH (CPU address hold time) READ cycle tRS (CPU read data setup time) tRH (CPU read data hold time) WRITE cycle tDD (CPU write data generation delay) tWH (CPU write data hold time) tWZ (CPU write data float delay, after tWH) 13 Memory Timing Parameters (Input/Output) READ Cycle tAA (memory address access time) tCE (memory chip enable access time) tOE (memory output enable access time) tOH (memory output hold time) tOZ (memory output data float delay, after tOH) WRITE cycle tIS (memory input data setup time) tIH (memory input data hold time) tAW (memory address to write time) tCW (memory chip enable to write time) tWP (memory write pulse width) 14 Successive Synchronous Read Cycles CLK R/W OE ADDR CE DATA 15 Successive Synchronous Read Cycles CLK R/W OE ADDR CE DATA 16 Successive Synchronous Read Cycles CLK R/W OE ADDR CE DATA 17 Successive Synchronous Read Cycles CLK R/W OE ADDR CE DATA 18 Successive Synchronous Read Cycles CLK R/W OE ADDR CE DATA 19 Successive Synchronous Read Cycles CLK R/W OE ADDR CE DATA 20 Successive Synchronous Read Cycles CLK where CPU read occurs R/W OE ADDR CE DATA 21 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tAH R/W OE ADDR CE DATA 22 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tAH R/W OE ADDR CE DATA tRS tRH 23 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tAH R/W OE ADDR CE DATA tRS tRH 24 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tAH R/W OE ADDR CE DATA tRS tRH tOH tOZ 25 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tAH R/W OE ADDR CE DATA tRS tRH tOH tOZ 26 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tOE tAH R/W OE ADDR CE DATA tRS tRH tOH tOZ 27 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tOE tAA tAH R/W OE ADDR CE DATA tRS tRH tOH tOZ 28 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tOE tAA tCE tRS tRH tOH tOZ 29 R/W OE tAH ADDR CE DATA Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tOE tAA tCE tRS read timing margin R/W OE tAH ADDR CE DATA tRH tOH tOZ 30 Clicker Quiz 31 1. The "Green (Fed-Ex) Line" for a READ cycle refers to the instant that the data "absolutely, positively has to be there" within nanoseconds for the memory read operation to be successful, which is: A. the read setup time prior to the end of the bus cycle B. the bus cycle minus the address generation delay C. the bus cycle minus the data generation delay D. the read hold time prior to the end of the bus cycle E. none of the above 32 2. If the value on the data bus changes before the "Green (Fed-Ex) Line": A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above 33 3. If the value on the data bus changes tRS after the "Green (Fed-Ex) Line": A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above 34 4. If the value on the data bus changes tRS + tRH after the "Green (Fed-Ex) Line": A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above 35 5. The following parameter has no influence on the read timing margin available: A. tAA B. tOE C. tOH D. tCE E. none of the above 36 Successive Synchronous Write Cycles CLK R/W WE ADDR CE DATA 37 Successive Synchronous Write Cycles CLK R/W WE ADDR CE DATA 38 Successive Synchronous Write Cycles CLK R/W WE ADDR CE DATA 39 Successive Synchronous Write Cycles CLK R/W WE ADDR CE DATA 40 Successive Synchronous Write Cycles CLK R/W WE ADDR CE DATA 41 Successive Synchronous Write Cycles CLK R/W WE ADDR CE DATA 42 Successive Synchronous Write Cycles CLK where write to memory occurs R/W WE ADDR CE DATA 43 Read/Write Memory (RWM) Each bit of memory (or SRAM cell) in a static RAM behaves as the circuit depicted below When the SEL input is asserted, the stored data is placed on the cell's output When both SEL and WR are asserted, the latch is open and a new data bit is stored SRAM cells are combined in an array with additional control logic to form a complete static RAM 44 Internal Structure of 8x4 SRAM 45 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tAH ADDR CE DATA 46 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tAH ADDR CE DATA tDD 47 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tAH ADDR CE DATA tDD tIS tIH 48 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tAH ADDR CE DATA tDD tIS tIH tWH tWZ 49 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tWP tAH ADDR CE DATA tDD tIS tIH tWH tWZ 50 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tWP tAW tAH ADDR CE DATA tDD tIS tIH tWH tWZ 51 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tWP tAW tCW tDD tAH ADDR CE DATA tIS tIH tWH tWZ 52 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tWP tAW tCW tDD write timing margin tAH ADDR CE DATA tIS tIH tWH tWZ 53 Clicker Quiz 54 1. The "Green (Fed-Ex) Line" for a WRITE cycle refers to the instant that the data "absolutely, positively has to be there" within nanoseconds for the memory write operation to be successful, which is: A. the write pulse width B. the input setup time prior to the end of the bus cycle C. the input setup time prior to the negation of write enable D. the input hold time following the negation of write enable E. none of the above 55 2. If the data supplied to memory changes tIS before the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above 56 3. If the data supplied to memory changes less than tIS before the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above 57 4. If the data supplied to memory changes less than tIH after the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above 58 5. If the data supplied to memory changes greater than tIH after the negation of write enable: A. bus fighting might occur B. the wrong value might be written to memory C. data might be written to the wrong address D. all of the above E. none of the above 59 Example: CPU Specifications Description Bus clock period Address generation delay Address hold time Read setup time Read hold time Write data generation delay Write hold time Write float delay (after tWH) Parameter tCY tAD tAH tRS tRH tDD tWH tWZ Value 200 ns 30 ns 20 ns 30 ns 20 ns 80 ns 30 ns 10 ns Assume all "glue logic" delays are 10 ns 60 "Glue Logic" Propagation Delays Delay of Address to CE' Address Decode PLD ABus CPU DBus R/W CLK CE Addr Memory Data OE WE Delay of R/W' and CLK to both OE' and WE' 61 Successive Synchronous Read Cycles CLK tCY R/W OE ADDR CE DATA 0 20 40 60 80 100 120 140 160 180 200 62 Successive Synchronous Read Cycles CLK tCY tAD tAH R/W OE ADDR CE DATA 0 20 40 60 80 100 120 140 160 180 200 63 Successive Synchronous Read Cycles CLK tCY tAD tAH R/W OE ADDR CE DATA 0 20 40 60 80 100 "glue logic" delay 120 140 160 180 200 64 Successive Synchronous Read Cycles CLK tCY tAD tAH R/W OE ADDR CE DATA tAD tAH 0 20 40 60 80 100 120 140 160 180 200 65 Successive Synchronous Read Cycles CLK tCY tAD tAH R/W OE ADDR CE DATA 0 20 40 60 "glue logic" delay 80 100 120 140 160 180 200 66 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tAH R/W OE ADDR CE DATA 0 20 40 60 80 100 120 140 160 180 200 67 Successive Synchronous Read Cycles CLK where CPU read occurs tCY tAD tAH R/W OE ADDR CE DATA 0 "window" during which data supplied by memory must remain stable 20 40 60 80 100 120 140 tRS 160 180 tRH 200 68 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tAH ADDR CE DATA 0 "glue logic" delay tDD 20 40 60 80 100 120 140 160 180 200 tWZ tWH 69 Example: SRAM specifications Description Address access time Chip enable access time Output enable access time Output hold from OE'/CE' negation or address change Output float delay following tOH Input (write) data setup time Input (write) data hold time Write pulse width Address valid prior to memory write Chip enable valid prior to memory write Parameter tAA tCE tOE tOH tOZ tIS tIH tWP tAW tCW Value 80 ns min 80 ns min 20 ns min 10 ns min 10 ns max 30 ns min 20 ns min 40 ns min 90 ns min 80 ns min 70 Successive Synchronous Read Cycles CLK tCY tAD tOE tAA tCE tRS 0 20 40 60 80 100 120 140 160 180 where SRAM "thinks" read occurs R/W OE tAH ADDR CE DATA tRH 200 tOH tOZ 71 read timing margin Critical Path Assessment Typically three (primary) critical "read" paths to consider tAA tCE tOE Why are the "write" paths typically NOT critical? address/data path is "one way" (instead of "round trip") 72 Timing Margin Definition: Definition: The difference between the "nominal" memory performance required and performance of actual memory component chosen Why a margin is needed: To accommodate needed: normal variations that occur in device performance due to operating temperature, lot variations, etc. What is a "safe" margin? Usually about margin? 10% of the parameter in question What is the consequence of insufficient margin? margin? Unstable performance! 73 Example: SRAM Specifications Description Address access time Chip enable access time Output enable access time Output hold from OE'/CE' negation or address change Output float delay following tOH Input (write) data setup time Input (write) data hold time Write pulse width Address valid prior to memory write Chip enable valid prior to memory write Parameter tAA tCE tOE tOH tOZ tIS tIH tWP tAW tCW Value 80 ns min 80 ns min 20 ns min 10 ns min 10 ns max 30 ns min 20 ns min 40 ns min 90 ns min 80 ns min 74 Successive Synchronous Write Cycles CLK tCY where write to memory occurs R/W WE tAD tWP tAW tCW tDD 0 20 40 60 80 100 120 140 160 180 tAH ADDR CE DATA tIS tIH 200 tWZ tWH 75 write timing margin Example: Conclusions This example illustrates the use of a 5 MHz (200 ns bus clock) CPU in conjunction with an 80 ns (tAA and tCE) SRAM If a CPU (as specified) is interfaced to an SRAM (as specified), and the "glue logic" delay is 10 ns, then the following timing margins will be realized: read timing margin: 40 ns write timing margin: 100 ns 76 Discussion Question What problems may be caused by excessive "float" delays in high-speed designs? highExcessive memory read float delay may overlap with CPU drive of bus on successive write cycle, causing bus fighting (excessive power dissipation, overheating, stress, premature device failure) 77 Clicker Quiz 78 1. If the nominal tCE for a CPU-memory interface is 50 ns, the speed of SRAM that should be utilized in order to provide a 10% read timing margin is: A. 45 ns B. 50 ns C. 55 ns D. 60 ns E. none of the above 79 2. If the SRAM read float delay exceeds the processor's write data generation delay: A. bus fighting might occur B. the wrong value might be read by the processor C. metastability might occur D. all of the above E. none of the above 80 3. A possible consequence of insufficient timing margin is: A. sensitivity to relative humidity B. sensitivity to operating temperature C. sensitivity to switching noise D. all of the above E. none of the above 81 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-B 9S12C Multiplexed Bus Expansion 82 Instructional Objectives To learn what a multiplexed bus is and how to interface it with standard memory components To learn about the control signals associated with the multiplexed 9S12C expansion bus To review bus timing analysis in the context of an actual microcontroller 83 Outline Introduction Operating modes of interest Register settings Internal resource re-mapping reWait state ("stretch") generation 9S12C A.C. timing specifications Example narrow mode SRAM interface Analysis of critical paths / SRAM choice References: Module Mapping Control (MMC) Block User Guide Multiplexed External Bus Interface (MEBI) Block User Guide HCS12 External Bus Design (AN2287) Examples of External Bus Design (AN2408) 84 Introduction Some applications require that the bus signals (address, data, and control) be available externally so that additional memory and/or peripherals can be interfaced to the microcontroller On the HC(S)12, Ports A & B (along with certain pins on Port E) can be used to expand the microcontroller's bus To minimize the number of pins required to expand the bus, the address and data information is multiplexed on these port pins 85 Introduction The address/data multiplexing on the HC(S)12 works as follows: on the first half of the bus cycle, the 16-bit 16address is emitted on the port pins the bus clock (ECLK) signal is used to latch the address externally on the second half of the bus cycle, the (8- or 16-bit) data is either read (input) or (816written (output) the ECLK (bus clock) signal is used to provide separation between output of an address and the transmission of data 86 Introduction The expanded data bus can be 8-bits 8("narrow mode") or 16-bits ("wide mode") ("narrow 16("wide Signals of interest include the following: Port A high byte of address/data (wide mode) or high byte of address/8-bit data (narrow mode) address/8 Port B low byte of address/data (wide mode) Port E bus control signals E bus clock (used to de-multiplex the address deand data) R/W' read/write enable LSTRB' low byte strobe (used to distinguish word writes from byte writes in "wide" mode) 87 9S12C Bus Signals Note: These signals are not available on the 9S12C32 88 Operating Modes of Interest Operating modes of interest normal single chip mode normal expanded narrow (8-bit data bus) (8 normal expanded wide (16-bit data bus) (16Mode out of reset determined by the MODA / MODB / MODC pins of chip 89 Operating Mode Selection 90 Register Settings MODE register MODC, MODB, MODA (bits 7, 6, & 5) indicate the current operating mode "000" special single chip mode "001" emulation narrow mode "010" special test mode "011" emulation wide mode "100" normal single chip mode "101" normal expanded narrow mode "110" special peripheral mode "111" normal expanded wide From "normal single chip" mode, only "normal expanded narrow/wide" modes are available 91 Register Settings MODE register IVIS (bit 3) allows bus activity associated with internal access to be visible on the external (expanded) bus useful for debugging (connection to logic analyzer) "0" internal bus operations are invisible "1" internal bus operations are visible indicates default mode out of reset 92 9S12C MODE Register 93 Register Settings PEAR ("Port E Assignment Register") NECLK (bit 4) no external E clock "0" PE.4 is used for E clock signal "1" PE.4 is used for general-purpose I/O general- LSTRE (bit 3) low byte strobe enable "0" PE.3 is used for general-purpose I/O general "1" PE.3 is used for LSTRB' signal RDWE (bit 2) read/write enable "0" PE.2 is used for general-purpose I/O general "1" PE.2 is used for R/W' signal indicates default mode out of reset for "normal single chip" mode 94 9S12C PEAR Register 95 Internal Resource Re-Mapping ReDefault locations of each HC(S)12 internal resource can be changed during program execution If conflicts occur, the following precedence applies: register space internal SRAM byte-erasable EEPROM (not on 9S12C32) byte flash external memory 96 Internal Resource Re-Mapping Registers ReINITRG (initialize register position) REG14...REG11 (bits 6-3) these bits specify the 6upper 5 bits of each internal registers address (write once in normal mode), enabling the register mode), block to be re-mapped to any 2K block within the refirst 32KB of the system's address space default is "00000" There is probably "no good reason" to re-map the reregister block from its default location 97 Internal Resource Re-Mapping Registers ReINITRM (initialize SRAM position) RAM15...RAM11 (bits 7-3) these bits specify the 7upper 5 bits of the (16-bit) SRAM address (write (16once in normal mode), enabling the SRAM to be mode), rere-mapped to any 2K block in memory default is "00001" the 2K block occupying locations $800-$FFF $800 RAMHAL (bit 0) this bit specifies the alignment of the internal SRAM "0" align RAM to begin at the lowest address of the mapped block "1" align RAM to end at the highest address of the mapped block (default) By default (out of reset), then, the 9S12C32 SRAM $800is mapped to locations $800-$FFF Setting INITRM = $39 maps the 9S12C32 SRAM to locations $3800-$3FFF (what Serial Monitor does) $3800- 98 Internal Resource Re-Mapping Registers ReINITEE (initialize EEPROM position) EEPROM is non-volatile "read mostly" memory non(byte-erasable/re(byte-erasable/re-writable, relatively slow erase) EE15...EE11 (bits 7-3) these bits specify the 7upper 5 bits of the (16-bit) EEPROM address (16(write once in normal mode), enabling the mode), EEPROM to be re-mapped to any 2K block in rememory default base address is device specific EEON (bit 0) enable EEPROM in memory map "0" EEPROM is disabled from memory map "1" EEPROM is enabled in memory map Note: The 9S12C32 does not have EEPROM 99 Internal Resource Re-mapping Registers ReMISC register ROMHM (bit 1) "ROM High Map" allow access to flash memory only in second (upper) half of address space "0" fixed page(s) of flash memory in lower half of address space are accessible (default) "1" direct access to flash memory in the lower half of the address space is disabled ROMON (bit 0) enable flash memory "0" disable flash memory from address space "1" enable flash memory in address space (default for "normal single chip" mode) Out of reset, the 9S12C32 flash memory is $8000mapped to locations $8000-$FFFF 100 9S12C32 User-Configurable Memory Map Out of reset, SRAM is mapped to 800-FFF Out of reset, Flash is mapped to 8000-FFFF 101 Wait State Generation MISC register EXSTR1, EXSTR0 (bits 3 & 2) determine amount of bus clock "stretch" (in E clock "high" state) to provide on external bus high" accesses "00" no stretch "01" one extra cycle "10" two extra cycles "11" three extra cycles indicates default mode out of reset 102 Summary The HC(S)12 can operate in a variety of special/normal modes, ranging from singlesinglechip to expanded wide/narrow Address/data is time-division multiplexed timeSeveral HC(S)12 pins control into which mode the processor boots The operating mode can be changed after the processor boots Various on-chip resources (SRAM, EEROM, onFlash, Registers) can be relocated within the system address space Memory mapping conflicts are automatically resolved 103 9S12C A.C. Specifications (Sample) 104 9S12C General External Bus Timing 105 9S12C General External Bus Timing address phase 106 9S12C General External Bus Timing address phase data phase 107 9S12C General External Bus Timing point at which address is externally latched address phase data phase 108 9S12C A.C. Specifications (Sample) 109 9S12C General External Bus Timing tCY 110 9S12C A.C. Specifications (Sample) 111 9S12C General External Bus Timing tCY tAD 112 9S12C A.C. Specifications (Sample) 113 9S12C General External Bus Timing tCY tAD tMAH 114 9S12C A.C. Specifications (Sample) 115 9S12C General External Bus Timing tCY tAD tMAH tDSR tDHR 116 9S12C A.C. Specifications (Sample) 117 9S12C General External Bus Timing tCY tAD tMAH tDDW tDSR tDHR 118 9S12C A.C. Specifications (Sample) 119 9S12C General External Bus Timing tCY tAD tMAH tDDW tDSR tDHR tDHW 120 9S12C A.C. Specifications (Sample) 121 9S12C General External Bus Timing tCY tAD tMAH tDDW tDSR tDHR tDSW tDHW "input setup" time (tIS) available on write 122 9S12C A.C. Specifications (Sample) 123 9S12C General External Bus Timing tCY tAD tACCA tDSR tDHR tMAH tDDW tDSW tDHW "input setup" time (tIS) available on write "address access" time (tAA) available on read 124 9S12C A.C. Specifications (Sample) 125 9S12C General External Bus Timing tCY tAD tACCA tDSR tDHR tMAH tDDW tRWD tDSW tDHW "input setup" time (tIS) available on write "address access" time (tAA) available on read 126 9S12C A.C. Specifications (Sample) 127 9S12C General External Bus Timing tCY tAD tACCA tDSR tDHR tMAH tDDW tRWD tDSW tDHW tRWH "input setup" time (tIS) available on write "address access" time (tAA) available on read 128 Clicker Quiz 129 1. The word multiplexed, when used to describe an expanded microprocessor bus, means: A. address and data are sent over the same wires simultaneously B. address and data are sent over the same wires, but not at the same time C. address and data are sent over the same wires bi-directionally D. address and data are sent over separate wires, but not at the same time E. none of the above 130 2. If memory mapping conflicts occur, the HC(S)12 gives the lowest priority to: A. register space B. internal SRAM C. byte-erasable EEPROM D. flash EEPROM E. external memory 131 3. The default address space for SRAM out of reset is: A. $800 - $FFF B. $3800 - $3FFF C. $0000 - $7FFF D. $8000 - $FFFF E. none of the above 132 4. The default address space for Flash out of reset is: A. $800 - $FFF B. $3800 - $3FFF C. $0000 - $7FFF D. $8000 - $FFFF E. none of the above 133 5. The difference between "special" and "normal" HC(S)12 operating modes is: A. the processor feels better about itself when operating in "special" mode B. certain registers can be changed only once in "normal" mode, but can be changed any number of times in "special" mode C. certain registers can only be modified when the processor is running in "special" mode D. certain registers can be changed only once in "special" mode, but can be changed any number of times in "normal" mode 134 E. none of the above Example: Narrow Mode SRAM Interface Problem Statement: Interface a Cypress CY7C199 32K X 8 SRAM to a Freescale 9S12C128 microcontroller based on the circuit depicted in Figure 1 of AN2408. This SRAM should be mapped into the lower half (0000-7FFF) of the processor's address space. Instead of using discrete logic, however, you should fit the entire interface circuit into a single PLD (use a 5 ns device). Using OrCAD Capture, draw a complete schematic of your interface design. Next, create an ABEL file that implements your interface logic, and analyze the propagation delays (for tAA, tCE, and tOE) based on your PLD speed choice. Then, pick the lowest performance CY7C199 variant that provides a read timing margin of at least 10% (based on the critical path parameters listed previously). Finally, draw a timing diagram for your interface with all critical paths labeled, clearly indicating the available read timing margin. 135 Figure 1 of AN2408 136 Schematic Based on PLD PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 21 23 24 25 26 1 2 3 4 5 6 7 8 9 10 22 27 20 28 40 41 42 43 44 1 2 3 8 9 10 11 12 13 14 15 4 ECLK RW 5 27 7 26 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 TDI CLK0/I0 CLK1/I1 TCK TMS M4_32/FP44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 TDO 18 19 20 21 22 23 24 25 30 31 32 33 34 35 36 37 29 PA1 PA0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE WE CE VCC CY7C199 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA7 PA6 PA5 PA4 PA3 PA2 Note: Schematic is based on pin assignments generated automatically by the fitter for this PLD. 137 Interface Logic MODULE mem9s12c TITLE '9S12C Memory Interface' DECLARATIONS PA0..PA7 pin; " MCU Port A ECLK pin; " MCU E-clock RW pin; " MCU Read/Write !CS, !OE, !WE pin istype 'com'; LA8..LA15 pin istype 'reg_D'; " demultiplexed address EQUATIONS [LA8..LA15].D = [PA0..PA7]; [LA8..LA15].CLK = ECLK; CS = !LA15.Q & ECLK; " map SRAM into lower half of address space OE = RW & ECLK; WE = !RW & ECLK; END 138 Fitter Report (Summary) 139 Critical Path Analysis: OE' and WE' These are the combinational output delay paths (pertinent for OE and WE). 140 Critical Path Analysis: Latched Address These are the clock edge to latched output delay paths (where ECLK provides the clock edge). Note that the latched (de-multiplexed) address bus is valid 4 ns following the low-to-high ECLK transition; the CS signal, which here is dependent on LA15 and being gated with ECLK, is valid 7.5 ns following the low-to-high ECLK transition. 141 This adaptation of the published timing chart is not to scale due to the inclusion of one cycle of stretch Timing Diagram 142 Analysis / Choice of Slowest SRAM Variant Case shown is for 5-volt, 25 MHz operation with one cycle of stretch (per AN2408) and use of a 5 ns PLD (M4A3-32/32-5VC). Propagation delays were determined through use of the ispLEVER timing simulator. Here, the nominal tAA available is 42 ns, nominal tCE available is 38.5 ns, and nominal tOE available is 41 ns. To provide a 10% margin for the critical path (tCE), the SRAM chosen should have a tCE < 35 ns. Based on this, a 7C199-35 might work, but possibly exhibit an insufficient read timing margin. It would probably be a better idea to go with a slightly faster SRAM (7C199-25) to provide plenty of timing margin (this is the case illustrated on the timing diagram). But...look out for BUS FIGHTING!! 143 Register Settings MODE: Set for "normal expanded narrow" mode operation PEAR: Set NECLK bit = "0" and RDWE bit = "1" MISC: Set EXSTR1 and EXSTR0 bits = "01" (for one cycle of stretch), set ROMHM bit = "1" and ROMON bit = "1" 144 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-C General-Purpose I/O Ports 145 Outline Introduction Port pin function/use Direction, pull-up, and drive programmability pullPrinter interface example Handshaking signals and communications protocol Interface circuit and register initializations Program-driven I/O device driver Program Details on the Centronics parallel printer port Reference: Port Integration Module (PIM) Block Guide 146 Introduction The function/use of various 9S12C peripheralperipheralrelated pins is controlled by the Port Integration Module (PIM) The default out of reset is that all port-related portpins are configured for general-purpose generaldigital I/O If the module associated with a set of port pins is enabled, that module "takes over" enabled, control of the port Any unused port pins (even for those associated with an enabled module) can be configured for general-purpose I/O general147 Port Integration Module (PIM) 148 Introduction Any unused peripheral pins on the 9S12C can generalbe used for general-purpose digital I/O PAD pins can be used for digital I/O if the ATD module is not used; unused PAD pins can be used as digital inputs (only) if the ATD module is used (PAD6 and PAD7 are connected to pushbuttons on the docking module) unused PT pins can be used for digital I/O (PT0 and PT1 are connected to LEDs on the docking module) unused PM pins can be used for digital I/O if the MSCAN and/or SPI are not used PE0,1 can be used as digital I/O if no external interrupts are needed (IRQ, XIRQ) On the 9S12C32, Ports A & B are not padded 9S12C32, out (i.e., these ports have no external pins) 149 9S12C32 Available I/O Pins available for generalpurpose I/O if no external interrupts needed PAD pins can be used for digital I/O if ATD disabled unused PT pins can be used for digital I/O not padded out on `C32 NOT AVAILABLE for general-purpose I/O on microcontroller module available for generalpurpose I/O if MSCAN and/or SPI not used not padded out on `C32 150 Introduction A standard port pin has the following features: input/output data direction selection via a "data direction register" (DDR) DDR bit = 0 port pin is an INPUT DDR bit = 1 port pin is an OUTPUT 5V output drive with two selectable drive strengths controlled via a "reduced drive register" (RDR) RDR bit = 0 output port pin has "full drive" RDR bit = 1 output port pin has "reduced drive" Use of "reduced drive" reduces power dissipation and EMI (electromagnetic interference) generation 151 Data Direction Programmability Data Direction Register (DDR) Bit: 7 DDR 7 Reset: 0 6 DDR 6 0 5 DDR 5 0 4 DDR 4 0 3 DDR 3 0 2 DDR 2 0 1 DDR 1 0 0 DDR 0 0 DDRx = 0 means PTx is an input bit DDRx = 1 means PTx is an output bit Port Input/Output Data Register (PT) Bit: 7 6 5 4 3 2 1 0 PT 7 PT 6 PT 5 PT 4 PT 3 PT 2 PT 1 PT 0 Reset: Port Pins 152 9S12C D.C. Electrical Characteristics @ 5 VDC 153 Introduction A standard port pin has the following features: 5V input with selectable pull-up or pull-down pullpulldevice via a "pull enable register" (PER) PE bit = 0 pull device disabled PS bit ignored PE bit = 1 pull device enabled PS bit = 0 pull-up enabled pull PS bit = 1 pull-down enabled pull- Optional features (not available on all port pins) include: 5V analog input open drain outputs for "wired OR" connections interrupt inputs with "glitch filtering" 154 Block Diagram of Pin Functionality port input data (read) dual-rank input synchronizer port output data (write) data direction register externa l pin module/peripheral associated with port pin Note: If module/peripheral is enabled, it "takes over" the associated port pin(s) 155 Pin Configuration Summary 156 Port Read and Write Timing (8 MHz) Port data setup time = 120 ns hold time = 0 ns Port READ Timing Port write delay time = 40 ns Port Write Timing 157 Printer Interface Example Handshaking signals and communication protocols Interface circuit and register initializations ProgramProgram-driven I/O device driver Details on the Centronics parallel printer port 158 Handshaking and Communication Protocol In general, the maximum transfer rate of which an I/O device is capable does not match the maximum transfer rate of which the CPU is capable Communication (or synchronization) between an I/O device and CPU is therefore required for reliable data transfer, using handshaking signals signal from computer to I/O Device: DATA AVAILABLE or STROBE signal from I/O device to computer: BUSY or READY 159 Handshaking and Communication Protocol The sequence in which these signals are asserted and negated with respect to the data transfer is referred to as the communication protocol Example: Handshaking signals and communication protocol for a generic "Centronics" (parallel port) printer Centronics" STROBE: "I have the next ASCII character available for you to print" BUSY: "I'm currently printing the previous character you sent me (or something `bad' has happened), so please don't send me any more right now" 160 Handshaking and Communication Protocol Data Printer STROBE BUSY 161 Handshaking and Communication Protocol STROBE 1 BUSY DATA Previous Character STEP 1: Check to see if the printer is busy 162 Handshaking and Communication Protocol STROBE 1 BUSY 2 Next Character DATA Previous Character STEP 2: Send data to printer 163 Handshaking and Communication Protocol 3 STROBE 1 BUSY 2 Next Character DATA Previous Character STEP 3: CPU asserts STROBE signal 164 Handshaking and Communication Protocol 3 STROBE 1 4 BUSY 2 Next Character DATA Previous Character STEP 4: Printer asserts BUSY while printing 165 Handshaking and Communication Protocol 3 STROBE 1 4 5 BUSY 2 Next Character DATA Previous Character STEP 5: Printer negates BUSY when print cycle is complete 166 Centronics Printer Port Timing DATA STROBE 0.5 s 0.5 s 0.5 s BUSY 167 PrinterPrinter-Microcontroller Interface Printer Port X (bits 0-7) STROBE (Port Y, bit 1) BUSY (Port Y, bit 0) ...where Port X and Port Y are any available port pins 168 Register Initializations DDRX DDRY Pin 1 of Port Y RDRX RDRY PERX PERY 169 Register Initializations DDRX DDRY Pin 1 of Port Y RDRX RDRY PERX PERY 170 1111 1111 xxxx xx10 Register Initializations DDRX DDRY 1111 1111 xxxx xx10 Pin 1 of Set high (to indicate Port Y STROBE negated) RDRX RDRY PERX PERY 171 Register Initializations DDRX DDRY 1111 1111 xxxx xx10 Pin 1 of Set high (to indicate Port Y STROBE negated) RDRX 0000 0000 RDRY (normal drive default) PERX PERY 172 Register Initializations DDRX DDRY 1111 1111 xxxx xx10 Pin 1 of Set high (to indicate Port Y STROBE negated) RDRX 0000 0000 RDRY (normal drive default) PERX 0000 0000 PERY (no pull-up device default) 173 Program-Driven I/O 174 Program-Driven I/O read device status 175 Program-Driven I/O read device status is device ready? 176 Program-Driven I/O read device status is device ready? no 177 Program-Driven I/O read device status is device ready? no yes transfer data 178 ProgramProgram-Driven Device Driver A device driver is a low-level routine that lowtransfers data to/from an I/O device and generates any handshaking protocol required The printer device driver pchar functions as follows: checks printer status and waits if the printer is busy transfers the character passed in the A register to the printer strobes the printer 179 Printer Initialization Routine bmask smask pinit equ equ $01 $02 ; BUSY bit mask ; STROBE mask 180 Printer Initialization Routine bmask smask pinit equ equ movb $01 $02 #$FF,ddrx ; BUSY bit mask ; STROBE mask 181 Printer Initialization Routine bmask smask pinit equ equ movb movb $01 $02 #$FF,ddrx #$02,ddry ; BUSY bit mask ; STROBE mask 182 Printer Initialization Routine bmask smask pinit equ equ movb movb bset rts $01 $02 ; BUSY bit mask ; STROBE mask #$FF,ddrx #$FF,ddrx #$02,ddry #$02,ddry porty,smask 183 Printer Device Driver bmask smask pchar pwait equ equ pshc staa portx $01 $02 ; BUSY bit mask ; STROBE mask pulc rts 184 Printer Device Driver bmask smask pchar pwait equ equ pshc brset staa $01 $02 ; BUSY bit mask ; STROBE mask porty,bmask,pwait portx pulc rts 185 Printer Device Driver bmask smask pchar pwait equ equ pshc brset staa bclr pulc rts $01 $02 ; BUSY bit mask ; STROBE mask porty,bmask,pwait portx porty,smask ; 4 cycles 186 Printer Device Driver bmask smask pchar pwait equ equ pshc brset staa bclr bset pulc rts $01 $02 ; BUSY bit mask ; STROBE mask porty,bmask,pwait portx porty,smask ; 4 cycles porty,smask ; 4 cycles 187 Centronics Printer Port Timing DATA STROBE 0.5 s 0.5 s 0.5 s last cycle of STAA BUSY last cycle of BCLR last cycle of BSET Assume 8 MHz Bus Clock 125 ns/cycle STROBE duration = 4 cycles X 125 ns/cycle = 500 ns STROBE asserted 4 cycles X 125 ns/cycle = 500 ns following STAA 188 Centronics DB25 connector pin assignments 189 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-D Buffered I/O Handling 190 Outline Motivation for buffering data Illustration of circular buffers Circular buffer handling algorithms Example application 191 Motivation for Buffering Basic idea: most systems have producers and consumers of data Examples computer "A" sending data to computer "B" computer sending data to an output device (e.g., printer) computer receiving data from an input device (e.g., analog-to-digital converter) analog-to- 192 Motivation for Buffering Problems data may be coming in (or need to be output) when the "other end" is not ready for it data rate (production/consumption) may be different at each end many CPU cycles can be spent in "spin wait" loops (time spent waiting on a device handshake signal or synchronization variable) Solution data buffering helps "smooth out" program execution and reduce CPU time wasted in "spin wait" loops 193 Circular Buffers One type of data buffering scheme that can be used is a circular buffer (also called a "FIFO" queue) A circular buffer is based on the following synchronization rule: if the producer tries to put data in a full buffer, buffer, the producer will be delayed until the consumer takes data from the buffer if the consumer tries to take data from an empty buffer, the consumer will be buffer, delayed until the producer has put more data in the buffer 194 Circular Buffers Two pointers: IN points to the next available location in which the producer may place data OUT points to the next data item that the consumer should output IN OUT 195 Circular Buffers Called "circular" because the IN and OUT pointers "chase" each other around buffer locations in a "modulo" fashion (as the consumer process takes "bytes" of data out of the buffer) One of the six "basic CPU food groups" gives "process starvation" a whole new meaning! 196 Circular Buffers empty condition: IN = OUT partially filled full condition: (IN+1) mod bufsize = OUT bufsize = 8 IN OUT 0 7 6 5 1 2 3 4 197 Circular Buffers empty condition: IN = OUT partially filled full condition: (IN+1) mod bufsize = OUT bufsize = 8 OUT A 0 7 6 5 1 B 2 3 4 C D IN 198 Circular Buffers empty condition: IN IN = OUT partially filled full condition: (IN+1) mod bufsize = OUT OUT A 0 7 1 B 2 3 5 4 C D G bufsize = 8 6 F E 199 Circular Buffers IN OUT Note: Due to the need to distinguish between the "empty" and "full" conditions, the buffer is "full" when it contains bufsize-1 data items A 0 7 1 B 2 3 5 4 C D G 6 F E 200 Circular Buffer Algorithms Producer process 1. Check state of buffer 2. If buffer is FULL, wait for space FULL, 3. Else, place character in buffer at location pointed to by IN 4. Increment IN pointer modulo BUFSIZE 5. Exit 201 Circular Buffer Algorithms Consumer Process 1. Check state of buffer 2. If buffer is EMPTY, wait for data EMPTY, 3. Else, get data from location pointed to by OUT pointer 4. Increment OUT pointer modulo BUFSIZE 5. Exit 202 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-E Interrupt Handling 203 Outline Interrupt handling basics HC(S)12 interrupt handling specifics References: MC9S12C Family Device User Guide, Sec. 5 S12CPU Reference Manual, Sec. 7 204 Interrupt Handling Basics Interrupt (definition): An unexpected (asynchronous) hardware-induced hardwaresubroutine call (may also be referred to as an event or as an exception) exception) RealReal-Time: Handling of interrupts ("events") must be completed within fixed time constraints ("mission critical timing") 205 Interrupt Handling Basics Vector: Locations in memory that "point to where to go" in order to service an interrupt request, i.e., a pointer to an interrupt service routine ("ISR") ("ISR") Sources of interrupts: Can either be on-chip ondevices (e.g., timers, communications controllers, analog-to-digital converter) or analog-tooffoff-chip devices (e.g., printer, sensor) 206 Interrupt Handling Basics NonNon-maskable a CPU interrupt input/source that cannot be ignored (or "masked out") by the out") processor usually reserved for catastrophic system failures (e.g., system error or power failure) usually denoted "NMI" (non-maskable NMI" (noninterrupt), or in the case of the HC(S)12, "XIRQ" XIRQ" 207 Interrupt Handling Basics Maskable an interrupt that can be (temporarily) ignored by the processor (e.g., if it is currently performing a higher (or equal) priority task than the incoming ("pending") interrupt request) typically referred to as "application interrupt requests" and denoted "IRQ" or requests" "INT" some processors provide multiple, prioritized application interrupts 208 Interrupt Handling Basics Context switch CPU activity associated with changing from one task (e.g., a "main-line "mainprogram") to another task (e.g., an interrupt service routine) the machine state or "context" (typically context" consisting of all CPU registers) needs to be saved for the task being "rolled out" and loaded for the task being "rolled in" 209 Interrupt Handling Basics Prioritization the assignment of relative priorities to the various interrupt signals the HC(S)12 determines relative priority of multiple interrupt requests based on vector address (position in vector table) 210 Interrupt Handling Basics Preemption the ability of an incoming higher priority interrupt request to "roll out" or out" "preempt" a lower priority interrupt service routine currently in progress multiple, prioritized application interrupt inputs are typically required to support preemption 211 Interrupt Handling Basics LevelLevel-sensitive interrupt input a CPU interrupt input signal that must be latched externally this latch, which must then be cleared under software control by the interrupt service routine, is called a device flag most CPU interrupt inputs are level sensitive 212 Interrupt Handling Basics EdgeEdge-sensitive interrupt input a CPU interrupt input that requires no external latch on some CPUs, specific interrupt inputs can be programmed to be edge sensitive 213 Maskable Interrupt Device Flag CLR D Q Q 214 Maskable Interrupt Device Flag Edge-triggered "D" flip flop with asynchronous clear input CLR D Q Q 215 Maskable Interrupt Device Flag Edge-triggered "D" flip flop with asynchronous clear input CLR "1" D Q Q 216 Maskable Interrupt Device Flag Edge-triggered "D" flip flop with asynchronous clear input CLR "1" Interrupt Request (from device) D Q Q 217 Maskable Interrupt Device Flag Edge-triggered "D" flip flop with asynchronous clear input Flag Clear (from CPU) "1" Interrupt Request (from device) CLR D Q Q 218 Maskable Interrupt Device Flag Edge-triggered "D" flip flop with asynchronous clear input Interrupt Enable Bit (from CPU) Flag Clear (from CPU) "1" Interrupt Request (from device) CLR D Q Q IRQ (to CPU) 219 Interrupt Handling Basics Interrupt servicing latency the amount of time that expires between when a device asserts the CPU's interrupt request input and when the CPU fetches the first instruction of the interrupt service routine consists of two components instruction completion latency (non(nondeterministic) processor latency (deterministic) 220 Interrupt Handling Basics Instruction completion latency the amount of time for the CPU to complete the current instruction in progress note that most CPUs cannot be interrupted midmid-instruction this time is non-deterministic since: non instructions are typically variable length in execution cycles interrupts are asynchronous with respect to the CPU clock reasonable bounds on the instruction completion latency can be estimated 221 Interrupt Handling Basics Processor latency the time between when the interrupt input signal is recognized by the CPU and when the first instruction of the interrupt service routine is fetched most CPUs examine their interrupt inputs at the beginning of each fetch cycle the processor latency is also referred to as the "context switch" overhead switch" 222 HC(S)12 Interrupt Handling Specifics Interrupt sources two interrupt request inputs IRQ standard application interrupt XIRQ pseudo-non-maskable interrupt pseudo-non- total of over 20 on-chip sources on separate vector for each interrupt and reset source 223 9S12C32 External Interrupt Pins External interrupt pins are on Port E 224 HC(S)12 Interrupt Handling Specifics Interrupt masking application interrupts (including IRQ interrupt input) masked by "I" bit in CC register "0" "not masked" (i.e., enabled) masked" "1" "masked" (i.e., not enabled) masked" XIRQ input (non-maskable interrupt input) (nonis masked after system reset by "X" bit in CC register once enabled, it remains enabled (i.e., the X bit cannot be set by software) until the CPU is reset 225 HC(S)12 Interrupt Handling Specifics Interrupt masking most of the HC(S)12 on-chip onperipherals have their own interrupt enable/disable bits (control registers with IRQ "mask" or "enable" bits) external application interrupts may require external device flags and mask registers 226 HC(S)12 Interrupt Handling Microsequence Software Exception Hardware Interrupt Continue Fetch Cycle Stack CPU Registers N Mask Bit Set in CC Register? Y Set "I" (and "X") Bits in CC Register Load Interrupt Vector into PC Execute Interrupt Service Routine 227 HC(S)12 Register Stacking Order SP CCR B A X high byte X low byte Y high byte Y low byte PC high byte PC low byte 228 Address FFFE-FFFF FFFC-FFFD FFFA-FFFB FFF8-FFF9 FFF6-FFF7 FFF4-FFF5 FFF2-FFF3 FFF0-FFF1 FFEE-FFEF FFEC-FFED FFEA-FFEB FFE8-FFE9 FFE6-FFE7 FFE4-FFE5 FFE2-FFE3 FFE0-FFE1 FFDE-FFDF FFDC-FFDD FFDA-FFDB FFD8-FFD9 FFD6-FFD7 FFD2-FFD3 FF8C-FF8D Interrupt Source Reset Clock Monitor Failure COP Failure TRAP SWI XIRQ Signal IRQ Signal Real Time Interrupt Timer Channel 0 Timer Channel 1 Timer Channel 2 Timer Channel 3 Timer Channel 4 Timer Channel 5 Timer Channel 6 Timer Channel 7 Timer Overflow Pulse Accumulator Overflow Pulse Accum Input Edge SPI SCI Analog-to-Digital Converter PWM Emergency Shutdown CCR Mask Bit <nonmaskable> <nonmaskable> <nonmaskable> <nonmaskable> <nonmaskable> X bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I Bit 229 9S12C32 Interrupt Vector Locations (partial) HC(S)12 Interrupt Service Routine Structure Vector to ISR (CPU microcode) Start Clear Device Flag Service Request RTI 230 HC(S)12 Interrupt Handling Specifics Interrupt control INTCR (interrupt control) register IRQE (bit 7) "0" IRQ input pin is (active low) level sensitive "1" IRQ input is (negative) edge sensitive IRQEN (bit 6) "0" external IRQ pin disconnected "1" external IRQ pin connected indicates default state after reset 231 HC(S)12 Interrupt Handling Specifics Interrupt priority A hardware priority hierarchy determines which interrupt is serviced first when simultaneous requests are made The external interrupt request pin (IRQ) is typically assigned the highest (maskable) interrupt priority The default priority for maskable interrupt sources follows the address order of the interrupt vector (higher address, higher priority) 232 Clicker Quiz 233 1. Interrupt servicing latency is defined as: A. the time it takes to execute an interrupt service routine B. the time it takes to get to an interrupt service routine once the interrupt request is recognized C. the time it takes to fetch the first instruction of the interrupt service routine once the interrupt request is asserted D. the time it takes to clear the device flag once the interrupt request is asserted E. none of the above 234 2. The nondeterministic component of interrupt servicing latency is the: A. processor latency B. context switch overhead C. instruction completion latency D. instruction fetch latency E. none of the above 235 3. The following step is NOT included as part of the IRQ interrupt handling microsequence: A. look up vector address B. set X bit of CCR C. set I bit of CCR D. push CCR register onto stack E. none of the above 236 4. If an XIRQ request interrupts an IRQ service routine in progress, it is referred to as: A. presumption B. recursion C. preemption D. procrastination E. none of the above 237 5. An IRQ request could interrupt an IRQ routine in progress if: A. the I bit of the CCR is cleared at the beginning of each IRQ service routine B. the X bit of the CCR is cleared at the beginning of each IRQ service routine C. the IRQE bit of the INTCR register is changed D. the IRQEN bit of the INTCR register is changed E. none of the above 238 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-F Buffered, Interrupt-Driven Printer Design Example 239 Outline Design considerations InterruptInterrupt-driven printer interface circuit Device driver routines declarations and initialization routine application program interface routine interrupt service routine interrupt vector re-mapping reReferences: MC9S12C Family Device User Guide, Sec. 5 S12CPU Reference Manual, Sec. 7 240 Design considerations What does an interrupt from the printer mean? mean? Why does the printer interrupt potentially need to be masked? masked? Why is data buffering particularly useful in this design example? 241 Handshaking and Communication Protocol STROBE 1 BUSY DATA Previous Character STEP 1: Check to see if the printer is busy 242 Handshaking and Communication Protocol STROBE 1 BUSY 2 Next Character DATA Previous Character STEP 2: Send data to printer 243 Handshaking and Communication Protocol 3 STROBE 1 BUSY 2 Next Character DATA Previous Character STEP 3: CPU asserts STROBE signal 244 Handshaking and Communication Protocol 3 STROBE 1 4 BUSY 2 Next Character DATA Previous Character STEP 4: Printer asserts BUSY while printing 245 Handshaking and Communication Protocol 3 STROBE 1 4 5 BUSY 2 Next Character DATA Previous Character STEP 5: Printer negates BUSY when print cycle is complete generate interrupt (means: "send me the next character") 246 Design considerations What does an interrupt from the printer mean? mean? Why does the printer interrupt potentially need to be masked? masked? Why is data buffering particularly useful in this design example? 247 Maskable Printer Interrupt Device Flag Edge-triggered "D" flip flop with asynchronous clear input Printer Interrupt Enable (PIE) bit (from CPU) IRQ (to CPU) IRQ can only be asserted if the Printer Interrupt Enable (PIE) bit is high Flag Clear (from CPU) "1" Interrupt Request (from device) CLR D Q Q 248 Design considerations Here, the interrupt masking capability allows the CPU to ignore the printer's request to "send me the next character" when there are none to send Can be thought of as a Digital BinkyTM Without a PIE bit, the CPU would incessantly service "meaningless" printer meaningless" interrupt requests If the device flag is set, but the interrupt enable bit is cleared, the interrupt is referred to as pending 249 250 Design considerations What does an interrupt from the printer mean? mean? Why does the printer interrupt potentially need to be masked? masked? Why is data buffering particularly useful in this design example? 251 Motivation for Buffering Problems data may be coming in (or need to be output) when the "other end" is not ready for it data rate (production/consumption) may be different at each end many CPU cycles can be spent in "spin wait" loops (time spent waiting on a device handshake signal or synchronization variable) Solution data buffering helps "smooth out" program execution and reduce CPU time wasted in "spin wait" loops 252 Outline Design considerations InterruptInterrupt-driven printer interface circuit Device driver routines declarations and initialization routine application program interface routine interrupt service routine 253 Interrupt-Driven Printer Interface Port X.7 . . Port Y.2 IRQ Printer Port Y.3 Port X.0 . CLR D Q Q "1" STROBE BUSY Port Y.1 ...where Port X and Port Y are any available port pins 254 InterruptInterrupt-Driven Printer Interface Port X used to send data to printer Pin 0 of Port Y ("Port Y.0" formerly used to input BUSY signal from printer) not used why is it NOT needed here? When an interrupt is generated by the printer, it automatically means it is "not busy" Pin 1 of Port Y ("Port Y.1") used to supply STROBE signal to printer Pin 2 of Port Y ("Port Y.2") used as the printer interrupt enable bit Pin 3 of Port Y ("Port Y.3") used to supply (active low) FLAG CLEAR signal to the printer device flag 255 Outline Design considerations InterruptInterrupt-driven printer interface circuit Device driver routines declarations and initialization routine application program interface routine interrupt service routine interrupt vector re-mapping re- 256 Declarations smask imask cmask psize pbuf pin pout equ equ equ equ rmb fcb fcb $02 $04 $08 ; STROBE mask ; PIE enable mask ; flag clear mask buffer size printer buffer printer IN ptr printer OUT ptr 100t ; psize; 0 ; 0 ; 257 IRQIRQ-Related Register Initializations Interrupt control and priority registers INTCR (interrupt control) register IRQE (bit 7) "0" IRQ input pin is (active low) level sensitive "1" IRQ input is (negative) edge sensitive IRQEN (bit 6) "0" external IRQ pin disconnected "1" external IRQ pin connected indicates default state after reset 258 Initialization Routine smask imask cmask pinit equ equ equ movb movb bset bclr bset bclr clr bset bclr bset cli rts $02 ; printer STROBE mask $04 ; printer intr en mask $08 ; dev flag clear mask #$FF,ddrx #$0E,ddry porty,cmask porty,cmask ;assert FLG_CLR' porty,cmask ;to initialize porty,imask ;clear PIE bit portx ;ASCII null porty,smask porty,smask ;assert STROBE' porty,smask ;to initialize ;enable IRQ 259 Useful Macro Macro for incrementing B register mod BUFSIZE Example: Example: incBmod 20 ; increments B modulo 20 incBmod MACRO incb cmpb #\1 bne $+3 clrb ENDM 260 Device Driver API Application program interface that places characters in the printer buffer (the "producer") 1. Check status of printer buffer 2. If FULL, wait for space 3. Else, put character in buffer at IN 4. Increment IN modulo BUFSIZE 5. Enable ("unmask") printer interrupts 6. Exit 261 Device Driver API ; Buffered printer spooler routine ; Character passed in A register placed in PBUF ; ; STEP (1) Check PBUF status bps ldab pin incBmod psize ;(B)=(PIN+1)mod PSIZE (B)=(PIN+1)mod pshb ;save on stack ; STEP (2) If FULL, wait for space pwait cmpb beq pout ;perform FULL check ;perform pwait ;wait if PBUF full 262 Device Driver API ; STEP (3) Put character in PBUF at IN ldx #pbuf ldab pin staa b,x ;PBUF[PIN] = (A) PBUF[PIN] ; STEP (4) Increment IN modulo PSIZE pulb ;retrieve from stack stab pin ;PIN=PIN+1 mod PSIZE ;PIN=PIN+1 ; STEP (5) Enable printer interrupts bset porty,imask ; STEP (6) Exit rts 263 Device Driver ISR Interrupt service routine that outputs next character in buffer to the printer (the "consumer") 1. Check status of printer buffer 2. If EMPTY, disable ("mask") printer interrupts and exit 3. Else, clear printer device flag 4. Output character pointed to by OUT 5. Assert printer's STROBE signal 6. Increment OUT modulo BUFSIZE 7. Exit 264 Device Driver ISR ; Printer interrupt service routine ; ; STEP (1) Check PBUF status prisr ldab pout cmpb pin bne pok ;if not empty, print ; STEP (2) If buffer is empty, disable printer ; interrupts and exit bclr porty,imask rti 265 Device Driver ISR ; Printer interrupt service routine ; ; STEP (3) Clear printer device flag pok bclr porty,cmask bset porty,cmask ; STEP (4) Output character pointed to by OUT ldx #pbuf ldaa b,x ;(A)=PBUF[POUT] (A)=PBUF[POUT] staa portx 266 Device Driver ISR ; Printer interrupt service routine ; ; STEP (5) Strobe printer bclr porty,smask bset porty,smask ; STEP (6) Increment OUT mod PSIZE incBmod psize stab pout ;POUT=(POUT+1) mod PSIZE POUT=(POUT+1) ; STEP (7) Exit rti 267 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-G Clocks and Reset Generator (CRG) and Real-Time Interrupt (RTI) 268 Outline Introduction Phase locked loop (PLL) and system clocks generator Clock monitor (CM) Computer operating properly (COP) watchdog timer Real time interrupt (RTI) subsystem Example application: shot clock Reference: Clocks and Reset Generator (CRG) Block User Guide 269 Introduction Main features of the CRG block include: phase locked loop (PLL) frequency multiplier system clock generator clock monitor (CM) computer operating properly (COP) watchdog timer system reset generation real time interrupt (RTI) 270 9S12C32 CRG Block Oscillator, Phase Locked Loop (PLL), and Reset Generation Computer Operating Properly (COP), Clock Monitor (CM), and Real Time Interrupt (RTI) subsystems 271 CRG Block Diagram 272 Phase Locked Loop (PLL) OSCCLK is the crystal oscillator frequency (on 9S12C32, 8 MHz) PLL allows CPU to run a a different clock frequency than OSCCLK (on 9S12C32, the maximum bus clock frequency is 24 MHz) MHz) PLLCLK = 2 X OSCCLK X (SYNR + 1) / (REFDIV + 1) SYNR REFDIV is the OSCCLK divider, SYNR is the PLL multiplier 273 System Clocks Generator Note: If PLL not engaged, bus clock is OSCCLK/2 core clock C R Y S T A L bus clock core clock is 2X bus clock, but a CPU cycle corresponds to one bus clock OSCCLK 274 Clock Monitor (CM) If no OSCCLK edges are detected, the clock monitor within the oscillator block generates a clock monitor fail event CRG then goes into self-clock mode or selfgenerates a system reset The clock monitor function is enabled/disabled by the CME control bit in the PLLCTL register 275 Computer Operating Properly (COP) FreeFree-running watchdog timer that enables the user to check that a program is running and sequencing properly COP times out (and causes a system reset) if it is not "strobed" under software control strobed" within a programmable time frame A "strobe" consists of the sequence $55 followed by $AA written to the ARMCOP register The watchdog timeout rate is set via the COPCTL register 276 Real Time Interrupt (RTI) An interrupt that occurs at a fixed (programmable) rate Used for servicing tasks that require periodic service stopwatch / "shot clock" display update / refresh waveform generation stepper motor sequencing 277 Real Time Interrupt (RTI) Range of programmable interrupt rate: 0.128 131 milliseconds (approx.) Timing reference is OSCCLK (buffered 8 MHz crystal oscillator on 9S12C32) Registers CRGFLG (CRG Flags) register RTIF (bit 7) RTI device flag "0" RTI device flag is clear "1" RTI device flag is set The RTI device flag is cleared by writing a "1" to the RTIF bit 278 Real Time Interrupt (RTI) Registers CRGINT (CRG Interrupt Enable) register RTIE (bit 7) RTI interrupt enable "0" RTI interrupt disabled "1" RTI interrupt enabled RTICTL RTI Control register (bits 6-4) pre-scale rate select bits 6- pre (bits 3-0) modulus counter select bits 3indicates default state after reset 279 RTI Frequency Divide Rates (OSCCLK = 8 MHz) pre-scale rate modulus counter 280 RTI Frequency Divide Rates (OSCCLK = 8 MHz) pre-scale rate 8.192 ms 0.128 ms modulus counter 131.072 ms 2.048 ms 281 Example Application: "Shot Clock" 24 second (NBA) or 35 second (NCAA) "countdown" clock two pushbuttons provide control left reset shot clock right start/stop shot clock use RTI as "time base" for shot clock base" role of interrupt service routine: keep track of the number of RTI interrupts that have accumulated (use variable "RTICNT" for this purpose) set "one second" flag (and reset "RTICNT" to zero) when "one second's worth" of RTI interrupts has accumulated 282 "Shot Clock" Update Algorithm - 1 If the "one second" flag is set, the following actions should take place: clear the "one second" flag if the "run/stop" flag is set (i.e., clock is running), then decrement the shot clock value by one (in BCD) update the seven-segment display sevenIf the left pushbutton ("reset shot clock") flag is set, the following actions should take place: clear the left pushbutton flag reset the display to "35" (or "24" if NBA mode) 283 "Shot Clock" Update Algorithm - 2 If the right pushbutton ("start/stop") flag is set, the following actions should take place: toggle the "run/stop" flag toggle the "run/stop" LED clear the right pushbutton flag If the shot clock has reached "00", the following actions should take place: clear the "run/stop" flag turn on the "time expired" LED turn off the "run/stop" LED 284 Shot Clock Initializations Required CRGINT (CRG Interrupt Enable) register RTIE (bit 7) RTI interrupt enable "0" RTI interrupt disabled "1" RTI interrupt enabled RTICTL RTI Control register (bits 6-4) pre-scale rate select bits 6- pre (bits 3-0) modulus counter select bits 3Pick select bits based on desired interrupt rate...see chart 285 RTI Frequency Divide Rates (OSCCLK = 8 MHz) 8.192 ms 286 Shot Clock Initializations Required CRGINT (CRG Interrupt Enable) register RTIE (bit 7) RTI interrupt enable "0" RTI interrupt disabled "1" RTI interrupt enabled RTICTL RTI Control register (8.192 ms rate) (bits 6-4) pre-scale rate select bits = 111 6- pre (bits 3-0) modulus counter select bits= 0000 3Questions: How many RTI interrupts must accumulate to reach one second at this rate, and how accurate will the time base be? (And, is this the "best" we can do?) 287 Excerpt from RTI One-Second Time Base Spreadsheet Modulus Pre-Scalar PERIOD (ms) 1 10 0.128 2 10 0.256 3 10 0.384 4 10 0.512 5 10 0.640 6 10 0.768 7 10 0.896 8 10 1.024 9 10 1.152 10 10 1.280 11 10 1.408 12 10 1.536 13 10 1.664 14 10 1.792 15 10 1.920 16 10 2.048 1 11 0.256 2 11 0.512 3 11 0.768 4 11 1.024 5 11 1.280 6 11 1.536 7 11 1.792 8 11 2.048 9 11 2.304 10 11 2.560 11 11 2.816 12 11 3.072 13 11 3.328 14 11 3.584 15 11 3.840 16 11 4.096 1 12 0.512 2 12 1.024 3 12 1.536 4 12 2.048 5 12 2.560 6 12 3.072 7 12 3.584 8 12 4.096 9 12 4.608 10 12 5.120 11 12 5.632 12 12 6.144 13 12 6.656 14 12 7.168 15 12 7.680 16 12 8.192 RTICNT 7812 3906 2604 1953 1562 1302 1116 976 868 781 710 651 600 558 520 488 3906 1953 1302 976 781 651 558 488 434 390 355 325 300 279 260 244 1953 976 651 488 390 325 279 244 217 195 177 162 150 139 130 122 Act FAST 999.936 999.936 999.936 999.936 999.680 999.936 999.936 999.424 999.936 999.680 999.680 999.936 998.400 999.936 998.400 999.424 999.936 999.936 999.936 999.424 999.680 999.936 999.936 999.424 999.936 998.400 999.680 998.400 998.400 999.936 998.400 999.424 999.936 999.424 999.936 999.424 998.400 998.400 999.936 999.424 999.936 998.400 996.864 995.328 998.400 996.352 998.400 999.424 Err FAST 0.0064% 0.0064% 0.0064% 0.0064% 0.0320% 0.0064% 0.0064% 0.0576% 0.0064% 0.0320% 0.0320% 0.0064% 0.1600% 0.0064% 0.1600% 0.0576% 0.0064% 0.0064% 0.0064% 0.0576% 0.0320% 0.0064% 0.0064% 0.0576% 0.0064% 0.1600% 0.0320% 0.1600% 0.1600% 0.0064% 0.1600% 0.0576% 0.0064% 0.0576% 0.0064% 0.0576% 0.1600% 0.1600% 0.0064% 0.0576% 0.0064% 0.1600% 0.3136% 0.4672% 0.1600% 0.3648% 0.1600% 0.0576% Act SLOW 1000.064 1000.192 1000.320 1000.448 1000.320 1000.704 1000.832 1000.448 1001.088 1000.960 1001.088 1001.472 1000.064 1001.728 1000.320 1001.472 1000.192 1000.448 1000.704 1000.448 1000.960 1001.472 1001.728 1001.472 1002.240 1000.960 1002.496 1001.472 1001.728 1003.520 1002.240 1003.520 1000.448 1000.448 1001.472 1001.472 1000.960 1001.472 1003.520 1003.520 1004.544 1003.520 1002.496 1001.472 1005.056 1003.520 1006.080 1007.616 Err SLOW 0.0064% 0.0192% 0.0320% 0.0448% 0.0320% 0.0704% 0.0832% 0.0448% 0.1088% 0.0960% 0.1088% 0.1472% 0.0064% 0.1728% 0.0320% 0.1472% 0.0192% 0.0448% 0.0704% 0.0448% 0.0960% 0.1472% 0.1728% 0.1472% 0.2240% 0.0960% 0.2496% 0.1472% 0.1728% 0.3520% 0.2240% 0.3520% 0.0448% 0.0448% 0.1472% 0.1472% 0.0960% 0.1472% 0.3520% 0.3520% 0.4544% 0.3520% 0.2496% 0.1472% 0.5056% 0.3520% 0.6080% 0.7616% 288 Shot Clock Initializations Required clear variable RTICNT (that keeps track of the current number of RTI interrupts accumulated) to zero clear "I" bit (IRQ interrupt mask) of CC register to zero (CLI) 289 RTI Initialization Routine ; Initializes RTI for 8.192 ms interrupt rate ; Enables system (IRQ) interrupts (IRQ) ; ; STEP (1) Clear RTI count clr rticnt ; STEP (2) Configure RTI for 8.192 ms interrupt rate movb #$70,rtictl #$70,rtictl ; STEP (3) Enable RTI and system IRQ interrupts bset crgint,$80 cli rts 290 RTI Interrupt Service Routine Algorithm for servicing RTI 1. Clear RTI device flag 2. Increment RTICNT 122 3. If RTICNT < _____ then exit 4. Else, RTICNT = 0 5. Set "one second" flag 6. Exit Note: 122 x 8.192 ms = 0.999424 sec How accurate is this clock? Runs a bit "fast" off by 0.02 seconds in NCAA mode 291 RTI Interrupt Service Routine ; Keeps track of when one second has expired ; Calls CLOCK and resets RTI interrupt counter rticnt fcb 0 ; RTI interrupt count ; STEP (1) Clear RTI device flag rti_isr bset crgflg,$80 ; STEP (2) Increment RTI count inc rticnt ; STEP (3) If RTICNT < 122, exit ldaa rticnt cmpa #122 blt rti_exit 292 RTI Interrupt Service Routine ; STEP (4) Clear RTICNT and update clock clr rticnt bset onesec,$01 ; STEP (5) Exit rti_exit rti 293 Thought Questions Would picking a different combination of "pre"prescale rate" and "modulus counter select" bits in the RTICTL register allow us to create a more accurate RTI-based shot clock? RTIWhat is the fundamental limitation of the RTI interrupt rate generation/selection? What "mechanism" would provide greater "fine tuning" control over a periodic interrupt rate, and in which of the 9S12C32 modules might we expect to such a mechanism? 294 RTI Frequency Divide Rates (OSCCLK = 8 MHz) pre-scale rate 8.192 ms 0.128 ms modulus counter 131.072 ms 2.048 ms 295 Clicker Quiz 296 1. Initializing CRGINT to $36 produces the following RTI interrupt rate (period), assuming an 8 MHz OSCCLK: A. 1.792 ms B. 3.072 ms C. 3.584 ms D. 4.096 ms E. none of the above 297 2. If CRGINT is set to $36, the following value of RTICNT should be used to produce a time base of approximately one second: A. 122 B. 244 C. 279 D. 488 E. none of the above 298 3. If CRGINT is set to $36 and an RTICNT of 279 is used, the one-second time base error will be: A. 0.0064% B. 0.032% C. 0.0576% D. 0.352% E. none of the above 299 2011 Edition by D. G. Meyer Microcontroller-Based Digital System Design Module 2-H External Microcontroller Interfaces 300 Outline Switching D.C. Loads Optically Isolated Inputs Keypads (Switch Matrices) Rotary Pulse Generators (RPG) Switch (SPST Contact) Debouncer Position Control (Steppers and Servos) LCD Interface / Serial I/O Expansion Digitally Controlled Potentiometer Temperature and Humidity Sensors Digital Compass Accelerometers Hall Effect Sensors Pressure/Force Sensors Ultrasonic Range Finders IR Remote Decoders RF Links (Transmitters/Receivers) 301 Switching D.C. Loads Basic BJT-based switching circuit ("saturated mode") V L LOAD C "current-controlled switch" Port Pin B E NPN BJT IC = hFE x IB Choose BJT based on following parameters ICmax continuous VCE breakdown hFE (D.C. current gain), also called 302 Switching D.C. Loads Use either BJTs or power MOSFETs BJTs: cheap, but may require a significant amount of base current to drive into saturation MOSFETs: tend to be more expensive, but require virtually no gate current to operate Inductive loads require arc suppression diode VL Energy stored in an inductive load must be dissipated, otherwise the "inductive kickback" can damage the switching device 303 Switching D.C. Loads BJT limitations have to use Darlington (more expensive) to get high IC capacity with large hFE generally need base current on the order of (a few) milliamps to switch transistor if "something bad" happens to transistor, can take port pin (and possibly microcontroller) with it use optical isolator to provide protection C B NPN Darlington E 304 Switching D.C. Loads Optically isolated BJT VL LOAD NPN BJT 305 Switching D.C. Loads Optically isolated BJT VL Vcc LOAD NPN BJT active low port pin R1 306 Switching D.C. Loads Optically isolated BJT VL Vcc LOAD NPN BJT active low port pin R1 Assume Vcc = 5 V, VLED = 1.5 V, and VOL @ 10 mA = 0.8V R1 = 2.7/0.01 = 270 307 Switching D.C. Loads Optically isolated BJT VL Vcc VL LOAD R2 active low port pin R1 NPN BJT Assume Vcc = 5 V, VLED = 1.5 V, and VOL @ 10 mA = 0.8V R1 = 2.7 / 0.01 = 270 308 Switching D.C. Loads Optically isolated BJT VL Vcc VL LOAD R2 active low port pin NPN BJT R1 Assume switching 1 amp load, and that hFE of transistor is 100 need 10 mA of base current to saturate transistor (assume VL is 12 V, VBEsat of transistor is 0.7 V, and that VCEsat of photo transistor is 0.3 V) R2 = 11.0 / 0.01 = 1100 309 Switching D.C. Loads Basic MOSFET-based switching circuit VL LOAD "voltage-controlled switch" N-channel power MOSFET Port Pin G D S Choose MOSFET based on following parameters IDmax continuous VDS breakdown rDS (on) (drain-to-source "on" resistance) 310 Switching D.C. Loads MOSFET limitations be careful to choose a MOSFET with a small rDS(on) when switching high current loads (heat, voltage drop) tend to be more "fragile" than BJTs (MOSFETs can be damaged by ESD) if "something bad" happens to transistor, can take port pin (and possibly microcontroller) with it can use same optical isolation circuit used with BJT 311 Optically-Isolated Inputs Off-board (external, remotely located) switch/data inputs should be optically isolated helps reduce noise helps prevent ESD-induced damage prevents "strange" voltages from entering board eliminates ground loops 312 "Ben Franklin Experiment" 313 "Ben Franklin Experiment" 314 "Ben Franklin Experiment" 315 "Ben Franklin Experiment" 316 Optically-Isolated Inputs Off-board (external, remotely located) switch/data inputs should be optically isolated helps reduce noise helps prevent ESD-induced damage prevents "strange" voltages from entering board eliminates ground loops | + Isolated Power Supply (or Battery) Remote Switch 317 Optically-Isolated Inputs Off-board (external, remotely located) switch/data inputs should be optically isolated helps reduce noise helps prevent ESD-induced damage prevents "strange" voltages from entering board eliminates ground loops Vcc L = closed | + H = open Isolated Power Supply (or Battery) Remote Switch 318 Scanned Keypad 319 Scanned Keypad row return lines active low column scan lines 320 Scanned Keypad H H H H row return lines active low column scan lines H H L 321 Scanned Keypad H H H H row return lines active low column scan lines H L H 322 Scanned Keypad H H H H row return lines active low column scan lines L H H 323 Scanned Keypad H H H H row return lines active low column scan lines H H L 324 Scanned Keypad H H H H row return lines active low column scan lines H L H 325 Scanned Keypad H L H H row return lines active low column scan lines L H H 326 Keypad Encoder 327 Rotary Pulse Generator (RPG) 328 RPGs Determine direction of rotation by concatenating "previous" and "current" codes, and using as look-up table index 329 Switch (SPST Contact) Debouncer 330 Position Control Position control required in many applications complications inertia/mechanical loading startup torque different than run torque gear backlash stepping actuators are a good solution for many positioning problems rotational linear why steppers are a good choice high resolution without gearing fast positioning (up to 1000 steps/sec) position error (usually) does not accumulate wide range of high and low torque (large/small) available simple/efficient drive circuitry 331 Stepper Motor Interface 332 L Y L 01 H 00 H 10 11 X VMOTOR FULL STEP MODE 333 H Y L 01 L 00 H 10 11 X VMOTOR FULL STEP MODE 334 H Y H 01 L 00 L 10 11 X VMOTOR FULL STEP MODE 335 L Y H 01 H 00 L 10 11 X VMOTOR FULL STEP MODE 336 L Y L 01 H 00 H 10 11 X VMOTOR FULL STEP MODE 337 L Y H 01 H 00 H 10 11 X VMOTOR HALF STEP MODE 338 L Y L 01 H 00 H 10 11 X VMOTOR HALF STEP MODE 339 H Y L 01 H 00 H 10 11 X VMOTOR HALF STEP MODE 340 H Y L 01 L 00 H 10 11 X VMOTOR HALF STEP MODE 341 H Y H 01 L 00 H 10 11 X VMOTOR HALF STEP MODE 342 H Y H 01 L 00 L 10 11 X VMOTOR HALF STEP MODE 343 H Y H 01 H 00 L 10 11 X VMOTOR HALF STEP MODE 344 L Y H 01 H 00 L 10 11 X VMOTOR HALF STEP MODE 345 L Y H 01 H 00 H 10 11 X VMOTOR HALF STEP MODE 346 Hobbyist Servos Position control Single-wire interface Can not rotate more than ~270 why servos are a good choice Low overhead for control logic-level interface Simple interface (PWM) Pulse width (0.9-2.9s) Refresh period (12-20ms) why servos may not be a good choice Limited range of motion Lower torque 347 LCD Interface 348 Clicker Quiz 349 1. Given that the motor coil requires 1 A of current to operate, that the NPN switching transistor has a VBEsat of 0.6 V and an hFE = 200, and that the microcontroller port pin can source up to 10 mA of current at a VOH of 4.2 V, a suitable value for R would be: A. B. C. D. E. 100 270 720 1000 none of the above 12 V MOTOR 9S12C32 Port Pin NPN R 350 2. If the microcontroller port pin was only capable of sourcing up to 2 mA at a VOH of 4.2 V (e.g., based on changing the pin from "full" drive to "reduced" drive mode), the minimum hFE required to operate the 1 A motor coil would be: 12 V A. B. C. D. E. 100 500 1000 5000 none of the above MOTOR 9S12C32 Port Pin NPN R 351 3. The purpose of the diode in the circuit is to: A. B. C. D. E. protect the microcontroller port pin to dissipate energy in the motor coil when the transistor turns off to dissipate energy in the motor coil when the transistor turns on to limit the amount of current drawn from the 12 V motor supply none of the above 12 V MOTOR 9S12C32 Port Pin NPN R 352 4. Use of optically isolated inputs: A. B. C. D. E. helps prevent ESD-induced damage eliminates ground loops prevents port pins from being driven over/under rated input voltage swing all of the above none of the above 353 5. The following ABEL program does not realize an 8-bit shift register: MODULE shiftregA TITLE `8-bit Shift Register A' DECLARATIONS clock pin; serial_in pin; q0..q7 pin istype `reg'; EQUATIONS [q1..q7] := [q0..q6]; q0 := serial_in; [q0..q7].clk = clock; END MODULE shiftregB TITLE `8-bit Shift Register B' DECLARATIONS clock pin; serial_in pin; q0..q7 pin istype `reg'; EQUATIONS [q0..q7].clk = clock; q7 := serial_in; [q0..q6] := [q1..q7]; (A) END (B) MODULE shiftregC TITLE `8-bit Shift Register C' DECLARATIONS clock pin; serial_in pin; q0..q7 pin istype `reg'; EQUATIONS [q7..q1] := [q6..q0]; q0 := serial_in; [q7..q0].clk = clock; END MODULE shiftregD TITLE `8-bit Shift Register D' DECLARATIONS clock pin; serial_in pin; q0..q7 pin istype `reg'; EQUATIONS q7.d = serial_in; [q0..q6].d = [q1..q7].q; [q0..q7].clk = clock; (C) END (D) (E) none of the above 354 Digitally Controlled Potentiometer 355 Digital Thermometer 356 Humidity and Temperature Sensor 357 Digital Compass 358 Accelerometer 359 Hall Effect Sensor 360 Pressure (Force) Sensor 361 Ultrasonic Range Finder 362 IR Remote 363 RF Link (Transmitter) 364 RF Link (Receiver) 365 ...
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