Unformatted text preview: 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 1 Static and Dynamic Behavior of Digital Circuits
1 Module 1
Desired Outcome: "An ability to analyze static and dynamic behavior of digital circuits" Part A: Review of Basic Electronic Components Part B: Logic Signals and Gates Part C: Steady State Electrical Behavior of CMOS Circuits Part D: Dynamic Behavior of CMOS Circuits Part E: Other CMOS Input/Output Structures and Logic Families
2 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 1A Review of Basic Electronic Components
3 Basic Electronic Concepts
VOLTAGE difference in electrical potential, expressed in volts CURRENT the flow of charge in a conductor between two points having a difference in potential, expressed in amperes (amps) Waterfall analogy voltage is proportional to height of waterfall, current is proportional to flow of waterfall POWER amount of energy, expressed in watts, watts, typically calculated as the product of the voltage drop across a device and the current flowing through it
4 Basic Electronic Concepts
RESISTOR a device that limits the amount of current flowing through a circuit, measured in ohms () Resistance is also referred to as impedance The inverse of impedance is admittance Fundamental relationship the voltage drop (VR) across a resistor is equal to the product of the current flowing through it (IR) and the value of the (I resistance (R) called Ohm's Law VR = IR x R
5 Basic Electronic Concepts
CAPACITOR a device that stores an electric charge, measured in farads (F) Fundamental relationships a resistorcapacitor (RC) network charges resistorand discharges exponentially the voltage across a capacitor cannot change instantaneously the product of R and C is called the RC time constant VC = VIN x (1  et/RC) VIN VC
6 Basic Electronic Concepts
DIODE a device that restricts the flow of current to a single direction (from its anode to its cathode) cathode) Fundamental relationships a diode through which current is flowing (because the voltage at the anode is greater than at the cathode) is forward biased if current is not flowing through a diode (because the voltage at the cathode is greater than at the anode), the diode is reverse biased
7 Basic Electronic Concepts
LIGHT EMITTING DIODE (LED) a diode that emits visible (red/yellow/green/blue/white) or invisible (infrared) light when forwarded biased Fundamental relationships the brightness of an LED is proportional to the amount of current flowing through it current) (called the forward current) a resistor is placed in series with an LED to limit the amount of current flowing through it the voltage drop across an LED when it is forward biased is called the forward voltage 8 Basic Electronic Concepts
FIELD EFFECT TRANSISTOR (FET) a 3terminal device (gate, source, drain) that 3provides a voltagecontrolled impedance voltageTwo basic types Nchannel: high potential on gate causes transistor to turn on (low impedance between source and drain) Pchannel: low potential on gate causes transistor to turn on
Nchannel D Pchannel D
9 G S G S Basic Electronic Concepts
FET acts as a voltagecontrolled switch voltageVCC Nchannel G + VGS RL D S Voltagecontrolled resistance: increase VGS decrease RDS Note: normally, VGS 0 As RDS decreases, power delivered to load (RL) increases  FETs are used to construct Complementary Metal Oxide Semiconductor (CMOS) logic circuits and can also be used to switch DC loads 10 Basic Electronic Concepts
BIPOLAR JUNCTION TRANSISTOR (BJT) a 3terminal device (base, emitter, collector) 3that provides a currentcontrolled impedance currentTwo basic types Nchannel: small current flowing into base through emitter causes large current to flow from collector to emitter Pchannel: small current flowing out of base through emitter causes large current to flow from emitter to collector
Nchannel C E Pchannel C E
11 B B Basic Electronic Concepts
BJT acts like a currentcontrolled switch current NPN
small BE current B C E LARGE CE CURRENT BJTs are used to construct TransistorTransistor Logic (TTL) and can also be used to switch high voltage/current DC loads
12 Basic Electronic Concepts
INTEGRATED CIRCUIT (IC) a collection of logic gates and/or other electronic circuits fabricated on a single silicon chip PROGRAMMABLE LOGIC DEVICE (PLD) an integrated circuit onto which a generic logic circuit can be programmed (and be subsequently erased and reprogrammed) reCOMPUTER a digital device that sequentially executes a stored program MICROPROCESSOR a singlechip singleembodiment of the major functional blocks of a computer
13 Basic Electronic Concepts
MICROCONTROLLER a complete computer on a chip, including integrated peripherals (memory, analogtodigital analogtoconversion, serial communications, pulsepulsewidth modulation, timers, network interface) SOCIALLY REDEEMING something that has inherent value (like studying digital systems design) DIGIJOCK(ETTE) a person who enjoys learning about digital systems 14 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 1B Logic Signals and Gates
15 Reading Assignment: 3rd Ed., pp. 7995; 4th Ed., pp. 7996 7979Instructional Objectives:
To learn a definition of Boolean algebra To learn about the three major operators in Boolean algebra and the symbols used to represent them To learn about the basic logic gates that are used to implement digital circuits To learn about the circuits that are used to implement logic gates
16 Outline
Definition of Boolean Algebra Logic signals and assertion levels Combinational digital logic circuits Boolean's "big three" operators Logic families CMOS logic Switch analogies and implementations 17 Boolean Algebra
Definition: Definition: A Boolean Algebra is a triplet [K, +, ] consisting of a finite set of elements, K, subject to an equivalence relationship, "=", and two "= binary operators denoted "+" (OR) and "+ "" (AND); such that for every element X and Y contained in K, the operations X + Y and X Y are uniquely defined and Huntington's Postulates (described later) are satisfied.
18 Boolean Algebra
Definition: Definition: An equivalence relation is
some relation R defined on a set K which satisfies the following three basic properties: Reflexive  for every X in the set K, the relationship XRX holds Symmetric  for every X and Y in the set K, the relationship YRX holds whenever the relationship XRY holds Transitive  for every X, Y, and Z in the set K, if the relationships XRY and YRZ hold, then the relationship XRZ holds
19 Boolean Algebra
Definition: Definition: A binary variable, X, is a twovariable, twovalued quantity such that: if X 1, then X = 0 if X 0, then X = 1 K = {0, 1} 20 Boolean Algebra
Huntington's Postulates
P1. The operations are closed For all X and Y K, (a) X + Y K (b) X Y K P2. For each operation, there exists an identity element (a) There exists an element 0 K such that for all X K, X + 0 = X (b) There exists an element 1 K such that for all X K, X 1 = X 21 Boolean Algebra
Huntington's Postulates
P3. The operations are commutative For all X and Y K, (a) X + Y = Y + X (b) X Y = Y X P4. The operations are distributive For all X, Y and Z K, (a) X + (Y Z) = (X + Y) (X + Z) (b) X (Y + Z) = XY + XZ 22 Boolean Algebra
Huntington's Postulates
P5. For every element X K there exists an element X K (called the complement X of X) such that (a) X + X = 1 X (b) X X = 0 X P6. There exist at least two elements, X and Y K, such that X Y 23 Logic Signals
A logic value, 0 or 1, is often referred binary digit to as a binary digit or bit The words "LOW" and "HIGH" are "LOW" "HIGH" "1 often used in place of "0" and "1" to "0 refer to logic signals LOW  a signal in the range of "lower" voltages (e.g., 0  1.5 volts for CMOS logic), which is interpreted as a logic 0 HIGH  a signal in the range of "higher" voltages (e.g., 3.5  5.0 volts for CMOS logic), which is interpreted as a logic 1
24 Logic Signals
Note: Note: The assignment of 0 and 1 to LOW and HIGH, respectively, is referred to as HIGH, a positive logic convention (or simply "positive logic") a positive logic signal that is asserted is in the HIGH state, and is therefore referred to as an "active high" signal a positive logic signal that is negated is in the LOW state 25 Logic Signals
The opposite assignment (1 to LOW and 0 to HIGH) is referred to as a negative HIGH) logic convention (or "negative logic") a negative logic signal that is asserted is in the LOW state, and is therefore referred to as an "active low" signal a negative logic signal that is negated is in the HIGH state 26 Logic Signals
A logic circuit can be represented as simply a "black box" with a certain number of inputs and outputs
X1 X2 . . . f f (X1,X2, ... , Xn) Xn Since the inputs of a digital logic circuit can be viewed as discrete 0 and 1 values, the circuit's "logical" operation can be described using a table that lists discrete 0 and 1 functional outputs
27 Combinational Circuits
A logic circuit whose outputs depend only on its current inputs is called a combinational circuit A truth table can be used to fully describe the operation of a combinational logic circuit Three basic logic functions AND, OR, and NOT can be used to build any digital combinational logic circuit (idea of logical completeness) completeness) 28 Boolean's Big Three
An AND gate produces a 1 output if and only if all of its inputs are 1 An OR gate produces a 1 output if one or more of its inputs are 1 A NOT gate (usually called an inverter) inverter) produces an output value that is the inversion opposite of its input value bubble 29 Another "102" (Two)
A NAND gate produces the opposite of an AND gate's output A NOR gate produces the opposite of an OR gate's output 30 Time Matters
Logic gates require a certain amount of "think time" to produce a new output in response to changing inputs referred to as the propagation delay of the gate The propagation delay of a logic circuit may vary depending on whether its output signal is transitioning from lowtohigh (rise lowtopropagation delay) or from hightolow (fall delay) hightopropagation delay) delay) A timing diagram can be used to show how a logic circuit responds to timevarying timeinput signals
31 Time Matters
Time response of a combinational circuit 32 Logic Families
There are many ways to design a digital logic gate, from mechanical relays and vacuum tubes to microscopic transistors The most successful bipolar logic family is TransistorTransistor Logic (TTL) ransistor(TTL) Complementary MetalOxide Semiconductor etal(CMOS) circuits now account for the vast CMOS) majority of the worldwide Integrated Circuit IC) (IC) market CMOS logic is both the most capable and the easiest to understand commercial digital logic technology
33 CMOS Logic
CMOS logic levels indeterminate region undefined input yields undefined output Note: CMOS circuits using other power supply voltages (e.g., 3.3 or 2.7 volts) partition the voltage range similarly
34 CMOS Logic
MOS transistor Modeled as a 3terminal device that acts like a voltagecontrolled resistance In digital logic applications, a MOS transistor is operated so that its resistance is either very high (transistor is "off") or very low (transistor is "on")
35 CMOS Logic
There are two types of MOS transistors Nchannel MOS (NMOS) D G
VGS Voltagecontrolled resistance: increase VGS decrease RDS Note: normally, VGS 0 S S
Voltagecontrolled resistance: decrease VGS decrease RDS Note: normally, VGS 0
36 Pchannel MOS (PMOS)
VGS G D Basic CMOS Inverter Circuit
circuit diagram logical behavior switch analogy 37 Basic CMOS NAND Gate
"OR" "AND"
38 Basic CMOS NOR Gate
"AND" "OR"
39 Exercise:
Transform this 2input NOR gate into a 3input NOR gate 40 Exercise:
Transform this 2input NOR gate into a 3input NOR gate 41 Exercise:
Transform this 2input NOR gate into a 3input NOR gate C
42 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 1C Steady State Electrical Behavior of CMOS Circuits
43 Reading Assignment: 3rd Ed., pp. 96113; 4th Ed., pp. 96114 9696Instructional Objectives:
To be able to read and understand device data sheets and specifications, in order to create reliable and robust realworld circuits realand systems To be able to use data on logic levels to calculate the DC noise margin of a circuit To be able to use data on sourcing and sinking currents to calculate fanout fanTo learn about the deleterious side effects of excessive output loading, unused inputs, noise spikes, and electrostatic discharge
44 Outline
Overview Data sheets Noise Logic levels and noise margins Sourcing and sinking current NonNonideal inputs FanFanin and Fanout FanEffects of loading Unused inputs Current spikes and decoupling Electrostatic discharge
45 Overview
Objective: To be able to design real circuits using CMOS or other logic families need to ensure that the "digital abstraction" abstraction" is valid for a given circuit need to provide adequate engineering design margins to ensure that a circuit will work properly under a variety of conditions need to be able to read and understand data sheets and specifications, in order to create reliable and robust realworld realcircuits and systems
46 Data Sheet for a Typical CMOS Device 47 Noise
The main reason for providing engineering design margins is to ensure proper operation in the presence of noise Examples of noise sources: cosmic rays magnetic fields generated by machinery power supply disturbances the "switching action" of the logic circuits "switching action" themselves 48 Logic Levels and Noise Margins
Typical inputoutput transfer inputcharacteristic of a CMOS inverter Problem: Typical, NOT guaranteed! 49 Logic Levels and Noise Margins
Factors that cause the transfer characteristic to vary power supply voltage temperature output loading conditions under which a device was fabricated Sound engineering practice dictates that we use more "conservative" conservative" specifications for LOW and HIGH
50 Logic Levels and Noise Margins
Definitions: Definitions: VOHmin  the minimum output voltage in
the HIGH state VIHmin  the minimum input voltage
guaranteed to be recognized as a HIGH VILmax  the maximum input voltage
guaranteed to be recognized as a LOW VOLmax  the maximum output voltage in
the LOW state
51 Logic Levels and Noise Margins
CMOS levels are typically a function of the power supply "rails" VOHmin Vcc 0.1v VIHmin 70% of Vcc VILmax 30% of Vcc VOLmax GND + 0.1v
DC noise margin is a measure of how much noise it takes to corrupt a worstcase output voltage into a value that may not be recognized properly by an input 52 Data Sheet for a Typical CMOS Device 53 Logic Levels and Noise Margins
Calculation of DC noise margin (or the "noise immunity margin") DCNM = min (VOHmin VIHmin, VILmax VOLmax) Example: HCExample: HCseries CMOS DCNM = min (4.4 3.15, 1.35 0.1)
= 1.25 v
54 NonNonideal Inputs
If the inputs to a CMOS circuit are not close to the Vcc / GND rails, the "on" transistor may not be fully on and the "off" transistor may not be fully off causing power dissipation of the device to increase 55 Clicker Quiz 56 1. For CMOS gates, VIHmin is typically:
A. B. C. D. E. 10% of the supply voltage (Vcc) 30% of the supply voltage (Vcc) 50% of the supply voltage (Vcc) 70% of the supply voltage (Vcc) 90% of the supply voltage (Vcc) 57 2. For CMOS gates, the switching threshold
is typically: A. B. C. D. E. 10% of the supply voltage (Vcc) 30% of the supply voltage (Vcc) 50% of the supply voltage (Vcc) 70% of the supply voltage (Vcc) 90% of the supply voltage (Vcc) 58 3. If a CMOS gate input voltage is 50% of its Vcc
(power supply) voltage, then: A. the logic gate will dissipate less power than it would if the input was 1% of its power supply voltage B. the logic gate will dissipate less power than it would if the input was 99% of its power supply voltage C. the logic gate will dissipate more power than it would if the input was either 1% or 99% of its power supply voltage D. the logic gate will dissipate no power E. none of the above
59 Sourcing and Sinking Current
CMOS gate inputs have a very high impedance and consume very little current from the circuits that drive them I IL the maximum current that flows into the input in the LOW state the maximum current that flows into the input in the HIGH state I IH For CMOS logic, the input current is very small it takes very little power to maintain a CMOS input in either the HIGH or LOW state
60 Sourcing and Sinking Current
IC manufacturers specify a maximum load for the output in each state (HIGH or LOW) and guarantee a worstcase output voltage worstfor that load IOLmax  the maximum current that the
output can "sink" in the LOW state while still maintaining an output voltage no greater than VOLmax IOHmax  the maximum current that the
output can "source" in the HIGH state while still maintaining an output voltage no less than VOHmin
61 Sourcing and Sinking Current
Circuit definitions of IOLmax and IOHmax X X sinking current (positive)
current arrow
NOTE: Convention is for the input/output current arrows to point "in" sourcing current (negative)
62 Sourcing and Sinking Current
Often times gate outputs need to drive devices that require a nontrivial amount of noncurrent to operate called a resistive load or D.C. load When driving a resistive load, the output of a CMOS circuit is not nearly as ideal as described previously In either output state, the CMOS output transistor that is "on" has a nonzero nonresistance, and a load connected to its output terminal will cause a voltage drop across this resistance
63 Sourcing and Sinking Current
Therefore, most CMOS devices have two sets of loading specifications "CMOS loads" device output connected to other CMOS inputs, which consume very little current "D.C. loads" device output connected to resistive loads (devices that consume significant current) Note: With "D.C. loads" the output voltage swing of a CMOS circuit may significantly degrade
64 FanFanin
Definition: Definition: The number of inputs a gate can have in a particular logic family is called the logic family's fanin fanCMOS gates with more than two inputs can be obtained by extending the "series"seriesparallel" circuit designs (e.g., for NAND and NOR gates) illustrated in the previous lecture In practice, the additive "on" resistance of series transistors limits the fanin of CMOS fangates to a relatively small number Gates with a large number of inputs can be made faster and smaller by cascading gates with fewer inputs 65 FanFanout
Definition: Definition: The number of gate inputs that a gate output can drive without exceeding its worstcase loading specifications worst depends on characteristics of both the output device and the inputs being driven must be examined for both the "sourcing" and "sinking" cases practical limitations due to capacitive loading (AC vs. DC fanout) fan FanFanout = min ( IOHmax / IIH, IOLmax / IIL)
66 Data Sheet for a Typical CMOS Device 67 FanFanout
Example: HCExample: HCseries CMOS FanFanout = min ( IOHmax / IIH, IOLmax / IIL ) = min (0.02 mA / 0.001 mA, 0.02 mA / 0.001 mA)
= 20
Note: DC fanout is considerably greater in this case if the output voltage swing is degraded ... but DCNM is lower and signal transitions times are longer, causing speed degradation
68 Practical Fanout FanIn a practical application, a gate output may drive a "mixture" of loads HIGHHIGHstate fanout The sum of the IIHmax fanvalues of all the driven inputs must be less than or equal to the IOHmax of the driving output LOWLOWstate fanout The sum of the IILmax fanvalues of all the driven inputs must be less than or equal to the IOLmax of the driving output The "practical" fanout is the minimum of the HIGH and LOWstate fanouts 69 Clicker Quiz 70 DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH VOL)/2 VOH = 3.50 V IOH = 5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 A IIL = 2.0 mA 1. The DC noise margin for this logic family is:
A. B. C. D. E. 0.50 V 1.00 V 1.50 V 2.00 V none of the above
71 DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH VOL)/2 VOH = 3.50 V IOH = 5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 A IIL = 2.0 mA 2. The practical fanout for this logic family is:
A. B. C. D. E. 1 2 5 10 none of the above
72 3. The nominal (minimum) case for the outputs
of logic family "A" to be able to successfully drive the inputs of logic family "B" is: A. fanoutAB 1 and DCNMAB < 0 B. fanoutAB 0 and DCNMAB < 1 C. fanoutAB 1 and DCNMAB > 0 D. fanoutAB 0 and DCNMAB > 1 E. none of the above
73 Effects of Loading
Loading a gate output beyond its rated fanout can have several deleterious effects: fan in the LOW state, the output voltage (VOL) may increase beyond VOLmax in the HIGH state, the output voltage (VOH) may fall below VOHmin output rise and fall times may increase beyond their specifications the operating temperature of the device may increase, thereby reducing the reliability of the device and eventually causing device failure
74 Unused Inputs
Unused ("spare") CMOS inputs should never be left unconnected ("floating") A small amount of circuit noise can temporarily make a floating input look HIGH Instead, unused inputs should be: tied to another input of the same gate tied HIGH (for AND and NAND gates) tied LOW (for OR and NOR gates)
pullup resistor pulldown resistor 75 Current Spikes and Decoupling
When a CMOS gate output changes state, the P and Nchannel transistors are both PNpartially on simultaneously, causing a current spike Current spikes often show up as noise on the power supply and ground connections Decoupling capacitors (between Vcc and GND) must be distributed throughout a printed circuit board (PCB) to supply extra current during transitions to CMOS ICs VERY IMPORTANT FOR SENIOR DESIGN PROJECTS!! 76 Electrostatic Discharge
CMOS device inputs are subject to damage from electrostatic discharge (ESD) Apply these precautions in lab: before handling a CMOS device, touch a source of earth ground transport CMOS devices in conductive bags, foam, or tubes handle circuit boards containing CMOS devices by the edges; touch a ground edges; terminal on the board to earth ground before "poking around with it"
77 Clicker Quiz 78 1. When a gate's rated IOH specification is
exceeded, the following is likely to happen: A. the VOH of the gate will increase and the tTLH of the gate will decrease B. the VOH of the gate will decrease and the tTLH of the gate will increase C. the VOL of the gate will increase and the tTHL of the gate will increase D. the VOL of the gate will decrease and the tTHL of the gate will decrease E. none of the above 79 2. When a gate's rated IOL specification is
exceeded, the following is likely to happen: A. the VOH of the gate will increase and the tTLH of the gate will decrease B. the VOH of the gate will decrease and the tTLH of the gate will increase C. the VOL of the gate will increase and the tTHL of the gate will increase D. the VOL of the gate will decrease and the tTHL of the gate will decrease E. none of the above 80 3. The largest source of noise in a digital
circuit is from: A. RF communication devices (e.g., cell phones) B. cosmic rays C. power line disturbances D. the logic gates themselves E. none of the above 81 4. Electromagnetic interference could cause
a "floating" (unconnected) gate input to: A. change from hightolow or from lowtohigh (be unpredictable) B. increase the VIH of the gate relative to its specified value C. decrease the VIL of the gate relative to its specified value D. pick up the satellite broadcast of a Purdue basketball victory E. none of the above 82 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 1D Dynamic Behavior of CMOS Circuits
83 Reading Assignment: 3rd Ed., pp. 113122; 4th Ed., 114128 113114Instructional Objectives:
To learn what factors influence the performance of a CMOS circuit To learn the definition of transition time and how to measure it To learn how to analyze and estimate the transition times of a CMOS circuit To learn about the effects of capacitive loading on a CMOS circuit To learn the definition of propagation delay and how to measure it To learn about the sources of power dissipation in a CMOS circuit 84 Outline
Overview Transition time Capacitive loading Propagation delay Power consumption 85 Overview
The speed and power consumption of a CMOS device depend on the dynamic ("A.C.") characteristics of the device and its load Logic designers must carefully examine the effects of output loading and redesign where the loading is too high Speed (performance) depends on two characteristics: transition time propagation delay 86 Transition Time
Definition: Definition: The amount of time that the output of a logic circuit takes to change from one state to another rise time (tr or tTLH): the time an output signal takes to transition from lowtohigh lowto fall time (tf or tTHL): the time an output hightosignal takes to transition from hightolow Gate outputs can not change state instantaneously (i.e., with a transition time of zero) because they need to charge the stray capacitance of the wires and other components they drive
87 Transition Time
"ideal" "less ideal" "reality" Note: tf is typically not equal to tr 88 Transition Time
To avoid difficulties in defining the endpoints, transition times are normally measured one of two different ways: at the boundaries of the valid logic levels (i.e., VIHmin and VILmax) at the 10% and 90% points of the output waveform Using the first convention (above), the rise and fall times indicate how long it takes for an output signal to pass through the (undefined) indeterminate region between LOW and HIGH
89 Transition Time
The transition times of a CMOS circuit depend mainly on two factors: the "on" transistor resistance the load capacitance Stray capacitance (called an "A.C. load") "A.C. load") arises from at least three different sources: output circuits including transistors, internal wiring, and packaging wiring that connects a gate output to other gate inputs input circuits including transistors, internal wiring, and packaging
90 Transition Time
A gate output's load can be modeled by an equivalent load circuit with 3 components: RL and VL represent the D.C. load they determine the steady state voltages and currents present and do not have much effect on transition times CL represents the A.C. (capacitive) load it determines the voltages and currents present while the output is changing, as well as how long it takes to change from one state to another
91 Equivalent Circuit for Transition Time Analysis of a CMOS Output 92 Model of a CMOS LOWtoHIGH LOWtoTransition (with Negligible DC Load)
Capacitor is initially discharged RP CL rise time The time constant is RPCL VIHmin VILmax
93 Model of a CMOS HIGHtoLOW HIGHtoTransition (with Negligible DC Load)
Capacitor is initially charged CL RN Fall time The time constant is RNCL VIHmin VILmax
94 Example
Given that a CMOS inverter's Pchannel MOSFET Phas an ON resistance of 200, that its Nchannel 200 NMOSFET has an ON resistance of 100, and that the 100 capacitive (or "A.C.") load CL = 200 pF, calculate the fall time initial conditions 95 Example
Given that a CMOS inverter's Pchannel MOSFET Phas an ON resistance of 200, that its Nchannel 200 NMOSFET has an ON resistance of 100, and that the 100 capacitive (or "A.C.") load CL = 200 pF, calculate the fall time initial conditions output goes low 96 Example
Fall time calculation:
t = RnCLln (Vout/VDD) = 1002001012ln (Vout / 5.0) = 20109ln (Vout / 5.0) t3.5 = 20109ln (3.5/5.0) = 7.13 ns t1.5 = 20109ln (1.5/5.0) = 24.08 ns fall time = 24.08 7.13 = 16.95 ns
97 Transition Time
Conclusion: Conclusion: An increase in load capacitance causes an increase in the RC time constant and a corresponding increase in the output transition (rise/fall) times Load capacitance must be minimized to obtain high circuit performance this can be achieved by: minimizing the number of inputs driven by a given signal creating multiple copies of the signal (using "buffers") careful physical layout of the circuit
98 Transition Time
Rule of Thumb: In practical circuits, the Thumb: transition time can be estimated using the RC time constant of the charging or discharging circuit Final note: Calculated transition times are note: sensitive to the choice of logic levels (i.e., VIHmin and VILmax) 99 Example
Given that a CMOS inverter's Pchannel MOSFET Phas an ON resistance of 200, that its Nchannel 200 NMOSFET has an ON resistance of 100, and that the 100 capacitive (or "A.C.") load CL = 200 pF, estimate the fall time and rise time Fall time estimate: RN X CL = 100 X 200 pF = 1 X 102 X 2 X 1010 = 2 X 108 = 20 X 109 = 20 ns Rise time estimate: RP X CL = 200 X 200 pF = 2 X 102 X 2 X 1010 = 4 X 108 = 40 X 109 = 40 ns
100 Propagation Delay
Definition: Definition: The electrical path from a particular input signal of a logic element to its output signal is called a signal path Definition: Definition: The amount of time it takes for a change in an input signal to cause a corresponding change in a gate's output signal is called the propagation delay (tp) The propagation delay for an output signal going from LOWtoHIGH (tPLH) may be LOWtodifferent than the propagation delay of that signal going from HIGHtoLOW (tPHL) HIGHto101 Propagation Delay
Ignoring rise and fall times Measured at midpoints of transitions 102 Propagation Delay
Several factors lead to nonzero nonpropagation delays in CMOS circuits: the rate at which transistors change state is influenced both by semiconductor physics and the circuit environment (input signal transition time, input capacitance, and output loading) multistage devices (e.g., noninverting nongates) may require several internal transistors to change state before the output can change state
103 Example
Find each of the following, rounded to the nearest ns (assume each division is 1 ns) 104 Example
Find each of the following, rounded to the nearest ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns 105 Example
Find each of the following, rounded to the nearest ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns 106 Example
Find each of the following, rounded to the nearest ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly's definition = 2 ns (30%70%) 107 Example
Find each of the following, rounded to the nearest ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly's definition = 2 ns (30%70%) Rise time (tTLH) based on standard 10%90% definition = 3.5 ns 108 Example
Find each of the following, rounded to the nearest ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly's definition = 2 ns (30%70%) Rise time (tTLH) based on standard 10%90% definition = 3.5 ns Fall time (tTHL) based on Wakerly's definition = 1 ns (70%30%)
109 Example
Find each of the following, rounded to the nearest ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly's definition = 2 ns (30%70%) Rise time (tTLH) based on standard 10%90% definition = 3.5 ns Fall time (tTHL) based on Wakerly's definition = 1 ns (70%30%) Fall time (tTHL) based on standard 90%10% definition = 2.5 ns
110 Power Consumption
Definition: Definition: The power consumption (dissipation) of a CMOS circuit whose output is not changing is called static (quiescent) power dissipation Most CMOS circuits have very low static power dissipation CMOS circuits only dissipate a significant amount of power during transitions this is called dynamic power dissipation 111 Power Consumption
Sources of dynamic power dissipation: the partial "shortcircuiting" of the CMOS "shortoutput structure (e.g., when the input voltage is not close to one of the power supply rails) called "PT" (power due to (power output transitions) transitions) the capacitive load on the output (power is dissipated in the "on" resistance of the active transistor to charge/discharge the capacitive load) called "PL" (power due (power to charging/discharging load) load)
112 Power Consumption
Total dynamic power dissipation (PT + PL) is proportional to the square of the power supply voltage times the transition frequency Conclusions: power dissipation increases linearly as the frequency of operation increases reducing the power supply voltage results in a quadratic reduction of the power dissipation 113 Example
A microcontroller dissipates 100 mW of power when operated at a clock frequency MHz. of 10 MHz. What will be its power dissipation if the clock frequency is reduced to 2 MHz? MHz? Answer: 2/10 X 100 mW = 20 mW 114 Example
A microcontroller dissipates 100 mW of power when operated at a supply voltage of 5 VDC. What will be the its power VDC. dissipation if the supply voltage is reduced to 3 VDC? VDC? Answer: (3/5)2 X 100 mW = 36 mW 115 Clicker Quiz 116 1. Assume a CMOS microprocessor dissipates 100 milliwatts of power when operated at a clock frequency of 100 MHz with a supply voltage of 5 V. If the frequency of operation is reduced from 100 MHz to 40 MHz (and the supply voltage remains 5 V), the power dissipation will be reduced to: A. 16 mW B. 25 mW C. 40 mW D. 64 mW E. none
117 2. Assume a CMOS microprocessor dissipates 100 milliwatts of power when operated at a clock frequency of 100 MHz with a supply voltage of 5 V. If the supply voltage is reduced from 5 V to 4 V (and the frequency of operation remains 100 MHz), the power dissipation will be reduced to: A. 16 mW B. 25 mW C. 40 mW D. 64 mW E. none
118 3. Assume a CMOS microprocessor dissipates 100 milliwatts of power when operated at a clock frequency of 100 MHz with a supply voltage of 5 V. If the frequency of operation is reduced to 1 Hz (and the supply voltage remains 5 V) , the power dissipation will be reduced to: A. 16 mW B. 25 mW C. 40 mW D. 64 mW E. none
119 4. The rise time for the inverter is approximately: A. 1.0 ns B. 1.5 ns C. 2.0 ns D. 3.0 ns E. none 120 5. The fall propagation delay for the inverter is approx: A. 1.0 ns B. 1.5 ns C. 2.0 ns D. 3.0 ns E. none 121 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 1E Other CMOS Input/Output Structures and Logic Families
122 Reading Assignment: 3rd Ed., pp. 123142, 149154, 166171; 1231491664th Ed., pp. 129154, 158170 129158Instructional Objectives:
To learn about specialized CMOS circuit structures, including: Schmitttrigger inputs Schmitt threestate outputs three open drain outputs To learn what wired logic is and how it works To lean how to interface TTL and CMOS gates
123 Outline
Overview SchmittSchmitttrigger inputs TriTristate outputs Open drain outputs Driving LEDs Wired logic CMOS/TTL interfacing 124 Overview
The basic CMOS circuit has been "tailored" in many ways to produce gates for specific applications This circuit tailoring has been motivated by the need for: higher performance than can be achieved with "standard" NAND/NOR gates "conditioning" noisy, slowly changing logic signals allowing logic elements to communicate via buses
125 SchmittSchmittTrigger Inputs
Definition: Definition: A Schmitt trigger is a special circuit that shifts the switching threshold depending on whether the input is changing from LOWtoHIGH or from HIGHtoLOW LOWtoHIGHtoThe difference between the two thresholds is called hysteresis
Symbol used to denote hysteresis 126 Comparison of an Ordinary Inverter to a Schmitt Trigger for a Noisy, Slowly Changing Input Signal Regular Inverter Schmitt trigger
127 Comparison of an Ordinary Inverter to a Schmitt Trigger for a Noisy, Slowly Changing Input Signal Regular Inverter Schmitt trigger
128 SchmittSchmittTrigger Inputs
Observations: Schmitttrigger inputs have better noise Schmittimmunity margin than ordinary gates for noisy or slowly changing signals "Distorted" logic signals of this type typically occur in physically long connections, connections, such as I/O buses and computer interface cables Rule of "foot" Logiclevel signals can be sent reliably over a cable for only a few feet
129 ThreeThreeState Logic
Definition: Definition: A gate output that has a third "electrical state" is called a threestate threeoutput (or tristate output) trioutput) This third electrical state is called the high impedance, Hiimpedance, HiZ, or floating state In the high impedance state, the gate output effectively appears to be disconnected from the rest of the circuit ThreeThreestate devices have an extra input, typically called the Output Enable (OE), for enabling data to "flow through" the device (when asserted) or placing the output in the high impedance state (when negated) 130 CMOS ThreeState Buffer ThreeL L L
The most common use of these devices is to create data buses (collection of signal lines) over which computational subsystems can (bidirectionally) send and receive data
131 H HiZ Hi CMOS ThreeState Buffer ThreeH L H
The most common use of these devices is to create data buses (collection of signal lines) over which computational subsystems can (bidirectionally) send and receive data
132 H L CMOS ThreeState Buffer ThreeH H L
The most common use of these devices is to create data buses (collection of signal lines) over which computational subsystems can (bidirectionally) send and receive data
133 L H OpenOpenDrain Outputs
Definition: Definition: A CMOS output structure that does not include a pchannel transistor is pcalled an opendrain output openAn opendrain output is in one of two states: openLOW or "open" (i.e., disconnected) An underscored diamond is used to indicate that an output is open drain An opendrain output requires an external openpullup resistor to passively pull it high in the "open" state (since the output structure open" pullup) does NOT include a pchannel active pullup) p134 OpenOpenDrain CMOS NAND Gate H H Symbol that denotes an opendrain output
135 OpenOpenDrain Gate Driving a Load
Note: Rise time of an opendrain output is much slower than that of a standard gate 136 Driving LEDs
One application for opendrain outputs is opendriving lightemitting diodes (LEDs) light R = (VCC VOL VLED) / ILED
This is OHM'S LAW
137 Driving LEDs
Standard CMOS gate outputs can also be used to drive LEDs, either by "sinking" current (LOW) or "sourcing" current (HIGH) Question: Which method is preferred? 138 Example: Based on the data provided in Table 33
of the course text, calculate the value of the LED current limiting resistor for the worst case current sinking configuration. Also calculate the amount of power dissipated by the current limiting resistor. Assume VLED is 1.9 volts. 139 Table 3.3 from DDPP 140 SOLUTION:
VR = 5.0 VLED VOL = 5.0 1.9 0.33 = 2.77 V NOTE: Here, use "Max" value indicated for VOL of 0.33 V R = VR/IOL = 2.77/0.004 = 693 PR = R x IOL2 = 693 x (0.004)2 = 11.1 milliwatts NOTE: Can also calculate power dissipation of resistor using VR x IOL or (VR2)/R 4.0 mA 0.33 VDC 141 Example: Based on the data provided in Table 33
of the course text, calculate the value of the LED current limiting resistor for the worst case current sourcing configuration. Also calculate the amount of power dissipated by the current limiting resistor. Assume VLED is 1.9 volts. 142 Table 3.3 from DDPP 143 SOLUTION:
VR = VOH VLED = 3.84 1.9 = 1.94 V NOTE: Here, use "Min" value indicated for VOH of 3.84 V R = VR/IOH = 1.94/0.004 = 485 PR = R x IOH2 = 485 x (0.004)2 = 7.8 milliwatts NOTE: Can also calculate power dissipation of resistor using VR x IOH or (VR2)/R 4.0 mA 3.84 VDC 144 Clicker Quiz 145 DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH VOL)/2 VOH = 3.50 V IOH = 5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 A IIL = 2.0 mA 1. When interfacing an LED that has a forward
voltage of 1.5 V to this logic family in a current sourcing configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value:
A. 200 B. 300 C. 400 D. 500 E. none of these
146 DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH VOL)/2 VOH = 3.50 V IOH = 5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 A IIL = 2.0 mA 2. When interfacing an LED that has a forward
voltage of 1.5 V to this logic family in a current sinking configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value:
A. 200 B. 300 C. 400 D. 500 E. none of these
147 Wired Logic
Definition: Definition: Wired logic is performed if the outputs of several opendrain gates are tied opentogether with a single pullup resistor pull NOT an actual gate! Caution: This ONLY works for opendrain outputs!
148 Illustration of "Fighting" Illustration of what happens if two ordinary CMOS gate outputs are tied together... (don't try this at home!) 149 PullPullup Resistors
In opendrain applications, two calculations openbracket the allowable values of the pullup pullresistor R: LOW The sum of the current through R plus the LOW state input currents of the gate inputs driven must not exceed the IOLmax of the active device HIGH The voltage drop across R in the HIGH state must not reduce the output voltage below the VIHmin of the driven gate inputs
150 Pullup Resistor Calculation
High State
Here, the pullup resistor must be no more than the value Rmax such that the voltage drop across it does not exceed 5.0 2.4 = 2.6 V when 60 A of current is flowing through it. Applying Ohm's Law , we find that Rmax is 2.6/0.00006 = 43,333 ohms. 151 Pullup Resistor Calculation
Low State
Here, the constraint is that the pullup resistor must be chosen such that the voltage drop across it must be at least 5.0 0.4 = 4.6 V when 3.2 mA is flowing through it. Applying Ohm's Law, we find that Rmin is 4.6/0.0032 = 1438 ohms. 1438 R 43,333
152 Example: Given the following circuit, with all of its inputs connected to a LOW logic level:
VCC R L L
1 3 2 7403 1 2 O.D. 7404 L L 1 3 2 7403 O.D. If the offstate leakage current of each of the 74x03 opendrain NAND gate outputs is 5 A, and the IIH required by the 74x04 inverter is 90 A, determine the value of the pullup resistor R to obtain a VIH of 4.9 V at the 74x04 input. 153 Solution:
VCC 5.0 VDC 4.9 VDC
1 2 100 A
L L
1 3 2 7403 R O.D. 7404 L L 1 3 2 7403 90 A 5 A O.D. Current through R = IR = 5 A + 5 A + 90 A = 100 A Voltage drop across R = VR = 5.0 4.9 = 0.1 R = VR/IR = 0.1/0.0001 = 1000 154 Clicker Quiz 155 VCC = 5 VDC R H H 1 3 2 74HC03 1 2 O.D.
7404 Assume that measurements taken in laboratory reveal that a 74HC03 (opendrain CMOS NAND gate) will produce a VOL = 0.2 V when sinking +2 mA of current. Also, assume that the IIL required by a 7404 (standardseries TTL inverter) to recognize a logic "0" is 0.4 mA and that its IIH (to recognize a logic "1") is +40 A.
156 1. Based on the laboratory measurements cited in the figure, what is the "ON" resistance of the 74HC03's active output device? A. 10 B. 20 C. 100 D. 1000 E. none of the above
157 2. If the capacitive load on the output of the NAND gate is 20 pF, estimate the fall time of the signal at the input to the inverter (assuming "ON" resistance calculated in previous problem): A. 2 ns B. 16 ns C. 20 ns D. 160 ns E. none of the above
158 3. Calculate the value of the pullup resistor that allows the opendrain NAND gate to produce a VOL = 0.2 V when sinking 2 mA of current (i.e., IOL = +2 mA) and pulling the input of the 7404 low. A. 1000 B. 2000 C. 3000 D. 8000 E. none of the above
159 4. If the capacitive load on the output of the NAND gate is 20 pF, estimate the rise time of the signal at the input to the inverter assuming a pullup resistor value of 3000 (calculated in previous problem): A. 2 ns B. 16 ns C. 20 ns D. 60 ns E. none of the above
160 5. Assuming that the offstate leakage current of the 74HC03 is +10 A, calculate the value of the pullup resistor that produces a VIH = 4.5 V at the 7404 input. A. 4000 B. 9000 C. 10,000 D. 90,000 E. none of the above
161 CMOS/TTL Interfacing
A typical system design may contain a mixture of CMOS and/or TTL families, due to: parts availability special requirements It is important for a designer to understand the implications of connecting TTL outputs to CMOS inputs, and vice versa Factors to consider: DC noise margin fanout fan capacitive loading
162 CMOS/TTL Interfacing
All of the CMOS (and TTL) devices that we will discuss have part numbers of the form: 74FAMnn
where "FAM" is an alphabetic mnemonic and nn is a numeric function designator Devices in different families with the same nn perform the same function The prefix "74" has no social significance (it was "made popular" by Texas Instruments) The prefix "54" is used to signify "milspec" "milparts (wider temperature range)
163 TTL/CMOS Input/Output Levels 164 Parameters of Interest  1
IImax ______ The maximum input current for any
value of input voltage CINmax The maximum capacitance of an input ______ VILmax The maximum voltage that an input ______
is guaranteed to recognize as LOW VIHmin The minimum voltage that an input is ______
guaranteed to recognize as HIGH 165 Parameters of Interest  2
IOLmaxC The maximum current that an output _______
can supply in the LOW state while driving a CMOS load IOLmaxT The maximum current that an output _______ can supply in the LOW state while driving a TTL load VOLmaxC The maximum voltage that a LOW _______ output is guaranteed to produce driving a CMOS load VOLmaxT The maximum voltage that a LOW _______ output is guaranteed to produce driving a TTL load 166 Parameters of Interest  3
IOHmaxCThe maximum current that an output _______
can supply in the HIGH state while driving a CMOS load IOHmaxT The maximum current that an output _______ can supply in the HIGH state while driving a TTL load VOHminC The minimum voltage that a HIGH _______ output is guaranteed to produce driving a CMOS load VOHminT The minimum voltage that a HIGH _______ output is guaranteed to produce driving a TTL load 167 ...
View
Full
Document
This note was uploaded on 02/05/2012 for the course ECE 270 taught by Professor Staff during the Spring '08 term at Purdue.
 Spring '08
 Staff

Click to edit the document details