Unformatted text preview: 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 2 Boolean Algebra and Combinational Logic Circuits
1 Module 2
Desired Outcome: "An ability to represent Boolean functions in standard forms, to map and minimize them, and to implement them as combinational logic circuits" Part A: Switching Algebra Part B: Combinational Circuit Analysis and Synthesis Part C: Mapping and Minimization Part D: Timing Hazards Part E: XOR/XNOR Functions
2 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 2A Switching Algebra
3 Reading Assignment: 3rd Ed., pp. 193209; 4th Ed., pp. 183199 193183Instructional Objectives:
To learn the theory and terminology associated with switching algebra To learn about the variety of ways in which a logic function can be represented 4 Outline
Overview Axioms Duality Theorems SingleVariable Single Two and ThreeVariable TwoThree nVariable Standard Forms
5 Overview
Formal analysis techniques for digital circuits are based on a twovalued algebraic twosystem called Boolean algebra (named after George Boole, who invented it in 1854) Claude Shannon (1938) showed how to adapt Boolean algebra to analyze and describe the behavior of circuits built from relays In Shannon's switching algebra, the algebra, condition of a relay contact (open/closed) is (open/closed) represented by a variable X (equal to 0/1) In today's logic technologies, these values correspond to voltage LOW or HIGH
6 Axioms
Definition: Definition: The axioms (or postulates) of a postulates) mathematical system are a minimal set of basic definitions that we assume to be true, from which all other information about the system can be derived Notation: Notation: A prime ( ) will be used to denote an inverter's function (i.e., the complement of a logic signal) note that prime is an algebraic operator, that X is an expression, operator, expression, and that Y=X is an equation X can be read as X prime NOT X or X bar prime, X,
7 Axioms
Definition: Definition: The function of a 2input AND 2gate is called logical multiplication and is symbolized by a multiplication dot () Definition: Definition: The function of a 2input OR gate 2is called logical addition and is symbolized algebraically by a plus sign (+) Definition: Definition: By convention, multiplication (AND) has precedence over addition (OR) Example: W X + Y Z = (W X) + (Y Z) 8 Axioms
(A1) X = 0 if X 1 (A3) 0 0 = 0 (A4) 1 1 = 1 (A5) 0 1 = 1 0 = 0 (A1) X = 1 if X 0 (A3) 1 + 1 = 1 (A4) 0 + 0 = 0 (A5) 1 + 0 = 0 + 1 = 1 (A2) If X = 0, then X = 1 (A2) If X = 1, then X = 0 Note: The second axiom in each pair is referred to as the dual of the first one (and vice versa) Also Note: These 5 pairs of axioms completely define switching algebra
9 Duality
Definition: Definition: The dual of an expression is formed through the simultaneous interchange of the operators "" and "+" " and the elements "0" and "1" Important Principle: If two Boolean Principle: expressions can be proven to be equivalent using a given sequence of axioms or theorems, then the dual expressions may be proven to be equivalent by simply applying the sequence of dual axioms or theorems 10 Theorems
Definition: Definition: Switching algebra theorems are statements, known always to be true, that allow manipulation of algebraic expressions Definition: Definition: A technique called perfect induction can be used to prove switching algebra theorems ("perfect" implies the use of all possible combinations of the values of the variables thus, it is an exhaustive type of proof) 11 SingleSingleVariable Theorems
(T1) X + 0 = X (T2) X + 1 = 1 (T3) X + X = X (T4) (X) = X (T5) X + X = 1 (T5) X X = 0 (T1) X 1 = X (T2) X 0 = 0 (T3) X X = X Identities Null elements Idempotency Involution Complements 12 TwoTwo and ThreeVariable Theorems Three(T6) X + Y = Y + X (T6) X Y = Y X (T7) (X + Y) + Z = X + (Y + Z) (T7) (X Y) Z = X (Y Z) Commutivity Associativity (T8) X Y + X Z = X (Y + Z) Distributivity (T8) (X + Y) (X + Z) = X + Y Z (T9) X + X Y = X (T9) X (X + Y) = X Covering 13 TwoTwo and ThreeVariable Theorems ThreeExample: Example: Proof of T8' using perfect induction 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1
14 TwoTwo and ThreeVariable Theorems ThreeExample: Example: Proof of T9 using other theorems (T9) X + X Y = X 1 + X Y = X (1 + Y) =X1 =X (T1) (T8) (T2) (T1) 15 TwoTwo and ThreeVariable Theorems Three(T10) X Y + X Y = X (T10) (X + Y) (X + Y) = X Combining Consensus (T11) X Y + X Z + Y Z = X Y + X Z (T11) (X + Y) (X + Z) (Y + Z) = (X + Y) (X + Z) Note: In all theorems, it is possible to replace each variable with an arbitrary logic expression
16 TwoTwo and ThreeVariable Theorems ThreeExample: Example: Using only the axioms and theorems described thus far, verify the following equivalence expression: X Y + Y Z + X Z = X Y + X Z Main "Tricks":  Multiply by (X + X)  Factor out common terms 17 TwoTwo and ThreeVariable Theorems ThreeExample: Example: Using only the axioms and theorems described thus far, verify the following equivalence expression: XY + YZ + XZ = XY + YZ(X + X) + XZ = XY + XYZ + XY Z + XZ = XY(1 + Z) + XZ(Y + 1) = XY + XZ
18 NVariable Theorems
Generalized Idempotency (T12) X + X + ... + X = X (T12) X X ... X = X DeMorgan's Law (T13) (X1 X2 ... Xn) = X1 + X2 + ... + Xn (T13) (X1 + X2 + ... + Xn) = X1 X2 ... Xn Generalized DeMorgan's Law (T14) [F(X1,X2, ... ,Xn)] = F (X1,X2, ... , Xn)
D
19 Equivalent Circuits According to DeMorgan's Theorem
(X Y) = X + Y (T13) Observation: A logically equivalent circuit can be formed by taking the dual of the operator(s) and complementing all the inputs and outputs 20 Practice  1
Example: Write the name of the switching algebra axiom or theorem:
Null Elements (T2') _________________ X0 = 0 Complements (T5) _________________ X + X = 1 Complements (T5') _________________ XX = 0 (Generalized) Idempotency (T3 or T12) _________________ X+X+X=X Involution (T4) _________________ (X) = X 21 Practice  2
Example: Write the name of the switching algebra axiom or theorem:
Covering (T9') _________________ X(X+Y) = X Distributivity (T8) _________________ (X+Y)(X+Z) = X + YZ Associativity (T7) _________________ (X+Y)+Z = X+(Y+Z) Commutivity (T6') _________________ XYZ = ZXY 22 Practice  3
Example: Prove T9 using perfect induction. T9 X (X + Y) = X X Y (X + Y) X(X+Y) X 0 0 0 1 1 0 1 1 0 1 1 1 0 0 1 1 0 0 1 1 23 Practice  4
Example: Prove T9 using other theorems. T9 X (X + Y) = X
X (X + Y) = XX + XY = X + XY = X(1 + Y) = X (1) =X (T8) (T3') (T8) (T2) (T1')
24 Standard Forms
Definition: Definition: A literal is a variable or the complement of a variable Definition: Definition: A product term is a single literal or a logical product of two or more literals Definition: sumofDefinition: A sumofproducts expression is a logical sum of product terms Definition: Definition: A sum term is a single literal or a logical sum of two or more literals Definition: productofDefinition: A productofsums expression is a logical product of sum terms
25 Examples
W, X, Y WXZ Literals Product Term Sum of Products Expression Sum Term X Y + W Z X + Y + Z (X + Y) (W + Z) Product of Sums Expression 26 Standard Forms
Definition: Definition: A normal term is a product or sum term in which no variable appears more than once Definition: Definition: An nvariable minterm is a normal product term with n literals Definition: Definition: An nvariable maxterm is a normal sum term with n literals Definition: Definition: The canonical sum of a logic function is a sum of minterms corresponding to input combinations for which the function produces a "1" output Definition: Definition: The canonical product of a logic function is a product of maxterms corresponding to input combinations for which the function produces a "0" output 27 Standard Forms 0 complemented Example: Example: Minterms 1 true 28 Standard Forms 0 true Example: Example: Maxterms 1 complemented 29 Standard Forms
Definition: Definition: The minterm list that "turns on" an output function is called the on set Definition: Definition: The maxterm list that "turns off" an output function is called the off set Summary: Summary: There are numerous ways a combinational logic function can be defined truth table algebraic sum of minterms minterm list algebraic product of maxterms maxterm list
30 Example
Based on the truth table, determine the following X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F(X,Y,Z) 1 0 0 1 0 0 1 1 F(X,Y,Z) expressed as:
an onset: ____________________ onan offset: ____________________ off a sum of minterms: _____________________________ a product of maxterms: __________________________ _______________________________________________
31 Example
Based on the truth table, determine the following X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F(X,Y,Z) 1 0 0 1 0 0 1 1 F(X,Y,Z) expressed as: X,Y,Z(0,3,6,7) an onset: ____________________ onan offset: ____________________ off a sum of minterms: _____________________________ a product of maxterms: __________________________ _______________________________________________
32 Example
Based on the truth table, determine the following X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F(X,Y,Z) 1 0 0 1 0 0 1 1 F(X,Y,Z) expressed as: X,Y,Z(0,3,6,7) an onset: ____________________ on X,Y,Z(1,2,4,5) an offset: ____________________ off a sum of minterms: _____________________________ a product of maxterms: __________________________ _______________________________________________
33 Example
Based on the truth table, determine the following X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F(X,Y,Z) 1 0 0 1 0 0 1 1 F(X,Y,Z) expressed as: X,Y,Z(0,3,6,7) an onset: ____________________ on X,Y,Z(1,2,4,5) an offset: ____________________ off a sum of minterms: X'Y'Z' + X'YZ + XYZ' + XYZ _____________________________ a product of maxterms: __________________________ _______________________________________________
34 Example
Based on the truth table, determine the following X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F(X,Y,Z) 1 0 0 1 0 0 1 1 F(X,Y,Z) expressed as: X,Y,Z(0,3,6,7) an onset: ____________________ on X,Y,Z(1,2,4,5) an offset: ____________________ off a sum of minterms: X'Y'Z' + X'YZ + XYZ' + XYZ _____________________________ a product of maxterms: __________________________ (X+Y+Z')(X+Y'+Z) (X'+Y+Z)(X'+Y+Z') _______________________________________________
35 Example
Given the truth table for F(X,Y,Z), determine the truth table for the DUAL function, FD(X,Y,Z)
X Y Z F(X,Y,Z) 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1
36 Example
Given the truth table for F(X,Y,Z), determine the truth table for the DUAL function, FD(X,Y,Z)
X Y Z F(X,Y,Z) 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 X Y Z FD(X,Y,Z) 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0
37 Example
Given the truth table for F(X,Y,Z), determine the truth table for the DUAL function, FD(X,Y,Z)
X Y Z F(X,Y,Z) 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 X Y Z FD(X,Y,Z) 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 X Y Z FD(X,Y,Z) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 1 0 1 1 0
38 Example
Given the truth table for F(X,Y,Z), determine the truth table for the COMPLEMENT function, F'(X,Y,Z) F'
X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F(X,Y,Z) 1 0 0 1 0 0 1 1
39 Example
Given the truth table for F(X,Y,Z), determine the truth table for the COMPLEMENT function, F'(X,Y,Z) F'
X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F(X,Y,Z) 1 0 0 1 0 0 1 1 X Y Z F'(X,Y,Z) 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 0
40 Clicker Quiz 41 1. If the function F(X,Y,Z) is represented by the ON SET X,Y,Z(0,3,5,6), then the complement of this function F(X,Y,Z) is represented by the ON SET: A. X,Y,Z(0,3,5,6) B. X,Y,Z(1,2,4,7) C. X,Y,Z(1,2,4,6) D. X,Y,Z(1,3,5,7) E. none of the above
42 2. If the function F(X,Y,Z) is represented by the ON SET X,Y,Z(0,3,5,6), then the dual of this function FD(X,Y,Z) is represented by the ON SET: A. X,Y,Z(0,3,5,6) B. X,Y,Z(1,2,4,7) C. X,Y,Z(1,2,4,6) D. X,Y,Z(1,3,5,7) E. none of the above
43 3. The expression (XY)Z = X(YZ) is an example of: A. commutitivity B. associativity C. distributivity D. consensus E. none of the above
44 4. The expression X + Y + Z = Y + Z + X is an example of: A. commutitivity B. associativity C. distributivity D. consensus E. none of the above
45 5. The expression (X+Y)(X+Z)(Y+Z) = (X+Y)(X+Z) is an example of: A. commutitivity B. associativity C. distributivity D. consensus E. none of the above 46 6. The expression (X+Y)(X+Z) = X + YZ is an example of: A. commutitivity B. associativity C. distributivity D. consensus E. none of the above
47 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 2B Combinational Circuit Analysis and Synthesis
48 Reading Assignment: 3rd Ed., pp. 209219; 4th Ed., pp. 199210 209199Instructional Objectives:
To learn how to analyze combinational logic circuits To learn how to realize logic functions using commonlycommonlyavailable gates To learn how to transform a word description into a logic function 49 Outline
Overview Combinational Circuit Analysis Combinational Circuit Synthesis 50 Overview
We analyze a combinational logic circuit by obtaining a formal description of its logic function X1 X2 . . . f f (X1,X2, ... , Xn) Xn) Xn A combinational logic circuit is one whose outputs depend only on its current inputs
51 Overview
Once we have a description of the logic function, we can: determine the behavior of the circuit for various input combinations manipulate an algebraic description to suggest different circuit structures transform an algebraic description into a standard form (e.g., sumofproducts for sumofPLD implementation) use an algebraic description of the circuit's functional behavior in the analysis of a larger system that includes the circuit
52 Combinational Analysis  Example
0 0 0 1 0 0 0 1 1 1 53 Combinational Analysis  Example
0 0 1 1 1 1 0 0 1 1 54 Combinational Analysis  Example
0 1 0 0 0 1 1 1 0 1 55 Combinational Analysis  Example
0 1 1 0 0 0 0 0 0 1 56 Combinational Analysis  Example
1 0 0 1 0 0 0 1 1 0 57 Combinational Analysis  Example
1 0 1 1 1 1 0 0 1 0 58 Combinational Analysis  Example
1 1 0 1 0 0 0 1 0 0 59 Combinational Analysis  Example
1 1 1 1 1 1 0 0 0 0 60 Combinational Analysis  Example Truth Table The "on set" of this function is f (X,Y,Z) = X,Y,Z(1,2,5,7) The canonical sum of this function is f (X,Y,Z) = XYZ + XYZ + XYZ + XYZ 61 Combinational Analysis  Example The "off set" of this function is f (X,Y,Z) = X,Y,Z(0,3,4,6) The canonical product of this function is f (X,Y,Z) = (X+Y+Z) (X+Y+Z) + + + (X+Y+Z) (X+Y+Z) + 62 Combinational Analysis  Example Writing the function implemented by this circuit "directly" yields f (X,Y,Z) = ((X+Y)Z) + (XYZ) = XZ + YZ + XYZ 63 Combinational Analysis  Example The expression f (X,Y,Z) = XZ + YZ + XYZ corresponds to a different circuit ("twolevel ANDOR") for the same logic function
64 Graphical Application of DeMorgan's Law Recall that an equivalent symbol can be drawn for a gate by taking the dual of the operator and complementing all of the inputs and outputs
65 Graphical Application of DeMorgan's Law Step 1: Starting at the "output end", replace the "OR" gate with an AND gate that has its inputs and outputs complemented
66 Graphical Application of DeMorgan's Law Step 2: Migrate the "inversion bubbles", as appropriate, by applying involution Conclusion: A twolevel ANDOR circuit is equivalent to a twolevel NANDNAND circuit!
67 Graphical Application of DeMorgan's Law
Example: Determine the function implemented by a twolevel NANDNOR circuit
A B F(A,B,C,D) C D Level 1 Level 2 68 Graphical Application of DeMorgan's Law
Example: Determine the function implemented by a twolevel NANDNOR circuit (continued)
A B F(A,B,C,D) C D Equivalent symbol for NOR gate
69 Graphical Application of DeMorgan's Law
Example: Determine the function implemented by a twolevel NANDNOR circuit (continued)
A B F(A,B,C,D) = ABCD C D Apply involution Apply associativity A B C D F(A,B,C,D)
70 Clicker Quiz 71 1. The ON set for a 3input NAND gate (with inputs X, Y, and Z) is: A. X,Y,Z(7) B. X,Y,Z(0) C. X,Y,Z(0,1,2,3,4,5,6) D. X,Y,Z(1,2,3,4,5,6,7) E. none of the above
72 2. The OFF set for a 3input NOR gate (with inputs X, Y, and Z) is: A. X,Y,Z(7) B. X,Y,Z(0) C. X,Y,Z(0,1,2,3,4,5,6) D. X,Y,Z(1,2,3,4,5,6,7) E. none of the above
73 3. A NOR gate is logically equivalent to: A. an AND gate with inverted inputs B. an OR gate with inverted inputs C. a NAND gate with inverted inputs D. a NOR gate with inverted inputs E. none of the above
74 4. An OR gate is logically equivalent to: A. an AND gate with inverted inputs B. an OR gate with inverted inputs C. a NAND gate with inverted inputs D. a NOR gate with inverted inputs E. none of the above
75 5. A circuit consisting of a level of NOR gates followed by a level of AND gates is logically equivalent to: A. a multiinput OR gate B. a multiinput AND gate C. a multiinput NOR gate D. a multiinput NAND gate E. none of the above
2 3 1 2 3 2 3 1 1 76 Combinational Synthesis
The starting point for designing a combinational logic circuit is usually a word description of a problem Example: Example: Design a 4bit prime number 44detector (or, Given a 4bit input combination M = N3N2N1N0, design a function that produces a "1" output for M = 1, 2, 3, 5, 7, 11, 13 and a "0" output for all other numbers) numbers) f (N3,N2,N1,N0) = N3,N2,N1,N0(1,2,3,5,7,11,13)
77 Combinational Synthesis  Example 78 Combinational Synthesis
A circuit realizes ("makes real") an expression if its output function equals that expression Such a circuit is called a realization of the function Typically there are many possible realizations of the same function Circuit transformations can be made algebraically or graphically 79 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 2C Mapping and Minimization
80 Reading Assignment: 3rd Ed., pp. 220233; 4th Ed., pp. 210222 220210Instructional Objectives:
To learn how to represent a logic function using a Karnaugh Map ("Kmap") ("KTo learn how to minimize a logic function using a Kmap KTo learn what incompletely specified functions are and how to minimize them 81 Outline
Overview Representation of Logic Functions Using Kmaps KMinimization of Logic Functions Using Kmaps NANDNANDWired AND Configuration Incompletely Specified Functions where they occur how to minimize them
82 Overview
Minimization is an important step in both ASIC (application specific integrated circuit) design and in PLDbased (programmable PLDlogic device) design Extra gates and gate inputs require more chip area ("real estate") and thereby increase cost and power consumption Canonical sum and product expressions (which can be determined "directly" from a truth table) are particularly expensive because the number of minterms [maxterms] grows exponentially with the number of variables
83 Overview
Minimization reduces the cost of twolevel twoANDANDOR, ORAND, NANDNAND, NORNOR ORNANDNORcircuits by: minimizing the number of firstlevel gates first minimizing the number of inputs on each firstfirstlevel gate minimizing the number of inputs on the secondsecondlevel gate Most minimization methods are based on a generalization of the Combining Theorems (T10 and T10): Expression X + Expression X = Expression
84 Overview
Limitations of minimization methods no restriction on fanin is assumed (i.e., the fantotal number of inputs a gate can have is assumed to be "infinite") "infinite") minimization of a function of more than 4 or 5 variables is not practical to do "by hand" (a computer program must be used!) both true and complemented versions of all input variables are assumed to be readily available (i.e., the cost of input inverters is not considered) This latter assumption is very appropriate for PLDbased design, but often violated in gatelevel and ASICbased design 85 Karnaugh Maps
A Karnaugh map (or "Kmap") is a graphical "K map") representation of a logic function's truth table The map for an nvariable logic function is an narray with 2n cells, one for each possible input combination (minterm) (minterm) 86 Karnaugh Maps
Several things to note concerning Kmaps: K the small number in the corner of each square indicates the minterm number the entries in the squares correspond to the "on set" of the function the labels are placed in such a way that the minterms on any pair of adjacent squares differ by only one literal the sides of the map are considered to be contiguous adjacent, like squares may be combined in groups of 2k to reduce the number of product terms in an expression (a grouping of 2k squares will eliminate k variables)
87 Karnaugh Maps
An alternate drawing for a 2variable Kmap 2KX Y Y
0 2 X 1 3 88 Karnaugh Maps
Example: Example: f (X,Y) = X+ Y
X Y Y
0 X
2 1 1 0
3 1 1 89 Karnaugh Maps
An alternate drawing for a 3variable Kmap 3KX Z Z
0 2 6 X
4 1 3 7 5 Y Y Y 90 Karnaugh Maps
Example: Example: f (X,Y,Z) = XY + YZ
X X
6 4 2 Z Z 0 1 3 7 5 Y Y Y 91 Karnaugh Maps
Example: Example: f (X,Y,Z) = XY + YZ
X X
6 4 2 Z Z 0 1
1 1 Y 3 7 5 Y Y 92 Karnaugh Maps
Example: Example: f (X,Y,Z) = XY + YZ
X X
6 4 2 Z Z 0 1
1 1 Y 3 1 Y 7 1 5 Y 93 Karnaugh Maps
Example: Example: f (X,Y,Z) = XY + YZ
X X 0 1 Y
6 2 4 Z Z 0 1
1 0 1 0 0 Y 1 Y 3 7 5 94 Karnaugh Maps
An alternate drawing for a 4variable Kmap 4KW
0 4 12 W
8 Y Z Z Z 1 5 13 9 3 7 15 11 Y 2 6 14 10 X X X
95 Karnaugh Maps
Example: Example: f (W,X,Y,Z) = XZ + WZ + WX W
0 4 12 W
8 Y Z Z Z 1 5 13 9 3 7 15 11 Y 2 6 14 10 X X X
96 Karnaugh Maps
Example: Example: f (W,X,Y,Z) = XZ + WZ + WX W
0 4 12 W
8 Y 1
1 5 13 9 1 Z Z Z 3 7 15 11 Y 2 1 X 6 14 10 1 X X 97 Karnaugh Maps
Example: Example: f (W,X,Y,Z) = XZ + WZ + WX W
0 4 12 W
8 Y 1
1 5 13 1 1 1 1 Z Z Z 1 1 9 3 7 15 11 Y 2 1 X 6 14 10 X X
98 Karnaugh Maps
Example: Example: f (W,X,Y,Z) = XZ + WZ + WX W
0 4 W
12 8 Y 1
1 5 1 1 1 1 1 1 1 1 Z Z Z 13 1 1 9 3 7 15 11 Y 2 1 X 6 14 10 X X
99 Karnaugh Maps
Example: Example: f (W,X,Y,Z) = XZ + WZ + WX W
0 4 W
12 8 Y 1
1 1 1 1 1 0
13 1 1 1 1 X Z Z Z 0 0 1 X 5 1 1 0 9 3 7 15 11 Y 2 6 14 10 X 100 Minimization
Definition: Definition: A minimal sum of a logic function f is a sumofproducts expression sumoffor f such that no sumofproducts sumofexpression for f has fewer product terms, and any sumofproducts expression with sumofthe same number of product terms has at least as many literals Translation: The minimal sum has the fewest possible product terms (firstlevel gates / secondlevel gate inputs) and the fewest possible literals (firstlevel gate inputs)
101 Minimization
Definition: Definition: A logic function p implies a logic function f if for every input combination such that p = 1, then f = 1 also (i.e., if p implies f , then f is "1" for every input combination that p is "1", and maybe some more or "f covers p ") Definition: Definition: A prime implicant of an nnvariable logic function f is a normal product term P that implies f , such that if any literal is removed from P, then the resulting product term does not imply f
102 Minimization
Translation: Translation: A prime implicant is the largest possible grouping of size 2k adjacent, like squares W W
0 4 Y 1
1 1 1 1 1 12 8 0
13 1 1 1 1 X Z Z Z Prime Implicant NOT a Prime Implicant
103 0 0 1 X 5 1 1 0 9 3 7 15 11 Y 2 6 14 10 X Minimization
Prime Implicant Theorem: A minimal sum is Theorem: a sum of prime implicants (i.e., to find a minimal sum, we need not consider any product terms that are not prime implicants) implicants) Definition: Definition: An essential prime implicant has at least one square in the grouping not shared by another prime implicant, i.e., it has implicant, at least one "unique" square, called a distinguished 1cell 1Definition: nonDefinition: A nonessential prime implicant is a grouping with no unique squares Definition: Definition: The cost criterion we will use is that gate inputs and outputs are of equal cost
COST = No. of Gate Inputs + No. of Gate Outputs
104 Minimization Procedure
STEP 1: Circle all the prime implicants W
0 4 W
12 8 Y 0
1 0 1 1 0 1
13 0 0 0 1 X Z Z Z 0 0 0 X 5 0 1 1 9 3 7 15 11 Y 2 6 14 10 X 105 Minimization Procedure
STEP 2: Note the essential prime implicants W
0 4 W
12 8 Y 0
1 0 1 1 0 1
13 0 0 0 1 X Z Z Z 0 0 0 X 5 0 1 1 9 3 7 15 11 Y 2 6 14 10 X 106 Minimization Procedure
STEP 2: Note the essential prime implicants W
0 4 W
12 8 Y 0
1 0 1 1 0 1
13 0 0 0 1 X Z Z Z 0 0 0 X 5 0 1 1 9 3 7 15 11 Y 2 6 14 10 X 107 Minimization Procedure
STEP 2: Note the essential prime implicants W
0 4 W
12 8 Y 0
1 0 1 1 0 1
13 0 0 0 1 X Z Z Z 0 0 0 X 5 0 1 1 9 3 7 15 11 Y 2 6 14 10 X 108 Minimization Procedure
STEP 3: If there are still any uncovered squares, include nonessential prime nonimplicants W W
0 4 Y 0
1 0 1 1 0 12 8 1
13 0 0 0 1 X Z One Possibility Z Z
109 0 0 0 X 5 0 1 1 9 3 7 15 11 Y 2 6 14 10 X Minimization Procedure
STEP 4: Write a minimal, nonredundant nonsumofsumofproducts expression W
0 4 W
12 8 Y 0
1 0 1 1 0 1
13 0 0 0 1 X Z 0 0 0 X 5 0 1 1 9 f
Z Z 3 7 15 11 (W,X,Y,Z) = W Z X + WXZ + WYZ + XYZ Y 2 6 14 10 X 110 W' X Z 2 3 4 1 W X Z' 2 3 4 1 2 3 1 4 5 W Y Z' 2 3 4 1 X Y Z 2 3 4 1 One possible circuit implementation (ANDOR): COST is 16 inputs + 5 outputs = 21
111 W' X Z 2 3 4 1 W X Z' 2 3 4 1 2 3 1 4 5 W Y Z' 2 3 4 1 X Y Z 2 3 4 1 EQUIVALENT circuit implementation, obtained through graphical application of DeMorgan's Law Note: ANDOR NANDNAND COST is 16 inputs + 5 outputs = 21 (same)
112 Minimization Procedure
REVISIT STEP 3: If there are still any uncovered squares, include nonessential nonprime implicants W W
0 4 Y 0
1 0 1 1 0 12 8 1
13 0 0 0 1 X Z Z Z
113 0 0 0 X 5 0 1 1 9 Another Possibility 3 7 15 11 Y 2 6 14 10 X Minimization Procedure
REVISIT STEP 4: Write a minimal, nonnonredundant sumofproducts expression sumofW
0 4 W
12 8 Y 0
1 0 1 1 0 1
13 0 0 0 1 X Z 0 0 0 X 5 0 1 1 9 f
Z Z 3 7 15 11 (W,X,Y,Z) = W Z X + WXZ + WYZ + WXY Y 2 6 14 10 X 114 Clicker Quiz 115 W 0 Y 0 1 1 1 0 W 0 Z 1 Z 1 Y 0 X 1 1 0 0 X 1 0 X Z 1. The number of prime implicants is: A. 1 B. 2 C. 3 D. 4 E. 5
116 W 0 Y 0 1 1 1 0 W 0 Z 1 Z 1 Y 0 X 1 1 0 0 X 1 0 X Z 2. The number of essential prime implicants is: A. 1 B. 2 C. 3 D. 4 E. 5 117 W 0 Y 0 1 1 1 0 W 0 Z 1 Z 1 Y 0 X 1 1 0 0 X 1 0 X Z 3. The number of nonessential prime implicants is: A. 1 B. 2 C. 3 D. 4 E. 5 118 W 0 Y 0 1 1 1 0 W 0 Z 1 Z 1 Y 0 X 1 1 0 0 X 1 0 X Z 4. The number of terms in the minimal sum is: A. 1 B. 2 C. 3 D. 4 E. 5 119 W 0 Y 0 1 1 1 0 W 0 1 1 Y 0 X 1 1 0 0 X 1 0 X 5. The ON SET for this function: Z A. W,X,Y,Z(2,4,5,6,9,10,11,12) B. W,X,Y,Z(3,4,5,7,9,13,14,15) Z C. W,X,Y,Z(3,4,5,7,9,10,11,13) D. W,X,Y,Z(2,4,5,6,9,13,14,15) Z E. none of the above
120 Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 1 1 1 1
13 1 1 0 1 Z Z Z
121 1 0 0 X 5 1 0 0 9 3 7 15 11 Y 2 6 14 10 X X Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 1 1 1 1
13 1 1 0 1 Z Z Z
122 1 0 0 X 5 1 0 0 9 prime implicants 3 7 15 11 Y 2 6 14 10 X X Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 1 1 1 1
13 1 1 0 1 Z Z Z
123 1 0 0 X 5 1 0 0 9 essential prime implicants 3 7 15 11 Y 2 6 14 10 X X Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 1 1 1 1
13 1 1 0 1 Z Z Z
124 1 0 0 X 5 1 0 0 9 essential prime implicants 3 7 15 11 Y 2 6 14 10 X X Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 1 1 1 1
13 1 1 0 1 Z Z Z
125 1 0 0 X 5 1 0 0 9 essential prime implicants 3 7 15 11 Y 2 6 14 10 X X Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 1 1 1 1
13 1 1 0 1 Z Z Z
126 1 0 0 X 5 1 0 0 9 essential prime implicants 3 7 15 11 Y 2 6 14 10 X X Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 12 W
8 Y 1
1 5 0 1 1 1
13 1 1 0 0
9 1 1 0 1 Z Z Z
127 1
3 Y 0 0 X 7 15 11 nonnonessential prime implicant needed to cover function 2 6 14 10 X X Minimization Procedure
Exercise: Exercise: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 12 W
8 Y 1
1 5 0 1 1 1
13 1 1 0 0
9 1 1 0 1 Z Z Z f (W,X,Y,Z) = 1
3 Y 0 0 X 7 15 11 WY + X + Y WX + W Y Z X + Y Z 2 6 14 10 X X
128 Minimization Procedure
Question: Question: How could a minimal productofproductofsums expression for this function be found? W
0 4 W
12 8 Y 1
1 0 1 1 0 1
13 1 1 0 0 Z Z Z 1 0 0 X 5 1 0 0 9 3 7 15 11 Group zeroes to get a minimum sumofproducts expression for f Y 2 6 14 10 X X
129 Minimization Procedure
Question: Question: How could a minimal productofproductofsums expression for this function be found? W
0 4 W
12 8 Y 1
1 0 1 1 0 1
13 1 1 0 0 Z Z Z 1 0 0 X 5 1 0 0 9 3 7 15 11 Group zeroes to get a minimum sumofproducts expression for f Find essential prime implicants
130 Y 2 6 14 10 X X Minimization Procedure
Question: Question: How could a minimal productofproductofsums expression for this function be found? W
0 4 W
12 8 Y 1
1 0 1 1 0 1
13 1 1 0 0 Z Z Z 1 0 0 X 5 1 0 0 9 3 7 15 11 Group zeroes to get a minimum sumofproducts expression for f Find essential prime implicants
131 Y 2 6 14 10 X X Minimization Procedure
Question: Question: How could a minimal productofproductofsums expression for this function be found? W
0 4 W
12 8 Y 1
1 0 1 1 0 1
13 1 1 0 0 Z Z Z 1 0 0 X 5 1 0 0 9 3 7 15 11 Group zeroes to get a minimum sumofproducts expression for f Find essential prime implicants
132 Y 2 6 14 10 X X Minimization Procedure
Question: Question: How could a minimal productofproductofsums expression for this function be found? W
0 4 W
12 8 Y 1
1 0 1 1 0 1
13 1 1 0 0 Z Z Z 1 0 0 X 5 1 0 0 9 3 7 15 11 Group zeroes to get a minimum sumofproducts expression for f Find essential prime implicants Y 2 6 14 10 X X Function is completely covered 133 Minimization Procedure
Question: Question: How could a minimal productofproductofsums expression for this function be found? W
0 4 W
12 8 Y 1
1 0 1 1 0 1
13 1 1 0 0 Z Z Z f = WY + X Y + W Z X Apply DeMorgan's Law 1 0 0 X 5 1 0 0 9 3 7 15 11 Y 2 6 14 10 f = (W+Y)(X+Y) (W+X+Z) 134 X X W' Y' 2 1 3 X Y' W X' Z 2 1 3 2 3 4 1 2 3 4 1 One possible circuit implementation (ORAND): COST is 10 inputs + 4 outputs = 14
135 W' Y' 2 1 3 X Y' W X' Z 2 1 3 2 3 4 1 2 3 4 1 EQUIVALENT circuit implementation, obtained through graphical application of DeMorgan's Law Note: ORAND NORNOR COST is 10 inputs + 4 outputs = 14 (same)
136 More Minimization Examples
Assuming that only true variables are available, realize the function represented by X,Y,Z(0,2,3,6) two different ways: (a) using a single 7400 (quad 2input NAND) plus a single 7410 (triple 3input NAND) (b) using a single 7403 (quad 2input opendrain NAND) Key to Solution: The "NANDWired AND" configuration realizes the complement of the NANDNAND configuration implement F 137 Solution to (a)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y Given: X,Y,Z(0,2,3,6) 138 Solution to (a)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y F(X,Y,Z) = XY 139 Solution to (a)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y F(X,Y,Z) = XY + XZ 140 Solution to (a)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y F(X,Y,Z) = XY + XZ + YZ 141 Solution to (a)
X Z Z 1 0 Y
X Y
U1B X 1 1 Y
U1A 1 3 2 7400 7400 U1D 12 11 13 6 5 7400 1 2 13 7410 7400 U1A 12 7410 4 3 4 5 U2B 6 10 1 0 0 0 Y F(X,Y,Z) = XY + XZ + YZ U1C 9 8 Z F(X,Y,Z) 142 Solution to (b)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y Given: X,Y,Z(0,2,3,6) 143 Solution to (b)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y F(X,Y,Z) = XY 144 Solution to (b)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y F(X,Y,Z) = XY + XZ 145 Solution to (b)
X Z Z 1 0 Y 1 1 Y 1 0 X 0 0 Y F(X,Y,Z) = XY + XZ + YZ 146 Solution to (b)
X Z Z 1 0 Y 1 1 Y
Y X 1 0 0 0
VCC F(X,Y,Z) = XY + XZ + YZ Y
U1A 1 3 2 VCC U1B 10K 6 5 7403 U1C 7403 9 8 X
10K 4 F(X,Y,Z) Z X Z 10 7403 U1D 12 11 13 7403 147 "Conversion" Example
Express the complement of the following function in minimal productofsums form: F(X,Y,Z) = (X + Y) (X + Y + Z) (X + Y + Z) F(X,Y,Z) = __________________ Map ______ F(X,Y,Z) = ________ F(X,Y,Z) in minimal POS form = ___________________
148 "Conversion" Example
Express the complement of the following function in minimal productofsums form: F(X,Y,Z) = (X + Y) (X + Y + Z) (X + Y + Z) F(X,Y,Z) = XY + XYZ + XYZ X Z Z 0 0 Y 1 1 Y 1 1 X 0 1 Y
149 Map zeroes F(X,Y,Z) = ________ F(X,Y,Z) in minimal POS form = ___________________ "Conversion" Example
Express the complement of the following function in minimal productofsums form: F(X,Y,Z) = (X + Y) (X + Y + Z) (X + Y + Z) F(X,Y,Z) = XY + XYZ + XYZ X Z Z 0 0 Y 1 1 Y 1 1 X 0 1 Y Map zeroes F(X,Y,Z) = Y + XZ F(X,Y,Z) in minimal POS form = Y (X + Z) 150 Incompletely Specified Functions
There are some logic functions that do not assign a specific binary output value (0/1) to each of the 2n input combinations Since there are essentially some unused combinations, combinations, these functions are referred to as incompletely specified functions The unused combinations are often called don't cares or the dset Example: Example: Binary Coded Decimal (BCD), where 4 binary digits are used to represent a decimal digit (0  9)10 here there are 6 unused combinations (1010  1111)2
151 Incompletely Specified Functions
Application: Application: Determine a logic function that will be "1" if the BCD digit input satisfies the following inequality: 1 < N10 < 9 F = W,X,Y,Z (2,3,4,5,6,7,8) + d(10,11,12,13,14,15)
On Set dSet 152 BCD Inequality Detector Example
N10 WXYZ F(W,X,Y,Z) 0 1 2 3 4 5 6 7 8 9 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0 0 1 1 1 1 1 1 1 0
153 Incompletely Specified Functions
To minimize an incompletely specified function, we modify the procedure for circling sets of 1's (prime implicants) as follows: implicants) allow d's to be included when circling sets of 1's, to make the sets as large as 1's, possible do not circle any sets that contain only d's look for distinguished 1cells only, not 1distinguished dcells dSome hardware description languages provide a means for the designer to specify don't care inputs
154 BCD Inequality Detector Example
W
0 4 W
12 8 Y 0
1 1 1 1 1 d
13 1 0 d Z Z Z 0 1 1 X 5 d d d 9 3 7 15 11 Y 2 6 14 10 d X X Minimum SP: f (W,X,Y,Z) = X + Y + WZ Cost: 5 gate inputs + 2 gate outputs = 7
155 BCD Inequality Detector Example
W
0 4 W
12 8 Minimum PS: 1 0 d Z Z Z WZ + WXY (W + Z) (W + X + Y) Cost: 7 gate inputs + 3 gate outputs = 10 f (W,X,Y,Z) = Y 0
1 1 1 1 1 d
13 f (W,X,Y,Z) = 0 1 1 X 5 d d d 9 3 7 15 11 Y 2 6 14 10 d X X Conclusion: The SP implementation costs less
156 Incompletely Specified Functions
Example: Example: Find a minimal sumofproducts sumofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 d 1 d 0
13 0 d 0 0 X Z Z Z
f (W,X,Y,Z) = WX + WY Cost: 6 gate inputs + 3 gate outputs = 9 cost units
157 d 1 1 X 5 d 0 d 9 3 7 15 11 Y 2 6 14 10 X Incompletely Specified Functions
Example: Example: Find a minimal productofsums productofexpression for the function mapped below W
0 4 W
12 8 Y 1
1 0 d 1 d 0
13 0 d 0 0 X Z Z Z
W d 1 1 X 5 d 0 d 9 3 7 15 11 Y 2 6 14 10 X f (W,X,Y,Z) = W + XY f (W,X,Y,Z) = W (X+Y) Cost: 4 gate inputs + 2 gate outputs = 6 cost units
158 Clicker Quiz 159 X Z Z 1 0 Y 1 0 Y 0 1 X d 0 Y 1. The cost of a minimal sum of products realization of this
function (assuming both true and complemented variables are available) would be: A. 9 B. 10 C. 11 D. 12 E. none of the above
160 X Z Z 1 0 Y 1 0 Y 0 1 X d 0 Y 2. The cost of a minimal products of sum realization of this
function (assuming both true and complemented variables are available) would be: A. 9 B. 10 C. 11 D. 12 E. none of the above
161 X Z Z 1 0 Y 1 0 Y 0 1 X d 0 Y 3. Assuming the availability of only true input variables, the
fewest number of 2input NAND gates that are needed to realize this function is: A. 6 B. 7 C. 8 D. 9 E. none of the above
162 X Z Z 1 0 Y 1 0 Y 0 1 X d 0 Y 4. Assuming the availability of only true input variables, the
fewest number of 2input NOR gates that are needed to realize this function is: A. 6 B. 7 C. 8 D. 9 E. none of the above
163 X Z Z 1 0 Y 1 0 Y 0 1 X d 0 Y 5. Assuming the availability of only true input variables, the
fewest number of 2input opendrain NAND gates that are needed to realize this function is: A. 6 B. 7 C. 8 D. 9 E. none of the above
164 X Z Z 1 0 Y 1 0 Y 0 1 X d 0 Y 6. The number of pullup resistors required for realizing this
function using only 2input open drain NAND gates (assuming the availability of only true input variables) is: A. 1 B. 2 C. 3 D. 4 E. none of the above
165 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 2D Timing Hazards 166 Reading Assignment: 3rd Ed., pp. 244248; 4th Ed., pp. 224228 244224Instructional Objectives:
To learn what causes timing hazards in combinational logic circuits and how they can be eliminated To learn how timing hazards can be used to create specialpurpose circuits special 167 Outline
Timing hazards Static Dynamic Elimination of timing hazards Clever utilization of timing hazards 168 Timing Hazards
The combinational circuit analysis methods described thus far ignore propagation delay and predict only the steady state behavior Gate propagation delay may cause the transient behavior of logic circuit to differ from that predicted by steady state analysis A circuit's output may produce a short glitch) pulse (often called a glitch) at time when steady state analysis predicts the output should not change A hazard is said to exist when a circuit has the possibility of producing such a glitch
169 Timing Hazards
Definition: staticDefinition: A static1 hazard is a pair of input combinations that: (a) differ in only one input variable and (b) both produce a "1" output, such that it is possible for a output, momentary "0" output to occur during a transition in the differing input variable
1 1 0 1
170 Timing Hazards
Definition: staticDefinition: A static0 hazard is a pair of input combinations that: (a) differ in only one input variable and (b) both produce a "0" output, such that it is possible for a output, momentary "1" output to occur during a transition in the differing input variable A static0 hazard is just the dual of a static1 hazard
171 Timing Hazards
A Kmap can be used to detect static Khazards in a twolevel sumofproducts or twosumofproductofproductofsums circuit Important: Important: The existence or nonexistence of static hazards depends on the circuit design (i.e., realization) of a logic function realization) A properly designed twolevel sumoftwosumofstaticproducts (ANDOR) circuit has no static0 (ANDhazards but may have static1 hazards staticExistence of static1 hazards can be staticpredicted from a Kmap K172 Timing Hazards
Using a Kmap to graphically detect the Kpossibility of a static1 hazard: staticX Z Z
0 2 X 0 1
6 0
1 1 1 4 1 0 0 3 7 5 f (X,Y,Z) = XZ+YZ +Y Y Y Y Note: It is possible for the output to momentarily glitch to "0" if the AND gate that covers one of the combinations goes to "0" before the AND gate covering the other input combination goes to "1"
173 Timing Hazards
Solution: Solution: Include an extra product term (AND gate) to cover the hazardous input pair X Z Z
0 2 X 0 1 Y
6 0
1 1 1 4 1 0 Y f (X,Y,Z) = XZ+YZ 0 Y 3 7 5 + XY The extra product term is the consensus of the two original terms in general, consensus terms must be added to eliminate hazards
174 Timing Hazards
A dynamic hazard is the possibility of an output changing more than once as the result of a single input transition Multiple output transitions can occur if there are multiple paths with different delays from the changing input to the changing output 175 Timing Hazards
Important: Important: Not all hazards are hazardous in fact, some can be quite useful! Consider the case in which we would like to detect a lowtohigh transition (the "leading edge") lowtoof a logic signal TPHL TPLH 176 Timing Hazards
Designing hazardfree circuits hazard very few practical applications require the design of hazardfree combinational hazardcircuits (e.g., feedback sequential circuits) techniques for finding hazards in arbitrary circuits are difficult to use if cost is not a problem, then a "brute force" method of obtaining a hazardfree hazardrealization is to use the complete sum functions that have nonadjacent product nonterms are inherently hazardous when subjected to simultaneous input changes
177 Clicker Quiz 178 X 2 1 2 1 3 Y 1. Steady state analysis of this circuit would predict that its output will always be: A. 0 B. 1 C. 50% of VCC D. HiZ E. none of the above
179 X 2 1 2 1 3 Y 2. This circuit exhibits the following type of hazard when its input, X, transitions from lowtohigh: A. static0 B. static1 C. dynamic D. HiZ E. none of the above
180 X 2 1 2 1 3 Y 3. This circuit exhibits the following type of hazard when its input, X, transitions from hightolow: A. static0 B. static1 C. dynamic D. HiZ E. none of the above
181 1 ms
X Y
2 1 2 1 3 2 1 2 1 3 2 1 3 F 4. Steadystate analysis of the function realized by this
circuit for the input waveforms shown predicts that the output F(X,Y) should: A. should always be low B. should always be high C. should be identical to the input D. should be the complement of the input E. none of the above 182 1 ms
X Y
2 1 2 1 3 2 1 2 1 3 2 1 3 F 5. Dynamic analysis of the output F(X,Y) reveals that:
A. a static "0" hazard will be generated in response to lowtohigh transitions of the input waveform B. a static "1" hazard will be generated in response to lowtohigh transitions of the input waveform C. a static "0" hazard will be generated in response to hightolow transitions of the input waveform D. a static "1" hazard will be generated in response to hightolow transitions of the input waveform E. none of the above 183 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 2E XOR/XNOR Functions 184 Reading Assignment: 3rd Ed., pp. 410413; 4th Ed., pp. 447448 410447Instructional Objectives:
To learn about XOR/XNOR functions and their properties To learn how to implement "nonreducible" "nonBoolean functions using XOR/XNOR gates 185 Outline
XOR and XNOR functions Implementation of "nonreducible" "nonfunctions using XOR/XNOR gates 186 XOR/XNOR Functions
An ExclusiveOR (XOR) gate is a 2input Exclusive(XOR) 2gate whose output is "1" if exactly one of its inputs is "1" (or, an XOR gate produces an output of "1" if its inputs are different) different) An ExclusiveNOR (XNOR) gate is the Exclusive(XNOR) complement of an XOR gate it produces an output of "1" if its inputs are the same An XNOR gate is also referred to as an Equivalence (or XAND) gate XAND) Although XOR is not one of the basic functions of switching algebra, discrete XOR gates are commonly used in practice
187 XOR/XNOR Functions
The "ring sum" operator is sometimes used to denote the XOR function: X Y = XY + XY X XY The XNOR operator can be thought of as either the DUAL or the COMPLEMENT of the XOR operator
188 XOR Properties
Properties of the XOR operator X X = XX + XX = 0 + 0 = 0 X XX X X = XX + XX = 0 + 0 = 0 XX X X 1 = X1 + X0 = X X X X 1 = X1 + X0 = X X (X Y) = X Y 1 Y) XY=YX X (Y Z) = (X Y) Z X(Y Z) = (XY) (XZ) (XY) XZ)
189 XOR KMap KKmap of 2variable XOR function 2X Y = XY + XY X XY X Y Y
0 X
2 0 1 1
3 1 0 Leads to a "checkerboard" Kmap, that cannot be reduced (either SP or PS form)
190 74x86 Multigate 2input XOR Designs XOR and XNOR Equivalent Symbols 191 XOR NVariable Functions NThe XOR (or XNOR) of n variables can be realized with tree or cascade circuits 192 NonNonReducible Functions
Functions that cannot be significantly reduced using conventional minimization techniques can sometimes be simplified by implementing them with XOR/XNOR gates Candidate functions that may be simplified this way have Kmaps with "diagonal 1's" KTechnique: Technique: Write out function in SP form, and "factor out" XOR/XNOR expressions 193 NonReducible Functions
Example: Kmap with diagonal 1's W
0 4 W
12 8 Y 1
1 0 1 0 0 0
13 0 0 0 1 X Z Z Z 0 0 0 X 5 0 1 0 9 3 7 15 11 Y 2 6 14 10 X 194 NonReducible Functions
Example: Kmap with diagonal 1's W
0 4 W
12 8 Y 1
1 0 1 0 0 0
13 0 0 0 1 X Z Z Z 0 0 0 X 5 0 1 0 9 F(W,X,Y,Z) = WXYZ + WXYZ + WXYZ + WXYZ 3 7 15 11 Y 2 6 14 10 X 195 NonReducible Functions
Example: Kmap with diagonal 1's W
0 4 W
12 8 Y 1
1 0 1 0 0 0
13 0 0 0 1 X Z 0 0 0 X 5 0 1 0 9 F(W,X,Y,Z) = WXYZ + WXYZ + WXYZ + WXYZ 3 7 15 11 Z = XZ (WY + WY) + XZ (WY + WY) Y 2 6 14 10 Z X 196 NonReducible Functions
Example: Kmap with diagonal 1's W
0 4 W
12 8 Y 1
1 0 1 0 0 0
13 0 0 0 1 X Z 0 0 0 X 5 0 1 0 9 F(W,X,Y,Z) = WXYZ + WXYZ + WXYZ + WXYZ 3 7 15 11 Z = XZ (WY + WY) + XZ (WY + WY) Y 2 6 14 10 Z = (XZ +XZ)(WY+WY) X 197 NonReducible Functions
Example: Kmap with diagonal 1's W
0 4 W
12 8 Y 1
1 0 1 0 0 0
13 0 0 0 1 X Z 0 0 0 X 5 0 1 0 9 F(W,X,Y,Z) = WXYZ + WXYZ + WXYZ + WXYZ 3 7 15 11 Z = XZ (WY + WY) + XZ (WY + WY) Y 2 6 14 10 Z = (XZ +XZ)(WY+WY) = (X Z) (W Y) 198 X NonReducible Functions
Implementation of "diagonal 1's" function using XOR/XNOR gates COST = 6 inputs + 3 outputs = 9 199 NonReducible Functions
Implementation of "diagonal 1's" function using minimum SoP circuit COST = 20 inputs + 5 outputs = 25 200 NonReducible Functions
Example: "X"map W
0 4 W
12 8 Y 1
1 0 1 1 0 0
13 1 0 0 1 X Z Z Z 0 0 1 X 5 1 1 0 9 3 7 15 11 Y 2 6 14 10 X 201 NonReducible Functions
Example: "X"map W
0 4 W
12 8 Y 1
1 0 1 1 0 0
13 1 0 0 1 X Z Z Z
F(W,X,Y,Z) = XZ + XZ = (X Z) 0 0 1 X 5 1 1 0 9 3 7 15 11 Y 2 6 14 10 X 202 Clicker Quiz 203 X Y 2 1 2 1 3 2 1 2 1 3 2 1 3 F 1. The function realized by this circuit is a: A. 2input XOR B. 2input XNOR C. 2input AND D. 2input OR E. none of the above 204 VCC X' Y X Y' 1 3 2 7403 4 6 5 7403 OD OD 2. The ON set of the function realized by this circuit is: A. X,Y(0,2) B. X,Y(0,3) C. X,Y(1,2) D. X,Y(1,3) E. none of the above 205 X Y 2 1 3 2 1 3 Z F 3. The ON set of the function realized by this circuit is: A. X,Y,Z(0,3,4,7) B. X,Y,Z(1,2,5,6) C. X,Y,Z(0,3,5,6) D. X,Y,Z(1,2,4,7) E. none of the above 206 4. The XOR property listed below that is NOT true is: A. X 0 = X B. X 1 = X C. X X = X D. X X = 1 E. none of the above
207 5. The following is NOT an equivalent symbol for an XOR gate: A. B. C. D. E. none of the above
208 ...
View
Full Document
 Spring '08
 Staff
 Logic gate, Karnaugh map, Combinational Logic Circuits, x,y,z

Click to edit the document details