2-Mod3_CP_2011

2-Mod3_CP_2011 - 2011 Edition by D. G. Meyer Introduction...

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Unformatted text preview: 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3 Hardware Description Languages and Combinational Building Blocks 1 Module 3 Desired Outcome: "An ability to use a hardware description language (ABEL) to specify combinational logic circuits, including various `building blocks' such as decoders, multiplexers, encoders, tri-state buffers." tri Part A: Combinational PLDs and ABEL Part B: ispLever Demo Part C: Decoders Part D: Encoders Part E: Tri-State Buffers Tri Part F: Multiplexers Part G: XOR/XNOR Functions 2 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3-A Combinational PLDs and ABEL 3 Reading Assignment: 3rd Ed., pp. 249-263, 337-351; 2493374th Ed., pp. 237-255, 370-383 237370Instructional Objectives: To learn what a programmable logic device (PLD) is and how they can be used to implement combinational functions To learn what a hardware description language is and how it can be used to create designs for implementation on PLDs To learn about a specific hardware description language (ABEL) and associated compiler (ispLeverTM) 4 Outline Overview Combinational PLDs ABEL and ispLeverTM 5 Overview The first PLDs were programmable logic arrays (PLAs) PLAs are combinational, two-level AND-OR twoANDdevices that can be programmed to realize and sum-of-products expression sum-ofLimitations number of inputs (n) (n number of outputs (m) (m number of product ("P") terms (p) (p Such a device might be described as an n x m PLA with p product terms 6 Overview Each input is connected to a buffer that produces both a true and a complemented version of the signal for use in the array Connections are made by fuses, which are fuses, actual fusible links (one-time programmable (onedevices) or non-volatile memory cells non(erasable, re-programmable devices) reEach AND gate's inputs can be any subset of the primary input signals and their complements Each OR gate's inputs can be any subset of the AND gate outputs 7 Overview 4 x 3 PLA with 6 product terms Potential connections indicated by "X" 8 Overview Compact view of 4 x 3 PLA with 6 P-terms 9 Overview 4 x 3 PLA programmed to implement three logic equations I1I2 + I1I2I3I4 I1I3 + I1I3I4 + I2 I1I2 + I1I3 + I1I2I4 10 Combinational PLDs A special case of PLA is the programmable array logic (PAL) device Unlike a PLA, a PAL device has a fixed OR array (i.e., AND gates can not be shared) Each output has an individual tri-state enable, tricontrolled by a dedicated AND gate There is an inverter between the output of the OR gate and the external pin Some of the output pins may also be used as inputs (called "I/O pins") pins") tri-state buffer OFF, input only triOFF, tri-state buffer ON, either output-only, output triON, output-only, cascaded to another function input, or feedback to create a sequential circuit 11 Combinational PLDs Generic Array Logic (GAL) devices can be configured to emulate the AND-OR, flip-flop, ANDflipand output structure of a variety of combinational and sequential PAL devices A macrocell is associated with each output pin which contains the configuration logic for the output structure of that pin In its combinational configuration, a GAL device includes output polarity control Output polarity control is important because it allows minimization software to implement either the sum-of-products or product-ofsum-ofproduct-ofsums realization of a logic function 12 Combinational PLDs Erasable Programmable Logic Devices are often referred to as EPLDs these devices use a floating gate technology similar to that used in non-volatile "flash" memory nonIn lab, we will use GAL16V8, GAL22V10, and GAL26V12 EPLDs Special instruments, called universal programmers, programmers, are required to "burn" (or program) program) the fuse pattern into a EPLD (although many of the larger EPLDs are in-circuit programmable) inprogrammable) 13 GAL16V8 Block Diagram number of AND array inputs number of macrocells/outputs 14 GAL16V8 Macrocell 15 GAL16V8 Macrocell Multiplexers select lines controlled by fusible links 16 GAL16V8 Macrocell allows macrocell to be used for combinational circuits or sequential circuits 17 GAL16V8 Macrocell If tri-state buffer is disabled, the macrocell pin can be used as an input 18 GAL16V8 Macrocell If tri-state buffer is enabled, can select combinational or sequential feedback 19 GAL16V8 Macrocell Allows up to 8 product terms 20 GAL16V8 Macrocell Allows use of SOP or POS form of function 21 GAL16V8 Macrocell Allows 4 possibilities for controlling tri-state output buffer 22 GAL16V8 Macrocell 1. a single product term expression leaves only 7 product terms for function in this case Allows 4 possibilities for controlling tri-state output buffer 23 GAL16V8 Macrocell 2. the common OE pin Allows 4 possibilities for controlling tri-state output buffer 24 GAL16V8 Macrocell 3. always ON (Vcc) Allows 4 possibilities for controlling tri-state output buffer 25 GAL16V8 Macrocell 4. always OFF (Gnd) Allows 4 possibilities for controlling tri-state output buffer 26 GAL16V8 Pinout clock or data input data inputs macrocell pins (inputs or outputs) common output enable pin 27 Clicker Quiz 28 1. The following is not a means provided for programming the tri-state enable control: A. using the OE input (pin 11) B. writing an expression consisting of a single product term C. always enabled D. always disabled E. none of the above 29 2. A function consisting of more than 8 product terms can be implemented on a 16V8 PLD by: A. turning off the tri-state buffer B. routing the output of one macrocell to the input of another macrocell C. using the OE input (pin 11) D. using some of the output pins as input pins E. none of the above 30 3. Using the OE input (pin 11) to control the tri-state output buffer allows: A. a single-product-term expression to be written for the tri-state enable B. the macrocell I/O pins to be used as a bidirectional bus C. implementation of a function consisting of more than 8 product terms D. use of some of the input pins as output pins E. none of the above 31 4. A "side effect" of writing a single-product-term expression for the tri-state enable is: A. only 7 product terms are available for realizing the macrocell's output function B. the OE pin (pin 11) can be used as an additional input C. the macrocell's I/O pin can be used bidirectionally D. all of the above E. none of the above 32 5. The mechanism within a macrocell that allows it to be programmed as "Combinatorial Output Active Low" vs. "Combinatorial Output Active High" is: A. the tri-state output buffer B. the XOR gate C. the AND array D. the OR gate E. none of the above 33 ABEL and ispLeverTM ABEL is a hardware description language (HDL) that allows designers to specify logic functions for realization in PLDs We will use the Lattice ispLeverTM software package in lab, which features several options for specifying logic functions including ABEL You can obtain your own "trial" copy of this software from the Lattice Semiconductor web site (www.latticesemi.com) (www.latticesemi.com) 34 ABEL and ispLeverTM An ABEL program is a text file containing: documentation (program name, comments) declarations that identify the inputs and outputs of the logic functions to be performed statements that specify the logic functions to be performed [optionally] "test vectors" that specify expected functional outputs for certain input combinations ABEL source files are transformed into a fuse map file by an ABEL compiler (ispLever) A universal programmer is used to burn the fuse map file into the device 35 ABEL and ispLeverTM ABEL program structure identifiers must begin with a letter or underscore a program file begins with a Module statement the title statement specifies a title string comments begin with a double quote and end with another double quote (or end of line, whichever comes first) pin declarations tell the compiler about symbolic names associated with the external pins of the device 36 ABEL and ispLeverTM ABEL program structure... the istype keyword precedes a list of one or more properties, separated by commas, that tells the compiler the type of output signal (combinational, registered, active high, active low) the Equations statement indicates that logic equations defining output signals as functions of input signals will follow equations are written like assignment statements (X = Y;) in a conventional (X Y;) programming language, with each equation terminated by a semicolon 37 ABEL and ispLeverTM ABEL program structure... the following symbols are used for logical operations: & # ! $ AND OR NOT XOR Note: AND (&) has precedence over OR (#) !$ XNOR 38 ABEL and ispLeverTM ABEL program structure... the Truth_Table statement indicates that a truth table function specification follows the [optional] Test_Vectors statement indicates that test vectors follow test vectors associate input combinations with expected output values, and are used for simulation and testing the End statement marks the end of a module 39 MODULE TITLE abel_ex 'ABEL Combinational Example for GAL16V8' DECLARATIONS " Input pins A pin 2; B pin 3; C pin 4; D pin 5; " Output pins X pin 12 istype 'com'; Y pin 13 istype 'com'; Z pin 14 istype 'com'; EQUATIONS X = A&B # !C&D; Y = !B&D # !A&B&D; Z = A & !B&C&!D; END A Sample ABEL Program 40 MODULE TITLE ttab_ex 'Truth Table (Instruction ROM) Example for GAL16V8' DECLARATIONS " Input pins A0..A3 pin 2..5; MRD pin 11; range " Output pins D0..D2 pin 12..14 istype 'com'; TRUTH_TABLE ([A3,A2,A1,A0]->[D2,D1,D0]) [ 0, 0, 0, 0]->[ 0, 0, 0]; [ 0, 0, 0, 1]->[ 0, 0, 1]; [ 0, 0, 1, 0]->[ 0, 1, 0]; [ 0, 0, 1, 1]->[ 0, 0, 1]; [ 0, 1, 0, 0]->[ 0, 1, 1]; [ 0, 1, 0, 1]->[ 0, 0, 1]; [ 0, 1, 1, 0]->[ 0, 0, 0]; [ 0, 1, 1, 1]->[ 0, 0, 1]; [ 1, 0, 0, 0]->[ 1, 0, 0]; [ 1, 0, 0, 1]->[ 0, 0, 1]; [ 1, 0, 1, 0]->[ 1, 0, 1]; [ 1, 0, 1, 1]->[ 0, 0, 1]; [ 1, 1, 0, 0]->[ 1, 1, 0]; [ 1, 1, 0, 1]->[ 0, 0, 1]; [ 1, 1, 1, 0]->[ 1, 1, 1]; [ 1, 1, 1, 1]->[ 0, 0, 1]; EQUATIONS Another Sample ABEL Program truth table "IN "OUT "ANA "OUT "ORA "OUT "IN "OUT "ROR "OUT "ROL "OUT "ASR "OUT "ASL "OUT set [D2..D0].OE = MRD; END 41 Clicker Quiz 42 1. Which of the following is not a valid ABEL identifier? A. X2 B. 2X C. XY D. _XY E. none of the above 43 2. Which of the following is an example of a range? A. X0..X3 B. [X0..X3] C. GA..GE D. [GA..GE] E. none of the above 44 3. Which of the following is an example of a set? A. X0..X3 B. [X0..X3] C. GA..GE D. [GA..GE] E. none of the above 45 4. For pin declarations, which of the following statements is not true? A. pin declarations associate symbolic names with the device's physical pins B. pin numbers are optional C. if the pin number is omitted, the pin numbers are assigned by the "fitter" program based on the PLD characteristics D. the pin may be declared active high or active low E. none of the above 46 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3-B ispLeverTM Demo (and Game Show) 47 Reading Assignment: ispLeverTM On-line OnDocumentation Instructional Objectives: To learn how to use the Lattice ispLeverTM PLD compiler To review some of the major topics introduced in Chapter 4 by working a complete design example 48 Outline Comprehensive Design Example and Game Show ispLeverTM Demo 49 Design Problem Statement You have been asked to design a circuit that determines grades based on the characters (E,R,S,T) in a student's last name, as follows: Give a grade of "A" if name contains an R and a T -or- an R and not an S orGive a grade of "B" if name contains an E and not an R and not a S -or- does not contain an R orand not a T and not an S Give a grade of "C" if name contains an S and not a T Give a grade of "D" if name contains a T and not an E and not an R Give a grade of "F" if none of the above (name contains an E and an S and a T and not an R) 50 K-Map of "Grade Distribution" E 0 4 E 12 S B 1 A A A C A 8 B B T T D D C R 5 13 A 9 3 7 15 S A C 11 F 10 2 6 14 C T R R 51 Options Map and minimize all 5 functions, implement with several discrete CMOS ICs, subject to the following limitations: only "true" variables are available only ICs in "DK-1" parts kit can be used "DK 7400 quad 2-input NAND 27402 quad 2-input NOR 27404 hex inverter 7410 triple 3-input NAND 3- Create an ABEL file that specifies the desired functionality using a truth table, implement with a single 16V8 PLD 52 Working K-Map for "A" SoP KE 0 4 12 E 1 8 S 0 1 1 5 0 9 T T T A = S + TR R 0 0 0 R 1 1 0 13 1 1 0 0 0 3 7 15 11 S 2 6 14 10 0 R R COST = 6 inputs + 3 outputs = 9 53 Working K-Map for "A" PoS KE 0 4 12 E 1 8 S 0 1 1 5 0 9 T T T A = R + ST A = R (S + T) 0 0 0 R 1 1 0 13 1 1 0 0 0 3 7 15 11 S 2 6 14 10 0 R R COST = 4 inputs + 2 outputs = 6 54 Cheaper than SoP Working K-Map for "B" SoP KE 0 4 12 E 0 8 S 1 1 0 5 1 9 T T T B = ES + R R S T 0 0 0 R 0 0 0 13 0 0 0 1 0 3 7 15 11 S 2 6 14 10 0 R R COST = 8 inputs + 3 outputs = 11 55 Working K-Map for "B" PoS KE 0 4 12 E 0 8 S 1 1 0 5 1 9 T T T B = S + R + E T B = S R (E+T) 0 0 0 R 0 0 0 13 0 0 0 1 0 3 7 15 11 S 2 6 14 10 0 R R COST = 5 inputs + 2 outputs = 7 56 Cheaper than SoP Working K-Map for "C" SoP KE 0 4 12 E 0 8 S 0 1 0 5 0 9 T T T C = ST 0 0 1 R 0 0 1 13 0 0 1 0 0 3 7 15 11 S 2 6 14 10 1 R R COST = 3 inputs + 2 outputs = 5 57 Working K-Map for "C" PoS KE 0 4 12 E 0 8 S 0 1 0 5 0 9 T T T C = S + T C = ST 0 0 1 R 0 0 1 13 0 0 1 0 0 3 7 15 11 S 2 6 14 10 1 R R COST = 2 inputs + 1 output = 3 58 Cheaper than SoP Working K-Map for "D" SoP KE 0 4 12 E 0 8 S 0 1 0 5 0 9 T T T D = E R T 1 1 0 R 0 0 0 13 0 0 0 0 0 3 7 15 11 S 2 6 14 10 0 R R COST = 4 inputs + 2 outputs = 6 59 Working K-Map for "D" PoS KE 0 4 12 E 0 8 S 0 1 0 5 0 9 T T T D = E R T 1 1 0 R 0 0 0 13 0 0 0 0 0 3 7 15 11 S 2 6 14 10 0 R R COST = 3 inputs + 1 output = 4 60 Cheaper than SoP Working K-Map for "F" - SoP KE 0 4 12 E 0 8 S 0 1 0 5 0 9 T T T F = ESR T 0 0 0 R 0 0 0 13 0 0 0 0 1 3 7 15 11 S 2 6 14 10 0 R R COST = 5 inputs + 2 outputs = 7 61 Working K-Map for "F" - PoS KE 0 4 12 E 0 8 S 0 1 0 5 0 9 T T T 0 0 0 R 0 0 0 13 F = E+S+R+T F = ESR T 0 0 0 0 1 3 7 15 11 S 2 6 14 10 0 R R COST = 4 inputs + 1 output = 5 62 Cheaper than SoP Final Answer... 1/4 - 7402 2/3 - 7404 1/3 - 7410 1/6 - 7404 1/2 - 7402 1/2 - 7400 1/4 - 7402 2/3 - 7410 1/4 - 7400 3/4 - 7400 5/6 - 7404 1 - 7402 1 - 7410 4 integrated circuits total 63 ispLeverTM Demo - 1 64 ispLeverTM Demo - 2 65 ispLeverTM Demo - 3 66 ispLeverTM Demo - 4 67 ispLeverTM Demo - 5 68 ispLeverTM Demo - 6 69 ispLeverTM Demo - 7 70 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3-C Combinational Building Blocks: Decoders 71 Reading Assignment: 3rd Ed., pp. 351-367; 4th Ed., pp. 384-398 351384Instructional Objectives: To learn what decoders are and how they can be used in the design of digital systems To learn how to specify decoding functions in ABEL 72 Outline Overview Binary decoders Decoders in ABEL Special purpose decoders 73 Overview Definition: Definition: A decoder is a multiple-input, multiplemultiplemultiple-output logic circuit that converts coded inputs into coded outputs The input code generally has fewer bits than the output code In a one-to-one mapping, each input code one-toword produces a different output code word 74 Overview The most commonly used input code is an n-bit binary code, where an n-bit word nrepresents one of 2n different coded values Sometimes an n-bit binary code is truncated nto represent fewer than 2n values (e.g., BCD) The most commonly used output code is a 1-out-of-m code, which contains m bits, out-ofwhere only one bit is asserted at any time (the output code bits are mutually exclusive) exclusive) 75 Binary Decoders The most common decoder circuit is an n-to-2n decoder or binary decoder toBinary decoders have an n-bit binary input ncode and a 1-out-of-2n output code 1-out-ofApplication: Application: Used to activate exactly one of 2n outputs based on an n-bit value nAnalogy: ElectronicallyAnalogy: Electronically-controlled rotary selector switch 76 Binary Decoders Example: Generic 2-to-4 decoder 77 Binary Decoders Example: Example: 74x138 3-to-8 decoder, with one 3-toactive high enable (G1) and two active low (G1) enables (!G2A and !G2B) !G2B) An output is asserted if and only if the decoder is enabled (EN = G1 & !G2A & !G2B) and the output is selected (corresponding to a specific combination of select lines C, B, and A) A) 78 74x138 3-to-8 Decoder 79 Binary Decoders Exercise: Using a `138, design a circuit that will illuminate one of eight LEDs based on the binary number entered on three switches 80 Binary Decoders Exercise: Using a `138, design a circuit that will illuminate one of eight LEDs based on the binary number entered on three switches H L L 81 Binary Decoders Exercise: Using a `138, design a circuit that will illuminate one of eight LEDs based on the binary number entered on three switches H L L Vcc 82 Binary Decoders Exercise: Using a `138, design a circuit that will illuminate one of eight LEDs based on the binary number entered on three switches Vcc H L L Vcc 83 Binary Decoders Exercise: Using a `138, design a circuit that will illuminate one of eight LEDs based on the binary number entered on three switches Vcc H L L Vcc NOTE: Only one LED is on at a time 84 Key Observations Key Observation #1: each output of an n to 2n binary decoder represents a minterm of an n-variable Boolean function; therefore, any arbitrary Boolen function of n-variables can be implemented with an n-input binary decoder by simply "OR-ing" the needed outputs Key Observation #2: if the decoder outputs are active low, a NAND gate can be used to "OR" the minterms of the function (representing its ON set) Key Observation #3: if the decoder outputs are active low, an AND gate can be used to "OR" the minterms of the complement function (representing its OFF set) Key Observation #4: a NAND gate (or AND gate) with at most 2n-1 inputs is needed to implement an arbitrary n-variable function using an n to 2n binary decoder (that has active low outputs) 85 Key Observations General circuit for implementing an arbitrary n-variable function using a decoder, for case where ON set has 2n-1 members VCC Z Y X 1 2 3 6 4 5 A B C G1 G2AN G2BN Y 0N Y 1N Y 2N Y 3N Y 4N Y 5N Y 6N Y 7N 15 14 13 12 11 10 9 7 F(X,Y,Z) How does circuit change if ON set has > 2n-1 members? 86 Key Observations General circuit for implementing an arbitrary n-variable function using a decoder, for case where ON set has 2n-1 members VCC Z Y X 1 2 3 6 4 5 A B C G1 G2AN G2BN Y 0N Y 1N Y 2N Y 3N Y 4N Y 5N Y 6N Y 7N 15 14 13 12 11 10 9 7 F(X,Y,Z) How does circuit change if ON set has > 2n-1 members? Use an AND gate in conjunction with the OFF set 87 Clicker Quiz 88 VCC Z Y X 1 2 3 6 4 5 A B C G1 G2AN G2BN Y 0N Y 1N Y 2N Y 3N Y 4N Y 5N Y 6N Y 7N 15 14 13 12 11 10 9 7 F(X,Y,Z) 1. The ON set realized by this decoder-based circuit is: A. X,Y,Z(0,3,5,6) B. X,Y,Z(1,2,4,7) C. X,Y,Z(1,2,5,6) D. X,Y,Z(0,3,4,7) E. none of the above 89 VCC Z Y X 1 2 3 6 4 5 A B C G1 G2AN G2BN Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N 15 14 13 12 11 10 9 7 F(X,Y,Z) 2. The ON set realized by this decoder-based circuit is: A. X,Y,Z(0,3,5,6) B. X,Y,Z(1,2,4,7) C. X,Y,Z(1,2,5,6) D. X,Y,Z(0,3,4,7) E. none of the above 90 Decoders in ABEL Example 1: Implement the equivalent of a 1: 74x138 using a 16V8 PLD Example 2: Implement a 3-to-8 decoder with 2: 3-toactive high outputs using a 16V8 PLD 91 MODULE dec138 TITLE '74x138 decoder implemented using 16V8' DECLARATIONS " Enable input pins G1 pin 1; !G2A pin 2; !G2B pin 3; " Select input pins C, B, A pin 4, 5, 6; " Output pins Note active low pin declarations !Y0, !Y1, !Y2, !Y3, !Y4, !Y5, !Y6, !Y7 pin 19..12 istype 'com'; " Intermediate equation EN = G1 & G2A & G2B; EQUATIONS Y0 = EN & Y1 = EN & Y2 = EN & Y3 = EN & Y4 = EN & Y5 = EN & Y6 = EN & Y7 = EN & END !C !C !C !C C C C C & & & & & & & & !B !B B B !B !B B B & & & & & & & & !A; A; !A; A; !A; A; !A; A; 92 MODULE dec138ah TITLE '3-to-8 active high decoder implemented using 16V8' DECLARATIONS " Enable input pins G1 pin 1; !G2A pin 2; !G2B pin 3; " Select input pins C, B, A pin 4, 5, 6; " Output pins Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 pin 19..12 istype 'com'; " Intermediate equation EN = G1 & G2A & G2B; EQUATIONS Y0 = EN & Y1 = EN & Y2 = EN & Y3 = EN & Y4 = EN & Y5 = EN & Y6 = EN & Y7 = EN & END !C !C !C !C C C C C & & & & & & & & !B !B B B !B !B B B & & & & & & & & !A; A; !A; A; !A; A; !A; A; 93 Special Purpose Decoders A seven-segment decoder has 4-bit BCD as seven4its input code and the "seven-segment code" "sevenas its output code (e.g., 74x79) 94 95 96 97 98 74x79 BCD-to-7-Segment Decoder 99 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3-D Combinational Building Blocks: Encoders 100 Reading Assignment: 3rd Ed., pp. 376-383; 4th Ed., pp. 408-415 376408Instructional Objectives: To learn what encoders are and how they can be used in the design of digital systems To learn how to specify encoding functions in ABEL 101 Outline Overview Priority Encoders ABEL Implementation of Encoders 102 Overview Definition: Definition: An encoder is an "inverse decoder" the role of inputs and outputs is reversed, and there are more input code bits than output code bits The simplest encoder to build is a 2n-to-n or tobinary encoder L L H L L L L L L H L 103 Priority Encoders A common application is to encode the number of a device requesting service from a microprocessor-based system microprocessor- Problem: More than one device may be requesting service at any given time 104 Priority Encoders Solution: Solution: Assign priority to the input lines, such that when multiple inputs are asserted simultaneously, the highest priority (highest numbered) input "wins" such a device is called a priority encoder An easy way to specify this functionality in ABEL is to use a truth table Example: Example: An 8-to-3 encoder with active high 8-toinputs and outputs, including a "strobe" output (GS) to indicate if any input has been asserted 105 MODULE TITLE pri_enc '8-to-3 Priority Encoder Using 16V8' DECLARATIONS " Input pins I0..I7 pin; "Input 0 - lowest priority, Input 7 - highest " Output pins E0..E2 pin istype 'com'; "E2 E1 E0 - encoded output GS pin istype 'com'; "strobe output (asserted if any input asserted) " Short-hand for don't care X = .X.; TRUTH_TABLE ([I7,I6,I5,I4,I3,I2,I1,I0]->[E2,E1,E0,GS]) [ 0, 0, 0, 0, 0, 0, 0, 0]->[ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 0, 0, 1]->[ 0, 0, 0, 1]; [ 0, 0, 0, 0, 0, 0, 1, X]->[ 0, 0, 1, 1]; [ 0, 0, 0, 0, 0, 1, X, X]->[ 0, 1, 0, 1]; [ 0, 0, 0, 0, 1, X, X, X]->[ 0, 1, 1, 1]; [ 0, 0, 0, 1, X, X, X, X]->[ 1, 0, 0, 1]; [ 0, 0, 1, X, X, X, X, X]->[ 1, 0, 1, 1]; [ 0, 1, X, X, X, X, X, X]->[ 1, 1, 0, 1]; [ 1, X, X, X, X, X, X, X]->[ 1, 1, 1, 1]; END " " " " " " " " " none active input 0 wins input 1 wins input 2 wins input 3 wins input 4 wins input 5 wins input 6 wins input 7 wins 106 product terms in SoP realization Title: 8-to-3 Priority Encoder Using 16V8 P-Terms --------4/4 4/3 4/1 8/1 ========= 20/9 Fan-in -----7 6 4 8 Fan-out ------1 1 1 1 Type ---Pin Pin Pin Pin product terms in !SoP realization Name (attributes) ----------------E0 E1 E2 G 9 12 0 2 Best P-Term Total: Total Pins: Total Nodes: Average P-Term/Output: Equations: a node is a macrocell that does not have a pin associated with it E0 = (I7 # I5 & !I6 # I3 & !I4 & !I6 # I1 & !I2 & !I4 & !I6); E1 = (I6 # I7 # I2 & !I4 & !I5 # I3 & !I4 & !I5); E2 = (I4 # I5 # I6 # I7); G = (I0 # I1 # I2 # I3 # I4 # I5 # I6 # I7); 107 Clicker Quiz 108 Title: 8-to-3 Priority Encoder Using 16V8 (ispLever Reduced Equation Report) P-Terms --------4/4 4/3 4/1 8/1 ========= 20/9 Fan-in -----7 6 4 8 Fan-out ------1 1 1 1 Type ---Pin Pin Pin Pin Name (attributes) ----------------E0 E1 E2 GS 9 12 0 2 Best P-Term Total: Total Pins: Total Nodes: Average P-Term/Output: Equations: E0 = (!I6 & !I4 & !I2 & I1 # !I6 & !I4 & I3 # !I6 & I5 # I7); E1 = (!I5 & !I4 & I2 # !I5 & !I4 & I3 # I6 # I7); E2 = (I4 # I5 # I6 # I7); GS = (I1 # I0 # I2 # I3 # I4 # I5 # I6 # I7); Reverse-Polarity Equations: !E0 = (!I7 & !I5 & !I3 & !I1 # !I7 & !I5 & !I3 & I2 # !I7 & !I5 & I4 # !I7 & I6); !E1 = (!I7 & !I6 & !I3 & !I2 # !I7 & !I6 & I4 # !I7 & !I6 & I5); !E2 = (!I7 & !I6 & !I5 & !I4); !GS = (!I7 & !I6 & !I5 & !I4 & !I3 & !I2 & !I1 & !I0); 109 1. The Best P-Term Total shown in the report indicates: A. the minimum number of pins needed to implement the logic function B. the minimum number of macrocells needed to implement the logic function C. the minimum number of OR gates needed to implement the logic function D. the minimum number of AND gates needed to implement the logic function E. none of the above 110 2. The number of P-Terms needed to realize the !E0 (reverse-polarity) equation is: A. 1 B. 2 C. 4 D. 8 E. none of the above 111 3. The number of P-Terms needed to realize the GS (positive-polarity) equation is: A. 1 B. 2 C. 4 D. 8 E. none of the above 112 Commercial Priority Encoders The 74x148 is a commercial, MSI 8-input 8priority encoder; it differs from our "generic" ABEL 8-to-3 encoder in the following ways: 8-to it has EI ("enable in") and EO ("enable out") signals that enable it to be cascaded all of its inputs and outputs are active low enable input request inputs encoded outputs strobe output enable output 113 Example: Create an ABEL file that implements the equivalent functionality of a 74x148 MODULE pld74148 TITLE '74x148 3:8 Priority Encoder' DECLARATIONS !I7..!I0 pin; " prioritized inputs (#7 highest) !EI pin ; " enable input !EO pin istype 'com' ; " enable output !GS pin istype 'com' ; " strobe output !A2..!A0 pin istype 'com' ; " encoded output X = .X. ; " short-hand for don't care TRUTH_TABLE ([EI,I7,I6,I5,I4,I3,I2,I1,I0]->[EO,A2,A1,A0,GS]) [ 0, X, X, X, X, X, X, X, X]->[ 0, 0, 0, 0, 0]; [ 1, 0, 0, 0, 0, 0, 0, 0, 0]->[ 1, 0, 0, 0, 0]; [ 1, 0, 0, 0, 0, 0, 0, 0, 1]->[ 0, 0, 0, 0, 1]; [ 1, 0, 0, 0, 0, 0, 0, 1, X]->[ 0, 0, 0, 1, 1]; [ 1, 0, 0, 0, 0, 0, 1, X, X]->[ 0, 0, 1, 0, 1]; [ 1, 0, 0, 0, 0, 1, X, X, X]->[ 0, 0, 1, 1, 1]; [ 1, 0, 0, 0, 1, X, X, X, X]->[ 0, 1, 0, 0, 1]; [ 1, 0, 0, 1, X, X, X, X, X]->[ 0, 1, 0, 1, 1]; [ 1, 0, 1, X, X, X, X, X, X]->[ 0, 1, 1, 0, 1]; [ 1, 1, X, X, X, X, X, X, X]->[ 0, 1, 1, 1, 1]; END " " " " " " " " " " disabled no inputs active input #0 wins input #1 wins input #2 wins input #3 wins input #4 wins input #5 wins input #6 wins input #7 wins 114 Keypad Encoders Another common use for encoders is to encode keypads and keyboards Example: Example: Design a 10-to-4 priority encoder 10-tofor encoding a BCD keypad using a 16V8 Solution: Solution: Modify the 8-to-3 priority encoder 8-toABEL file described previously 115 MODULE TITLE bcd_enc '10-to-4 BCD Priority Encoder Using 16V8' DECLARATIONS " Input pins K0..K9 pin; " key inputs (0 - lowest priority, 9 - highest) " Output pins E0..E3 pin istype 'com'; " E3 E2 E1 E0 - encoded BCD output KS pin istype 'com'; " key strobe (high when any key pressed) X = .X.; TRUTH_TABLE ([K9,K8,K7,K6,K5,K4,K3,K2,K1,K0]->[E3,E2,E1,E0,KS]) [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]->[ 0, 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1]->[ 0, 0, 0, 0, 1]; [ 0, 0, 0, 0, 0, 0, 0, 0, 1, X]->[ 0, 0, 0, 1, 1]; [ 0, 0, 0, 0, 0, 0, 0, 1, X, X]->[ 0, 0, 1, 0, 1]; [ 0, 0, 0, 0, 0, 0, 1, X, X, X]->[ 0, 0, 1, 1, 1]; [ 0, 0, 0, 0, 0, 1, X, X, X, X]->[ 0, 1, 0, 0, 1]; [ 0, 0, 0, 0, 1, X, X, X, X, X]->[ 0, 1, 0, 1, 1]; [ 0, 0, 0, 1, X, X, X, X, X, X]->[ 0, 1, 1, 0, 1]; [ 0, 0, 1, X, X, X, X, X, X, X]->[ 0, 1, 1, 1, 1]; [ 0, 1, X, X, X, X, X, X, X, X]->[ 1, 0, 0, 0, 1]; [ 1, X, X, X, X, X, X, X, X, X]->[ 1, 0, 0, 1, 1]; END 116 Clicker Quiz 117 MODULE TITLE diff_pri 'Different Priority Encoder' DECLARATIONS A,B,C,D pin; E0..E1 pin istype 'com'; GS pin istype 'com'; X = .X.; TRUTH_TABLE ([ [ [ [ [ [ END A, 0, 0, 0, 0, 1, B, 0, 0, 0, 1, X, C, 0, 0, 1, X, X, D]->[E1,E0,GS]) 0]->[ 0, 0, 0]; 1]->[ 1, 1, 1]; X]->[ 1, 0, 1]; X]->[ 0, 1, 1]; X]->[ 0, 0, 1]; 118 1. The highest priority input is: A. A B. B C. C D. D E. none of the above 119 2. The lowest priority input is: A. A B. B C. C D. D E. none of the above 120 3. If input A is asserted, the outputs will be: A. E1=0, E0=0, GS=0 B. E1=0, E0=0, GS=1 C. E1=1, E0=1, GS=0 D. E1=1, E0=1, GS=1 E. none of the above 121 4. When inputs B and C are asserted simultaneously (and A is negated) the outputs will be: A. E1=0, E0=0, GS=1 B. E1=0, E0=1, GS=1 C. E1=1, E0=0, GS=1 D. E1=1, E0=1, GS=1 E. none of the above 122 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3-E Combinational Building Blocks: Tri-State Buffers 123 Reading Assignment: 3rd Ed., pp. 385-394; 4th Ed., pp. 418-427 385418Instructional Objectives: To learn more about tri-state buffers and how trito use them To learn how to specify tri-state outputs in triABEL 124 Outline TriTri-State Buffers TriTri-State Buffer Specification in ABEL 125 Tri-State Buffers TriThreeThree-state ("tri-state") devices allow ("trimultiple sources to share a single "party line" (provided only one device "talks" on the line at a time) Basic variations: The buffer may be inverting or non-inverting, and the tri-state enable can either be active low or active high 126 Tri-State Buffers TriThreeThree-state devices are typically designed so that they go into the Hi-Z (high impedance) Histate faster than they come out of the Hi-Z Histate (i.e., tpLZ and tpHZ are both less than tpZL and tpZH) Given this "rule", if one tri-state device is tridisabled and another tri-state device is trienabled simultaneously, then the first device will get off the "party line" before the second one gets on this prevents fighting 127 Party line example 128 Tri-State Buffers TriIn practice it is difficult to ensure that the enable inputs of different tri-state devices trichange "simultaneously" The only safe way to use tri-state devices is trito design control logic that guarantees a dead time on the party line during which no one is driving it 129 Tri-State Buffers TriDefinition: Definition: A bus is a collection of signals with a "common purpose" (e.g., sending the address of an item in memory, sending the data to be written to memory, etc.) Recall that hysteresis improves the noise immunity margin on buses A common application of tri-state buffers is triis to interface I/O (input/output) ports to microprocessormicroprocessor-based systems 130 Tri-State Buffers TriBuses can be bi-directional (i.e., data may be bitransferred in either direction) A bus transceiver contains pairs of tri-state tribuffers connected in opposite directions between each pair of pins, so that data can be transferred in either direction 131 74x245 Bus Transceiver 132 Tri-State Buffers TriIn ABEL, an attribute suffix ".OE" is attached to a signal name on the left-hand side of an leftequation to indicate that the equation applies to the output enable for that signal Example: Example: Create an ABEL file that implements a 4:2 priority encoder with tri-state encoded trioutputs (E1, E0). This design should include an active high output strobe (GS) that is asserted when any input is asserted. (The tritristate buffer will enable the encoder to connect directly to a microprocessor data bus, and only "talk" on the bus when enabled.) enabled.) 133 MODULE prienc42 TITLE '4-to-2 Priority Encoder with Tri-State Enable' DECLARATIONS " Input pins I0..I3 pin; " Input 0 - lowest priority, Input 3 - highest " Output pins E0..E1 pin istype 'com'; " E1 E0 - encoded output GS pin istype 'com'; " strobe output (asserted if any input asserted) EN pin; " tri-state enable control input " Short-hand for don't care X = .X.; TRUTH_TABLE ([I3,I2,I1,I0]->[E1,E0,GS]) [ 0, 0, 0, 0]->[ 0, 0, 0]; [ 0, 0, 0, 1]->[ 0, 0, 1]; [ 0, 0, 1, X]->[ 0, 1, 1]; [ 0, 1, X, X]->[ 1, 0, 1]; [ 1, X, X, X]->[ 1, 1, 1]; EQUATIONS " " " " " no inputs active input 0 wins input 1 wins input 2 wins input 3 wins [E0..E1].OE = EN; END 134 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3-F Combinational Building Blocks: Multiplexers 135 Reading Assignment: 3rd Ed., pp. 398-409; 4th Ed., pp. 432-443 398432Instructional Objectives: To learn what multiplexers are and how they can be used in the design of digital systems To learn how multiplexer functionality can be specified in ABEL 136 Outline Multiplexers Standard MSI Multiplexers De-multiplexers and Buses DeMultiplexers in ABEL 137 Multiplexers Definition: Definition: A multiplexer is a digital switch that uses n select lines to determine which of 2n inputs is connected to its output It is often called a mux for short Each of the input paths may be b bits wide An overall enable signal (EN) is usually provided (if EN negated, all outputs are "0") The equation implemented by an n select line multiplexer is the sum-of-products form sum-ofof a general n-variable function nF(X,Y) = a0XY + a1XY + a2XY + a3XY 138 Multiplexer Truth Table Analogy X Y F(X,Y) 0 0 0 1 1 0 1 1 a0 a1 a2 a3 D0 D1 D2 D3 F F(X,Y) i1 i0 Functional values assigned to each combination X Y 139 Multiplexer Truth Table Analogy X Y F(X,Y) 0 0 0 1 1 0 1 1 0 0 0 1 D0 D1 D2 D3 F F(X,Y) i1 i0 AND function X Y 140 Multiplexer Truth Table Analogy X Y F(X,Y) 0 0 0 1 1 0 1 1 0 1 1 1 D0 D1 D2 D3 F F(X,Y) i1 i0 OR function X Y 141 Multiplexer Truth Table Analogy X Y F(X,Y) 0 0 0 1 1 0 1 1 0 1 1 0 D0 D1 D2 D3 F F(X,Y) i1 i0 XOR function X Y 142 Multiplexer Truth Table Analogy X Y F(X,Y) 0 0 0 1 1 0 1 1 1 0 0 1 D0 D1 D2 D3 F F(X,Y) i1 i0 XNOR function X Y 143 Multiplexer Truth Table Analogy X Y F(X,Y) 0 0 0 1 1 0 1 1 a0 a1 a2 a3 D0 D1 D2 D3 F F(X,Y) i1 i0 Question: How many different functions of N variables are possible? X Y 144 Multiplexer Truth Table Analogy X Y F(X,Y) 0 0 0 1 1 0 1 1 a0 a1 a2 a3 D0 D1 D2 D3 F F(X,Y) i1 i0 Answer: 2 2N X Y 145 Multiplexer Structure 146 MSI Multiplexers The sizes of commercially available MSI multiplexers are limited by the number of pins available in inexpensive IC packages Example: Example: 74x151 8-to-1 (8:1) multiplexer 8-toMSI multiplexers can be "expanded" two different ways: increase width by adding multiplexers in parallel with common select lines increase number of inputs by combining the outputs of multiple multiplexers 147 74x151 148 Example: Given the 74x151 (8-to-1) multiplexer circuit, below, determine which "data" switches should be closed to implement the function F(C,B,A) = CA + C(AB) VCC F(C,B,A) 4 3 2 1 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7 A B C G W Y 6 5 Circle the data input switches that should be closed: D0 D1 D2 D3 D4 D5 D6 D7 149 Example: Given the 74x151 (8-to-1) multiplexer circuit, below, determine which "data" switches should be closed to implement the function F(C,B,A) = CA + C(AB) VCC F(C,B,A) 4 3 2 1 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7 A B C G W Y 6 5 Circle the data input switches that should be closed: D0 D1 D2 D3 D4 D5 D6 D7 F(C,B,A) = CA + C(AB) = CA + C(BA + BA) = CA + CBA + CBA 150 Example: Given the 74x151 (8-to-1) multiplexer circuit, below, determine which "data" switches should be closed to implement the function F(C,B,A) = CA + C(AB) VCC F(C,B,A) 4 3 2 1 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7 A B C G W Y 6 5 C A A 0 1 B 1 0 B 0 1 C 0 1 B Circle the data input switches that should be closed: D0 D1 D2 D3 D4 D5 D6 D7 F(C,B,A) = CA + C(AB) = CA + C(BA + BA) = CA + CBA + CBA 151 Example: Given the 74x151 (8-to-1) multiplexer circuit, below, determine which "data" switches should be closed to implement the function F(C,B,A) = CA + C(AB) VCC F(C,B,A) 4 3 2 1 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7 A B C G W Y 6 5 C A A 0 1 B 1 0 B 0 1 C 0 1 B Circle the data input switches that should be closed: D0 D1 D2 D3 D4 D5 D6 D7 F(C,B,A) = CA + C(AB) = CA + C(BA + BA) = CA + CBA + CBA C,B,A (0,3,4,6) 152 Example: Given the 74x151 (8-to-1) multiplexer circuit, below, determine which "data" switches should be closed to implement the function F(C,B,A) = CA + C(AB) VCC F(C,B,A) 4 3 2 1 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7 A B C G W Y 6 5 C A A 0 1 B 1 0 B 0 1 C 0 1 B Circle the data input switches that should be closed: D0 D1 D2 D3 D4 D5 D6 D7 F(C,B,A) = CA + C(AB) = CA + C(BA + BA) = CA + CBA + CBA C,B,A (0,3,4,6) 153 De-multiplexers and Buses DeGiven that a multiplexer can select one of n sources of data to transmit on a bus, then a de-multiplexer can be used to route the dedata bus to one of m destinations The function of a de-multiplexer is just the deinverse of a multiplexer A binary decoder with an enable input can be used as a de-multiplexer deThe names "decoder" and "de-multiplexer" "deare often used interchangeably 154 Driving/Receiving a Bus A Decoder Used as a De-multiplexer 155 Multiplexers in ABEL Multiplexer functionality can be expressed in ABEL several different ways: using conventional sum-of-products sum-ofexpressions using sets and relations Example: 8-toExample: 8-to-1 X 1 bit multiplexer (74x151) using a 16V8 PLD Example: 4-toExample: 4-to-1 X 8 bit multiplexer using a MACH221 PLD 156 MODULE mux811 TITLE '8-to-1 X 1-bit Multiplexer (74x151)' DECLARATIONS " Data inputs D0..D7 pin 1..8; " Enable EN pin 9; " Select lines S0..S2 pin 11..13; " Outputs Y pin 14; Y_L pin 15; " complemented output EQUATIONS Y = EN & (!S2&!S1&!S0&D0 # !S2&!S1& S0&D1 # !S2& S1&!S0&D2 # !S2& S1& S0&D3 # S2&!S1&!S0&D4 # S2&!S1& S0&D5 # S2& S1&!S0&D6 # S2& S1& S0&D7); Y_L = !Y; END Two ABEL Programs That Implement a 74x151 MODULE mux811 TITLE '8-to-1 X 1-bit Multiplexer (74x151)' DECLARATIONS " Data inputs D0..D7 pin 1..8; " Enable EN pin 9; " Select lines S0..S2 pin 11..13; " Outputs Y pin 14; !Y_L pin 15; " complemented output EQUATIONS Y = EN & (!S2&!S1&!S0&D0 # !S2&!S1& S0&D1 # !S2& S1&!S0&D2 # !S2& S1& S0&D3 # S2&!S1&!S0&D4 # S2&!S1& S0&D5 # S2& S1&!S0&D6 # S2& S1& S0&D7); Y_L = EN & (!S2&!S1&!S0&D0 # !S2&!S1& S0&D1 # !S2& S1&!S0&D2 # !S2& S1& S0&D3 # S2&!S1&!S0&D4 # S2&!S1& S0&D5 # S2& S1&!S0&D6 # S2& S1& S0&D7); END 157 MODULE mux811 TITLE '8-to-1 X 1-bit Multiplexer (74x151)' DECLARATIONS " Data inputs D0..D7 pin 1..8; " Enable EN pin 9; " Select lines S0..S2 pin 11..13; " Outputs Y pin 14; Y_L pin 15; " complemented output EQUATIONS Y = EN & (!S2&!S1&!S0&D0 # !S2&!S1& S0&D1 # !S2& S1&!S0&D2 # !S2& S1& S0&D3 # S2&!S1&!S0&D4 # S2&!S1& S0&D5 # S2& S1&!S0&D6 # S2& S1& S0&D7); Y_L = !Y; END Two ABEL Programs That Implement a 74x151 MODULE mux811 TITLE '8-to-1 X 1-bit Multiplexer (74x151)' DECLARATIONS " Data inputs D0..D7 pin 1..8; " Enable EN pin 9; " Select lines S0..S2 pin 11..13; " Outputs Y pin 14; !Y_L pin 15; " complemented output EQUATIONS Y = EN & (!S2&!S1&!S0&D0 # !S2&!S1& S0&D1 # !S2& S1&!S0&D2 # !S2& S1& S0&D3 # S2&!S1&!S0&D4 # S2&!S1& S0&D5 # S2& S1&!S0&D6 # S2& S1& S0&D7); Y_L = EN & (!S2&!S1&!S0&D0 # !S2&!S1& S0&D1 # !S2& S1&!S0&D2 # !S2& S1& S0&D3 # S2&!S1&!S0&D4 # S2&!S1& S0&D5 # S2& S1&!S0&D6 # S2& S1& S0&D7); END Question: What's the difference? 158 MODULE mux418a TITLE '4-to-1 X 8-bit Multiplexer' DECLARATIONS EN pin; " output enable control line S0..S1 pin; " select inputs A0..A7, B0..B7, C0..C7, D0..D7 pin; " 8-bit input buses Y0..Y7 pin istype `com'; " 8-bit output bus " A B C D Y Sets = [A0..A7]; = [B0..B7]; = [C0..C7]; = [D0..D7]; = [Y0..Y7]; EQUATIONS Y.OE = EN; Y = !S1&!S0&A # !S1&S0&B # S1&!S0&C # S1&S0&D; END 159 MODULE mux418 TITLE '4-to-1 X 8-bit Multiplexer' DECLARATIONS EN pin; " output enable control line S0..S1 pin; " select inputs A0..A7, B0..B7, C0..C7, D0..D7 pin; " 8-bit input buses Y0..Y7 pin; " 8-bit output bus " Sets SEL = [S1..S0]; A = [A0..A7]; B = [B0..B7]; C = [C0..C7]; D = [D0..D7]; Y = [Y0..Y7]; EQUATIONS Y.OE = EN; WHEN (SEL == 0) THEN ELSE WHEN (SEL == 1) ELSE WHEN (SEL == 2) ELSE WHEN (SEL == 3) END Y = A; THEN Y = B; THEN Y = C; THEN Y = D; 160 Clicker Quiz 161 MODULE bigmux TITLE 'Big Multiplexer' DECLARATIONS EN pin; S0..S1 pin; A0..A7, B0..B7, C0..C7, D0..D7 pin; Y0..Y7 pin istype 'com'; A B C D Y = = = = = [A0..A7]; [B0..B7]; [C0..C7]; [D0..D7]; [Y0..Y7]; EQUATIONS Y.OE = EN; Y = !S1&!S0&A # !S1&S0&B # S1&!S0&C # S1&S0&D; END 162 1. The number of equations generated by this program (that would be burned into a PLD that realized this design) is: A. 2 B. 8 C. 9 D. 16 E. none of the above 163 2. When EN=0, S1=1, and S0=1, the outputs [Y0..Y7]: A. will all be Hi-Z B. will all be zero C. will all be one D. will be equal to the inputs [D0..D7] E. none of the above 164 3. When EN=1, S1=1, and S0=1, the outputs [Y0..Y7]: A. will all be Hi-Z B. will all be zero C. will all be one D. will be equal to the inputs [D0..D7] E. none of the above 165 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 3-G Combinational Building Blocks: XOR/XNOR Functions 166 Reading Assignment: 3rd Ed., pp. 410-417; 4th Ed., pp. 447410447452 Instructional Objectives: To learn how to specify XOR/XNOR functions in ABEL Outline: XOR/XNOR functions in ABEL 167 XOR Functions in ABEL Most PLDs have little capability of realizing XOR functions directly an n-input XOR function would thus require 2n-1 product terms to implement (recall the checkerboard K-map) The XOR operator in ABEL is "$" An XNOR function in ABEL can therefore be expressed as "!$" 168 Example MODULE bigxor TITLE '9-input XOR Function' DECLARATIONS A,B,C,D,E,F,G,H,I pin; XOUT pin istype 'com'; EQUATIONS XOUT = A $ B $ C $ D $ E $ F $ G $ H $ I; END Question: How many product terms are needed to implement this design? _______ Question: Will this design, as specified, fit into a 16V8 PLD? ______________________ _____________________________________ 169 Example MODULE bigxor TITLE '9-input XOR Function' DECLARATIONS A,B,C,D,E,F,G,H,I pin; XOUT pin istype 'com'; EQUATIONS XOUT = A $ B $ C $ D $ E $ F $ G $ H $ I; END Question: How many product terms are needed to implement this design? _______ 28 = 256 170 PALCE16V8 Macrocell Allows up to 8 product terms from Module 3-A 171 Example MODULE bigxor TITLE '9-input XOR Function' DECLARATIONS A,B,C,D,E,F,G,H,I pin; XOUT pin istype 'com'; EQUATIONS XOUT = A $ B $ C $ D $ E $ F $ G $ H $ I; END Question: How many product terms are needed to implement this design? _______ 28 = 256 Question: Will this design, as specified, fit NO into a 16V8 PLD? ______________________ _____________________________________ 172 Example MODULE bigxor TITLE '9-input XOR Function' DECLARATIONS A,B,C,D,E,F,G,H,I pin; XOUT pin istype 'com'; EQUATIONS XOUT = A $ B $ C $ D $ E $ F $ G $ H $ I; END Question: How many product terms are needed to implement this design? _______ 28 = 256 Question: Will this design, as specified, fit NO into a 16V8 PLD? ______________________ 16V8 macrocells have a max of 8 P-terms _____________________________________ 173 Example Question: Will this design, as specified by the ABEL source file given, fit into a 16V8? MODULE treexor TITLE 'Tree XOR' DECLARATIONS A,B,C,D,E,F,G,H,I,J,K,L pin; T1..T3 pin istype 'com'; XOUT pin istype 'com'; EQUATIONS T1 = A $ B $ C $ D; T2 = E $ F $ G $ H; T3 = I $ J $ K $ L; XOUT = T1 $ T2 $ T3; END Answer: ____ Reason: _____________ _____________________ _____________________ 174 Example Question: Will this design, as specified by the ABEL source file given, fit into a 16V8? MODULE treexor TITLE 'Tree XOR' DECLARATIONS A,B,C,D,E,F,G,H,I,J,K,L pin; T1..T3 pin istype 'com'; XOUT pin istype 'com'; EQUATIONS T1 = A $ B $ C $ D; T2 = E $ F $ G $ H; T3 = I $ J $ K $ L; XOUT = T1 $ T2 $ T3; END Yes Answer: ____ Reason: _____________ _____________________ _____________________ 175 Example Question: Will this design, as specified by the ABEL source file given, fit into a 16V8? MODULE treexor TITLE 'Tree XOR' DECLARATIONS A,B,C,D,E,F,G,H,I,J,K,L pin; T1..T3 pin istype 'com'; XOUT pin istype 'com'; EQUATIONS T1 = A $ B $ C $ D; T2 = E $ F $ G $ H; T3 = I $ J $ K $ L; XOUT = T1 $ T2 $ T3; END Yes Answer: ____ Reason: Each expression _____________ can be realized using 8 _____________________ (or fewer) P-terms _____________________ 176 Example Question: If a 10 ns 16V8 PLD is used to implement this design, what propagation delay will be observed at the XOUT pin? MODULE treexor TITLE 'Tree XOR' DECLARATIONS A,B,C,D,E,F,G,H,I,J,K,L pin; T1..T3 pin istype 'com'; XOUT pin istype 'com'; EQUATIONS T1 = A $ B $ C $ D; T2 = E $ F $ G $ H; T3 = I $ J $ K $ L; XOUT = T1 $ T2 $ T3; END Answer: _____ Reason: _____________ _____________________ _____________________ 177 Example Question: If a 10 ns 16V8 PLD is used to implement this design, what propagation delay will be observed at the XOUT pin? MODULE treexor TITLE 'Tree XOR' DECLARATIONS A,B,C,D,E,F,G,H,I,J,K,L pin; T1..T3 pin istype 'com'; XOUT pin istype 'com'; EQUATIONS T1 = A $ B $ C $ D; T2 = E $ F $ G $ H; T3 = I $ J $ K $ L; XOUT = T1 $ T2 $ T3; END 20 ns Answer: _____ Reason: _____________ _____________________ _____________________ 178 Example Question: If a 10 ns 16V8 PLD is used to implement this design, what propagation delay will be observed at the XOUT pin? MODULE treexor TITLE 'Tree XOR' DECLARATIONS A,B,C,D,E,F,G,H,I,J,K,L pin; T1..T3 pin istype 'com'; XOUT pin istype 'com'; EQUATIONS T1 = A $ B $ C $ D; T2 = E $ F $ G $ H; T3 = I $ J $ K $ L; XOUT = T1 $ T2 $ T3; END 20 ns Answer: _____ Reason: Two passes _____________ through the PLD are _____________________ are required _____________________ 179 Clicker Quiz 180 MODULE maxxor TITLE 'GAL16V8 13-input XOR Fn' DECLARATIONS I1..I13 pin 1..9, 11..14; XOUT pin 16 istype 'com'; T1..T3 pin 17..19 istype 'com'; EQUATIONS T1 = I1 $ T2 = I5 $ T3 = I9 $ XOUT = T1 END I2 $ I3 $ I6 $ I7 $ I10 $ I11 $ T2 $ T3 I4; I8; $ I12; $ I13; 181 1. The number of GAL16V8 input pins that are unused in this design is: A. 0 B. 1 C. 2 D. 3 E. none of the above 182 2. The number of GAL16V8 macrocells (and their associated I/O pins) that are unused is: A. 0 B. 1 C. 2 D. 3 E. none of the above 183 3. It is not possible to utilize any of the unused GAL16V8 input pins and/or macrocells (and/or their associated I/O pins) to make the XOR function "bigger" because: A. the propagation delay would become excessive B. if an unused I/O pin was declared as an input, there would be no macrocell(s) available that could effectively use it C. if an unused I/O pin was declared as an output, there would be no product terms available for it to effectively use D. no additional pins or macrocells are available E. none of the above 184 ...
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