2-Mod4_CP_2011

2-Mod4_CP_2011 - 2011 Edition by D. G. Meyer Introduction...

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Unformatted text preview: 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4 Introduction to Sequential Circuits 1 Module 4 Desired Outcome: "an ability to analyze, design, and implement sequential circuits and use a hardware description language (e.g., ABEL) to specify them" Part A: Bistable Elements Part B: The Basic Set-Reset (S-R) Latch Set(S Part C: Data (D) Latches and Various Flip-Flops Flip Part D: State Machine Structure & Analysis Part E: State Machine Synthesis Part F: ABEL Sequential Design Features Part G: Clocking Considerations Parts H & I: State Machine Design Examples 2 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-A Bistable Elements 3 Reading Assignment: 3rd Ed., pp. 529-534; 4th Ed. 521-526 529521Instructional Objectives: To learn the definition of a sequential circuit To learn how to analyze a bistable element To learn what constitutes metastable behavior Outline: Introduction Bistable Elements Digital Analysis Analog Analysis Metastable Behavior 4 Introduction Logic circuits are classified into two types: a combinational logic circuit is one whose outputs depend only on its current inputs a sequential logic circuit is one whose outputs depend not only on its current inputs, but also its current state (arrived at by its past sequence of inputs) The state of a sequential circuit is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit's future behavior 5 Introduction In a digital logic circuit, state variables are binary values a circuit with n binary state variables has 2n possible states Since there are a only finite number of states possible, sequential circuits are sometimes called finite state machines The state changes of most sequential circuits occur at times specified by a free-running freeCLOCK signal By convention, a CLOCK signal is active high if state changes occur in response to the clock signal's rising edge (or when it is high) high) 6 Introduction Similarly, a CLOCK signal is active low if state changes occur in response to the clock signal's falling edge (or when it is low) low) The clock period is the time between successive transitions in the same direction The clock frequency (measured in Hertz, or cycles-percycles-per-second) is the reciprocal of the clock period The duty cycle is the percentage of time that the clock signal is at its asserted level Most digital systems use a quartz-crystal quartzoscillator to generate a clock signal 7 Clock Signals 8 Introduction There are two basic types of sequential circuits that account for the majority of practical discrete designs: a feedback sequential circuit uses ordinary gates and feedback loops to create sequential circuit building blocks such as latches and flip-flops flip a clocked synchronous state machine uses latches and flip-flops (in particular, edgeflipedgetriggered "D" flip-flops) to create circuits flipwhose inputs are examined and whose outputs change state in accordance with a controlling clock signal 9 Bistable Elements The "simplest" sequential circuit consists of a pair of inverters forming a feedback loop: This element has no inputs and therefore no way of controlling or changing its state When power is first applied, it randomly comes up in one state or the other and stays there forever ("not very useful") 10 Digital Analysis of Bistable This circuit is called a bistable because, based on (strictly) digital analysis, it has two stable states: if Q is HIGH, then the bottom inverter has a high input and a LOW output, which forces the top inverter's output HIGH if Q is LOW, then the bottom inverter has a LOW input and a HIGH output, which forces Q to go LOW Based on this analysis, a single state variable ("Q") could be used to describe the state of this circuit 11 Analog Analysis of Bistable Given the feedback connection, we know that Vin1 = Vout2 and Vin2 = Vout1 Transfer fns: Vout1 = T(Vin1) Vout2 = T(Vin2) The feedback loop is in equilibrium if the input and output voltages of both inverters are constant DC values consistent with their transfer functions 12 Analog Analysis of Bistable The equilibrium points can be found graphically they are the points at which the two transfer functions meet: the two stable equilibrium points correspond to the two states identified in the "digital" analysis, with Q (Q_L) either "0" (LOW) or "1" (HIGH) the metastable equilibrium point occurs with Vout1 and Vout2 about halfway between a valid logic "1" voltage and a valid logic "0" voltage here, Q and Q_L are not valid logic signals but the loop equations are satisfied 13 Metastable Behavior The metastable point is not truly stable, because random noise will tend to drive a circuit operating at the metastable point toward one of the stable operating points 14 Metastable Behavior Metastable behavior of a bistable can be compared to the behavior of a ball dropped onto a hill: if ball is dropped from overhead, it will probably roll down immediately to one side of the hill or the other if ball lands right at the top, it may sit there a while before random forces start it rolling 15 Metastable Behavior Important: If the "simplest" sequential circuit is susceptible to metastable behavior, you can be sure that all sequential circuits are susceptible (and it is not something that only occurs at power-up) Consider what happens if we try to "kick" the ball from side of the hill to the other: 16 Metastable Behavior Important: If the "simplest" sequential circuit is susceptible to metastable behavior, you can be sure that all sequential circuits are susceptible (and it is not something that only occurs at power-up) Consider what happens if we try to "kick" the ball from side of the hill to the other: "clueless clip art" 17 Metastable Behavior Important: If the "simplest" sequential circuit is susceptible to metastable behavior, you can be sure that all sequential circuits are susceptible (and it is not something that only occurs at power-up) Consider what happens if we try to "kick" the ball from side of the hill to the other: "clueless Vista user" 18 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-B The Set-Reset (S-R) Latch 19 Reading Assignment: 3rd Ed., pp. 534-538; 4th Ed. 526-530 534526Instructional Objectives: To learn the difference between a latch and a flip flop To learn how to write present state - next state equations, equations, construct present state - next state tables, tables, construct state transition diagrams, diagrams, and construct timing charts that describe the operation of a sequential circuit To learn how to analyze an S-R latch S- 20 Outline Latches and Flip-Flops FlipSetSet-Reset (S-R) Latch (SAnalysis Basic Operation Response to 1-1 Input Combination 1 Response to a Glitch/Hazard S-R Latch Propagation Delay S-R Latch Input Pulse Width S-R Latch Variants S'-R' Latch S' S-R Latch with Enable 21 Latches and Flip Flops Latches and flip-flops are the basic building flipblocks of most sequential circuits a flip-flop is a sequential device that flipsamples its inputs and changes its outputs only at times determined by a clocking signal a latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time (independent of a clocking signal) Because the functional behavior of latches and flip flops is quite different, it is important different, to know which type is being used in a design 22 S-R Latch An S-R ("set-reset") latch based on NOR gates can be implemented as follows: It has a "set" (S) input and a "reset" (R) input and two outputs (Q and QN) that are normally complements of each other 23 S-R Latch Asserting S sets (presets) the Q output to "1" Asserting R resets (clears) the Q output to "0" If both S and R are "0", the circuit behaves like the bistable element a feedback loop retains one of two logic states, Q = 0 or Q = 1 24 S-R Latch 25 S-R Latch If both S and R are "1" both outputs go LOW; "1", if both S and R return to "0" simultaneously, the circuit goes to a random next state 26 Exercise Construct a timing chart for the S-R latch Solution: Start by writing next state equations that describe the circuit, and from them construct a present state - next state table Q(t+) = R(t)QN(t) QN(t+) = S(t)Q(t) 27 Exercise PS-NS table: Q(t+) = R(t)QN(t) QN(t+) = S(t)Q(t) Present State Q(t) QN(t) 00 01 10 11 28 Present Inputs: S(t) R(t) 00 01 10 11 11 01 10 00 01 01 00 00 10 00 10 00 00 00 00 00 Next State Exercise From the PS-NS table, construct a state transition diagram (STD) 00 SR Q QN 10 01 11 29 Exercise From the PS-NS table, construct a state transition diagram (STD) 11 00 SR Q QN 10 11 30 01 00 01 10 Exercise From the PS-NS table, construct a state transition diagram (STD) 10,11 11 00 SR Q QN 10 11 31 01 00 01 00, 01 10 Exercise From the PS-NS table, construct a state transition diagram (STD) 10,11 11 00 SR Q QN 01,11 10 00,10 32 01 00 01 00, 01 10 11 Exercise From the PS-NS table, construct a state transition diagram (STD) 10,11 11 00 SR Q QN 01,11 10 00,10 33 01 00 01 00, 01 10 dd 11 Exercise From the STD, construct a timing chart S R Q QN 34 Exercise From the STD, construct a timing chart S R Q QN Initial Conditions 35 Exercise From the STD, construct a timing chart S R Q QN Initial Conditions 36 Exercise From the STD, construct a timing chart S R Q QN Initial Conditions 37 Exercise From the STD, construct a timing chart S R Q QN Initial Conditions 38 Exercise From the STD, construct a timing chart S R Q QN 39 Exercise From the STD, construct a timing chart S R Q QN 40 Exercise From the STD, construct a timing chart S R Q QN 41 Exercise From the STD, construct a timing chart S R Q QN 42 Exercise From the STD, construct a timing chart S R Q QN 43 Exercise From the STD, construct a timing chart S R Q QN 44 Exercise From the STD, construct a timing chart S R Q QN 45 Exercise From the STD, construct a timing chart S R Q QN 46 Exercise From the STD, construct a timing chart S R Q QN 47 Exercise From the STD, construct a timing chart S R Q QN 48 Exercise From the STD, construct a timing chart S R Q QN 49 Exercise From the STD, construct a timing chart S R Q QN 50 Exercise From the STD, construct a timing chart S R Q QN 51 Exercise From the STD, construct a timing chart S R Q QN 52 Exercise From the STD, construct a timing chart S R Q QN 53 Exercise From the STD, construct a timing chart tPLH S R Q QN tPHL 54 Exercise From the STD, construct a timing chart tPLH tPLH S R Q QN tPHL tPHL 55 Exercise From the STD, construct a timing chart tPLH tPLH S R Q QN tPHL tPHL tPLH = 2 x tPHL 56 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 57 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN Initial Conditions 58 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN Initial Conditions 59 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN Initial Conditions 60 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 61 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 62 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 63 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 64 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 65 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 66 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 67 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 68 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 69 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 70 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 71 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 72 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 73 Exercise Investigate the response of an S-R latch to the "1-1" input combination S R Q QN 74 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 75 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN Initial Conditions 76 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN Initial Conditions 77 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN Initial Conditions 78 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN Initial Conditions 79 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 80 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 81 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 82 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 83 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 84 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 85 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 86 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 87 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 88 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 89 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 90 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 91 Exercise Investigate the response of an S-R latch to a glitch or hazard S R Q QN 92 S-R Latch Propagation Delay The propagation delay of a latch is the time it takes for a transition on an input signal to produce a transition on an output signal A given latch may have several different propagation delay specifications, one for each pair of input and output signals Also, the propagation delay may be different depending on whether the output makes a LOW-toLOW-to-HIGH or HIGH-to-LOW transition HIGH-toExample: pLH(S Example: tpLH(SQ) is the rise propagation delay of the Q output in response to the S input being asserted (latch being "set") 93 S-R Latch Input Pulse Width Minimum-pulse-width specifications are usually given for the S and R inputs (the latch may go into the metastable state if a pulse shorter than TPW(min) is applied to S or R 94 S-R Latch An S-R "S-bar, R-bar" latch with active low set and reset inputs can be built using NAND gates 95 S-R Latch with Enable An S-R latch can be modified to be sensitive to its inputs only when an enabling input "C" is asserted The circuit behaves like an S-R latch when C is "1", and retains its state when C is "0" If both S and R are "1" when C changes from "1" to "0", the next state is unpredictable and the output may become metastable 96 Clicker Quiz 97 Q1. For the circuit shown, the following output combination cannot occur at any time: A. B. C. D. E. X=0, Y=0 X=0, Y=1 X=1, Y=0 X=1, Y=1 none of the above A 2 1 3 X 2 1 B 3 Y 98 Q2. If the input combination A=0, B=1 is applied to this circuit, the (steady state) output will be: A. B. C. D. E. X=0, Y=0 X=0, Y=1 X=1, Y=0 X=1, Y=1 unpredictable A 2 1 3 X 2 1 B 3 Y 99 Q3. If the input combination A=1, B=0 is applied to this circuit, the (steady state) output will be: A. B. C. D. E. X=0, Y=0 X=0, Y=1 X=1, Y=0 X=1, Y=1 unpredictable A 2 1 3 X 2 1 B 3 Y 100 Q4. If the input combination A=0, B=0 is applied to this circuit, followed immediately by the input combination A=1, B=1, the (steady state) output will be: A. B. C. D. E. X=0, Y=0 X=0, Y=1 X=1, Y=0 X=1, Y=1 unpredictable A 2 1 3 X 2 1 B 3 Y 101 Q5. If the propagation delay of each gate is 10 ns, the minimum length of time that (valid) input combinations need to be asserted in order to prevent metastable behavior is: A A. 10 ns X B. 20 ns C. 30 ns Y D. 40 ns B E. none of the above 2 3 1 2 3 1 102 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-C Data (D) Latches and Various Flip-Flops 103 Reading Assignment: 3rd Ed., pp. 538-543; 4th Ed. 530-535 538530- Instructional Objectives: To learn about different types of commonly used latches and flip-flops flip Transparent D latch D flip-flop flip T flip-flop flip- Outline: Transparent D Latch D Flip-Flop FlipD Flip-Flop with Enable FlipT flip-flop flip- 104 Transparent D Latch In situations where we simply need to store a "bit" of information, a D latch can be used Note that a D latch is just an S-R latch, with D connected to the S input and D connected to the R input (this eliminates the troublesome "1-1" input combination) 105 Transparent D Latch When the enable input C is asserted, the latch is said to be "open" and the path from the D input to the Q output is "transparent" hence the name transparent latch When the enable input C is negated, the latch "closes" the Q output retains its last value and no longer changes in response to D 106 Transparent D Latch There are four propagation delay parameters that must be considered: tpLH(CQ) and tpHL(CQ) tpLH(DQ) and tpHL(DQ) 107 Transparent D Latch There is a "window" of time around the falling edge of C when the D input must not change the time prior to this edge that the D input must remain stable is the setup time the time after this edge that the D input must remain stable is the hold time 108 Edge-Triggered D Flip-Flop A positive-edge-triggered D flip flop combines a pair of D latches to create a circuit that samples its D input and changes its Q and QN outputs at the rising edge of a controlling CLOCK (CLK) signal the first latch, called the master, opens and follows the input when CLK is 0 the second latch, called the slave, opens and reads the master's output when CLK is 1 this is when the output state change occurs (note that the master latch is closed at this point and thus "immune" to input changes) 109 Edge-Triggered D Flip-Flop A triangle on the D flip-flop's CLK input indicates edge-triggered behavior and is called a dynamic input indicator The characteristic equation of a D flip-flop is Q* = D (i.e., the next state is the current input) D flip-flops are included in the macrocells of most sequential PLDs, and are therefore the "most popular" (and easy) way to realize clocked synchronous state machines The characteristic equation for every other type of flip-flop can easily be synthesized using a D flip-flop 110 Edge-Triggered D Flip-Flop One way an edge-triggered D flip flop can be constructed is illustrated below 111 Edge-Triggered D Flip-Flop A NAND gate implementation of a masterslave edge-triggered flip flop appears below The (active low) PR_L ("preset") input is equivalent to the S input on an S-R latch The (active low) CLR_L ("clear") input is equivalent to the R input on an S-R latch PR_L and CLR_L can be used to asynchronously set or reset the flip flop 112 Edge-Triggered D Flip-Flop For edge-triggered flip-flops, all propagation delays are measured from the rising edge of the CLK signal The "window" during which the D input must remain stable is tsetup prior to the CLK edge and thold after the CLK edge 113 Clicker Quiz 114 Q1. The duty cycle of the clocking signal is: A. 20% B. 33% C. 40% E. none of the above D. 67% 115 Q2. The nominal setup time provided for the D flip-flop is: A. 5 ns B. 10 ns C. 15 ns E. none of the above D. 20 ns 116 Q3. The nominal hold time provided for the D flip-flop is: A. 5 ns B. 10 ns C. 15 ns E. none of the above D. 20 ns 117 Q4. The clock pulse width provided for the D flip-flop is: A. 5 ns B. 10 ns C. 15 ns E. none of the above D. 20 ns 118 Q5. The tPLH(CQ) of the D flip-flop is: A. 5 ns B. 10 ns C. 15 ns E. none of the above D. 20 ns 119 Q6. The tPHL(CQ) of the D flip-flop is: A. 5 ns B. 10 ns C. 15 ns E. none of the above D. 20 ns 120 Edge-Triggered D Flip-Flop D flip flops can also be designed to be negative-edgenegative-edge-triggered An inversion bubble on the CLK input is used to indicate that a flip flop is triggered on the HIGH-to-LOW transition of the CLK signal 121 Exercise: Assume a positive edge-triggered D flip-flop ("X") and a transparent D latch ("Y") are supplied the signals given on the timing chart (next slide). Plot the response of each, noting the initial states. Assume the propagation delays of the flip-flop and latch are negligible relative to the period of "C". 122 Solution: A X Y C 123 D Flip-Flop with Enable A commonly desired function in D flip-flops is to retain the last value stored (rather than load a new one) at the clock edge This is accomplished by adding an enable input, called EN or CE (clock enable), which uses a 2:1 multiplexer to control the value applied to the internal D flip-flop input 124 Edge-Triggered T Flip Flop A positive edge-triggered toggle (T) flip-flop changes to the complement of its former state in response to LOW-to-HIGH transitions on its T input T flip-flops are commonly used in counter circuits and clock frequency dividers The characteristic equation for a basic T flip-flop is Q* = Q T_CLK T_CLK Q 125 Edge-Triggered T Flip Flop A basic T flip-flop can be constructed from a D flip-flop with its QN output tied to its D input T_CLK 126 Edge-Triggered T Flip Flop An enable input can be added to a T flip-flop that will only allow the flip-flop to change state if the enable input (EN) is "1" The characteristic equation for a T flip-flop with enable is Q* = TQ + TQ = TQ a) T EN Q ( T T CLK Q CLK Q 127 Edge-Triggered T Flip Flop A T flip-flop with enable can be constructed using a D flip-flop by implementing the T flip-flop characteristic equation T CLK 128 Exercise: Complete the PS-NS table for an S-R flip-flop and derive its characteristic equation S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 1 0 1 0 1 0 1 S Q Q 0 2 6 1 3 7 S 4 5 R R R Q* = ______________________ 129 Exercise: Complete the PS-NS table for an S-R flip-flop and derive its characteristic equation S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d S Q Q 0 2 6 1 3 7 S 4 5 R R R Q* = ______________________ 130 Exercise: Complete the PS-NS table for an S-R flip-flop and derive its characteristic equation S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d S Q Q 0 S 6 0 1 R 2 0 3 d d 4 1 1 R 1 0 7 5 R Q* = ______________________ 131 Exercise: Complete the PS-NS table for an S-R flip-flop and derive its characteristic equation S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d S Q Q 0 S 6 0 1 R 2 0 3 d d 4 1 1 R 1 0 7 5 R Q* = ______________________ 132 Exercise: Complete the PS-NS table for an S-R flip-flop and derive its characteristic equation S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d S Q Q 0 S 6 0 1 R 2 0 3 d d 4 1 1 R 1 0 7 5 R S + R'Q Q* = ______________________ 133 Exercise: Complete the PS-NS table for a D flip-flop and derive its characteristic equation D 0 0 1 1 Q Q* 0 1 0 1 D Q Q 0 2 1 3 D Q* = ______________________ 134 Exercise: Complete the PS-NS table for a D flip-flop and derive its characteristic equation D 0 0 1 1 Q Q* 0 0 1 0 0 1 1 1 D Q Q 0 2 1 3 D Q* = ______________________ 135 Exercise: Complete the PS-NS table for a D flip-flop and derive its characteristic equation D 0 0 1 1 Q Q* 0 0 1 0 0 1 1 1 D Q Q 0 2 D 0 1 1 1 0 3 Q* = ______________________ 136 Exercise: Complete the PS-NS table for a D flip-flop and derive its characteristic equation D 0 0 1 1 Q Q* 0 0 1 0 0 1 1 1 D Q Q 0 2 D 0 1 1 1 0 3 Q* = ______________________ 137 Exercise: Complete the PS-NS table for a D flip-flop and derive its characteristic equation D 0 0 1 1 Q Q* 0 0 1 0 0 1 1 1 D Q Q 0 2 D 0 1 1 1 0 3 D Q* = ______________________ 138 Exercise: Complete the PS-NS table for a T flip-flop and derive its characteristic equation T 0 0 1 1 Q Q* 0 1 0 1 T Q Q 0 2 1 3 T Q* = ______________________ 139 Exercise: Complete the PS-NS table for a T flip-flop and derive its characteristic equation T 0 0 1 1 Q Q* 0 0 1 1 0 1 1 0 T Q Q 0 2 1 3 T Q* = ______________________ 140 Exercise: Complete the PS-NS table for a T flip-flop and derive its characteristic equation T 0 0 1 1 Q Q* 0 0 1 1 0 1 1 0 T Q Q 0 T 2 0 1 1 0 1 3 Q* = ______________________ 141 Exercise: Complete the PS-NS table for a T flip-flop and derive its characteristic equation T 0 0 1 1 Q Q* 0 0 1 1 0 1 1 0 T Q Q 0 T 2 0 1 1 0 1 3 QT' + Q'T = Q T Q* = ______________________ 142 Clicker Quiz 143 Q1. A "D" latch is called transparent because its output: A. B. C. D. is always equal to its input is equal to its input when the latch is closed is equal to its input when the latch is open changes state as soon as the latch is clocked E. none of the above 144 Q2. Metastable behavior of an edgetriggered D flip-flop can be caused by: A. violating its minimum setup time requirement B. violating its minimum hold time requirement C. violating its minimum clock pulse width requirement D. all of the above E. none of the above 145 Q3. The minimum number of gates needed to implement a positive edge-triggered D flip-flop using only 2-input NAND gates is: A. 8 B. 9 C. 10 D. 11 E. 12 146 Q4. The minimum number of gates needed to implement a negative edge-triggered D flip-flop using only 2-input NAND gates is: A. 8 B. 9 C. 10 D. 11 E. 12 147 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-D Clocked Synchronous State Machine Structure and Analysis 148 Reading Assignment: 3rd Ed., pp. 550-561; 4th Ed. 540-553 550540- Instructional Objectives: To learn about state machine structure To learn the difference between a Mealy and Moore model of a sequential circuit To review the flip-flop characteristic equations flipand learn how they can be used to analyze clocked synchronous state machines Outline: Introduction State Machine Structure Review of Flip-Flop Characteristic Equations FlipState Machine Analysis 149 Reading Assignment: 3rd Ed., pp. 550-561; 4th Ed. 540-553 550540- Instructional Objectives: To learn about state machine structure To learn the difference between a Mealy and Moore model of a sequential circuit To review the flip-flop characteristic equations flipand learn how they can be used to analyze clocked synchronous state machines Outline: Introduction State Machine Structure Review of Flip-Flop Characteristic Equations FlipState Machine Analysis 150 Introduction Before formally analyzing the flip-flops we fliphave just introduced, we will first study the operation of clocked synchronous state machines "State machine" is a generic name given to sequential circuits "Clocked" indicates that the flip flops employ a CLOCK input "Synchronous" means that all the flip-flops in flipthe state machine use the same CLOCK signal 151 State Machine Structure Clocked synchronous state machines consist of three basic blocks: next state logic combinational circuitry that provides the "excitation" necessary to transition to the next state, based on the current state and the present inputs state memory (flip flops) set of N flipflipflops that store the current state of the machine (providing 2N distinct states) output logic combinational circuitry that uses the current state (and possibly current inputs) to determine the outputs generated 152 State Machine Structure In a Moore machine, the outputs are only a function of the current state 153 State Machine Structure In a Mealy machine, the outputs are a function of the current state as well as the current inputs 154 State Machine Structure With appropriate circuit or drawing manipulations, one state machine model can be mapped into another The exact classification of a state machine into one style or another is ultimately not very important What is important is how the structure chosen satisfies your design requirements 155 Characteristic Equations (Review) The characteristic equations of the various flip-flops described previously are: flip S-R: Q* = S + RQ R D: Q* = D T: Q* = Q T We will use these characteristic equations as the basis for analyzing state machines Analysis in this context means writing the next state equations that describe the circuit's behavior 156 State Machine Analysis The analysis of a clocked synchronous state machine has four basic steps: Determine the next state and the output functions based on the circuit diagram Use the next state and output functions to construct a present state - next state / output table (PS-NS / O) (PS- 157 State Machine Analysis The analysis of a clocked synchronous state machine has four basic steps: Draw a state transition diagram (STD) that presents the information tabulated in the present state - next state / output table in graphical form Draw a timing diagram that shows the timing relationship between the input, output, and clocking signals 158 Exercise 1 Analyze the following Mealy state machine: 159 Exercise 1 Analyze the following Mealy state machine: ENQ0 + ENQ0 160 Exercise 1 Analyze the following Mealy state machine: ENQ0 + ENQ0 ENQ1 + EN(Q1Q0) 161 Exercise 1 Analyze the following Mealy state machine: ENQ0 + ENQ0 ENQ0Q1 ENQ1 + EN(Q1Q0) 162 Exercise 1 STEP 1: Write the next state equations for each D flip-flop and the output logic function Q0* = ENQ0 + ENQ0 = EN Q0 Q1* = ENQ1 + EN(Q1 Q0) MAX = ENQ0Q1 163 Exercise 1 STEP 2: Construct a PS-NS / O table PS PI NS Output Q1 Q0 EN Q1* Q0* MAX 164 Exercise 1 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 PI NS Output EN Q1* Q0* MAX 0 0 0 0 1 0 1 0 165 Exercise 1 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 0 1 0 1 PI NS Output EN Q1* Q0* MAX 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 166 Exercise 1 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 0 1 0 1 1 0 1 0 PI NS Output EN Q1* Q0* MAX 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 167 Exercise 1 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 PI NS Output EN Q1* Q0* MAX 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 0 0 1 168 Exercise 1 STEP 3: Construct a Mealy state transition diagram 169 Exercise 1 STEP 3: Construct a Mealy state transition diagram EN MAX Q1 Q0 170 Exercise 1 STEP 3: Construct a Mealy state transition diagram EN MAX Q1 Q0 00 01 11 10 171 Exercise 1 STEP 3: Construct a Mealy state transition diagram EN MAX Q1 Q0 0 0 00 0 0 01 11 0 0 0 0 10 172 Exercise 1 STEP 3: Construct a Mealy state transition diagram EN MAX Q1 Q0 0 0 00 1 1 11 0 0 1 0 0 0 01 1 0 1 0 0 0 173 10 Exercise 1 STEP 4: Draw a timing chart 174 Exercise 1 STEP 4: Draw a timing chart 175 Exercise 1 STEP 4: Draw a timing chart 176 Exercise 1 STEP 4: Draw a timing chart 177 Exercise 1 STEP 4: Draw a timing chart 178 Exercise 2 Analyze the following Moore state machine: 179 Exercise 2 Analyze the following Moore state machine: ENQ0 + ENQ0 180 Exercise 2 Analyze the following Moore state machine: ENQ0 + ENQ0 ENQ1 + EN(Q1Q0) 181 Exercise 2 Analyze the following Moore state machine: ENQ0 + ENQ0 Q0Q1 ENQ1 + EN(Q1Q0) 182 Exercise 2 STEP 1: Write the next state equations for each D flip-flop and the output logic function Q0* = ENQ0 + ENQ0 = EN Q0 Q1* = ENQ1 + EN(Q1 Q0) MAXS = Q0Q1 183 Exercise 2 STEP 2: Construct a PS-NS / O table PS PI NS Output Q1 Q0 EN Q1* Q0* MAXS 184 Exercise 2 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 PI NS Output EN Q1* Q0* MAXS 0 0 0 0 1 0 1 0 185 Exercise 2 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 0 1 0 1 PI NS Output EN Q1* Q0* MAXS 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 186 Exercise 2 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 0 1 0 1 1 0 1 0 PI NS Output EN Q1* Q0* MAXS 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 187 Exercise 2 STEP 2: Construct a PS-NS / O table PS Q1 Q0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 PI NS Output EN Q1* Q0* MAXS 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 0 1 188 Exercise 2 STEP 3: Construct a Moore state transition diagram 189 Exercise 2 STEP 3: Construct a Moore state transition diagram EN Q1 Q0 MAXS 190 Exercise 2 STEP 3: Construct a Moore state transition diagram EN Q1 Q0 MAXS 00 0 01 0 11 1 10 0 191 Exercise 2 STEP 3: Construct a Moore state transition diagram EN Q1 Q0 MAXS 0 00 0 0 01 0 11 1 0 0 10 0 192 Exercise 2 STEP 3: Construct a Moore state transition diagram EN Q1 Q0 MAXS 0 00 0 1 0 01 0 1 1 11 1 0 10 0 0 193 1 Exercise 2 STEP 4: Draw a timing chart 194 Exercise 2 STEP 4: Draw a timing chart 195 Exercise 2 STEP 4: Draw a timing chart 196 Exercise 2 STEP 4: Draw a timing chart 197 Clicker Quiz 198 Q1. The next state equation represented by the following state transition diagram is: A. B. C. D. E. X* = AX + AX X* = AX + AX X* = A + X X* = AX none of the above 199 Q2. If designed for minimum cost, the next state equation for X is: A. B. C. D. E. X* = AY X* = X + Y X* = XY + AX X* = AY + XY none of the above 200 Q3. If designed for minimum cost, the next state equation for Y is: A. B. C. D. E. Y* = AY Y* = A + Y Y* = XY + AX Y* = AY + XY none of the above 201 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-E Clocked Synchronous State Machine Synthesis 202 Reading Assignment: 3rd Ed., pp. 563-576; 4th Ed., pp.553-566 563pp.553Instructional Objectives: To learn how to design clocked synchronous state machines To review the definition of Mealy and Moore models in the context of a comprehensive design example 203 Outline Introduction State Machine Design Procedure State Machine Design Examples 204 Introduction Designing a state table or state diagram is a creative process that is, in many ways, like writing a computer program: You have a fairly good idea of what the input and output signals should be, but perhaps an imprecise description of the desired relationship between them During the design you may have to identify and choose among different ways of doing things sometimes using common sense, sometimes arbitrarily You may have to identify and handle special cases that weren't included in the original description 205 Introduction Creative process... You will probably have to keep track of several ideas in your head during the design process Since the design process is not an algorithm, algorithm, there's no guarantee that you can complete it using a finite number of states or lines of code When you finally run the state machine or program, it will do exactly what you told it to do no more, no less There's no guarantee the thing will work the first time you may have to debug and iterate the entire process 206 State Machine Design State machine design steps Given a word description, construct a state/output table or transition diagram Minimize any "obvious" redundant states in the translated description Choose a set of state variables and assign binary state-variable combinations to the statenamed states Substitute the state-variable combinations stateinto the state/output table (and/or state transition diagram) to create a table that diagram) shows the desired next state-variable statecombination and output for each state/input combination 207 State Machine Design State machine design steps... If you haven't done so already, choose a flip-flop type for the state memory flip Construct an excitation table that shows the excitation values required to obtain the desired next state for each state-input statecombination Derive excitation equations from the excitation table Derive output equations from the transition/output table Draw a logic diagram (or realize the equations directly in a PLD) 208 Example: Derive the excitation table for an S-R flip-flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d Q Q* S 0 0 0 1 1 0 1 1 R 209 Example: Derive the excitation table for an S-R flip-flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d Q Q* S 0 0 0 0 1 1 0 1 1 R d 210 Example: Derive the excitation table for an S-R flip-flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d Q Q* S 0 0 0 0 1 1 1 0 1 1 R d 0 211 Example: Derive the excitation table for an S-R flip-flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d Q Q* S 0 0 0 0 1 1 1 0 0 1 1 R d 0 1 212 Example: Derive the excitation table for an S-R flip-flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q Q* 0 0 1 1 0 0 1 0 0 1 1 1 0 d 1 d Q Q* S 0 0 0 0 1 1 1 0 0 1 1 d R d 0 1 0 213 Example: Derive the excitation table for a T flip-flop T 0 0 1 1 Q Q* 0 0 1 1 0 1 1 0 Q Q* 0 0 0 1 1 0 1 1 T 0 214 Example: Derive the excitation table for a T flip-flop T 0 0 1 1 Q Q* 0 0 1 1 0 1 1 0 Q Q* 0 0 0 1 1 0 1 1 T 0 1 215 Example: Derive the excitation table for a T flip-flop T 0 0 1 1 Q Q* 0 0 1 1 0 1 1 0 Q Q* 0 0 0 1 1 0 1 1 T 0 1 1 216 Example: Derive the excitation table for a T flip-flop T 0 0 1 1 Q Q* 0 0 1 1 0 1 1 0 Q Q* 0 0 0 1 1 0 1 1 T 0 1 1 0 217 State Machine Design The steps for designing (synthesizing) a (synthesizing) clocked synchronous state machine starting from a word description or specification are the "reverse" of the analysis steps described previously Any type of flip-flop (S-R, D, T) may be flip(Schosen for the state memory; this choice, however, will determine how much work you will have to do when it's time to "turn the crank" (i.e., transform the next state equations into a circuit) We will focus on use of edge-triggered D edgeflip-flops for state machine synthesis flip218 Clicker Quiz 219 Q1. Identify which statement concerning state machine models is true: A. B. C. D. Mealy and Moore models that represent equivalent state machines will always have the same number of states Mealy and Moore models that represent equivalent state machines will always have a different number of states any Mealy model can be transformed into an equivalent Moore model, and vice-versa Mealy and Moore models that represent equivalent state machines, when realized, will exhibit the same observable behavior (i.e., if placed in a "black box", their observable behavior would be indistinguishable) none of the above 220 E. Q2. Designing a state machine based on minimum risk means: A. there are no hazards in the clocking signal B. there are no "don't cares" in the output equations C. there are no "don't cares" in the next state equations D. all of the above E. none of the above 221 Q3. An FSM design has 212 states; to reduce the number of flip-flops required by one, you would have to identify and eliminate _____ redundant state(s). A. B. C. D. E. 1 2 44 84 none of the above 222 Q4. Formal state-minimization procedures are seldom used by most digital designers because: A. B. there are situations where increasing the number of states may simplify the design or reduce its cost the designer can do more to simplify a state machine [than using formal state-minimization procedures] during the state-assignment phase of the design by carefully matching state meanings to the requirements of the problem, experienced digital designers can produce state tables with a minimal or near-minimal number of states all of the above none of the above 223 C. D. E. 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-F ABEL Sequential Circuit Design Features 224 Reading Assignment: 3rd Ed., pp. 627-641; 4th Ed., 612-625 627612Instructional Objective: To learn about the various sequential circuit design features of ABEL Outline: State Machines in ABEL Attribute Suffixes Popular Macrocells PLD Timing Parameters 225 State Machines in ABEL There are three basic ways state machines can be specified in ABEL table, as a "clocked" truth table, using the clocked truth table operator :> as a set of next state equations, using the equations, clocked assignment operator := as a state diagram, using a series of GOTO diagram, and/or IF-THEN-ELSE clauses to specify IF-THENthe state transitions Differences in macrocell architecture will determine the complexity of state machine that can be implemented with a given PLD 226 State Machines in ABEL ABEL allows three possible values on the rightright-hand side of an equation using an attribute suffix on the signal name ".Q" the actual flip-flop output pin before .Q" flipany programmable inversion ".FB" a value equal to the value that the .FB" output pin would have if enabled ".PIN" the actual signal at the PLD output .PIN" pin (this signal is floating or may be used as an input if the tri-state driver is not trienabled) 227 Attribute Suffixes in a Complex PLD 228 State Machines in ABEL ABEL allows equations to be written for other functions within a macrocell, again using attribute suffixes on the signal name: ".D" the flip-flop D input .D" flip ".CLK" the flip-flop CLOCK input .CLK" flip ".OE" the pin tri-state buffer output enable .OE" tri ".AP" the flip-flop asynchronous preset .AP" flip(equivalent to the "S" input on an S R latch) ".AR" the flip-flop asynchronous reset .AR" flip(equivalent to the "R" input on an S R latch) 229 Attribute Suffixes in a Complex PLD 230 16V8 Macrocell 231 2011 Edition by D. G. Meyer Flashback to Module 3.... 232 16V8 Macrocell Multiplexers select lines controlled by fusible links 233 16V8 Macrocell allows macrocell to be used for clocked sequential circuits use istype `reg' (instead of istype `com') 234 16V8 Macrocell If tri-state buffer is disabled, the macrocell pin can be used as an input 235 16V8 Macrocell If tri-state buffer is enable, can select combinational or sequential feedback 236 16V8 Macrocell Allows up to 8 product terms 237 16V8 Macrocell Allows use of SOP or POS form of function 238 16V8 Macrocell Allows 4 possibilities for controlling tri-state output buffer 239 16V8 Macrocell 1. a single product term expression leaves only 7 product terms for function in this case Allows 4 possibilities for controlling tri-state output buffer 240 16V8 Macrocell 2. the common OE pin Allows 4 possibilities for controlling tri-state output buffer 241 16V8 Macrocell 3. always ON (Vcc) Allows 4 possibilities for controlling tri-state output buffer 242 16V8 Macrocell 4. always OFF (Gnd) Allows 4 possibilities for controlling tri-state output buffer 243 22V10 Macrocell 244 22V10 Macrocell Same capabilities as 16V8, only have dedicated product term available for tri-state buffer enable plus common AR (async reset) and AP (async preset) 245 26V12 Macrocell 246 26V12 Macrocell Same capabilities as 22V10, only have two clock signals available instead of one (plus mux to select) 247 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-G Sequential Circuit Clocking Considerations 248 Reading Assignment: 3rd Ed., pp.662-669; 4th Ed., pp. 682-689 pp.662682Instructional Objective: To learn about sequential circuit clocking considerations Outline: Timing Diagrams and Specifications Event Clock Generation Circuits Periodic Clock Generation Circuits 249 Timing Diagrams and Specifications For synchronous systems, timing diagrams can be used to show the relationship between the clock and various input, output, and internal signals 250 Timing Diagrams and Specifications For synchronous systems, timing diagrams can be used to show the relationship between the clock and various input, output, and internal signals clock frequency (f) = 1/tclk duty cycle = tH/(tH+tL) time high time low clock period 251 Timing Diagrams and Specifications For synchronous systems, timing diagrams can be used to show the relationship between the clock and various input, output, and internal signals clock frequency (f) = 1/tclk duty cycle = tH/(tH+tL) time high flip-flip CQ prop delay flipCQ time low clock period 252 Timing Diagrams and Specifications For synchronous systems, timing diagrams can be used to show the relationship between the clock and various input, output, and internal signals clock frequency (f) = 1/tclk duty cycle = tH/(tH+tL) time high flip-flip CQ prop delay flipCQ time low clock period comb output prop delay 253 Timing Diagrams and Specifications For synchronous systems, timing diagrams can be used to show the relationship between the clock and various input, output, and internal signals clock frequency (f) = 1/tclk duty cycle = tH/(tH+tL) time high flip-flip CQ prop delay flipCQ time low clock period comb output prop delay flip-flop setup and hold times 254 Event Clock Generation Circuits Some applications of sequential circuits require that they be clocked by an event sensor firing (open drain transistor changing from high impedance to low impedance) contact closure (pushing a button) Problem: Problem: Mechanical switches have contacts that "bounce" (i.e., "make"/"break" multiple "bounce" times before the contacts "settle") Solution: Solution: Design a "bounce-free switch" "bounceswitch" (also referred to as a "bounce-less switch") "bounce255 Event Clock Generation Circuits Illustration: Illustration: S.P.S.T. ("single pole, single throw") N.O. ("normally open") pushbutton 256 Event Clock Generation Circuits Illustration: Illustration: S.P.S.T. ("single pole, single throw") N.O. ("normally open") pushbutton 257 Event Clock Generation Circuits Illustration: Illustration: S.P.S.T. ("single pole, single throw") N.O. ("normally open") pushbutton 258 Event Clock Generation Circuits Illustration: Illustration: S.P.S.T. ("single pole, single throw") N.O. ("normally open") pushbutton 259 Event Clock Generation Circuits Illustration: Illustration: S.P.S.T. ("single pole, single throw") N.O. ("normally open") pushbutton 260 Event Clock Generation Circuits Illustration: Illustration: S.P.S.T. ("single pole, single throw") N.O. ("normally open") pushbutton 261 Event Clock Generation Circuits Illustration: Illustration: S.P.S.T. ("single pole, single throw") N.O. ("normally open") pushbutton 262 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Initial/Default State (S-R latch reset) L N.C. H N.O. S' Q R' QN H L 263 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Pushbutton Pressed (S-R latch set) H N.C. L N.O. S' Q R' QN L H 264 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Pushbutton Bouncing (S-R latch stays in same state) H N.C. H N.O. S' Q R' QN L H 265 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Pushbutton Bouncing (S-R latch set) H N.C. L N.O. S' Q R' QN L H 266 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Pushbutton Bouncing (S-R latch stays in same state) H N.C. H N.O. S' Q R' QN L H 267 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Pushbutton Pressed (S-R latch set) H N.C. L N.O. S' Q R' QN L H 268 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Pushbutton Released (S-R latch reset) L N.C. H N.O. S' Q R' QN H L 269 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Pushbutton Bouncing (S-R latch stays in same state) H N.C. H N.O. S' Q R' QN H L 270 Classic Bounce-free Switch Circuit BounceBounceBounce-free switch implemented using S.P.D.T. ("single pole, double throw") pushbutton with an S R latch Initial/Default State (S-R latch reset) L N.C. H N.O. S' Q R' QN H L 271 Periodic Clock Generation Circuits Many applications of sequential circuits require a periodic clock R-C time constant oscillator circuit crystal oscillator circuit Issues of interest: frequency of operation duty cycle transition time ringing (undershoot / overshoot) stability (long term drift / short term "jitter") driving capability / need for buffers skew (different length paths on PCB) 272 TTL "Ring" Oscillator VCC 1 3 2 7403 R 4 6 5 7403 R 9 8 10 7403 R OUTPUT C Frequency is controlled by the values of R and C (since TTL, R should be in the range of 1-5 K) 273 CMOS "Ring" Oscillator 1 2 3 4 5 6 OUTPUT 74HC04 74HC04 74HC04 C R1 R2 f (2C(0.4Req + 0.7R2))-1 where Req = (R1R2)/(R1+R2) C 274 Classic Crystal Oscillator Circuit 1 2 3 4 OUTPUT 74HC04 74HC04 R1 R2 C1 C2 Crystal For a 1 MHz oscillator, use R1 = 22 M, R2 = 22 K, C1 = 20 pF, and C2 = 10 pF 275 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-H State Machine Design Examples 276 Reading Assignment: 3rd Ed., pp. 580-591; 4th Ed., 566-576 Ed., 580566Instructional Objectives: To review how to design clocked synchronous state machines using D flip-flips flipTo review the definition of Mealy and Moore models in the context of a comprehensive design example 277 Outline Introduction Moore Model Example Mealy Model Example 278 Exercise Design a clocked synchronous state machine that generates the following "light patterns" (using three LEDs) Mode 0: "single dot, left-to-right" 279 Exercise Design a clocked synchronous state machine that generates the following "light patterns" (using three LEDs) Mode 1: "single dot, right-to-left" 280 Exercise Design a clocked synchronous state machine that generates the following "light patterns" (using three LEDs) Mode 2: "building dots, left-to-right" 281 Exercise Design a clocked synchronous state machine that generates the following "light patterns" (using three LEDs) Mode 3: "building dots, right-to-left" 282 Exercise Preliminaries To specify in which of the 4 modes we want the circuit to operate, we will need 2 "mode control" inputs, M1 and M0, where: M0, 0 0 single dot, left-to-right left-to 0 1 single dot, right-to-left right-to 1 0 building dots, left-to-right left-to 1 1 building dots, right-to-left right-to A separate output function needs to be determined for each of the 3 LED outputs: L2, L1, and L0 (from left-to-right) L2, L1, left-to A state will be needed corresponding to the "all LEDs off" condition Try MOORE model first 283 STEP 1: Construct a state transition diagram Moore Model: M1 M0 STATE L2 L1 L0 284 STEP 1: Construct a state transition diagram A 000 00 00 D 001 00 B 100 C 010 00 285 STEP 1: Construct a state transition diagram 01 00 A 000 00 01 D 001 01 00 B 100 00 C 010 01 286 STEP 1: Construct a state transition diagram 01 00 A 000 00,10 01 10 D 001 01 00 B 100 C 010 01 00 10 F 111 10 E 110 287 STEP 1: Construct a state transition diagram 01,11 11 00 A 000 00,10 01 10 H 111 11 11 01 D 001 00 B 100 C 010 01 00 10 F 111 10 G 011 E 110 288 STEP 2: Minimize the number of states 01,11 00 A 000 00,10 01 10,11 X H ??? G 011 11 01 D 001 00 B 100 C 010 01 00 10 F 111 10 E 110 289 11 STEP 3: Assign state variable combinations 01,11 dd 00 000 000 A 111 000 110 011 G H 11 01 011 001 00 D 00,10 B 01 10,11 001 100 10 101 111 E 10 F 010 010 01 C 00 100 110 290 11 STEP 4: Construct a PS-NS/PO Table PS Q2 Q1 Q0 0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q2* Q1* 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 Q0* 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 PO L2 L1 L0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 291 STEP 4: Construct a PS-NS/PO Table... PS Q2 Q1 Q0 1 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Q2* 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 NS Q1* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q0* 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 PO L2 L1 L0 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 292 Exercise STEP 5: Choose flip-flop type flip already have decided to use D flip-flops flipSTEP 6: Construct an excitation table since we are using D flip-flops, our next flipstate equations are the D-input excitation Dequations STEP 7: Derive the excitation equations will require 5-variable K-maps...ugh! 5KSTEP 8: Derive output equations since we are using a Moore model, these will just be 3-variable functions...good! 3293 MODULE lseqA TITLE 'Light Sequencer Moore Model A' DECLARATIONS CLOCK pin; M0, M1 pin; Q2, Q1, Q0 pin istype 'reg'; L2, L1, L0 pin istype 'com'; truth_table ([Q2,Q1,Q0,M1,M0]:>[Q2,Q1,Q0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1]; 1]; 1]; 1]; 0]; 0]; 1]; 0]; 1]; 1]; 0]; 0]; 0]; 0]; 0]; 0]; [ [ [ [ [ [ [ [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; 0]; 0]; 1]; 0]; 0]; 0]; 0]; [ [ [ [ [ [ [ [ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; 0]; 1]; 0]; 0]; 0]; 0]; 0]; truth_table ([Q2,Q1,Q0]->[L2,L1,L0]) [ 0, 0 ,0]->[ 0, 0, 0]; [ 0, 0, 1]->[ 1, 0, 0]; [ 0, 1, 0]->[ 0, 1, 0]; [ 0, 1, 1]->[ 0, 0, 1]; [ 1, 0, 0]->[ 1, 1, 0]; [ 1, 0, 1]->[ 1, 1, 1]; [ 1, 1, 0]->[ 0, 1, 1]; [ 1, 1, 1]->[ 0, 0, 0]; EQUATIONS [Q2..Q0].CLK = CLOCK; END 294 Equations: Q2.D = ( M0 & M1 & !Q0.PIN & Q1.PIN & Q2.PIN # !M0 & M1 & !Q0.PIN & !Q1.PIN & Q2.PIN # M0 & M1 & Q0.PIN & Q1.PIN & !Q2.PIN # !M0 & M1 & Q0.PIN & !Q1.PIN & !Q2.PIN ); = ( CLOCK ); = ( M0 & Q0.PIN & Q1.PIN & !Q2.PIN # !M0 & !M1 & !Q0.PIN & Q1.PIN & !Q2.PIN # !M0 & !M1 & Q0.PIN & !Q1.PIN & !Q2.PIN # M0 & !Q0.PIN & !Q1.PIN & !Q2.PIN ); = ( CLOCK ); = ( # # # # Q0.C L2 = ( = !( # = !( # = ( !M0 & M1 & !Q0.PIN & !Q1.PIN M0 & M1 & !Q0.PIN & Q1.PIN & Q2.PIN !M1 & !Q0.PIN & !Q2.PIN !M0 & M1 & !Q1.PIN & !Q2.PIN !Q0.PIN & !Q1.PIN & !Q2.PIN ); CLOCK ); !Q0.PIN & !Q2.PIN Q1.PIN ); Q0.PIN & Q1.PIN !Q1.PIN & !Q2.PIN ); Q2.C Q1.D Q1.C Q0.D L1 L0 !Q0.PIN & Q1.PIN & Q2.PIN # Q0.PIN & !Q1.PIN & Q2.PIN # Q0.PIN & Q1.PIN & !Q2.PIN ); 295 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 00: Dot L R 01: Dot L R 10: Build L R 11: Build L R Here, let the output function be the state assignment 296 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 000 00: Dot L R 100 010 001 01: Dot L R 10: Build L R 11: Build L R Here, let the output function be the state assignment 297 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 000 00 00 00 010 00 00: Dot L R 100 001 01: Dot L R 10: Build L R 11: Build L R Here, let the output function be the state assignment 298 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 000 01 100 00 00 01 00 010 01 00 00: Dot L R 001 01 01: Dot L R 10: Build L R 11: Build L R Here, let the output function be the state assignment 299 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 10 110 000 10 100 01 111 10 01 00: Dot L R 00,10 00 00 00 01 010 001 01 01: Dot L R 10: Build L R 11: Build L R Here, let the output function be the state assignment 300 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 10 110 111 10,11 000 10 100 01 01,11 11 001 01 01 010 00: Dot L R 01: Dot L R 10: Build L R 11: Build L R 11 011 00,10 00 00 00 Here, let the output function be the state assignment 301 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 10 110 dd 10 100 01 101 111 10,11 000 01,11 11 001 01 01 010 00: Dot L R 01: Dot L R 10: Build L R 11: Build L R 11 011 00,10 00 00 00 Here, let the output function be the state assignment 302 TITLE 'Light Sequencer - Moore Model B' DECLARATIONS CLOCK pin; M0, M1 pin; Q2, Q1, Q0 pin istype 'reg'; "(serve as L2, L1, L0) truth_table ([Q2,Q1,Q0,M1,M0]:>[Q2,Q1,Q0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0]; 1]; 0]; 1]; 0]; 0]; 0]; 1]; 1]; 0]; 0]; 0]; 0]; 0]; 0]; 1]; [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; EQUATIONS [Q2..Q0].CLK = CLOCK; END 303 Q2.D Q2.C Q1.D = ( !M0 & M1 & !Q0.PIN & Q2.PIN # M0 & M1 & Q0.PIN & Q1.PIN & !Q2.PIN # M0 & !M1 & !Q0.PIN & Q1.PIN & !Q2.PIN # !M0 & !Q0.PIN & !Q1.PIN & !Q2.PIN ); = ( CLOCK ); = ( !M0 & Q0.PIN # !M1 & Q1.PIN # M0 & Q2.PIN # !Q0.PIN & !Q2.PIN ); = ( CLOCK ); = ( M0 & M1 & Q0.PIN & !Q2.PIN # !M0 & !M1 & !Q0.PIN & Q1.PIN & !Q2.PIN # M0 & !Q0.PIN & !Q1.PIN & !Q2.PIN ); = ( CLOCK ); Q1.C Q0.D Q0.C Note: Here the output functions are merely the state variables, i.e., L2=Q2, L1=Q1, L0=Q0 304 Conclusions We have seen that choosing the state assignment can make a significant difference in the amount of work we have to do The only formal way to find the best assignment is to try all the assignments that's too much work (even for students)! students)! To do this well, need experience as well as follow some practical guidelines (see text) Note we have a choice concerning how to handle unused states: minimal risk minimal cost 305 Exercise Now try MEALY model implementation, and compare with MOORE model done previously Inputs and outputs (review) To specify which of the 4 modes we want the circuit to operate, we will need 2 "mode control" inputs, M1 and M0, where: M0, 0 0 single dot, left-to-right left-to 0 1 single dot, right-to-left right-to 1 0 building dots, left-to-right left-to 1 1 building dots, right-to-left right-to A separate output function needs to be determined for each of the 3 LED outputs: L2, L1, and L0 (from left-to-right) L2, L1, left-to306 STEP 1: Construct a state transition diagram Mealy Model: M1 M0 L2 L1 L0 STATE NAME 307 STEP 1: Construct a state transition diagram A D B C 308 STEP 1: Construct a state transition diagram A 00 001 00 000 D 00 010 B 00 100 C 309 STEP 1: Construct a state transition diagram 01 000 A 00 001 00 000 01 100 D 01 001 00 010 B 00 100 C 01 010 310 STEP 1: Construct a state transition diagram 01 000 00 , 10 001 111 A 00 000 , 10 000 01 100 01 001 D 00 , 10 010 110 B 00 , 10 100 100 C 01 010 311 STEP 1: Construct a state transition diagram 01 , 11 000 000 00 , 10 001 111 A 00 000 , 10 000 01 , 11 100 111 D 01 , 11 001 001 00 , 10 010 110 B 00 , 10 100 100 C 01 , 11 010 011 312 STEP 2: Minimize the number of states STEP 3: Assign state variable combinations d1 000 00 , 10 001 111 00 d0 000 01 , 11 100 111 01 d0 100 10 01 , 11 010 011 11 d1 001 00 , 10 010 110 313 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 1 1 0 1 1 1 PO L2 L1 L0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 314 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 PO L2 L1 L0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 1 1 0 1 1 315 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 PO L2 L1 L0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 1 316 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 PO L2 L1 L0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 1 1 0 1 1 317 Exercise STEP 5: Choose flip-flop type flip already have decided to use D flip-flops flipSTEP 6: Construct an excitation table since we are using D flip-flops, our next flipstate equations are the D-input excitation Dequations STEP 7: Derive the excitation equations these are 4-variable functions...OK 4STEP 8: Derive output equations since we are using a Mealy model, these will also be 4-variable functions...OK 4318 MODULE lseq2A TITLE 'Light Sequencer - Mealy Model A' DECLARATIONS CLOCK pin; M0, M1 pin; Q1, Q0 pin istype 'reg'; L2, L1, L0 pin istype 'com'; truth_table ([Q1,Q0,M1,M0]:>[Q1,Q0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1]; 1]; 1]; 1]; 0]; 0]; 0]; 0]; 1]; 1]; 1]; 1]; 0]; 0]; 0]; 0]; truth_table ([Q1,Q0,M1,M0]->[L2,L1,L0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0]; 0]; 0]; 0]; 0]; 0]; 0]; 1]; 0]; 0]; 0]; 1]; 1]; 1]; 1]; 1]; EQUATIONS [Q1..Q0].CLK = CLOCK; END 319 Q1.D Q1.C Q0.D Q0.C L2 = ( !M0 & Q0.PIN & Q1.PIN # M0 & !Q0.PIN & Q1.PIN # M0 & Q0.PIN & !Q1.PIN # !M0 & !Q0.PIN & !Q1.PIN ); = ( CLOCK ); = ( = ( Q0.PIN ); CLOCK ); = ( !M0 & M1 & Q1.PIN # Q0.PIN & !Q1.PIN ); = ( !M0 & M1 & Q1.PIN # !Q0.PIN & Q1.PIN # M0 & M1 & Q0.PIN & !Q1.PIN ); = ( M0 & M1 & Q0.PIN # M0 & M1 & Q1.PIN # Q0.PIN & Q1.PIN ); 320 L1 L0 Revisit Steps 2 & 3: Did we pick the "best" state/output assignments possible? 00 001 00 , 01 100 , 1d 111 dd 000 11 01 d0 100 , 0d 010 , 10 110 d1 001 , 11 011 10 321 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 0 1 0 1 0 1 L2 0 0 0 0 PO L1 0 0 0 0 L0 0 0 0 0 0 1 1 0 1 1 322 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 L2 0 0 0 0 1 0 1 0 PO L1 0 0 0 0 0 0 0 0 L0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 323 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 L2 0 0 0 0 1 0 1 0 0 0 1 0 PO L1 0 0 0 0 0 0 0 0 1 1 1 1 L0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 1 1 324 STEP 4: Construct a PS-NS/PO Table PS Q1 Q0 0 0 PI M1 M0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 NS Q1* Q0* 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 L2 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 1 PO L1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 L0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 325 MODULE lseq2B TITLE 'Light Sequencer - Mealy Model B' DECLARATIONS CLOCK pin; M0, M1 pin; Q1, Q0 pin istype 'reg'; L2, L1, L0 pin istype 'com'; truth_table ([Q1,Q0,M1,M0]:>[Q1,Q0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1]; 1]; 1]; 1]; 0]; 0]; 0]; 0]; 1]; 1]; 1]; 1]; 0]; 0]; 0]; 0]; truth_table ([Q1,Q0,M1,M0]->[L2,L1,L0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0]; 0]; 0]; 0]; 0]; 1]; 0]; 1]; 0]; 0]; 0]; 1]; 1]; 0]; 1]; 1]; EQUATIONS [Q1..Q0].CLK = CLOCK; END 326 Q1.D Q1.C Q0.D Q0.C L2 = ( Q0.PIN & Q1.PIN # !Q0.PIN & !Q1.PIN ); = ( CLOCK ); = ( = ( Q0.PIN ); CLOCK ); = ( !M0 & M1 & Q1.PIN # M0 & Q0.PIN & Q1.PIN # !M0 & Q0.PIN & !Q1.PIN ); = !( # !M1 & Q0.PIN !Q1.PIN ); L1 L0 = ( M0 & M1 & Q1.PIN # !M0 & Q0.PIN & Q1.PIN # M0 & Q0.PIN & !Q1.PIN ); 327 Conclusions We have seen that the choice of model (Mealy vs. Moore) can have a significant impact on the complexity of the realization In the previous exercise, we saw the importance of making a "good" state assignment; we also saw that cursory state minimization can also sometimes be useful There is no substitute for practice in designing synchronous state machines much of engineering is "applied intuition", "applied intuition", and this is a good example of it! 328 Clicker Quiz 329 1 000 0 0 001 1 010 0 1 011 0 1 1 111 0 110 1 0 101 1 0 100 1 0 330 Module CQ Title `Program (A)' DECLARATIONS CLOCK, M pin; Q0..Q2 pin istype `reg'; EQUATIONS Q0 := !Q0; Q1 := !Q1 $ (!M&!Q0 # M&Q0); Q2 := !Q2 $ (!M&!Q1&!Q0 # M&Q1&Q0); [Q2..Q0].CLK = CLOCK; END Module CQ Title `Program (B)' DECLARATIONS CLOCK, M pin; Q0..Q2 pin istype `reg'; EQUATIONS Q0 := !Q0; Q1 := Q1 $ (!M&Q0 # M&!Q0); Q2 := Q2 $ (!M&Q1&Q0 # M&!Q1&!Q0); [Q2..Q0].CLK = CLOCK; END Module CQ Title `Program (C)' DECLARATIONS CLOCK, M pin; Q0..Q2 pin istype `reg'; EQUATIONS Q0 := !Q0; Q1 := Q1 $ (!M&!Q0 # M&Q0); Q2 := Q2 $ (!M&!Q1&!Q0 # M&Q1&Q0); [Q2..Q0].CLK = CLOCK; END Module CQ Title `Program (D)' DECLARATIONS CLOCK, M pin; Q0..Q2 pin istype `reg'; EQUATIONS [Q2..Q0] := [Q2..Q0] + 1 [Q2..Q0].CLK = CLOCK; END (E) None of the above 331 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 4-I More State Machine Design Examples 332 Reading Assignment: 3rd Ed., pp. 627-641; 4th Ed., pp. 612-625 627612Instructional Objective: To learn how to specify state machine behavior in ABEL Outline: Light Sequencer Revisited Character Sequence Display Digital Combination Lock 333 Light Sequencer Revisited The "light sequencer" covered previously can be specified in ABEL several different ways, including: as a Moore model implemented using the clocked truth table operator as a Moore model implemented using state diagram notation as a Mealy model implemented using the clocked truth table operator as a Mealy model implemented using state diagram notation 334 Review of "Improved" Moore Model State Transition Diagram 10 110 dd 10 100 01 101 111 10,11 000 01,11 11 001 01 01 010 00: Dot L R 01: Dot L R 10: Build L R 11: Build L R 335 11 011 00,10 00 00 00 MODULE moorels TITLE 'Improved Moore Model of Light Sequencer' DECLARATIONS M0, M1 pin; CLOCK pin; Q2, Q1, Q0 pin istype 'reg'; QALL = [Q2,Q1,Q0]; truth_table ([Q2,Q1,Q0,M1,M0]:>[Q2,Q1,Q0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0]; 1]; 0]; 1]; 0]; 0]; 0]; 1]; 1]; 0]; 0]; 0]; 0]; 0]; 0]; 1]; [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ EQUATIONS QALL.CLK = CLOCK; END 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 0]; 336 Q2.D = # # # # # # (!M1 & Q0.PIN M0 & !Q1.PIN Q0.PIN & !Q1.PIN !M1 & Q2.PIN Q0.PIN & Q2.PIN M0 & M1 & !Q0.PIN !M0 & Q1.PIN & !Q2.PIN); P16V8R +---------\ /---------+ | \ / | | ----| | 1 20 | | | | 2 19 | | | | 3 18 | | | | 4 17 | | | | 5 16 | | | | 6 15 | | | | 7 14 | | | | 8 13 | | | | 9 12 | | | | 10 11 | | | | | `---------------------------' CLOCK M0 M1 Vcc Q2.C = (CLOCK); Q1.D = # # # (!M0 & Q0.PIN !M1 & Q1.PIN M0 & Q2.PIN !Q0.PIN & !Q2.PIN); Q1.C = (CLOCK); Q0.D = # # # # (Q2.PIN !M0 & M1 !M1 & Q0.PIN !M0 & !Q1.PIN M0 & !Q0.PIN & Q1.PIN); !Q0 !Q1 !Q2 GND Q0.C = (CLOCK); 337 MODULE sdls TITLE 'Light Sequencer Using State Diagram' M1, M0 pin; CLOCK pin; Q2, Q1, Q0 pin istype 'reg'; QALL A0 A1 A2 A3 A4 A5 A6 A7 = = = = = = = = = [Q2,Q1,Q0]; [ 0, 0, 0]; [ 0, 0, 1]; [ 0, 1, 0]; [ 0, 1, 1]; [ 1, 0, 0]; [ 1, 0, 1]; [ 1, 1, 0]; [ 1, 1, 1]; state A3: if else if else if else if if else if else if else if (M1==0)&(M0==0) (M1==0)&(M0==1) (M1==1)&(M0==0) (M1==1)&(M0==1) (M1==0)&(M0==0) (M1==0)&(M0==1) (M1==1)&(M0==0) (M1==1)&(M0==1) then then then then then then then then A0 A0 A0 A7; A2 A0 A6 A0; state A4: state A5: goto A0; state A6: if else if else if else if if else if else if else if (M1==0)&(M0==0) (M1==0)&(M0==1) (M1==1)&(M0==0) (M1==1)&(M0==1) (M1==0)&(M0==0) (M1==0)&(M0==1) (M1==1)&(M0==0) (M1==1)&(M0==1) then then then then then then then then A0 A0 A7 A0; A0 A0 A0 A0; STATE_DIAGRAM QALL state A0: if else if else if else if if else if else if else if if else if else if else if (M1==0)&(M0==0) (M1==0)&(M0==1) (M1==1)&(M0==0) (M1==1)&(M0==1) (M1==0)&(M0==0) (M1==0)&(M0==1) (M1==1)&(M0==0) (M1==1)&(M0==1) (M1==0)&(M0==0) (M1==0)&(M0==1) (M1==1)&(M0==0) (M1==1)&(M0==1) then then then then then then then then then then then then A4 A1 A4 A1; A0 A2 A0 A3; A1 A4 A0 A0; state A7: state A1: EQUATIONS QALL.CLK = CLOCK; END state A2: 338 Q2.D = # # # # # # (!Q2.Q & !M1 !Q0.Q & !M1 !Q2.Q & M0 Q1.Q & M0 !Q0.Q & !M0 Q0.Q & M1 & M0 Q2.Q & !Q1.Q & !M0); CLOCK M1 P16V8R +---------\ /---------+ | \ / | | ----| | 1 20 | | | | 2 19 | | | | 3 18 | | | | 4 17 | | | | 5 16 | | | | 6 15 | | | | 7 14 | | | | 8 13 | | | | 9 12 | | | | 10 11 | | | | | `---------------------------' Vcc Q2.C = (CLOCK); Q1.D = # # # (Q2.Q !Q1.Q !Q2.Q !Q0.Q & & & & Q0.Q !M1 M0 !M0); M0 Q1.C = (CLOCK); Q0.D = # # # # # # (!Q2.Q & !Q0.Q !Q2.Q & !M1 !Q0.Q & !M1 !Q2.Q & M0 Q1.Q & !M0 !Q1.Q & Q0.Q & M0 Q2.Q & M1 & !M0); !Q0 !Q1 !Q2 GND Q0.C = (CLOCK); 339 Review of "Improved" Mealy Model State Transition Diagram 00: Dot L R 00 00 001 dd 000 01: Dot L R 10: Build L R 11: Build L R 01 d0 100 , 01 100 , 1d 111 11 , 0d 010 , 10 110 d1 001 , 11 011 10 340 MODULE mealyls TITLE 'Mealy Implementation of Light Sequencer' DECLARATIONS M0, M1 pin; Q1, Q0 pin istype 'reg'; CLOCK pin; L2, L1, L0 pin istype 'com'; truth_table ([Q1,Q0,M1,M0]:>[Q1,Q0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0]:>[ 1]:>[ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1]; 1]; 1]; 1]; 0]; 0]; 0]; 0]; 1]; 1]; 1]; 1]; 0]; 0]; 0]; 0]; truth_table ([Q1,Q0,M1,M0]->[L2,L1,L0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ EQUATIONS Q1.CLK = CLOCK; Q0.CLK = CLOCK; END 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0]; 0]; 0]; 0]; 0]; 1]; 0]; 1]; 0]; 0]; 0]; 1]; 1]; 0]; 1]; 1]; 341 Q1.D = (Q0.PIN & Q1.PIN # !Q0.PIN & !Q1.PIN); Q1.C = (CLOCK); CLOCK P16V8R +---------\ /---------+ | \ / | | ----| | 1 20 | | | | 2 19 | | | | 3 18 | | | | 4 17 | | | | 5 16 | | | | 6 15 | | | | 7 14 | | | | 8 13 | | | | 9 12 | | | | 10 11 | | | | | `---------------------------' Vcc Q0.D = (Q0.PIN); Q0.C = (CLOCK); L2 = (!M0 & M1 & Q1.PIN # M0 & Q0.PIN & Q1.PIN # !M0 & Q0.PIN & !Q1.PIN); L1 = (M1 & Q1.PIN # !Q0.PIN & Q1.PIN); L0 = (M0 & M1 & Q1.PIN # !M0 & Q0.PIN & Q1.PIN # M0 & Q0.PIN & !Q1.PIN); M0 M1 !L0 !L1 !L2 !Q0 !Q1 GND 342 MODULE sdmealy TITLE 'Mealy Model Implemented with State Diagram' DECLARATIONS M0, M1 pin; CLOCK pin; Q1, Q0 pin istype 'reg'; L2, L1, L0 pin istype 'com'; " State definitions QALL = [Q1,Q0]; A0 = [ 0, 0]; A1 = [ 0, 1]; A2 = [ 1, 0]; A3 = [ 1, 1]; state_diagram QALL state state state state A0: A1: A2: A3: goto goto goto goto A1; A2; A3; A0; EQUATIONS QALL.CLK = CLOCK; END truth_table ([Q1,Q0,M1,M0]->[L2,L1,L0]) [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0]; 0]; 0]; 0]; 0]; 1]; 0]; 1]; 0]; 0]; 0]; 1]; 1]; 0]; 1]; 1]; 343 Updating: Fit Design Starting: 'C:\VANTIS\CPLD11\fit.exe l27-4.tt2 -dev P16V8 -str -err automake.err' FIT Generic Device Fitter DesignDirect-CPLD 2.30 Copyright 1999 Vantis. All Rights Reserved. Input file: 'l27-4.tt2' Device 'P16V8' Note 4161: Using device architecture type P16V8R. Note 4079: Signal Q1 cannot be assigned (to pin 14) because too many feedbacks are used on 'Q1' pin 14. Note 4079: Signal Q0 cannot be assigned (to pin 14) because too many feedbacks are used on 'Q0' pin 14. Design does NOT fit Done: failed with exit code: 0001. L1 = (Q1 & !Q0 # Q1 & M1); Q1 := (Q1.FB & !Q0.FB # !Q1.FB & Q0.FB); Q1.C = (CLOCK); Q0 := (!Q0.FB); Q0.C = (CLOCK); L2 = (!Q1 & Q0 & !M0 # Q1 & M1 & !M0 # Q1 & Q0 & M0); Ooops... L0 = (Q1 & Q0 & !M0 # !Q1 & Q0 & M0 # Q1 & M1 & M0); 344 Bug Work-Around... truth_table ([Q1.q,Q0.q,M1,M0]->[L2,L1,L0]) MODULE BugFix TITLE 'sdmealy Bug Fix' DECLARATIONS M0, M1 pin; CLOCK pin; Q1, Q0 pin istype 'reg'; L2, L1, L0 pin istype 'com'; " State definitions QALL = [Q1,Q0]; A0 = [ 0, 0]; A1 = [ 0, 1]; A2 = [ 1, 0]; A3 = [ 1, 1]; state_diagram QALL state state state state A0: A1: A2: A3: goto goto goto goto A1; A2; A3; A0; [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ EQUATIONS QALL.CLK = CLOCK; END 345 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0]; 0]; 0]; 0]; 0]; 1]; 0]; 1]; 0]; 0]; 0]; 1]; 1]; 0]; 1]; 1]; Clicker Quiz 346 MODULE MCLEDS TITLE 'Multi-Color LED Light Machine for 16V8' DECLARATIONS M pin; " mode control input Q0..Q1 pin istype 'reg'; " state variables R,G,Y,B pin istype 'com'; " LEDs (red/green/yellow/blue) !NO,!NC pin; " N.O. and N.C. SPDT pushbutton inputs " (active low contact closures to GND) BSQ pin istype 'com'; " bounceless switch output CLOCK pin; " clock input (externally wired to BSQ output pin) TRUTH_TABLE([Q1,Q0, [ 0, 0, [ 0, 0, [ 0, 1, [ 0, 1, [ 1, 0, [ 1, 0, [ 1, 1, [ 1, 1, TRUTH_TABLE([Q1,Q0, [ 0, 0, [ 0, 0, [ 0, 1, [ 0, 1, [ 1, 0, [ 1, 0, [ 1, 1, [ 1, 1, M]:>[Q1,Q0]) 0]:>[ 1, 0]; 1]:>[ 1, 1]; 0]:>[ 1, 1]; 1]:>[ 0, 0]; 0]:>[ 0, 1]; 1]:>[ 0, 1]; 0]:>[ 0, 0]; 1]:>[ 1, 0]; M]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ 0]->[ 1]->[ R, 1, 1, 0, 1, 0, 1, 0, 1, G, 0, 0, 0, 1, 1, 1, 0, 1, Y, 0, 0, 1, 1, 0, 1, 0, 0, B]) 0]; 0]; 0]; 1]; 0]; 0]; 1]; 0]; EQUATIONS BSQ = NO # !NC & BSQ; [Q1..Q0].CLK = CLOCK; END 347 Q1. When M=0, the (repeating) colored LED sequence produced will be: A. B. C. D. E. RGYB... RYGB... BYGR... BGYR... none of the above 348 Q2. When M=1, the (repeating) colored LED sequence produced will be: A. B. C. D. E. RRGYBRGYRG... RRGRGYRGYB... RGYBRGYRGR... RRGYRGRGYB... none of the above 349 Digital Combination Lock Design a digital combination lock unlocks when a fixed combination (binary sequence) is entered: 101110 has three inputs: X combination data R relock / reset RESET asynchronous reset has three output indicators: LOCKED UNLOCKED ALARM 350 Digital Combination Lock Implement using Moore model will need an initial "locked" state will need six states to accept digits of combination (the last is "unlocked") will need an "alarm" state total number of states is eight; therefore, can implement with three state variables New concepts "sequence recognizer" accepting sequence final state (in accepting sequence) trap state 351 RX Q2 Q1 Q0 ------------L U A Combination: 101110 000 100 LOCKED 001 000 010 000 011 000 111 001 ALARM 110 010 UNLOCKED 101 000 100 000 352 RX Q2 Q1 Q0 ------------L U A Combination: 101110 000 100 01 001 00 000 010 000 01 011 000 01 111 001 110 010 101 00 000 100 01 000 353 RX Q2 Q1 Q0 ------------L U A Combination: 101110 1d 000 100 01 001 00 000 1d 010 000 01 1d 011 000 01 111 001 0d 110 010 1d 101 00 000 1d 100 01 000 1d 354 1d RX Q2 Q1 Q0 ------------L U A Combination: 101110 1d 000 100 00 01 001 00 000 01 1d 010 000 00 01 111 001 0d 110 010 1d 101 00 000 1d 01 1d 011 000 00 00 100 01 000 1d 355 1d 01 dd MODULE dcl TITLE 'Digital Combination Lock' X pin; "combination data input" R pin; "relock input" RESET pin; "asynchronous reset" CLOCK pin; Q2, Q1, Q0 pin istype 'reg'; LOCKED pin istype 'com'; "LOCKED indicator" UNLOCKED pin istype 'com'; "UNLOCKED indicator" ALARM pin istype 'com'; "ALARM indicator" QALL A0 A1 A2 A3 A4 A5 A6 A7 = = = = = = = = = [Q2,Q1,Q0]; [ 0, 0, 0]; [ 0, 0, 1]; [ 0, 1, 0]; [ 0, 1, 1]; [ 1, 0, 0]; [ 1, 0, 1]; [ 1, 1, 0]; [ 1, 1, 1]; state A3: if (R==1) then A0 else if (R==0)&(X==0) then A7 else if (R==0)&(X==1) then A4; if (R==1) then A0 else if (R==0)&(X==0) then A7 else if (R==0)&(X==1) then A5; if (R==1) then A0 else if (R==0)&(X==0) then A6 else if (R==0)&(X==1) then A7; if (R==1) then A0 (R==0) then A6; state A4: state A5: state A6: else if state A7: goto A7; EQUATIONS QALL.CLK = CLOCK; QALL.AR = RESET; LOCKED = !Q2&!Q1&!Q0; UNLOCKED = Q2&Q1&!Q0; ALARM = Q2&Q1&Q0; END STATE_DIAGRAM QALL state A0: if (R==1) then A0 else if (R==0)&(X==0) then A7 else if (R==0)&(X==1) then A1; if (R==1) then A0 else if (R==0)&(X==0) then A2 else if (R==0)&(X==1) then A7; if (R==1) then A0 else if (R==0)&(X==0) then A7 else if (R==0)&(X==1) then A3; state A1: state A2: 356 Q2.AR = (RESET); Q2.D = # # # # # (Q2.Q & Q1.Q & Q0.Q Q1.Q & Q0.Q & !R Q2.Q & !Q1.Q & !Q0.Q & !R !Q2.Q & Q0.Q & !R & X Q2.Q & !Q1.Q & !R & !X !Q2.Q & !Q0.Q & !R & !X); CLOCK Q2.C = (CLOCK); R Q1.AR = (RESET); X Q1.D = # # # # (Q2.Q !Q2.Q !Q1.Q !Q2.Q !Q2.Q & & & & & Q1.Q & Q0.Q !R & !X !R & !X !Q1.Q & Q0.Q & !R Q1.Q & !Q0.Q & !R); RESET P22V10 +---------\ /---------+ | \ / | | ----| | 1 24 | | | | 2 23 | | | | 3 22 | | | | 4 21 | | | | 5 20 | | | | 6 19 | | | | 7 18 | | | | 8 17 | | | | 9 16 | | | | 10 15 | | | | 11 14 | | | | 12 13 | | | | | `---------------------------' Vcc Q0 Q2 UNLOCKED Q1.C = (CLOCK); Q0.AR = (RESET); Q0.D = # # # # (Q2.Q !Q2.Q !Q1.Q !Q2.Q !Q2.Q & & & & & Q1.Q & Q0.Q !Q0.Q & !R !Q0.Q & !R !Q1.Q & !R & X Q1.Q & !R & !X); LOCKED ALARM Q1 Q0.C = (CLOCK); GND LOCKED = (!Q2.Q & !Q1.Q & !Q0.Q); UNLOCKED = (Q2.Q & Q1.Q & !Q0.Q); ALARM = (Q2.Q & Q1.Q & Q0.Q); 357 ...
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This note was uploaded on 02/05/2012 for the course ECE 270 taught by Professor Staff during the Spring '08 term at Purdue.

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