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2-Mod4_LS_2011

# 2-Mod4_LS_2011 - ECE 270 Introduction to Digital System...

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ECE 270 Introduction to Digital System Design © 2011 by D. G. Meyer 1 Lecture Summary – Module 4-A Bistable Elements Reference: Text (4 th Ed.), pp. 521-526; (3 rd Ed.), pp. 529-534 overview o combinational vs. sequential circuits o state of sequential circuit o finite state machine o clock signal square4 assertion level square4 period / frequency square4 duty cycle o types of sequential circuits square4 feedback square4 clocked synchronous bistable elements o “simplest” sequential circuit o no inputs (no way of controlling/changing state) o randomly powers up into one state or the other o digital analysis: two stable states o single state variable (Q) o analog analysis: additional quasi-stable state (metastable) metastable behavior o comparable to dropping ball onto smooth hill o speed with which ball rolls to one side or the other depends on location it “hits” o important: if “simplest” sequential circuit is susceptible to metastable behavior, then clearly ALL sequential circuits are(!) Transfer functions (“inverter”): V out1 = T(V in1 ) V out2 = T(V in2 ) Equilibrium points: V in1 = V out2 V in2 = V out1 Random noise drives circuit to stable operating point

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ECE 270 Introduction to Digital System Design © 2011 by D. G. Meyer 2 Present State Present Input Next State Q(t) QN(t) S(t) R(t) Q(t+ τ ) QN(T+ τ ) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Lecture Summary – Module 4-B The Set-Reset (S-R) Latch Reference: Text (4 th Ed.), pp. 526-530; (3 rd Ed.), pp. 534-538 latches and flip-flops o flip-flop changes state based on clocking signal o latch changes its output any time it is enabled set-reset (S-R) latch o change bistable into latch by “adding an input” to each inverter (NOR gate) o two inputs square4 asserting S “sets” the latch state (Q output) to 1 square4 asserting R “resets” the latch state to 0 square4 if both S and R are negated, circuit behaves like bistable (retains its state) square4 if both S and R are asserted and then negated simultaneously, random next state exercise: construct a timing chart for the NOR-implemented S-R latch o assume each gate has delay τ o write the next state equations for Q and QN o create a present state – next state (PS-NS) table and state transition diagram (STD) Q(t+ τ ) = QN(t+ τ ) = 00 01 10 11
ECE 270 Introduction to Digital System Design © 2011 by D. G. Meyer 3 S R Q QN Present State Present Input Next State Q(t) QN(t) S(t) R(t) Q(t+ τ ) QN(T+ τ ) 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 exercise, continued… o construct a timing chart based on the initial conditions and given inputs exercise: investigate response to the “1-1” input combination exercise: investigate response to a “glitch” propagation delay – time for an output to respond to an input transition o need to specify “path” o example: t pLH(S Q)

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2-Mod4_LS_2011 - ECE 270 Introduction to Digital System...

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