2-Mod4_LS_2011

2-Mod4_LS_2011 - ECE 270 Introduction to Digital System...

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Unformatted text preview: ECE 270 Introduction to Digital System Design 2011 by D. G. Meyer 1 Lecture Summary Module 4-A Bistable Elements Reference: Text (4 th Ed.), pp. 521-526; (3 rd Ed.), pp. 529-534 overview o combinational vs. sequential circuits o state of sequential circuit o finite state machine o clock signal s assertion level s period / frequency s duty cycle o types of sequential circuits s feedback s clocked synchronous bistable elements o simplest sequential circuit o no inputs (no way of controlling/changing state) o randomly powers up into one state or the other o digital analysis: two stable states o single state variable (Q) o analog analysis: additional quasi-stable state (metastable) metastable behavior o comparable to dropping ball onto smooth hill o speed with which ball rolls to one side or the other depends on location it hits o important: if simplest sequential circuit is susceptible to metastable behavior, then clearly ALL sequential circuits are(!) Transfer functions (inverter): V out1 = T(V in1 ) V out2 = T(V in2 ) Equilibrium points: V in1 = V out2 V in2 = V out1 Random noise drives circuit to stable operating point ECE 270 Introduction to Digital System Design 2011 by D. G. Meyer 2 Present State Present Input Next State Q(t) QN(t) S(t) R(t) Q(t+ ) QN(T+ ) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Lecture Summary Module 4-B The Set-Reset (S-R) Latch Reference: Text (4 th Ed.), pp. 526-530; (3 rd Ed.), pp. 534-538 latches and flip-flops o flip-flop changes state based on clocking signal o latch changes its output any time it is enabled set-reset (S-R) latch o change bistable into latch by adding an input to each inverter (NOR gate) o two inputs s asserting S sets the latch state (Q output) to 1 s asserting R resets the latch state to 0 s if both S and R are negated, circuit behaves like bistable (retains its state) s if both S and R are asserted and then negated simultaneously, random next state exercise: construct a timing chart for the NOR-implemented S-R latch o assume each gate has delay o write the next state equations for Q and QN o create a present state next state (PS-NS) table and state transition diagram (STD) Q(t+ ) = QN(t+ ) = 00 01 10 11 ECE 270 Introduction to Digital System Design 2011 by D. G. Meyer 3 S R Q QN Present State Present Input Next State Q(t) QN(t) S(t) R(t) Q(t+ ) QN(T+ ) 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 exercise, continued o construct a timing chart based on the initial conditions and given inputs exercise: investigate response to the 1-1 input combination exercise: investigate response to a glitch propagation delay time for an output to respond to an input transition...
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2-Mod4_LS_2011 - ECE 270 Introduction to Digital System...

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