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Unformatted text preview: 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5 Arithmetic Logic Circuits
1 Module 5
Desired Outcome: "An ability to design and implement arithmetic logic circuits" Part A: Unsigned Number Base Conversion Part B: Signed Number Notation Part C: Radix Addition and Subtraction Part D: Adder, Subtractor, and Comparator Circuits Part E: Carry LookAhead Adder Circuits Look Part F: Multiplier Circuits Part G: BCD Adder Circuits 2 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5A Unsigned Number Base Conversion
3 Reading Assignment: 3rd Ed., pp. 2534; 4th Ed., pp. 2534 2525Instructional Objectives:
To learn how to perform base conversions To learn a "shortcut" that can be applied to conversion among bases that are powers of two Outline:
Unsigned Integer Base Conversion Base R to Base 10 Base 10 to Base R Shortcut for Conversion Among Powers of 2
4 Unsigned Integer Base Conversion
The first item of interest when discussing arithmetic is how to convert from one number base (or radix) to another A table of correspondence is a useful tool for comparing numbers in different bases The following notation will be used: (d3d2d1d0)R = (N)R = number in base R (c3c2c1c0)R = (N)10 = number in base 10 Note that the c's represent the converted corresponding digits, base 10 digits,
5 Table of Correspondence  Unsigned Integers
N2
0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 10000 N3
0 1 2 10 11 12 20 21 22 100 101 102 110 111 112 120 121 N4
0 1 2 3 10 11 12 13 20 21 22 23 30 31 32 33 100 N5
0 1 2 3 4 10 11 12 13 14 20 21 22 23 24 30 31 N6
0 1 2 3 4 5 10 11 12 13 14 15 20 21 22 23 24 N7
0 1 2 3 4 5 6 10 11 12 13 14 15 16 20 21 22 N8
0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 N9
0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 N10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N16
0 1 2 3 4 5 6 7 8 9 A B C D E F 10
6 Table of Correspondence  Unsigned Integers
N2
0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 10000 N3
0 1 2 10 11 12 20 21 22 100 101 102 110 111 112 120 121 N4
0 1 2 3 10 11 12 13 20 21 22 23 30 31 32 33 100 N5
0 1 2 3 4 10 11 12 13 14 20 21 22 23 24 30 31 N6
0 1 2 3 4 5 10 11 12 13 14 15 20 21 22 23 24 N7
0 1 2 3 4 5 6 10 11 12 13 14 15 16 20 21 22 N8
0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 N9
0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 N10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N16
0 1 2 3 4 5 6 7 8 9 A B C D E F 10
7 Table of Correspondence  Unsigned Integers
N2
0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 10000 N3
0 1 2 10 11 12 20 21 22 100 101 102 110 111 112 120 121 N4
0 1 2 3 10 11 12 13 20 21 22 23 30 31 32 33 100 N5
0 1 2 3 4 10 11 12 13 14 20 21 22 23 24 30 31 N6
0 1 2 3 4 5 10 11 12 13 14 15 20 21 22 23 24 N7
0 1 2 3 4 5 6 10 11 12 13 14 15 16 20 21 22 N8
0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 N9
0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 N10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N16
0 1 2 3 4 5 6 7 8 9 A B C D E F 10
8 Unsigned Integer Base Conversion
IMPORTANT: IMPORTANT: The conversion methods described here are only applicable to unsigned (or, "positive") numbers ALSO NOTE: Since the numbers we are NOTE: dealing with are unsigned, leading zeroes have "no social significance" (i.e., they can be added or removed without changing the value of the number) 9 Conversion of Integers: Base R10 R
Method: Method: Iterative Multiply and Add based on the fact that a number can be expressed in nested form, as follows: (d3d2d1d0)R = (N)10 = c3xR3 + c2xR2 + c1xR1 + c0xR0 = (((c3 x R + c2) x R + c1) x R + c0) (((c the expression evaluation proceeds from the innermost level of parenthesis to the innerouteroutermost level
10 Conversion of Integers: Base R10 R
Example: Example: Convert (4352)8 to base 10 (4352) 4 x 8 + 3 = 35 35 x 8 + 5 = 285 285 x 8 + 2 = 2282 Therefore, (4352)8 = (2282)10 11 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) _______ x ___ + ___ = _________ _______ x ___ + ___ = _________ _______ x ___ + ___ = _________ _______ x ___ + ___ = _________ _______ x ___ + ___ = _________ _______ x ___ + ___ = _________ _______ x ___ + ___ = _________
12 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) _______ x _2_ + ___ = _________ _______ x _2_ + ___ = _________ _______ x _2_ + ___ = _________ _______ x _2_ + ___ = _________ _______ x _2_ + ___ = _________ _______ x _2_ + ___ = _________ _______ x _2_ + ___ = _________
13 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _1_ = _________
14 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 _______ x _2_ + _1_ = _________ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _1_ = _________
15 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 ____3 ___1 ___1___ x _2_ + _1_ = ____3____ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _1_ = _________
16 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 ____3 ___1 ___1___ x _2_ + _1_ = ____3____ ___3 ___3___ x _2_ + _0_ = ____6____ ____6 _______ x _2_ + _1_ = _________ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _1_ = _________
17 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 ____3 ___1 ___1___ x _2_ + _1_ = ____3____ ___3 ___3___ x _2_ + _0_ = ____6____ ____6 ___13____ ___6 ___6___ x _2_ + _1_ = ___13____ _______ x _2_ + _0_ = _________ _______ x _2_ + _1_ = _________ _______ x _2_ + _1_ = _________
18 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 ____3 ___1 ___1___ x _2_ + _1_ = ____3____ ___3 ___3___ x _2_ + _0_ = ____6____ ____6 ___13____ ___6 ___6___ x _2_ + _1_ = ___13____ __13___ x _2_ + _0_ = ___26____ __13___ ___26____ _______ x _2_ + _1_ = _________ _______ x _2_ + _1_ = _________
19 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 ____3 ___1 ___1___ x _2_ + _1_ = ____3____ ___3 ___3___ x _2_ + _0_ = ____6____ ____6 ___13____ ___6 ___6___ x _2_ + _1_ = ___13____ __13___ x _2_ + _0_ = ___26____ __13___ ___26____ ___53____ __26___ x _2_ + _1_ = ___53____ __26___ _______ x _2_ + _1_ = _________
20 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 ____3 ___1 ___1___ x _2_ + _1_ = ____3____ ___3 ___3___ x _2_ + _0_ = ____6____ ____6 ___13____ ___6 ___6___ x _2_ + _1_ = ___13____ __13___ x _2_ + _0_ = ___26____ __13___ ___26____ ___53____ __26___ x _2_ + _1_ = ___53____ __26___ __53___ x _2_ + _1_ = __107____ __53___ __107____
21 Conversion of Integers: Base R10 R
Exercise: Exercise: Convert (01101011)2 to base 10 (01101011) ___0 ___0___ x _2_ + _1_ = ____1____ ____1 ___1 ___1___ x _2_ + _1_ = ____3____ ____3 ___3 ___3___ x _2_ + _0_ = ____6____ ____6 ___6 ___6___ x _2_ + _1_ = ___13____ ___13____ __13___ x _2_ + _0_ = ___26____ __13___ ___26____ __26___ x _2_ + _1_ = ___53____ __26___ ___53____ __107____ __53___ x _2_ + _1_ = __107____ __53___ _107_ Therefore, (01101011)2 = ( _107_ )10
22 Conversion of Integers: Base 10R 10
Method: Method: Iterative Division based on an iterative division of the number by the radix (base) to which it is being converted the remainders of each division become the digits of the converted number a quotient of zero indicates the conversion is complete 23 Conversion of Integers: Base 10R 10
Example: Example: Convert (727)10 to base 8 (727) 24 Conversion of Integers: Base 10R 10
Example: Example: Convert (727)10 to base 8 (727) 90 8 )727 720 7 25 Conversion of Integers: Base 10R 10
Example: Example: Convert (727)10 to base 8 (727) 90 8 )727 720 7 11 8 )90 88 2 26 Conversion of Integers: Base 10R 10
Example: Example: Convert (727)10 to base 8 (727) 90 8 )727 720 7 11 8 )90 88 2 1 8 )11  8 3 27 Conversion of Integers: Base 10R 10
Example: Example: Convert (727)10 to base 8 (727) 90 8 )727 720 7 11 8 )90 88 2 1 8 )11  8 3 0 8 )1 0 1 28 Conversion of Integers: Base 10R 10
Example: Example: Convert (727)10 to base 8 (727) 90 8 )727 720 7 11 8 )90 88 2 1 8 )11  8 3 0 8 )1 0 1 Therefore, (727)10 = (1327)8 (727) (1327)
29 Conversion of Integers: Base 10R 10
Exercise: Exercise: Convert (2623)10 to base 16 (2623) 30 Conversion of Integers: Base 10R 10
Exercise: Exercise: Convert (2623)10 to base 16 (2623) 163 16)2623 16) 2608 15 31 Conversion of Integers: Base 10R 10
Exercise: Exercise: Convert (2623)10 to base 16 (2623) 163 16)2623 16) 2608 15 10 16)163 16) 160 3 32 Conversion of Integers: Base 10R 10
Exercise: Exercise: Convert (2623)10 to base 16 (2623) 163 16)2623 16) 2608 15 10 16)163 16) 160 3 0 16)10 16)  0 10 33 Conversion of Integers: Base 10R 10
Exercise: Exercise: Convert (2623)10 to base 16 (2623) 163 16)2623 16) 2608 15 10 16)163 16) 160 3 0 16)10 16)  0 10 Therefore, (2623)10 = ( _A3F_ )16
34 Short Cut for Conversion Among Powers of 2
Method: Method: Size Log2R Groupings when converting a number from base "A" to base "B", where A and B are powers of 2 (e.g., 2, 4, 8, and 16), a "short cut" can be used an ndigit binary number can be written for each base A digit in the original number, where n = log2A starting at the least significant position, the converted binary digits can be regrouped into mdigit binary numbers, where m = log2B
35 Short Cut for Conversion Among Powers of 2
Example: Example: Convert (136)8 to base 2 and base 16 (136) 36 Short Cut for Conversion Among Powers of 2
Example: Example: Convert (136)8 to base 2 and base 16 (136) 1 3 6 37 Short Cut for Conversion Among Powers of 2
Example: Example: Convert (136)8 to base 2 and base 16 (136) 1 001 3 011 6 110 38 Short Cut for Conversion Among Powers of 2
Example: Example: Convert (136)8 to base 2 and base 16 (136) 1 001 0101 3 011 1110 6 110 39 Short Cut for Conversion Among Powers of 2
Example: Example: Convert (136)8 to base 2 and base 16 (136) 1 001 0101 5 3 011 E 1110 6 110 40 Short Cut for Conversion Among Powers of 2
Example: Example: Convert (136)8 to base 2 and base 16 (136) 1 001 0101 5 3 011 E 1110 6 110 Therefore, (136)8 = ( 1011110 )2 = ( 5E )16
41 Short Cut for Conversion Among Powers of 2
Exercise: Exercise: Convert (110101)2 to bases 8 and 16 (110101) 42 Short Cut for Conversion Among Powers of 2
Exercise: Exercise: Convert (110101)2 to bases 8 and 16 (110101) 110101 43 Short Cut for Conversion Among Powers of 2
Exercise: Exercise: Convert (110101)2 to bases 8 and 16 (110101) 110 0011 101 0101 110101 44 Short Cut for Conversion Among Powers of 2
Exercise: Exercise: Convert (110101)2 to bases 8 and 16 (110101) 6 110 0011 3 5 101 0101 5 110101 45 Short Cut for Conversion Among Powers of 2
Exercise: Exercise: Convert (110101)2 to bases 8 and 16 (110101) 6 110 0011 3 5 101 0101 5 110101 Therefore, (110101)2 = ( _65_ )8 = ( _35_ )16 _65_ _35_
46 Clicker Quiz
47 Clicker Quiz
1. The unsigned binary number (10001)2 is equivalent to the following unsigned base 10 number:
A. B. C. D. E. (17)10 (34)10 (62)10 (124)10 none of the above
48 Clicker Quiz
2. The unsigned hexadecimal number (3E)16 is equivalent to the following unsigned base 10 number:
A. B. C. D. E. (17)10 (34)10 (62)10 (124)10 none of the above
49 Clicker Quiz
3. The unsigned hexadecimal number (521)16 is equivalent to the following unsigned binary number:
A. B. C. D. E. (101 10 1)2 (101 010 01)2 (101 010 001)2 all of the above none of the above
50 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5B Signed Number Notation
51 Reading Assignment: 3rd Ed., pp. 3439; 4th Ed., pp. 3439 3434Instructional Objectives:
To learn the notations used to represent signed numbers in digital systems To learn how to extend the length of signed numbers Outline:
Signed Number Notation Sign and Magnitude Diminished Radix Radix Simplifications for Binary Numbers Sign Extension 52 Signed Numbers
In order to represent positive and negative numbers as a series of digits without "+" and "" signs, various signed number " notations have been devised We will discuss the three most commonly used signed number notations: sign and magnitude (SM) diminished radix (DR) radix (R) 53 Sign and Magnitude
The original signed number convention employed by "vacuum tube vintage digijocks" was sign and magnitude notation Here the leftmost digit (or "sign bit") leftindicates whether the number is positive or negative: "0" positive "R1" negative (where R is the radix or "R base of the number) 54 Sign and Magnitude
Examples: Examples: (+123)10 = SM(0123)10 (123)10 = SM(9123)10 (+144)5 = SM(0144)5 (144)5 = SM(4144)5
SM(0123)10 and SM(9123)10 are referred to as the sign and magnitude complements of one another
55 Sign and Magnitude
Negation Method: If N is a number in base R Method: with sign digit nS, such that (N)R = nSn3n2n1n0
then (N)R = (R1nS)n3n2n1n0 (R
Examples: Examples: (+1101)2 = SM(01101)2 (1101)2 = SM(11101)2
56 Diminished Radix
The negation (or complement) of a number represented in diminished radix (DR) notation can be found by subtracting each digit (including the sign digit) from (R1), (R i.e., the "radix minus one" or the "radix diminished by one" Examples: Examples: (+123)10 = DR(0123)10 (123)10 = (9999 0123)10 = DR(9876)10
DR(0123)10 and DR(9876)10 are referred to as the diminished radix complements of one another.
57 Diminished Radix
Negation Method: If N is a number in base R, Method: (N)R = (Rn 1)R (N)R
Examples: Examples: (+1101)2 = DR(01101)2 (1101)2 = DR(10010)2
Note that positive DR numbers have the same representation as positive SM numbers; negative DR and SM numbers, however, have different representations
58 Radix
The negation (or complement) of a number represented in radix (R) notation can be found by adding one to the least significant position of the diminished radix negation of that number Examples: Examples: (+123)10 = R(0123)10 (123)10 = (9999 0123 + 1)10 = R(9877)10
R(0123)10 and R(9877)10 are referred to as the radix complements of one another
59 Radix
Negation Method: If N is a number in base R, Method: (N)R = (Rn)R (N)R
Examples: Examples: (+1101)2 = R(01101)2 (1101)2 = R(10011)2
Note that positive R, DR, and SM numbers all have the same representation; negative R, DR, and SM numbers, however, all have different representations
60 Comparison of Signed Number Notations
N 10 +3 +2 +1 +0 0 1 2 3 4 SM 011 010 001 000 100 101 110 111  DR 011 010 001 000 111 110 101 100  R 61 Comparison of Signed Number Notations N10 SM DR R +3 011 011 +2 010 010 +1 001 001 Radix has +0 000 000 000 no "negative zero" 0 100 111  1 101 110 2 110 101 3 111 100 4   62 Comparison of Signed Number Notations N10 SM DR R All +3 011 011 011 positive numbers +2 010 010 010 identical +1 001 001 001 Radix has +0 000 000 000 no "negative zero" 0 100 111  1 101 110 2 110 101 3 111 100 4   63 Comparison of Signed Number Notations N10 SM DR R All +3 011 011 011 positive numbers +2 010 010 010 identical +1 001 001 001 Radix has +0 000 000 000 no "negative zero" 0 100 111  All 1 101 110 111 negative numbers 2 110 101 110 different 3 111 100 101 4   100 64 Comparison of Signed Number Notations N10 SM DR R All +3 011 011 011 positive numbers +2 010 010 010 identical +1 001 001 001 Radix has +0 000 000 000 no "negative zero" 0 100 111  All 1 101 110 111 negative numbers 2 110 101 110 different 3 111 100 101 Radix has extra negative 4   100 number 65 Simplifications for Binary
When finding the negations (complements) of binary (base 2) numbers, the methods simplify as follows: SM: complement the sign position DR (also called 1's complement ): complement each position R (also called 2's complement ): add 1 to the DR complement oror scan number from right to left; complement each position to the left of the first "1" encountered
66 Practice
If (N)2 = SM(01100)2, find (N)2 If (N)2 = DR(01100)2, find (N)2 If (N)2 = R(01100)2, find (N)2 67 Practice
If (N)2 = SM(01100)2, find (N)2
SM(11100) If (N)2 = DR(01100)2, find (N)2 If (N)2 = R(01100)2, find (N)2 68 Practice
If (N)2 = SM(01100)2, find (N)2
SM(11100)2 If (N)2 = DR(01100)2, find (N)2
DR(10011)2 If (N)2 = R(01100)2, find (N)2 69 Practice
If (N)2 = SM(01100)2, find (N)2
SM(11100)2 If (N)2 = DR(01100)2, find (N)2
DR(10011)2 If (N)2 = R(01100)2, find (N)2
R(10100)2
70 Sign Extension
Sometimes signed numbers of different length (number of bits) need to be added together here, the "shorter" number needs to be "padded" with leading digits to make it the two numbers the same length The rules for padding signed numbers with leading digits are as follows: SM: insert as many zeroes as needed to the right of the sign position DR & R: replicate the sign digit as many times as needed
71 Practice
Extend SM(09345)10 to 8 digits Extend DR(76500)8 to 8 digits Extend R(01100)2 to 8 digits Extend R(11100)2 to 8 digits 72 Practice
Extend SM(09345)10 to 8 digits
SM(00009345)10 Extend DR(76500)8 to 8 digits Extend R(01100)2 to 8 digits Extend R(11100)2 to 8 digits 73 Practice
Extend SM(09345)10 to 8 digits
SM(00009345)10 Extend DR(76500)8 to 8 digits
DR(77776500)8 Extend R(01100)2 to 8 digits Extend R(11100)2 to 8 digits 74 Practice
Extend SM(09345)10 to 8 digits
SM(00009345)10 Extend DR(76500)8 to 8 digits
DR(77776500)8 Extend R(01100)2 to 8 digits
R(00001100)2 Extend R(11100)2 to 8 digits 75 Practice
Extend SM(09345)10 to 8 digits
SM(00009345)10 Extend DR(76500)8 to 8 digits
DR(77776500)8 Extend R(01100)2 to 8 digits
R(00001100)2 Extend R(11100)2 to 8 digits
R(11111100)2
76 Comparison/Observations
SM and DR notation have a balanced set of positive and negative numbers, and have two representations for zero R notation has an unbalanced set of positive and negative numbers (there is an "extra negative number"), and has a single number"), representation for zero 99% of all computers use radix notation; our discussion on addition and subtraction will therefore focus on radix arithmetic (we will assume a prefix of "R" on all numbers subsequently used)
77 Clicker Quiz
78 Clicker Quiz
1. The fivebit radix number, R(10101)2, converted to sign and magnitude notation, is:
A. B. C. D. E. SM (10101)2 SM (01010)2 SM (11010)2 SM (11011)2 none of the above
79 Clicker Quiz
2. The fivebit diminished radix number, DR(10101)2, converted to sign and magnitude notation, is:
A. B. C. D. E. SM (10101)2 SM (01010)2 SM (11010)2 SM (11011)2 none of the above
80 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5C Radix Addition and Subtraction
81 Reading Assignment: 3rd Ed., pp. 3943; 4th Ed., pp. 3943 3939Instructional Objectives:
To learn how to perform addition and subtraction of signed binary numbers in radix notation To learn what overflow is, the conditions that cause it to occur, and how to detect it Outline:
Radix Addition Overflow Detection Radix Subtraction
82 Radix Arithmetic Addition
Method: Method: Add all digits, including the sign digits; ignore any carry out of the sign position Problem: Problem: Since we are working with numbers of fixed length, the result of an addition can yield a number which is too large to represent in the same number of digits this error condition is called overflow Important: Important: When overflow occurs, there is no valid numeric result
83 Overflow Detection
Summarization: Summarization: Overflow occurs if two positive numbers are added and a negative result is obtained, or if two negative numbers are added and a positive result is obtained (or, if numbers of like sign are added and a result with the opposite sign is obtained) Overflow cannot occur when adding numbers of opposite sign Another way to detect overflow: If the carry overflow: in to the sign position is different than the carry out of the sign position, then overflow has occurred
84 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 00110 +01010 00010 +01010 85 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) +6 +10 00110 +01010 00010 +01010 86 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) +6 +10 00110 +01010 10000 00010 +01010 87 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) +6 +10 00110 +01010 10000 00010 +01010 Here, added two positive numbers, but got a negative result OVERFLOW
88 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) +6 +10 +2 +10 00110 +01010 10000 00010 +01010 Here, added two positive numbers, but got a negative result OVERFLOW
89 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) +6 +10 +2 +10 00110 +01010 10000 00010 +01010 01100 Here, added two positive numbers, but got a negative result OVERFLOW
90 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) +6 +10 +2 +10 00110 +01010 10000 00010 +01010 01100 Here, added two positive numbers, but got a negative result OVERFLOW Here, added two positive numbers, and got a positive result (+12) OK!
91 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 11100 +10110 10011 +10001 92 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 11100 +10110 10011 +10001 93 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 11100 +10110 110010 10011 +10001 94 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 ignore 11100 +10110 110010 10011 +10001 95 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 ignore
Here, added two negative numbers, and got a negative result (14) OK!
96 11100 +10110 110010 10011 +10001 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 ignore
Here, added two negative numbers, and got a negative result (14) OK!
97 11100 +10110 110010 10011 +10001  13  15 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 ignore
Here, added two negative numbers, and got a negative result (14) OK!
98 11100 +10110 110010 10011 +10001 100100  13  15 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 ignore  13  15 11100 +10110 110010 ignore 10011 +10001 100100 Here, added two negative numbers, and got a negative result (14) OK!
99 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 4  10 ignore  13  15 11100 +10110 110010 ignore 10011 +10001 100100 Here, added two negative numbers, and got a negative result (14) OK! Here, added two negative numbers, but got a positive result OVERFLOW
100 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 10011 +01111 01111 +10000 101 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 13 +15 10011 +01111 01111 +10000 102 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 13 +15 10011 +01111 100010 01111 +10000 103 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 13 +15 ignore 10011 +01111 100010 01111 +10000 104 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 13 +15 ignore
Here, added numbers of opposite sign overflow cannot occur (result is +2)
105 10011 +01111 100010 01111 +10000 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 13 +15 ignore
Here, added numbers of opposite sign overflow cannot occur (result is +2)
106 10011 +01111 100010 01111 +10000 +15 16 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 13 +15 ignore
Here, added numbers of opposite sign overflow cannot occur (result is +2)
107 10011 +01111 100010 01111 +10000 11111 +15 16 Radix Arithmetic Addition
Examples: Examples: (all numbers are binary) 13 +15 ignore
Here, added numbers of opposite sign overflow cannot occur (result is +2) Again, added numbers of opposite sign overflow cannot occur (result is 1)
108 10011 +01111 100010 01111 +10000 11111 +15 16 Radix Arithmetic Subtraction
Method: Method: Take the radix complement of the subtrahend and ADD; the same rules for overflow apply Examples: Examples: 01011 01100 109 Radix Arithmetic Subtraction
Method: Method: Take the radix complement of the subtrahend and ADD; the same rules for overflow apply Examples: Examples: 01011 01100
Why does this work? Examples: 5  (+3) = 5 + (3) = 2 ( 9 (13) = 9 + (+13) = 22
110 Radix Arithmetic Subtraction
Method: Method: Take the radix complement of the subtrahend and ADD; the same rules for overflow apply Examples: Examples: +11 +12 01011 01100 111 Radix Arithmetic Subtraction
Method: Method: Take the radix complement of the subtrahend and ADD; the same rules for overflow apply Examples: Examples: +11 +12 01011 01100 01011 10011 + 1
minuend
Radix complement of subtrahend 112 Radix Arithmetic Subtraction
Method: Method: Take the radix complement of the subtrahend and ADD; the same rules for overflow apply Examples: Examples: +11 +12 01011 01100 01011 10011 + 1 11111
minuend
Radix complement of subtrahend 113 Radix Arithmetic Subtraction
Method: Method: Take the radix complement of the subtrahend and ADD; the same rules for overflow apply Examples: Examples: +11 +12 01011 01100 01011 10011 + 1 11111
minuend
Radix complement of subtrahend Here, added numbers of opposite sign overflow cannot occur (result is 1) 114 Radix Arithmetic Subtraction
Examples: Examples: 01011 10000 115 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 116 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 117 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 11011 118 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 1 1 0 1 1 Overflow 119 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 1 1 0 1 1 Overflow 10001 00010 120 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 1 1 0 1 1 Overflow 15 +2 10001 00010 121 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 1 1 0 1 1 Overflow 10001 11101 + 1
122 15 +2 10001 00010 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 1 1 0 1 1 Overflow 10001 11101 + 1 101111
123 15 +2 10001 00010 Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 1 1 0 1 1 Overflow 10001 11101 + 1 101111
124 15 +2 10001 00010 ignore Radix Arithmetic Subtraction
Examples: Examples: +11 16 01011 10000 01011 01111 + 1 1 1 0 1 1 Overflow 10001 11101 + 1 1 0 1 1 1 1 Overflow
125 15 +2 10001 00010 ignore Radix Arithmetic Subtraction
Examples: Examples: 01011 00000 126 Radix Arithmetic Subtraction
Examples: Examples: +11 0 01011 00000 127 Radix Arithmetic Subtraction
Examples: Examples: +11 0 01011 00000 01011 11111 + 1 101011 128 Radix Arithmetic Subtraction
Examples: Examples: +11 0 01011 00000 ignore 01011 11111 + 1 101011 129 Radix Arithmetic Subtraction
Examples: Examples: +11 0 01011 00000 ignore 01011 11111 + 1 101011 +11 130 Radix Arithmetic Subtraction
Examples: Examples: +11 0 01011 00000 ignore 15 1 10001 11111 01011 11111 + 1 101011 +11 131 Radix Arithmetic Subtraction
Examples: Examples: +11 0 01011 00000 ignore 15 1 10001 11111 10001 00000 + 1 10010
132 01011 11111 + 1 101011 +11 Radix Arithmetic Subtraction
Examples: Examples: +11 0 01011 00000 ignore 15 1 10001 11111 10001 00000 + 1 10010 01011 11111 + 1 101011 +11 14
133 Clicker Quiz
134 Clicker Quiz
1. When adding the fivebit signed numbers (10111)2 + (11001)2 using radix arithmetic, the result obtained is:
A. B. C. D. E. (10000)2 (110000)2 (11000)2 overflow (invalid result) none of the above
135 Clicker Quiz
2. When subtracting the fivebit signed numbers (10111)2  (11001)2 using radix arithmetic, the result obtained is:
A. B. C. D. E. (10000)2 (11000)2 (11110)2 overflow (invalid result) none of the above
136 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5D Adder, Subtractor, and Comparator Circuits
137 Reading Assignment: 3rd Ed., pp. 419427, 430434; 4194304th Ed., pp. 458466, 474478 458474Instructional Objectives:
To learn about the basic building blocks needed to construct digital arithmetic circuits To learn how to design an nbit radix nadder/subtractor circuit To learn what condition codes are and how they can be used To learn how to design an nbit comparator n138 Outline
Overview Half Adders Full Adders Radix Adder/Subtractors Adder/Subtractors Comparators Arithmetic Logic Unit 139 Overview
Addition is the most commonly performed arithmetic operation in digital systems An adder combines two arithmetic operands using the addition rules described in Lecture Module 5C 5The same addition rules (and circuits) are used for both signed (two's complement) and unsigned numbers Subtraction can be performed by taking the complement of the subtrahend and adding it to the minuend
140 Half Adders
A half adder is used to add two binary digits, Xi and Yi, to form a sum digit, Si, and a carry digit, Ci Xi 0 0 1 1 Yi 0 1 0 1 Ci 0 0 0 1 Si 0 1 1 0 Si = Xi Yi Ci = Xi Yi 141 Full Adders
A full adder is used to add three binary digits, Xi, Yi, Ci1 (where Ci1 is usually the carry in from a previous stage), to form a sum digit, Si, and a carry out digit, Ci 142 Full Adders
Xi 0 0 0 0 1 1 1 1 Yi 0 0 1 1 0 0 1 1 Ci1 0 1 0 1 0 1 0 1 Ci 0 0 0 1 0 1 1 1 Si 0 1 1 0 1 0 0 1 Si = Xi Yi Ci1 Ci = XiYi + XiCi1 + YiCi1
143 Exercise
Using only half adders and full adders, design a circuit that finds the (unsigned) sum of five binary digits Xi Yi HA Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si 144 Exercise
Using only half adders and full adders, design a circuit that finds the (unsigned) sum of five binary digits V W X Y Z S2S1S0
145 Xi Yi HA Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Exercise
Using only half adders and full adders, design a circuit that finds the (unsigned) sum of five binary digits
Y Z V W Xi Yi HA Ci Si
S2 S1 Xi Yi FA Ci1 Ci Si
S0 Xi Yi FA Ci1 Ci Si V W X X Y Z S2S1S0
146 Exercise
Using only half adders and full adders, design a circuit that finds the (unsigned) sum of five binary digits
Y Z V W Xi Yi HA Ci Si
S2 S1 Xi Yi FA Ci1 Ci Si
S0 Xi Yi FA Ci1 Ci Si V W X X Y Z S2S1S0
147 Also called a "population" (or vote) counter Clicker Quiz
148 The DigiVotaMatic is a threejudge score tabulation system that allows each judge to enter a score ranging from "0" (002) to "3" (112) on a pair of DIP switches, and displays the sum of the three scores (ranging from "0" to "9") on a 7segment LED.
149 Clicker Quiz
1. Implemented using a TRUTH_TABLE directive, a circuit that finds the sum of three 2bit unsigned numbers would require ___ rows in the table (following the declaration).
A. B. C. D. E. 16 32 64 128 none of the above
150 Clicker Quiz
2. Implemented using a TRUTH_TABLE directive, a circuit that finds the sum of three 2bit unsigned numbers would require ___ discrete entries in the table (following the declaration).
A. B. C. D. E. 64 128 640 1280 none of the above
151 Clicker Quiz
3. Implemented using a 16V8 PLD, a circuit that finds the sum of three 2bit unsigned numbers would require no more than ___ macrocells.
A. B. C. D. E. 2 4 8 16 none of the above
152 MultiMultiDigit Adder/Subtractor Circuits
Two binary words, each with n bits, can be added using a ripple adder a cascade of n fullfulladder stages, each of which handles one bit (also called an iterative circuit) The word ripple describes the flow of the carries from one full adder cell to the next Subtraction is performed by taking the diminished radix complement of the subtrahend (using XOR gates) and setting the least significant bit carryin (LSB Cin) to carry"1" (effectively forming the radix complement of the subtrahend)
153 Review of Radix Addition
Method: Method: Add all digits, including the sign digits; ignore any carry out of the sign position Problem: Problem: Since we are working with numbers of fixed length, the result of an addition can yield a number which is too large to represent in the same number of digits this error condition is called overflow Important: Important: When overflow occurs, there is no valid numeric result 154 Overflow Detection
Summarization: Summarization: Overflow occurs if two positive numbers are added and a negative result is obtained, or if two negative numbers are added and a positive result is obtained (or, if numbers of like sign are added and a result with the opposite sign is obtained) Overflow cannot occur when adding numbers of opposite sign Another way to detect overflow: If the carry overflow: in to the sign position is different than the carry out of the sign position, then overflow has occurred
155 Exercise
Design a 4bit radix ripple adder/subtractor that includes an overflow detection circuit Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si 156 Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit radix ripple adder/subtractor that includes an overflow detection circuit Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si 157 Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit radix ripple adder/subtractor that includes an overflow detection circuit Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si LSB Cin 158 Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit radix ripple adder/subtractor that includes an overflow detection circuit A3 Xi Yi FA Ci1 Ci Si S3 A2 Xi Yi FA Ci1 Ci Si S2 A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 Ci Si S0
159 LSB Cin Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 M= 0 add 1 subtract
M Design a 4bit radix ripple adder/subtractor that includes an overflow detection circuit B0 B2 B3 B1 A3 Xi Yi FA Ci1 Ci Si S3 A2 Xi Yi FA Ci1 Ci Si S2 A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 Ci Si S0 LSB Cin 160 Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 M= 0 add 1 subtract
M Design a 4bit radix ripple adder/subtractor that includes an overflow detection circuit B0 B2 B3 B1 A3 Xi Yi FA Ci1 Ci Si S3 A2 Xi Yi FA Ci1 Ci Si S2 A1 Xi Yi FA Ci1 Ci Si A0 Xi Yi FA Ci1 Ci Si S0 LSB Cin S1 VF (overflow) 161 Other Conditions of Interest
In addition to overflow, other conditions of interest following an arithmetic operation include the following: ZERO the result of the computation was 00...0 NEGATIVE the result of the computation was a negative number CARRY/BORROW the computation produced a carry out of the sign position after an addition, or addition, produced a borrow out of the sign position after a subtraction (the complement of the carry out) These conditions are sometimes referred to as "condition codes" or "flags" "condition codes" "flags"
162 Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 M= 0 add 1 subtract
M Add a ZERO Flag (ZF), NEGATIVE Flag (NF), and a CARRY/BORROW Flag (CF) B0 B2 B3 B1 A3 Xi Yi FA Ci1 Ci Si S3 A2 Xi Yi FA Ci1 Ci Si S2 VF A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 Ci Si S0 LSB Cin 163 Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 M= 0 add 1 subtract
M Add a ZERO Flag (ZF), NEGATIVE Flag (NF), and a CARRY/BORROW Flag (CF) B0 B2 B3 B1 A3 Xi Yi FA Ci1 Ci Si S3
NF A2 Xi Yi FA Ci1 Ci Si S2
VF A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 Ci Si S0
164 LSB Cin Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 M= 0 add 1 subtract
M Add a ZERO Flag (ZF), NEGATIVE Flag (NF), and a CARRY/BORROW Flag (CF) B0 B2 B3 B1 A3 Xi Yi FA Ci1 Ci Si S3
NF A2 Xi Yi FA Ci1 Ci Si S2
VF A1 Xi Yi FA Ci1 Ci Si S1
CF A0 Xi Yi FA Ci1 Ci Si S0
165 LSB Cin Exercise A3 A2 A1 A0 +/ B3 B2 B1 B0 S3 S2 S1 S0 M= 0 add 1 subtract
M Add a ZERO Flag (ZF), NEGATIVE Flag (NF), and a CARRY/BORROW Flag (CF) B0 B2 B3 B1 A3 Xi Yi FA Ci1 Ci Si S3
NF A2 Xi Yi FA Ci1 Ci Si S2
VF A1 Xi Yi FA Ci1 Ci Si S1
CF A0 Xi Yi FA Ci1 Ci Si S0
ZF 166 LSB Cin Clicker Quiz
167 Clicker Quiz
1. When performing radix addition, the XOR of the carry in to the sign position with the carry out of the sign position provides a means to:
A. generate a carry that is propagated forward B. generate a borrow that is propagated forward C. check for a negative result D. check for an invalid result E. none of the above
168 Clicker Quiz
2. Following a subtract operation, the carry flag (CF) can be used to:
A. generate a carry that is propagated forward B. generate a borrow that is propagated forward C. check for a negative result D. check for an invalid result E. none of the above 169 Clicker Quiz
3. Following an add operation, the negative flag (NF) can be used to:
A. generate a carry that is propagated forward B. generate a borrow that is propagated forward C. check for a negative result D. check for an invalid result E. none of the above 170 Comparators
Comparing two binary words for equality is a commonly used operation in computer systems a circuit that does this is called a comparator XOR and XNOR gates may be viewed as oneonebit comparators (from which larger comparators can be built) Circuits that determine an arithmetic relationship between two operands (greater or less than) are called magnitude comparators
171 Exercise
Design a 4bit (signed) magnitude comparator 4that determines if A=B, A<B, or A>B Solution: Solution: Calculate AB and examine the A condition codes ZERO ("ZF" for zero flag) NEGATIVE ("NF" for negative flag) CARRY ("CF" for carry/borrow flag) OVERFLOW ("VF" for overflow flag) Note: Note: Because a SUBTRACTION is being performed, need to complement the carry out of the sign to make it a BORROW Need to know how the various flags are affected for all possible results generated 172 A1 A0 B1 B0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ?
A=B A<B A>B A>B A>B A=B A>B A>B A<B A<B A=B A<B A<B A<B A>B A=B CF ZF NF VF
0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 173 A1 A0 B1 B0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ?
A=B A<B A>B A>B A>B A=B A>B A>B A<B A<B A=B A<B A<B A<B A>B A=B CF ZF NF VF
0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0
174 Exercise
Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si 175 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si 176 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si Xi Yi FA Ci1 Ci Si 177 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) Xi Yi FA Ci1 Ci Si S3 Xi Yi FA Ci1 Ci Si S2 Xi Yi FA Ci1 Ci Si S1 Xi Yi FA Ci1 Ci Si S0
178 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) A3 Xi Yi FA Ci1 Ci Si S3 A2 Xi Yi FA Ci1 Ci Si S2 A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 Ci Si S0
179 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) B0 B1 B3 B2 A3 Xi Yi FA Ci1 Ci Si S3 A2 Xi Yi FA Ci1 Ci Si S2 A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 1 Ci Si S0
180 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) B0 B1 B3 B2 A3 Xi Yi FA Ci1 Ci Si S3
NF A2 Xi Yi FA Ci1 Ci Si S2 A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 1 Ci Si S0
181 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) B0 B1 B3 B2 A3 Xi Yi FA Ci1 Ci Si S3
NF A2 Xi Yi FA Ci1 Ci Si S2
VF A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 1 Ci Si S0
182 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) B0 B1 B3 B2 A3 Xi Yi FA Ci1 Ci Si S3
NF CF A2 Xi Yi FA Ci1 Ci Si S2
VF A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 1 Ci Si S0
183 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) B0 B1 B3 B2 A3 Xi Yi FA Ci1 Ci Si S3
NF CF A2 Xi Yi FA Ci1 Ci Si S2
VF A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 1 Ci Si S0
ZF = AEQB
184 Exercise A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 CF NF VF ZF ? ALTB AGTB Design a 4bit magnitude comparator that determines if A=B (AEQB), A<B (ALTB), or A>B (AGTB) B0 B1 B3 B2 A3 Xi Yi FA Ci1 Ci Si S3
NF CF A2 Xi Yi FA Ci1 Ci Si S2
VF A1 Xi Yi FA Ci1 Ci Si S1 A0 Xi Yi FA Ci1 1 Ci Si S0
ZF = AEQB
185 Arithmetic Logic Unit
An arithmetic logic unit (ALU) is a multifunction multiregister ("collection of flipflops with a common flippurpose") that performs arithmetic and logical ("Boolean") operations For a fourfunction ALU, the control signals fourrequired are as follows: ALE: ALU Enable ALU ALX: ALU "X" function select ALU "X ALY: ALU "Y" function select ALU "Y AOE: A register tristate Output Enable tri 186 MODULE alu TITLE 'ALU Module' " " " " " " " " " " " " " " " " " " " " 4bit, 4function ALU with bidirectional data bus ADD: SUB: LDA: AND: OUT: AOE === 0 0 0 0 1 0 (Q3..Q0) (Q3..Q0) (Q3..Q0) (Q3..Q0) Value in ALE === 1 1 1 1 0 0 ALX === 0 0 1 1 d d < (Q3..Q0) + < (Q3..Q0) < DB3..DB0 < (Q3..Q0) & Q3..Q0 output ALY === 0 1 0 1 d d Function ======== ADD SUB LDA AND OUT <none> DB3..DB0 DB3..DB0 DB3..DB0 on data bus DB3..DB0 CF == ZF == NF == VF == > flag affected > flag not affected Note: If ALE = 0, the state of all register bits should be retained
187 ALU Multiplexer Block Diagram
ALY A1 ALY A0 X Y Cin S Ci1 i0 2:1 mux F Full Adder Cout Ci A1 ALX A0 D Q DBi AOE i0 2:1 mux F CLOCK A1 ALE A0 i0 2:1 mux F 188 DECLARATIONS CLOCK pin; " ALU control lines (enable & function select) ALE AOE ALX ALY pin; " overall ALU enable pin; " data bus tristate output enable pin; " function select pin; " Carry equations (declare as internal nodes) CY0..CY3 node istype 'com'; " Combinational ALU outputs (D flipflop inputs) " Used for flag generation (declare as internal nodes) ALU0..ALU3 node istype 'com'; " Bidirectional 4bit data bus (also, accumulator register bits) DB0..DB3 pin istype 'reg_d,buffer'; " Condition code register bits CF VF NF ZF pin pin pin pin istype istype istype istype 'reg_d,buffer'; 'reg_d,buffer'; 'reg_d,buffer'; 'reg_d,buffer'; " " " " carry flag overflow flag negative flag zero flag 189 " Declaration of intermediate equations " Least significant bit carryin (0 for ADD, 1 for SUB => ALY) CIN = ALY; " Intermediate equations for adder/subtractor SUM (S0..S7), " selected when ALX = 0 S0 S1 S2 S3 = = = = DB0.q DB1.q DB2.q DB3.q $ $ $ $ (DB0.pin (DB1.pin (DB2.pin (DB3.pin $ $ $ $ ALY) ALY) ALY) ALY) $ $ $ $ CIN; CY0; CY1; CY2; " Intermediate equations for LOAD and AND, selected when ALX = 1 L0 L1 L2 L3 = = = = !ALY&DB0.pin !ALY&DB1.pin !ALY&DB2.pin !ALY&DB3.pin # # # # ALY&DB0.q&DB0.pin; ALY&DB1.q&DB1.pin; ALY&DB2.q&DB2.pin; ALY&DB3.q&DB3.pin; 190 EQUATIONS " Ripple carry equations (CY3 is COUT) CY0 = DB0.q&(ALY$DB0.pin) # DB0.q&CIN # CY1 = DB1.q&(ALY$DB1.pin) # DB1.q&CY0 # CY2 = DB2.q&(ALY$DB2.pin) # DB2.q&CY1 # CY3 = DB3.q&(ALY$DB3.pin) # DB3.q&CY2 # " Combinational ALU equations ALU0 = !ALX&S0 # ALX&L0; ALU1 = !ALX&S1 # ALX&L1; ALU2 = !ALX&S2 # ALX&L2; ALU3 = !ALX&S3 # ALX&L3; " Register bit and data bus control equations [DB0..DB3].d = !ALE&[DB0..DB3].q # ALE&[ALU0..ALU3]; [DB0..DB3].clk = CLOCK; [DB0..DB3].oe = AOE; (ALY$DB0.pin)&CIN; (ALY$DB1.pin)&CY0; (ALY$DB2.pin)&CY1; (ALY$DB3.pin)&CY2; 191 " Flag register state equations CF.d = !ALE&CF.q # ALE&(!ALX&(CY3 $ ALY) # ALX&CF.q); CF.clk = CLOCK; ZF.d = !ALE&ZF.q # ALE&(!ALU3&!ALU2&!ALU1&!ALU0); ZF.clk = CLOCK; NF.d = !ALE&NF.q # ALE&ALU3; NF.clk = CLOCK; VF.d = !ALE&VF.q # ALE&(!ALX&(CY3 $ CY2) # ALX&VF.q); VF.clk = CLOCK; END 192 Clicker Quiz
193 Clicker Quiz
1. The condition code bits are generated based on the "D" inputs to the accumulator register flip flops rather than on its "Q" outputs because: A. we want the flags loaded into the condition code bits to reflect the arithmetic result loaded into the accumulator B. we want to reduce the load on the "Q" output bits C. the "Q" output signals are not available D. the "D" input signals are not inverted E. none of the above
194 Clicker Quiz
2. The condition code bits ("flags") need to be latched because : A. the state of the accumulator changes on each clock cycle B. a new arithmetic or logical result is computed on every clock cycle C. condition code bits that are not affected by a certain operation should stay in the same state D. when the AOE signal is negated, the state of the condition code bits might change if they were not latched 195 E. none of the above 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5E Carry LookAhead Adder Circuits
196 Reading Assignment: 3rd Ed., pp. 434438, 443444; 4344434th Ed., pp. 478482, 484488 478484Instructional Objectives:
To learn how to design faster adder/subtractor circuits using carry lookahead techniques lookTo learn how "hybrid" groupripple adder groupcircuits can be constructed using CLA blocks Outline:
Overview Carry LookAhead Adder Derivation LookCarry LookAhead Adder Organization Look197 Overview
In a previous module, we looked at one method of constructing an ndigit binary nadder from n full adders: connecting the carry out from one stage to the carry in of the next in a ripple fashion For large values of n, the propagation delay of a ripple adder can be excessive A significant speedup could be obtained by speedcalculating the carries in parallel, rather parallel, than iteratively a design that accomplishes this goal is the carry looklookahead (CLA) adder circuit (lookahead (lookanticipated) anticipated) 198 CLA Derivation
Consider the 4bit binary adder: 4Stage: Augend: Addend: Sum: 3 X3 Y3 S3 2 X2 Y2 S2 1 X1 Y1 S1 0 X0 Y0 S0
199 CLA Derivation
Definition: Definition: The generate function Gi = 1 if there is a carry out of stage i regardless of whether or not there is a carry in to stage i (i.e., both Xi and Yi are 1) G =X Y
i i i Definition: Definition: The propagate function Pi = 1 if a carry in to stage i will cause a carry out of stage i (i.e., either Xi = 0 and Yi = 1 or Xi = 1 and Yi = 0) P =X Y
i i i NOTE: Another valid definition of Pi is Xi+Yi the "XOR" definition leads to some CLA circuit simplifications, however 200 CLA Derivation
Illustration of propagate and generate 1 1 x 1 1 x + x 0 1 x Generate from stage 1 Propagated by stage 2
201 CLA Derivation
Note that the Pi and Gi functions can be generated using a half adder Xi 0 0 1 1 Yi 0 1 0 1 Ci 0 0 0 1 Si 0 1 1 0 Pi = Si = Xi Yi Gi = Ci = Xi Yi 202 CLA Derivation
Next we would like to write our basic full adder equations in terms of propagate and generate functions To do this, we will need to reexamine the Kmaps for the sum and carry equations of the full adder 203 Full Adder Review
Xi 0 0 0 0 1 1 1 1 Yi 0 0 1 1 0 0 1 1 Ci1 0 1 0 1 0 1 0 1 Ci 0 0 0 1 0 1 1 1 Si 0 1 1 0 1 0 0 1 204 Full Adder Review
Map of sum function: X Ci1 Ci1
0 2 X 1 0 Y
6 0
1 0 1 4 1 0 Y 1 Y 3 7 5 Si = Xi Yi Ci1 = Pi Ci1
205 Full Adder Review
Map of carry function: X Ci1 Ci1
0 2 X 0 1 Y
6 0
1 1 1 4 0 1 Y 0 Y 3 7 5 Ci = XiYi + Ci1(Xi Yi) = Gi + Ci1Pi
206 CLA Derivation
Rewriting the equations for our 4bit 4binary adder, we obtain the following: C1 = Cin C0 = G0 + CinP0 C1 = G1 + C0P1 C2 = G2 + C1P2 C3 = Cout = G3 + C2P3
207 CLA Derivation
We would like to write these equations in terms of available inputs (P's, G's, and Cin) rather than the intermediate carries (C0, C1, etc.) the key to doing this is successive expansion of the previous equations in terms of the equation for C0: C1 = G1 + C0P1 = G1 + (G0 + CinP0) P1 208 CLA Derivation
C1 = G1 + C0P1 = G1 + (G0 + CinP0)P1 What is this equation "saying"? = G1 + G0P1 + CinP0P1
Each term represents one possibility for obtaining a carry out of stage 1: there is a generate in stage 1 (G1 = 1) there is a generate in stage 0 (G0 = 1) which is propagated by stage 1 (P1 = 1) there is a carry in (Cin = 1) which is propagated by stages 0 (P0=1) and 1 (P1=1)
209 CLA Derivation Exercise
Write the remaining 4bit CLA adder carry 4equations: C2 = C3 = 210 CLA Derivation Exercise
Write the remaining 4bit CLA adder carry 4equations: C2 = G2 + G1P2 + G0P1P2 + CINP0P1P2 C3 = 211 CLA Derivation Exercise
Write the remaining 4bit CLA adder carry 4equations: C2 = G2 + G1P2 + G0P1P2 + CINP0P1P2 C3 = G3 + G2P3 + G1P2P3 + G0P1P2P3 + CINP0P1P2P3
212 CLA Organization
A3 B3 Xi Yi HA Ci Si G3 P3 Cout A2 B2 Xi Yi HA Ci Si G2 P2 A1 B1 Xi Yi HA Ci Si G1 P1 A0 B0 Xi Yi HA Ci Si G0 P0 Cin Carry and Sum Equations Si = Pi Ci1 S3 S2 S1 S0 Ci = Gi + Gi1Pi + Gi2Pi1Pi + ... + CinP0P1Pi where Gj = AjBj and Pj = AjBj 213 Observations
Note that regardless of the adder length (n), (n the time required to produce any sum digit is the same i.e., all sum digits are produced in parallel Large CLA adders are difficult to build in practice because of the "product term explosion" that occurs as the carry equations are expanded A reasonable compromise is to make a group ripple adder by cascading mbit CLA blocks together to make a kxmbit adder (where k is the number of CLA blocks)
214 16bit groupripple adder implemented using 74x283 4bit CLAs 215 Example: Implement a 4bit CLA using a 26V12, based on the following declarations
MODULE cla4 TITLE '4bit Carry LookAhead Adder for 26V12' DECLARATIONS X0..X3, Y0..Y3 pin; CIN pin; " carry in " sum outputs " carry outputs (C3 is carry out) " propagate functions " operands S0..S3 pin istype 'com'; C0..C3 pin istype 'com'; P0..P3 pin istype 'com'; G0 = X0&Y0; G1 = X1&Y1; G2 = X2&Y2; G3 = X3&Y3; " generate functions 216 Example: Implement a 4bit CLA using a 26V12, based on the following declarations
EQUATIONS P0 = X0$Y0; P1 = X1$Y1; P2 = X2$Y2; P3 = X3$Y3; C0 = G0 # CIN&P0; C1 = G1 # G0&P1 # CIN&P0&P1; C2 = G2 # G1&P2 # G0&P1&P2 # CIN&P0&P1&P2; C3 = G3 # G2&P3 # G1&P2&P3 # G0&P1&P2&P3 # CIN&P0&P1&P2&P3; S0 = CIN$P0; S1 = C0$P1; S2 = C1$P2; S3 = C2$P3; END
217 Example: Implement a 4bit CLA using a 26V12, based on the following declarations
EQUATIONS P0 = X0$Y0; P1 = X1$Y1; P2 = X2$Y2; P3 = X3$Y3; C0 = G0 # CIN&P0; C1 = G1 # G0&P1 # CIN&P0&P1; C2 = G2 # G1&P2 # G0&P1&P2 # CIN&P0&P1&P2; C3 = G3 # G2&P3 # G1&P2&P3 # G0&P1&P2&P3 # CIN&P0&P1&P2&P3; S0 = CIN$P0; S1 = C0$P1; S2 = C1$P2; S3 = C2$P3; END If a 10 ns PLD is used, what is the worst case propagation delay? 30 ns _____
218 Clicker Quiz
219 MODULE cla4_v2 TITLE '4bit Carry LookAhead Adder Block Version 2' DECLARATIONS X0..X3, Y0..Y3 pin; " operands CIN pin; " carry in (Cin) C0..C3 pin istype 'com'; " carry equations (C3 is Cout) S0..S3 pin istype 'com'; " sum outputs G0 G1 G2 G3 P0 P1 P2 P3 = = = = = = = = X0&Y0; X1&Y1; X2&Y2; X3&Y3; X0$Y0; X1$Y1; X2$Y2; X3$Y3; " generate function declarations " propagate function declarations EQUATIONS " carry C0 = G0 C1 = G1 C2 = G2 C3 = G3 equations # CIN&P0; # G0&P1 # CIN&P0&P1; # G1&P2 # G0&P1&P2 # CIN&P0&P1&P2; # G2&P3 # G1&P2&P3 # G0&P1&P2&P3 # CIN&P0&P1&P2&P3; " sum equations S0 = CIN$P0; S1 = C0$P1; S2 = C1$P2; S3 = C2$P3; END 220 Clicker Quiz
1. If coded as shown, the number of product terms required to implement the equation for C1 would be:
A. B. C. D. E. 3 4 7 10 none of the above
221 Clicker Quiz
2. If coded as shown, the number of product terms required to implement the equation for S1 would be:
A. B. C. D. E. 3 4 7 10 none of the above
222 Clicker Quiz
3. If coded as shown and realized in an Nnanosecond PLD, the worst case propagation delay (in nanoseconds) would be:
A. B. C. D. E. N 2N 3N 4N none of the above
223 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5F Multiplier Circuits
224 Reading Assignment: 3rd Ed., pp. 4547, 446450; 454464th Ed., pp. 4547, 494497 45494Instructional Objective:
To learn how to design combinational multiplier circuits Outline:
Overview Circuit Generalizations Realizations in ABEL
225 Overview
Consider a 3x3 unsigned binary multiplication:
Multiplicand: Multiplier: X2 X1 X0 Y2 Y1 Y0  226 Overview
Consider a 3x3 unsigned binary multiplication:
Multiplicand: Multiplier: X2 X1 X0 Y2 Y1 Y0 X2Y0 X1Y0 X0Y0 227 Overview
Consider a 3x3 unsigned binary multiplication:
Multiplicand: Multiplier: X2 X1 X0 Y2 Y1 Y0 X2Y0 X1Y0 X0Y0 X2Y1 X1Y1 X0Y1 228 Overview
Consider a 3x3 unsigned binary multiplication:
Multiplicand: Multiplier: X2 X1 X0 Y2 Y1 Y0 X2Y0 X1Y0 X0Y0 X2Y1 X1Y1 X0Y1 X2Y2 X1Y2 X0Y2  229 Overview
Consider a 3x3 unsigned binary multiplication:
Multiplicand: Multiplier: X2 X1 X0 Y2 Y1 Y0 X2Y0 X1Y0 X0Y0 X2Y1 X1Y1 X0Y1 X2Y2 X1Y2 X0Y2 P4 P3 P2 P1 P0 P5 Product 230 Overview
Most approaches to (unsigned) combinational binary multiplication are based on the "paper"paperandandpencil" shift and add algorithm Each row is called a product component a shifted multiplicand that is multiplied by 0 or 1 depending on the corresponding multiplier bit Each xiyj term represents a product component bit (the logical AND of multiplicand bit xi with multiplier bit yj) The product P = p5p4p3p2p1p0 is obtained by adding together all the product components
231 3x3 Circuit (2 diagonals, 3 rows)
X Y Z X Y Z CS CS X CS Y Z X CS Y Z X CS Y Z X CS Y Z 232 3x3 Circuit
X Y Z X Y Z CS CS X CS Y Z X CS Y Z X0 Y0 X CS Y Z X CS Y Z P0 233 X1 Y0 3x3 Circuit
X Y Z X Y Z CS CS 0 X CS Y Z X CS Y Z X0 Y0 X CS Y Z X CS Y Z P1 P0 234 X2 Y0 X1 Y0 3x3 Circuit
X Y Z X
0 CS CS Y Z 0 X CS Y Z X CS Y Z X0 Y2 X0 Y0 X CS Y Z X CS Y Z P2 P1 P0 235 X2 Y0 X1 Y0 3x3 Circuit
X
X2 Y1 CS Y Z X
0 CS Y Z 0 X CS Y Z X
0 CS Y Z X0 Y2 X0 Y0 X CS Y Z X CS
P3 Y Z X1 Y2 P2 P1 P0 236 X2 Y0 X1 Y0 3x3 Circuit
X
X2 Y1 CS Y Z X
0 CS Y Z 0 X
X2 Y2 CS Y Z X
0 CS Y Z X0 Y2 X0 Y0 X CS
P5 P4 Y Z X CS
P3 Y Z X1 Y2 P2 P1 P0 237 X2 Y0 X1 Y0 Critical Path Analysis
X
X2 Y1 CS Y Z X
0 CS Y Z 0 X
X2 Y2 CS Y Z X
0 CS Y Z X0 Y2 X0 Y0 X CS
P5 P4 Y Z X CS
P3 Y Z X1 Y2 P2 P1 P0 238 X2 Y0 X1 Y0 Critical Path Analysis
X
X2 Y1 CS Y Z X
0 CS Y Z 0 X
X2 Y2 CS Y Z X
0 CS Y Z X0 Y2 X0 Y0 X CS
P5 P4 Y Z X CS
P3 Y Z X1 Y2 P2 P1 P0 239 Generalizations
Generalizations for an NxM multiplier N = number of bits in multiplicand (top) M = number of bits in multiplier (bottom) produces an N+M digit result requires NxM AND gates to generate the product components requires N1 diagonals of full adders requires M rows of full adders 240 Exercise
Design a 4x2 multiplier array X3 X2 X1 Y1 X1Y0 X0Y1 P1 X0 Y0 X0Y0 P0 X3Y1 P5 P4 X3Y0 X2Y1 P3 X2Y0 X1Y1 P2 241 4x2 Circuit (3 diagonals, 2 rows)
X3 Y0 X2 Y0 X1 Y0 X
X3 Y1 CS Y Z X
0 CS Y Z X
0 CS Y Z 0 X0 Y0 X CS
P5 P4 Y Z X CS
P3 Y Z X CS
P2 Y Z 0 P1 P0
242 Exercise
Design a 2x4 multiplier array Y1 X1 X0Y1 X1Y0 Y0 X0 X0Y0 X3 X2 X3Y1 P5 P4 X2Y1 X3Y0 P3 X1Y1 X2Y0 P2 P1 P0
243 2x4 Circuit (1 diagonal, 4 rows)
X1 Y1 X1 Y0 X
X2 Y1 CS
X Y Z 0 CS
X3 Y1 Y Z X2 Y0 X0 Y0 X CS
X Y Z
0 Y Z X3 Y0 CS
P5 P4 P3 P2 P1 P0 244 2x4 Circuit implemented using 4bit adder
X3 Y1 X2 Y1 X1 Y1 X0 Y1 X3 Y0 X2 Y0 X1 Y0 X0 Y0 0 X3 X2 X1 X0 Cout Y3 Y2 Y1 Y0 Cin
0 4bit Adder S3 S2 S1 S0 P5 P4 P3 P2 P1 P0
245 Clicker Quiz
246 Clicker Quiz
1. A 6x4 unsigned binary multiplier array would require ___ rows of full adder cells.
A. B. C. D. E. 3 4 5 6 none of the above
247 Clicker Quiz
2. A 6x4 unsigned binary multiplier array would require ___ "diagonals" of full adder cells.
A. B. C. D. E. 3 4 5 6 none of the above
248 Clicker Quiz
3. A 6x4 unsigned binary multiplier array would require ___ full adder cells.
A. B. C. D. E. 10 18 20 24 none of the above 249 Clicker Quiz
4. A 6x4 unsigned binary multiplier array would require ___ AND gates to generate the product component bits.
A. B. C. D. E. 10 18 20 24 none of the above
250 Clicker Quiz
5. Assuming a large 10 ns PLD was used to generate each product component bit and implement each full adder cell, the worst case propagation delay of a 6x4 unsigned binary multiplier array would be ___ ns.
A. B. C. D. E. 80 90 100 110 none of the above 251 Clicker Quiz
6. A 4x6 unsigned binary multiplier array would require ___ rows of full adder cells.
A. B. C. D. E. 3 4 5 6 none of the above
252 Clicker Quiz
7. A 4x6 unsigned binary multiplier array would require ___ "diagonals" of full adder cells.
A. B. C. D. E. 3 4 5 6 none of the above
253 Clicker Quiz
8. A 4x6 unsigned binary multiplier array would require ___ full adder cells.
A. 10 B. 18 C. 20 D. 24 E. none of the above 254 Clicker Quiz
9. A 4x6 unsigned binary multiplier array would require ___ AND gates to generate the product component bits.
A. B. C. D. E. 10 18 20 24 none of the above
255 Clicker Quiz
10. Assuming a large 10 ns PLD was used to generate each product component bit and implement each full adder cell, the worst case propagation delay of a 4x6 unsigned binary multiplier array would be ___ ns.
A. B. C. D. E. 80 90 100 110 none of the above 256 Realizations in ABEL
Keys use expressions to define product components use addition operator (+) to form unsigned sum of product components Example: 4x4 multiplier realization 257 MODULE mul4x4 TITLE '4x4 Combinational Multiplier' DECLARATIONS X3..X0, Y3..Y0 pin; " multiplicand, multiplier P7..P0 pin istype 'com'; " product bits P = [P7..P0]; " Definition of product components PC1 = Y0 & [ 0, 0, 0, 0,X3,X2,X1,X0]; PC2 = Y1 & [ 0, 0, 0,X3,X2,X1,X0, 0]; PC3 = Y2 & [ 0, 0,X3,X2,X1,X0, 0, 0]; PC4 = Y3 & [ 0,X3,X2,X1,X0, 0, 0, 0]; EQUATIONS " Form unsigned sum of product components P = PC1 + PC2 + PC3 + PC4;
END Will fit in a Mach 432/32
258 P7.X1 = (X3 & X2 & Y2 & Y3 # Y1 & X3 & Y0 & X2 & Y3 # Y1 & X3 & X2 & X1 & Y3 # Y1 & X3 & X2 & X0 & Y3 # X3 & Y0 & X2 & X1 & X0 & Y3 # Y1 & X3 & Y0 & !X1 & X0 & Y2 & Y3 # !Y1 & X3 & !Y0 & X1 & !X0 & Y2 & Y3); P7.X2 = (X3 & !X2 & X1 & Y2 & Y3); P6.X1 = (P6_0 # !Y1 & X3 & !X1 & Y3 # X3 & !X2 & !Y2 & Y3 # !X3 & X2 & Y2 & !Y3 # X3 & !X1 & !X0 & Y2 & Y3); P6.X2 = (X2 & Y2); P5.X1 = (P5_0 # P5_1 # !Y1 & X2 & !Y2 & !Y3); P5.X2 = (!Y1 & X2); P4.X1 = (P4_0 # P4_1 # !Y1 & X1 & !X0 & !Y2 & Y3 # !X2 & X1 & !X0 & !Y2 & Y3 # !Y1 & !Y0 & X2 & Y2 & !Y3 # !Y0 & X2 & !X1 & Y2 & !Y3); P4.X2 = (Y1 & X3); P3.X1 = (P3_0 # !X2 & X1 & !X0 & Y2 # !Y1 & X0 & !Y2 & Y3); P3.X2 = (X3 & Y0); Equations Generated
P2.X1 = (Y1 & X1 & !X0 # !Y1 & X0 & Y2 # Y0 & X0 & Y2 # !X1 & X0 & Y2 # Y1 & !Y0 & X1 & !Y2); P5_0 = (!Y1 & X3 & Y0 & X2 & X1 & X0 # !Y1 & X3 & !Y0 & !X2 & !X0 & Y2 # Y1 & X3 & Y0 & X1 & X0 & !Y2 # Y1 & X3 & Y0 & X1 & X0 & Y3 # Y1 & Y0 & !X2 & X1 & X0 & Y3 # Y1 & !X3 & X2 & !X1 & !X0 & Y3 # Y1 & !Y0 & X2 & !X1 & !X0 & Y3 P6_0 = (!Y1 & X3 & !Y0 & X2 & Y2 # !Y1 & !Y0 & X2 & !X1 & Y2 # !Y1 & X2 & !X1 & !X0 & Y2 # !X3 & X2 & !X1 & !X0 & Y2 # !Y1 & X3 & !Y0 & X2 & Y3 # X3 & !Y0 & !X2 & !X1 & Y3 # !Y1 & X3 & !Y0 & !X0 & Y3 # !Y1 & X3 & X2 & !X0 & Y3 # X3 & !Y0 & !X1 & !X0 & Y3 # X3 & !X2 & !X1 & !X0 & Y3 # X3 & !Y0 & !X1 & Y2 & Y3 # Y1 & !X3 & Y0 & X2 & X1 & !Y2 & Y3 # Y1 & !X3 & X2 & X1 & X0 & !Y2 & Y3 # Y1 & X3 & Y0 & !X2 & X1 & Y2 & !Y3 # Y1 & X3 & !X2 & X1 & X0 & Y2 & !Y3); P3_0.X1 = (!X2 & !X1 & X0 # Y1 & !Y0 & !X2 & X0 # Y0 & X2 & X1 & X0 # Y1 & X2 & !X1 & !X0 # Y1 & Y0 & X2 & Y2 # Y1 & Y0 & X1 & Y2 # !Y1 & X1 & !X0 & Y2 # !Y1 & !Y0 & X2 & !X1 & X0 # Y1 & !Y0 & X2 & !X0 & !Y2 # !Y1 & X1 & X0 & !Y2 & !Y3 # !Y1 & X2 & !X1 & X0 & !Y2 & !Y3); P5_1 = (!Y1 & X3 & !X2 & !X1 & Y2 # X3 & !Y0 & !X1 & Y2 & Y3 # !X3 & X1 & X0 & Y2 & Y3 # X3 & !X1 & !X0 & Y2 & Y3 # !Y1 & !X3 & !Y0 & X2 & !Y3 # !Y1 & !X3 & X2 & !X0 & !Y3 # !Y1 & X3 & !X2 & Y2 & !Y3 # X3 & !X2 & !X1 & Y2 & !Y3 # X3 & Y0 & X2 & !Y2 & !Y3 # Y1 & !X3 & X2 & !X1 & !Y2 & Y3 # X3 & Y0 & X1 & X0 & !Y2 & Y3 # !Y1 & Y0 & X2 & X1 & !X0 & !Y3 # Y1 & !X3 & X2 & X1 & Y2 & !Y3 # Y1 & Y0 & X2 & X1 & Y2 & !Y3 # X3 & !Y0 & !X2 & !X0 & Y2 & !Y3); # !Y1 & !X3 & X2 & X1 & Y2 & Y3 # Y1 & Y0 & X1 & X0 & Y2 & Y3 # Y1 & X3 & !X2 & X1 & !Y2 & Y3 # !Y1 & !X3 & Y0 & X2 & !X1 & X0 & Y2 # Y1 & X3 & Y0 & !X2 & X0 & !Y2 & Y3 # Y1 & !X3 & !Y0 & X2 & !X0 & !Y2 & Y3 # Y1 & !X3 & Y0 & X2 & X0 & Y2 & !Y3 # !Y1 & X3 & Y0 & !X1 & X0 & Y2 & !Y3); P4_0 = (Y1 & X3 & Y0 & X2 & X1 & X0 # Y1 & X3 & Y0 & X1 & X0 & Y2 # Y1 & X3 & Y0 & X2 & !X1 & !Y2 # !Y1 & !X3 & X2 & X1 & X0 & Y3 # !Y1 & !Y0 & X2 & X1 & X0 & Y3 # Y1 & X3 & Y0 & !X1 & X0 & Y3 # X3 & Y0 & !X2 & !X1 & X0 & Y3 # Y1 & !X3 & X1 & !X0 & Y2 & Y3 # X3 & Y0 & !X1 & X0 & !Y2 & Y3 # Y1 & X2 & !X1 & X0 & !Y2 & Y3 # Y1 & X3 & Y0 & X2 & X1 & !Y3 # Y1 & X3 & Y0 & X1 & X0 & !Y3 # Y1 & X3 & Y0 & X1 & Y2 & !Y3 # X3 & Y0 & !X2 & X1 & Y2 & !Y3 # !Y1 & X3 & Y0 & X2 & X1 & !X0 & Y3); P4_1 = (!Y1 & !Y0 & X2 & !X1 & Y2 # !Y1 & X2 & !X1 & !X0 & Y2 # !X3 & X2 & !X1 & !X0 & Y2 # !Y0 & X2 & !X1 & !X0 & Y2 # Y1 & !Y0 & X1 & !X0 & Y3 # !X3 & !X2 & X1 & !X0 & Y3 # !Y0 & !X2 & X1 & !X0 & Y3 # !Y1 & !X3 & X1 & !Y2 & Y3 # !Y1 & !Y0 & X1 & !Y2 & Y3 # !Y0 & !X2 & X1 & !Y2 & Y3 # !Y1 & !X3 & X2 & !X1 & Y2 & !Y3 # Y1 & Y0 & X1 & X0 & Y2 & !Y3 # Y1 & !X2 & X1 & X0 & Y2 & !Y3 # !Y1 & !X3 & X2 & !X0 & Y2 & !Y3 # Y1 & Y0 & X2 & X1 & !Y2 & !Y3); P3_0.X2 = (X0 & !Y3); P2.X2 = (Y0 & X2); P1.X1 = (Y1 & X0); P1.X2 = (Y0 & X1); P0 = (Y0 & X0); 259 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 5G BCD Adder Circuits
260 Reading Assignment: 3rd Ed., pp. 4851; 4th Ed., pp. 4851 Ed. 4848Instructional Objective:
To learn how to design a decimal adder circuit Outline:
Overview General Circuit Model Decimal Addition and Correction Decimal Adder Circuits
261 Overview
Even though binary numbers are the most appropriate for the internal computations of a digital system, most people still prefer to deal with decimal numbers External interfaces of a digital system may need to read or display decimal numbers, and therefore need to perform arithmetic on decimal numbers directly The most commonly used decimal code is binarybinarycoded decimal (BCD) Some computers place two BCD digits in an 8bit byte ("packedBCD format") 8("packed262 Overview
Consider the problem of adding a pair of BCD digits the objective is to design a circuit that adds the two 4bit codes along 4with a carry in to produce a 4bit coded sum 4digit plus a carry out We would like to use standard 4bit binary 4adder modules (with which we are already familiar) as basic building blocks Note that because there are six "unused combinations" in BCD, a correction must be performed if the direct sum of the two 4bit 4codes exceeds 1001
263 General Circuit Model
General circuit model: Conventional 4bit binary adder Z4Z3Z2Z1Z0 is the direct sum obtained from the 4bit adder
264 Decimal Addition and Correction
3 + 4 7 0011 + 0100 0111 Result of ADD Here, direct addition of the 4bit BCD codes yields the correct 4bit BCD code for the sum digit
265 Decimal Addition and Correction
7 + 8 15 0111 + 1000 1111 + 0110 1 0101 Result of ADD Since result > 9, add 6 to adjust Carry out = ten's position
266 Decimal Addition and Correction
7 + 9 16 0111 + 1001 10000 + 0110 1 0110 Result of ADD Since result > 9, add 6 to adjust Carry out = ten's position
267 Decimal Adder Circuits
Summary of rules If the sum of the two BCD digits is less than or equal to nine (1001), no correction is needed If the sum is greater than nine, the result obtained directly from the 4bit adder 4must be corrected in order to represent the proper BCD digit Some microprocessors include a "decimal adjust" (DAA) instruction for performing this correction following the addition of BCD operands
268 N10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Z4 Z3 Z2 Z1 Z0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 Cout S3 S2 S1 S0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 Correction <none> <none> <none> <none> <none> <none> <none> <none> <none> <none> <add 6> <add 6> <add 6> <add 6> <add 6> <add 6> <add 6> <add 6> <add 6> <add 6> 269 BCD operands Cin BCD "Full Adder" Circuit Cout BCD sum
270 Example: The maximum value that can be
generated by a BCD full adder cell is 1910. Write the binary values (bit patterns) that depict this case.
1 1 1 1 0 0 0 1
X3 X2 X1 X0 Cout 1 1 0 0 1 0 0 0 Y3 Y2 Y1 Y0 Cin 4bit Adder S3 S2 S1 S0 1 10011 Z4 Z3 Z2 Z1 Z0 Correction Circuit S3 S2 S1 S0 Cout 1 1 0 0 1 271 Clicker Quiz
272 Clicker Quiz
1. If the BCD codes for 8 and 5 were added using a decimal full adder cell, with CIN = 1, the resulting 5bit output (Cout S3 S2 S1 S0) would be:
A. B. C. D. E. 01101 01110 10011 10100 none of the above 273 Clicker Quiz
2. If the BCD codes for 4 and 5 were added using a decimal full adder cell, with CIN = 1, the resulting 5bit output (Cout S3 S2 S1 S0) would be:
A. B. C. D. E. 01001 01010 10000 10001 none of the above 274 Decimal Adder Circuits
Thought questions: How could an ndigit BCD adder be constructed using the "decimal full adder" circuit just designed? How could this ndigit BCD adder be made ninto an ndigit BCD adder/subtractor? nadder/subtractor? Hint: How could the radix complement of a BCD digit (where the radix or base is 10) be generated? 275 Example: Design a circuit (ABEL file) that
generates the diminished radix (or 9's) complement of a BCD digit
MODULE ninescmp TITLE 'Nines Complement Box' DECLARATIONS X3..X0 pin; " Input code Y3..Y0 pin istype 'com'; " Output code TRUTH_TABLE ([X3, X2, X1, X0]>[Y3, Y2, Y1, Y0]) [ 0, 0, 0, 0]>[ 1, 0, 0, 1]; [ 0, 0, 0, 1]>[ 1, 0, 0, 0]; [ 0, 0, 1, 0]>[ 0, 1, 1, 1]; [ 0, 0, 1, 1]>[ 0, 1, 1, 0]; [ 0, 1, 0, 0]>[ 0, 1, 0, 1]; [ 0, 1, 0, 1]>[ 0, 1, 0, 0]; [ 0, 1, 1, 0]>[ 0, 0, 1, 1]; [ 0, 1, 1, 1]>[ 0, 0, 1, 0]; [ 1, 0, 0, 0]>[ 0, 0, 0, 1]; [ 1, 0, 0, 1]>[ 0, 0, 0, 0]; END
276 ...
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This note was uploaded on 02/05/2012 for the course ECE 270 taught by Professor Staff during the Spring '08 term at Purdue University.
 Spring '08
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