2-Mod6_CP_2011

2-Mod6_CP_2011 - 2011 Edition by D. G. Meyer Introduction...

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Unformatted text preview: 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6 Design and Implementation of a Simple Computer 1 Module 6 Desired Outcome: "An ability to design and implement a simple computer" Part A: Top-Down Specification Top Part B: Instruction Execution Tracing Part C: Bottom-Up Implementation Bottom Part D: Basic Extensions Part E: Advanced Extensions 2 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-A Top-Down Specification 3 Reading Assignment: 3rd Ed., pp. 750-753; 4th Ed., pp. 758-761; 750758Meyer Supplemental Text, pp. 1-18 Text, 1Instructional Objectives: To learn about top-down, bottom-up system topbottomdesign methodology To learn about the structure of a simple computer 4 Outline Introduction TopTop-Down, Bottom-Up Design Methodology BottomSimple Computer "Big Picture" A Simple Instruction Set A Simple Programming Example System Block Diagram 5 Introduction The focus thus far has been on a number of digital system "building blocks" state machines latches and flip-flops flip arithmetic logic circuits decoders, encoders, multiplexers basic gates (NAND, NOR, XOR, etc.) Question: Question: What is the primary utility of these building blocks? Building a computer or interfacing to an existing one 6 Introduction Question: Question: What is a computer? A device that sequentially executes a stored program Question: Question: What is a microprocessor? A single-chip embodiment of the major functional blocks of a computer Question: Question: What is a microcontroller? A microprocessor with a number of integrated peripherals typically used in control-oriented applications 7 Introduction Question: Question: How can we apply what we know about various digital system building blocks to design a simple computer? We need a structured approach that enables us to transform a "word" description of what a computer does into a block diagram Definition: Definition: The architecture of a computer is the arrangement and interconnection of its functional blocks 8 Introduction Analogy: Analogy: Designing and building a house - 1 Start with the "big picture"... 9 Introduction Analogy: Analogy: Designing and building a house - 2 Then develop a "floor plan"... 10 Introduction Analogy: Analogy: Designing and building a house - 3 Then embellish the floor plan with details (outlets, lights, plumbing, HVAC, etc.) 11 Introduction Analogy: Analogy: Designing and building a house - 4 When you're ready to build, how do you proceed? From the ground-up start with the foundation, create basic structure, embellish with finishing details Question: Question: What would you call the basic procedure we have just described? Top-down specification of functionality, bottom-up implementation of basic blocks 12 Simple Computer "Big Picture" We wish to apply this "top-down, bottom-up" "topbottommethodology to the design of a simple 8-bit 8computer (or, "microprocessor") First step: Draw the big picture step: LED Output Port Switch Input Port Start Clock 13 Simple Computer "Floor Plan" Question: Question: In the design of a computer, what is analogous to the floor plan of a house? The computer's programming model and instruction set Definition: Definition: The programming model of a computer is the set of "user" registers available to the programmer Definition: Definition: A collection of two or more flipflipflops with a common clock (and generally a common purpose) is called a register In the simple computer designed here, the programming model will contain a single data register "where the result accumulates" (the accumulator, or "A register" for short), 14 plus condition codes (CF, VF, NF, ZF) Simple Computer "Floor Plan" Definition: Definition: The instruction set of a computer is the set of operations the computer can be programmed to perform on data Instructions typically consist of several fields that indicate the operation to be performed ("operation code", or opcode) and the data opcode) on which the operation is to be performed (specified using an addressing mode) mode) Our 8-bit computer will utilize a 3-bit opcode 83field (thus allowing 8 different kinds of instructions to be implemented) and a 5-bit 5address field (thus allowing 32 locations) 15 Simple Computer "Floor Plan" Instruction format: XXX YYYYY XXX indicates operation to perform YYYYY indicates location of operand Called a "two address machine" since one operand will be the accumulator ("A") register and the other operand will be obtained from the specified location in memory 16 Simple Computer "Floor Plan" Instruction set: Opcode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Mnemonic LDA addr STA addr ADD addr SUB addr AND addr HLT Function Performed Load A with contents of location addr Store contents of A at location addr Add contents of addr to contents of A Subtract contents of addr from contents of A AND contents of addr with contents of A Halt Stop, discontinue execution Note: We will use parentheses to denote the contents of a register or memory location, e.g., "(A)" is read as "the contents of A" 17 Simple Programming Example Addr 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 Instruction LDA 01011 ADD 01100 STA 01101 LDA 01011 AND 01100 STA 01110 LDA 01011 SUB 01100 STA 01111 HLT Comments Load A with contents of location 01011 Add contents of location 01100 to A Store contents of A at location 01101 Load A with contents of location 01011 AND contents of 01100 with contents of A Store contents of A at location 01110 Load A with contents of location 01011 Subtract contents of location 01100 from A Store contents of A at location 01111 Stop discontinue execution 18 Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 10101010 01010101 Memory "Snapshot" 19 Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 10101010 01010101 Memory "Snapshot" Program Operands Results 20 Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 10101010 01010101 11111111 Add: 10101010 +01010101 11111111 CF = 0 NF = 1 VF = 0 ZF = 0 21 Add Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 10101010 01010101 11111111 00000000 AND: 10101010 01010101 00000000 CF = <unaffected> NF = 0 VF = <unaffected> ZF = 1 AND 22 Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 10101010 01010101 11111111 00000000 01010101 Sub: 10101010 -01010101 CF = 0 NF = 0 VF = 1 ZF = 0 10101010 10101010 + 1 1)01010101 Overflow! Sub 23 Simple Computer Block Diagram Question: Question: What functional blocks are necessary to implement a computer that executes a stored program consisting of the instructions we have just defined? Two basic steps are required to perform an instruction: (1) it must be fetched from memory, and (2) it must be decoded and executed 24 Simple Computer Block Diagram Functional blocks required: a place to store the program, operands, and computation results memory a way to keep track of which instruction is to be executed next program counter (PC) a place to temporarily "stage" an instruction while it is being executed instruction register (IR) a way to perform arithmetic and logic operations arithmetic logic unit (ALU) a way to coordinate and sequence the functions of the machine instruction decoder and micro-sequencer (IDMS) micro25 Data Memory Address 26 Program Counter Memory Address Data Address Bus 27 Program Counter Opcode Address Instruction Register Memory Address Data Data Bus Address Bus 28 Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 29 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 30 Notes About Block Diagram Each functional block is "self-contained" "self(which means each block can be designed and tested independently) independently) Additional instructions can be added by increasing the number of opcode bits Additional memory can be added by increasing the number of address bits The numeric range can be expanded by increasing the number of data bits 31 Clicker Quiz 32 Q1. The place where an instruction fetched from memory is "staged" while it is being decoded and executed is the: A. accumulator B. program counter C. instruction register D. microsequencer E. none of the above 33 Q2. The next instruction to fetch from memory is pointed to by the: A. B. C. D. E. accumulator program counter instruction register microsequencer none of the above 34 Q3. If two additional address bits were added to the Simple Computer, the number of memory locations the machine could access would increase: A. by two locations B. by four locations C. by two times the original number of locations D. by four times the original number of locations E. none of the above 35 Q4. The expression (10110) means: (A) + (10110) A. replace the contents of the accumulator with the sum of its current contents plus the contents of memory location 10110 B. replace the contents of the accumulator with the sum of its current contents plus the constant 10110 C. replace the contents of memory location 10110 with the sum of its current contents plus the contents of the accumulator D. add the constant 10110 to the contents of the accumulator and store the result in memory location 10110 E. none of the above 36 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-B Instruction Execution Tracing 37 Reading Assignment: Meyer Supplemental Text, pp. 18-24 Text, 18Instructional Objective: To learn how to trace the execution of an instruction through our simple computer 38 Outline Review of top-down specification phase of topdesign process Big picture Floor plan (instruction set) Block diagram Instruction execution tracing 39 Simple Computer "Big Picture" LED Output Port Switch Input Port Start Clock 40 Simple Computer "Floor Plan" Instruction set: Opcode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Mnemonic LDA addr STA addr ADD addr SUB addr AND addr HLT Function Performed Load A with contents of location addr Store contents of A at location addr Add contents of addr to contents of A Subtract contents of addr from contents of A AND contents of addr with contents of A Halt Stop, discontinue execution 41 Simple Computer Block Diagram Functional blocks required: a place to store the program, operands, and computation results memory a way to keep track of which instruction is to be executed next program counter (PC) a place to temporarily "stage" an instruction while it is being executed instruction register (IR) a way to perform arithmetic and logic operations arithmetic logic unit (ALU) a way to coordinate and sequence the functions of the machine instruction decoder and micro-sequencer (IDMS) micro42 Data Memory Address 43 Program Counter Memory Address Data Address Bus 44 Program Counter Opcode Address Instruction Register Memory Address Data Data Bus Address Bus 45 Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 46 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 47 Instruction Tracing In our simple computer, there are two basic steps (or phases) in "processing" an instruction: Step 1: The instruction pointed to by the 1: PC is fetched from memory and loaded into the IR Step 2: Based on the opcode field of the 2: instruction in the IR, the specified operation is executed by the ALU on the data pointed by address field of the instruction in the IR To better understand fetch/execute cycles, we wish to trace through the processing of several instructions 48 Simple Programming Example Addr 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 Instruction LDA 01011 ADD 01100 STA 01101 LDA 01011 AND 01100 STA 01110 LDA 01011 SUB 01100 STA 01111 HLT Comments Load A with contents of location 01011 Add contents of location 01100 to A Store contents of A at location 01101 Load A with contents of location 01011 AND contents of 01100 with contents of A Store contents of A at location 01110 Load A with contents of location 01011 Subtract contents of location 01100 from A Store contents of A at location 01111 Stop discontinue execution 49 Instruction Trace Worksheet Instruction Decoder and Micro-Sequencer Start Clock ? Address PC IR Opcode Address ? ? ? ? ? Data CF NF VF ZF Data Data ? A register Data Bus Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 ALU ? Cycle: ________ Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Address Bus 50 Instruction Trace Worksheet 1 Instruction Decoder and Micro-Sequencer Start Clock 00000 Address PC IR Opcode Address ? ? ? ? ? Data CF NF VF ZF Data Data ? A register Data Bus START Cycle: ________ Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 ALU Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Address Bus 51 Instruction Trace Worksheet 2 Instruction Decoder and Micro-Sequencer Start Clock 00000 00001 Address PC Address Bus = 00000 52 IR Opcode Address 000 01011 ? ? ? ? Data CF NF VF ZF Data Data ? A register Data Bus = 00001011 Cycle: Fetch LDA ________ Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 ALU Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Instruction Trace Worksheet 3 Instruction Decoder and Micro-Sequencer Start Clock 00001 Address PC Address Bus = 01011 53 IR Opcode Address 000 01011 ? 1 ? 0 Data CF NF VF ZF Data Data 10101010 A register Data Bus = 10101010 Exec LDA Cycle: ________ Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 ALU Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Instruction Trace Worksheet 4 Instruction Decoder and Micro-Sequencer Start Clock 00001 00010 Address PC Address Bus = 00001 54 IR Opcode Address 010 01100 ? 1 ? 0 Data CF NF VF ZF Data Data 10101010 A register Data Bus = 01001100 Fetch ADD Cycle: ________ Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 ALU Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Instruction Trace Worksheet 5 Instruction Decoder and Micro-Sequencer Start Clock 00010 Address PC IR Opcode Address 010 01100 0 1 0 0 Data CF NF VF ZF Data Data 11111111 A register Data Bus = 01010101 Cycle: ________ Exec ADD Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 ALU Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Address Bus = 01100 55 Instruction Trace Worksheet 6 Instruction Decoder and Micro-Sequencer Start Clock 00010 00011 Address PC IR Opcode Address 001 01101 0 1 0 0 Data CF NF VF ZF Data Data 11111111 A register Data Bus = 001 01101 Fetch STA Cycle: ________ Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 ALU Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Address Bus = 00010 56 Instruction Trace Worksheet 7 Instruction Decoder and Micro-Sequencer Start Clock 00011 Address PC Address Bus = 01101 57 IR Opcode Address 001 01101 0 1 0 0 Data CF NF VF ZF Data Data 11111111 A register Data Bus = 11111111 Cycle: ________ Exec STA Location 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10101010 01010101 11111111 ALU Memory Address Contents 00001011 01001100 00101101 00001011 10001100 00101110 00001011 01101100 00101111 10100000 Notes About Instruction Tracing The clock edges drive the synchronous functions of the computer (e.g., increment program counter, load instruction register) The decoded states (here, fetch and execute) enable the combinational functions of the computer (e.g., turn on tri-state buffers) tri- 58 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-C Bottom-Up Implementation 59 Reading Assignment: 3rd Ed., pp. 693-707, 854-861, 872-881; 6938548724th Ed., pp. 710-719, 821-827, 840-849; 710821840Meyer Supplemental Text, pp. 24-42 Text, 24Instructional Objectives: To learn how to design the individual blocks of a simple computer from the "bottom-up" "bottomTo learn how to use "complex" programmable logic devices (CPLDs) To learn a general procedure for understanding data flow and timing analysis 60 Outline BottomBottom-up Implementation Phase of Design Process Memory Program Counter Instruction Register Arithmetic Logic Unit Instruction Decoder and Microsequencer System Data Flow and Timing Analysis 61 BottomBottom-Up Implementation Having finished the "top-down" specification "topphase of the design process, we are now ready to implement each block identified from the "bottom-up" "bottomNote that, in practice, an important aspect of this process is to independently test (and debug) each block (or module) of the system as it is implemented If each module is independently tested and verified as it is implemented, then when the modules are assembled together into a system there is a much higher probability that it will "work the first time"! 62 Simple Computer Block Diagram Functional blocks required (review): a place to store the program, operands, and computation results memory a way to keep track of which instruction is to be executed next program counter (PC) a place to temporarily "stage" an instruction while it is being executed instruction register (IR) a way to perform arithmetic and logic operations arithmetic logic unit (ALU) a way to coordinate and sequence the functions of the machine instruction decoder and micro-sequencer (IDMS) micro63 Read/Write Memory (RWM) Memory Address Data 64 Read/Write Memory (RWM) The name read/write memory (RWM) is given to memory arrays in which we can store and retrieve information at any time Most of the RWMs used in digital systems are randomrandom-access memories (RAMs), which means that the time it takes to read or write a bit of memory is independent of the bit's location in the RAM In a static RAM (SRAM), once data is written to a given location, it remains stored as long as power is applied to the chip If power is removed, data is lost this is referred to as a volatile memory 65 Read/Write Memory (RWM) An SRAM has three (typically active low) low) control inputs: a chip select (CS) signal that serves as the overall enable for the memory chip an output enable (OE) signal that tells the memory chip to drive the data output lines with the contents of the memory location specified on its address lines a write enable (WE) signal that tells the memory chip to write the data supplied on its data input lines at the memory location specified on its address lines 66 Read/Write Memory (RWM) SRAM normally has two access operations: READ: An address is placed on the address lines while CS and OE are asserted; the latch outputs for the selected location are output on the data lines WRITE: An address is placed on the address lines, data is placed on the data lines, then CS and WE are asserted; the latches of the selected location open, and the data is stored 67 Read/Write Memory (RWM) Each bit of memory (or SRAM cell) in a static RAM behaves as the circuit depicted below When the SEL input is asserted, the stored data is placed on the cell's output When both SEL and WR are asserted, the latch is open and a new data bit is stored SRAM cells are combined in an array with additional control logic to form a complete static RAM 68 Internal Structure of 8x4 SRAM 69 Read/Write Memory (RWM) Some things to note: during read operations, the output data is a combinational function of the address inputs, so no "harm" is done by changing the address while CS and OE are asserted during write operations, data is stored in latches this means that data must meet certain setup and hold times with respect to the negation of the WE signal also during write operations, the address lines must be stable for a certain setup time before WR is asserted internally and for a hold time after WR is negated 70 Read/Write Memory (RWM) Most SRAMs utilize a bi-directional data bus bi(i.e., the same data pins are used for reading and writing data) 71 Simple Computer Memory The memory for our simple computer will contain 32 locations (5-bit address), each (58 bits wide (i.e., a "32x8" memory) The memory subsystem will have three control signals: MSL: Memory SeLect MOE: Memory Output Enable MWE: Memory Write Enable NOTE: For simplicity (and clarity) all system control signals as well as address and data bus signals will be assumed to be ACTIVE HIGH 72 Clicker Quiz 73 Q1. When a set of control signals are said to be mutually exclusive, it means that: A. all the control signals may be asserted simultaneously B. only one control signal may be asserted at a given instant C. each control signal is dependent on the others D. any combination of control signals may be asserted at a given instant E. none of the above 74 Q2. For the memory subsystem, the set of signals that are mutually exclusive is: A. B. C. D. E. MSL and MOE MSL and MWE MOE and MWE MSL, MOE, and MWE none of the above 75 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-C, continued Bottom-Up Implementation 76 Simple Computer Block Diagram Functional blocks required (review): a place to store the program, operands, and computation results memory a way to keep track of which instruction is to be executed next program counter (PC) a place to temporarily "stage" an instruction while it is being executed instruction register (IR) a way to perform arithmetic and logic operations arithmetic logic unit (ALU) a way to coordinate and sequence the functions of the machine instruction decoder and micro-sequencer (IDMS) micro77 Program Counter Memory Address Data Address Bus 78 Counter Registers (Digression) Definition: Definition: A register is a collection of two or more flip-flops with a common clock and, flipgenerally, a common purpose. Definition: Definition: The name counter is used for any clocked sequential circuit whose state diagram contains a single cycle 79 Counter Registers Definition: Definition: The modulus of a counter is the number of states in the cycle a counter with M states is called a modulo-M counter modulo(or sometimes a divide-by-M counter) divide-by- counter) Definition: Definition: A synchronous counter connects all of its flip-flop clock inputs to the same flipcommon CLOCK signal, so that all the flipflipflop outputs change state simultaneously The most commonly used counter type is an n-bit binary counter, with n flip-flops and 2n counter, flipstates, visited in the sequence 0, 1, 2, ... , 2n-1, 0, 1, 2, ... 80 Counter Registers Variations of the basic binary counter of interest include: providing an ENABLE input providing an ASYNCHRONOUS RESET providing a DOWN COUNT mode providing a SYNCHRONOUS RESET providing the capability to specify the modulus of the counter An ABEL file for an 8-bit version of each of 8the above will be illustrated; all designs fit in a single 22V10 PLD 81 Binary UP Counter The design of a basic binary UP counter is derived as follows: Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 When does Q0 change state? Every clock cycle What is the equation for Q0*? Q0* = Q0 82 Binary UP Counter The design of a basic binary UP counter is derived as follows: Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 When does Q1 change state? When Q0 = 1 What is the equation for Q1*? Q1* = Q1 Q0 83 Binary UP Counter The design of a basic binary UP counter is derived as follows: Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 When does Q2 change state? When Q0 = 1 AND Q1 = 1 What is the equation for Q2*? Q2* = Q2 (Q1 Q0) 84 Binary UP Counter The design of a basic binary UP counter is derived as follows: What is the next state equation for an arbitrary stage "K" (QK*) of a binary UP counter? QK* = QK (QK-1 QK-2 ... Q1 Q0) 85 MODULE count8 TITLE 'Basic 8-bit Binary UP Counter' DECLARATIONS Q0..Q7 pin istype 'reg'; CLOCK pin; EQUATIONS Q0 := !Q0; Q1 := Q1 $ Q2 := Q2 $ Q3 := Q3 $ Q4 := Q4 $ Q5 := Q5 $ Q6 := Q6 $ Q7 := Q7 $ Q0; (Q1&Q0); (Q2&Q1&Q0); (Q3&Q2&Q1&Q0); (Q4&Q3&Q2&Q1&Q0); (Q5&Q4&Q3&Q2&Q1&Q0); (Q6&Q5&Q4&Q3&Q2&Q1&Q0); [Q0..Q7].CLK = CLOCK; END 86 MODULE countadd TITLE '8-bit binary UP Counter Using ADD operator' DECLARATIONS Q0..Q7 pin istype 'reg'; CLOCK pin; COUNT = [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0]; EQUATIONS COUNT := COUNT +1; COUNT.CLK = CLOCK; END 87 MODULE count8er TITLE '8-bit Binary UP Counter with ENABLE and Asynchronous Reset' DECLARATIONS Q0..Q7 pin istype 'reg'; CLOCK pin; EN pin; ARESET pin; " If EN=0, stays in same state " If EN=1, counts UP " If ARESET asserted, resets to 00...0 (regardless of whether or not enabled) EQUATIONS Q0 := !EN&Q0 Q1 := !EN&Q1 Q2 := !EN&Q2 Q3 := !EN&Q3 Q4 := !EN&Q4 Q5 := !EN&Q5 Q6 := !EN&Q6 Q7 := !EN&Q7 # # # # # # # # EN&!Q0; EN&(Q1 $ EN&(Q2 $ EN&(Q3 $ EN&(Q4 $ EN&(Q5 $ EN&(Q6 $ EN&(Q7 $ Q0); (Q1&Q0)); (Q2&Q1&Q0)); (Q3&Q2&Q1&Q0)); (Q4&Q3&Q2&Q1&Q0)); (Q5&Q4&Q3&Q2&Q1&Q0)); (Q6&Q5&Q4&Q3&Q2&Q1&Q0)); [Q7..Q0].AR = ARESET; [Q0..Q7].CLK = CLOCK; END 88 Binary DOWN Counter The design of a basic binary DOWN counter is derived as follows: Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 When does Q0 change state? Every clock cycle What is the equation for Q0*? Q0* = Q0 89 Binary DOWN Counter The design of a basic binary DOWN counter is derived as follows: Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 When does Q1 change state? When Q0 = 0 What is the equation for Q1*? Q1* = Q1 Q0 90 Binary DOWN Counter The design of a basic binary DOWN counter is derived as follows: Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 When does Q2 change state? When Q0 = 0 AND Q1 = 0 What is the equation for Q2*? Q2* = Q2 (Q1 Q0) 91 Binary DOWN Counter The design of a basic binary DOWN counter is derived as follows: What is the next state equation for an arbitrary stage "K" (QK*) of a binary DOWN counter? QK* = QK (QK-1 QK-2 ... Q1 Q0) 92 MODULE cnt8ud TITLE '8-bit Binary UP/DOWN Counter' DECLARATIONS Q0..Q7 pin istype 'reg'; M, CLOCK pin; " M=0 count DOWN, M=1 count UP EQUATIONS Q0 := !Q0; Q1 := Q1 $ Q2 := Q2 $ Q3 := Q3 $ Q4 := Q4 $ Q5 := Q5 $ Q6 := Q6 $ Q7 := Q7 $ (M&Q0 # !M&!Q0); (M&Q1&Q0 # !M&!Q1&!Q0); (M&Q2&Q1&Q0 # !M&!Q2&!Q1&!Q0); (M&Q3&Q2&Q1&Q0 # !M&!Q3&!Q2&!Q1&!Q0); (M&Q4&Q3&Q2&Q1&Q0 # !M&!Q4&!Q3&!Q2&!Q1&!Q0); (M&Q5&Q4&Q3&Q2&Q1&Q0 # !M&!Q5&!Q4&!Q3&!Q2&!Q1&!Q0); (M&Q6&Q5&Q4&Q3&Q2&Q1&Q0 # !M&!Q6&!Q5&!Q4&!Q3&!Q2&!Q1&!Q0); [Q0..Q7].CLK = CLOCK; END 93 Resettable Counters In addition to an asynchronous reset (which allows to the counter to be placed in a known initial state), it is sometimes useful to provide a synchronous reset capability Such a counter is useful in applications where the number of states in the counting sequence is determined dynamically Example: Example: State counter in a computer's execute unit, where the number of cycles necessary to complete an instruction varies Another variation: Counter with a variation: "programmable" final state (modulo M) 94 MODULE rcnt8u TITLE 'Resettable 8-bit Binary UP Counter' DECLARATIONS Q0..Q7 pin istype 'reg'; R, CLOCK pin; " if R=1, next state will be 00...0 EQUATIONS Q0 := !R & Q1 := !R & Q2 := !R & Q3 := !R & Q4 := !R & Q5 := !R & Q6 := !R & Q7 := !R & !Q0; (Q1 $ (Q2 $ (Q3 $ (Q4 $ (Q5 $ (Q6 $ (Q7 $ Q0); (Q1&Q0)); (Q2&Q1&Q0)); (Q3&Q2&Q1&Q0)); (Q4&Q3&Q2&Q1&Q0)); (Q5&Q4&Q3&Q2&Q1&Q0)); (Q6&Q5&Q4&Q3&Q2&Q1&Q0)); [Q0..Q7].CLK = CLOCK; END 95 MODULE mrcnt8ud TITLE 'Modulo Resettable 8-bit Binary UP Counter' DECLARATIONS Q0..Q7 pin istype 'reg'; D0..D7 pin; CLOCK pin; R pin istype 'com'; " Counts UP to value input on D7..D0; next state is 00...0 EQUATIONS R = !(D0$Q0) & !(D1$Q1) & !(D2$Q2) & !(D3$Q3) & !(D4$Q4) & !(D5$Q5) & !(D6$Q6) & !(D7$Q7); Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 := := := := := := := := !R !R !R !R !R !R !R !R & & & & & & & & !Q0; (Q1 $ (Q2 $ (Q3 $ (Q4 $ (Q5 $ (Q6 $ (Q7 $ Q0); (Q1&Q0)); (Q2&Q1&Q0)); (Q3&Q2&Q1&Q0)); (Q4&Q3&Q2&Q1&Q0)); (Q5&Q4&Q3&Q2&Q1&Q0)); (Q6&Q5&Q4&Q3&Q2&Q1&Q0)); [Q0..Q7].CLK = CLOCK; END 96 Back to the Simple Computer... The program counter (PC) is basically a binary "up" counter with tri-state outputs triThe functions and corresponding control signals required are as follows: ARS: Asynchronous ReSet PCC: Program Counter Count enable POA: Program counter Output on Address bus tri-state buffer enable tri- 97 MODULE pc TITLE 'Program Counter Module' DECLARATIONS CLOCK pin; PC0..PC4 pin istype 'reg_D,buffer'; PCC pin; " PC count enable POA pin; " PC output on address bus tri-state enable ARS pin; " asynchronous reset (connected to START) EQUATIONS " PC0.d PC1.d PC2.d PC3.d PC4.d retain state !PCC&PC0.q # !PCC&PC1.q # !PCC&PC2.q # !PCC&PC3.q # !PCC&PC4.q # count up by 1 PCC&!PC0.q; PCC&(PC1.q $ PC0.q); PCC&(PC2.q $ (PC1.q&PC0.q)); PCC&(PC3.q $ (PC2.q&PC1.q&PC0.q)); PCC&(PC4.q $ (PC3.q&PC2.q&PC1.q&PC0.q)); = = = = = [PC0..PC4].oe = POA; [PC0..PC4].ar = ARS; [PC0..PC4].clk = CLOCK; END 98 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-C, continued Bottom-Up Implementation 99 Simple Computer Block Diagram Functional blocks required (review): a place to store the program, operands, and computation results memory a way to keep track of which instruction is to be executed next program counter (PC) a place to temporarily "stage" an instruction while it is being executed instruction register (IR) a way to perform arithmetic and logic operations arithmetic logic unit (ALU) a way to coordinate and sequence the functions of the machine instruction decoder and micro-sequencer (IDMS) micro100 Program Counter Opcode Address Instruction Register Memory Address Data Data Bus Address Bus 101 Instruction Register The instruction register (IR) is basically an 8-bit data register, with tri-state outputs on trithe lower 5 bits Note that the upper 3 bits (opcode field) are output directly to the instruction decoder and micro-sequencer microThe functions and corresponding control signals required are as follows: IRL: Instruction Register Load enable Instruction IRA: Instruction Register Address field tri-state output enable tri102 MODULE ir TITLE 'Instruction Register Module' DECLARATIONS CLOCK pin; " IR4..IR0 connected to address bus " IR7..IR5 supply opcode to IDMS IR0..IR7 pin istype 'reg_D,buffer'; DB0..DB7 pin; " data bus IRL pin; " IR load enable IRA pin; " IR output on address bus enable EQUATIONS " retain state load [IR0..IR7].d = !IRL&[IR0..IR7].q # IRL&[DB0..DB7]; [IR0..IR7].clk = CLOCK; [IR0..IR4].oe = IRA; [IR5..IR7].oe = [1,1,1]; END 103 Simple Computer Block Diagram Functional blocks required (review): a place to store the program, operands, and computation results memory a way to keep track of which instruction is to be executed next program counter (PC) a place to temporarily "stage" an instruction while it is being executed instruction register (IR) a way to perform arithmetic and logic operations arithmetic logic unit (ALU) a way to coordinate and sequence the functions of the machine instruction decoder and micro-sequencer (IDMS) micro104 Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 105 Arithmetic Logic Unit The arithmetic logic unit (ALU) is a multimultifunction register that performs all the arithmetic and logical (Boolean) operations necessary to implement the instruction set The functions and corresponding control signals required are as follows: ALE: ALU Enable ALU ALX: ALU "X" function select ALU "X ALY: ALU "Y" function select ALU "Y AOE: A register tri-state Output Enable tri- 106 MODULE alu TITLE 'ALU Module' " " " " " " " " " " " " " " " " " " " " 8-bit, 4-function ALU with bi-directional data bus ADD: SUB: LDA: AND: OUT: AOE === 0 0 0 0 1 0 (Q7..Q0) (Q7..Q0) (Q7..Q0) (Q7..Q0) Value in ALE === 1 1 1 1 0 0 ALX === 0 0 1 1 d d <- (Q7..Q0) + <- (Q7..Q0) <- DB7..DB0 <- (Q7..Q0) & Q7..Q0 output ALY === 0 1 0 1 d d DB7..DB0 DB7..DB0 DB7..DB0 on data bus DB7..DB0 CF == X X ZF == X X X X NF == X X X X VF == X X Function ======== ADD SUB LDA AND OUT <none> X -> flag affected -> flag not affected Note: If ALE = 0, the state of all register bits should be retained 107 DECLARATIONS CLOCK pin; " ALU control lines (enable & function select) ALE AOE ALX ALY pin; " overall ALU enable pin; " data bus tri-state output enable pin; " function select pin; " Carry equations (declare as internal nodes) CY0..CY7 node istype 'com'; " Combinational ALU outputs (D flip-flop inputs) " Used for flag generation (declare as internal nodes) ALU0..ALU7 node istype 'com'; " Bi-directional 8-bit data bus (also, accumulator register bits) DB0..DB7 pin istype 'reg_d,buffer'; " Condition code register bits CF VF NF ZF pin pin pin pin istype istype istype istype 'reg_d,buffer'; 'reg_d,buffer'; 'reg_d,buffer'; 'reg_d,buffer'; " " " " carry flag overflow flag negative flag zero flag 108 " Declaration of intermediate equations " Least significant bit carry-in (0 for ADD, 1 for SUB => ALY) CIN = ALY; " Intermediate equations for adder/subtractor SUM (S0..S7), " selected when ALX = 0 S0 S1 S2 S3 S4 S5 S6 S7 = = = = = = = = DB0.q DB1.q DB2.q DB3.q DB4.q DB5.q DB6.q DB7.q $ $ $ $ $ $ $ $ (DB0.pin (DB1.pin (DB2.pin (DB3.pin (DB4.pin (DB5.pin (DB6.pin (DB7.pin $ $ $ $ $ $ $ $ ALY) ALY) ALY) ALY) ALY) ALY) ALY) ALY) $ $ $ $ $ $ $ $ CIN; CY0; CY1; CY2; CY3; CY4; CY5; CY6; " Intermediate equations for LOAD and AND, selected when ALX = 1 L0 L1 L2 L3 L4 L5 L6 L7 = = = = = = = = !ALY&DB0.pin !ALY&DB1.pin !ALY&DB2.pin !ALY&DB3.pin !ALY&DB4.pin !ALY&DB5.pin !ALY&DB6.pin !ALY&DB7.pin # # # # # # # # ALY&DB0.q&DB0.pin; ALY&DB1.q&DB1.pin; ALY&DB2.q&DB2.pin; ALY&DB3.q&DB3.pin; ALY&DB4.q&DB4.pin; ALY&DB5.q&DB5.pin; ALY&DB6.q&DB6.pin; ALY&DB7.q&DB7.pin; 109 EQUATIONS " Ripple carry equations (CY7 is COUT) CY0 = DB0.q&(ALY$DB0.pin) # DB0.q&CIN # CY1 = DB1.q&(ALY$DB1.pin) # DB1.q&CY0 # CY2 = DB2.q&(ALY$DB2.pin) # DB2.q&CY1 # CY3 = DB3.q&(ALY$DB3.pin) # DB3.q&CY2 # CY4 = DB4.q&(ALY$DB4.pin) # DB4.q&CY3 # CY5 = DB5.q&(ALY$DB5.pin) # DB5.q&CY4 # CY6 = DB6.q&(ALY$DB6.pin) # DB6.q&CY5 # CY7 = DB7.q&(ALY$DB7.pin) # DB7.q&CY6 # " Combinational ALU equations ALU0 = !ALX&S0 # ALX&L0; ALU1 = !ALX&S1 # ALX&L1; ALU2 = !ALX&S2 # ALX&L2; ALU3 = !ALX&S3 # ALX&L3; ALU4 = !ALX&S4 # ALX&L4; ALU5 = !ALX&S5 # ALX&L5; ALU6 = !ALX&S6 # ALX&L6; ALU7 = !ALX&S7 # ALX&L7; " Register bit and data bus control equations [DB0..DB7].d = !ALE&[DB0..DB7].q # ALE&[ALU0..ALU7]; [DB0..DB7].clk = CLOCK; [DB0..DB7].oe = AOE; 110 (ALY$DB0.pin)&CIN; (ALY$DB1.pin)&CY0; (ALY$DB2.pin)&CY1; (ALY$DB3.pin)&CY2; (ALY$DB4.pin)&CY3; (ALY$DB5.pin)&CY4; (ALY$DB6.pin)&CY5; (ALY$DB7.pin)&CY6; ALU Multiplexer Block Diagram ALY A1 ALY A0 X Y Cin S Ci-1 i0 2:1 mux F Full Adder Cout Ci A1 ALX A0 D Q DBi AOE i0 2:1 mux F CLOCK A1 ALE A0 i0 2:1 mux F 111 " Flag register state equations CF.d = !ALE&CF.q # ALE&(!ALX&(CY7 $ ALY) # ALX&CF.q); CF.clk = CLOCK; ZF.d = !ALE&ZF.q # ALE&(!ALU7&!ALU6&!ALU5&!ALU4&!ALU3&!ALU2&!ALU1&!ALU0); ZF.clk = CLOCK; NF.d = !ALE&NF.q # ALE&ALU7; NF.clk = CLOCK; VF.d = !ALE&VF.q # ALE&(!ALX&(CY7 $ CY6) # ALX&VF.q); VF.clk = CLOCK; END 112 Clicker Quiz 113 Block Diagram for Bit 3 of a Simple Computer ALU Q2 Qi-1 Q1 Q0 Q0 ALY A1 A0 X Y Cin S ALY i0 2:1 mux F Full Adder Cout C2 C3 A1 A0 D Q ALX i0 DB3 Q3 AOE 2:1 mux F CLOCK A1 A0 ALE i0 2:1 mux F 114 Q1. If the input control combination AOE=0, ALE=1, ALX=0, ALY=0 is applied to this circuit, the function performed will be: A. B. C. D. E. ADD SUBTRACT LOAD NEGATE none of the above 115 Q2. If the input control combination AOE=0, ALE=1, ALX=1, ALY=0 is applied to this circuit, the function performed will be: A. B. C. D. E. ADD SUBTRACT LOAD NEGATE none of the above 116 Q3. If the input control combination AOE=1, ALE=1, ALX=1, ALY=1 is applied to this circuit, the function (inadvertently) performed on (A) will be equivalent to: A. logical left shift B. logical right shift C. rotate left D. rotate right E. none of the above 117 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-C, continued Bottom-Up Implementation 118 Simple Computer Block Diagram Functional blocks required (review): a place to store the program, operands, and computation results memory a way to keep track of which instruction is to be executed next program counter (PC) a place to temporarily "stage" an instruction while it is being executed instruction register (IR) a way to perform arithmetic and logic operations arithmetic logic unit (ALU) a way to coordinate and sequence the functions of the machine instruction decoder and micro-sequencer (IDMS) micro119 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 120 Instruction Decoder and Microsequencer The instruction decoder and microsequencer (IDMS) is a state machine that orchestrates the activity of all the other functional blocks There are two basic steps involved in "processing" each instruction of a program (called a micro-sequence): micro-sequence): fetching the instruction from memory (at the location pointed to by the PC), loading it into the IR, and incrementing the PC executing the instruction staged in the IR based on the opcode field and the operand address field 121 Instruction Decoder and Microsequencer Since there are only two states (fetch and execute), a single flip-flop can be used to flipimplement the state counter ("SQ") The control signals that need to be asserted during the fetch cycle include: POA: turn on PC output buffers MSL: select memory MOE: turn on memory output buffers IRL: enable IR load PCC: enable PC count NOTE: The synchronous functions (IRL and PCC) will take place on the clock edge that causes the state counter to transition from the FETCH state to the EXECUTE state 122 Instruction Decoder and Microsequencer The control signals that need to be asserted during an execute cycle for the synchronous ALU functions (ADD, SUB, LDA, AND) are: IRA: turn on operand address output buffers MSL: select memory MOE: turn on memory data output buffers ALE: enable ALU operation ALX, ALY: select ALU function The control signals that need to be asserted during an execute cycle for STA are: IRA: turn on operand address output buffers MSL: select memory MWE: enable memory write AOE: turn on A register output buffers 123 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 124 IRA IRL Decoded State Instruction Mnemonic Instruction Decoder and Microsequencer In order to stop execution (i.e., disable all the functional blocks) when a HLT instruction is executed, an additional flip-flop will be used flip(called "RUN") , as follows: when the START pushbutton is pressed, the RUN flip-flop will be asynchronously set flip when a HLT instruction is executed, the RUN flip-flop will be asynchronously flipcleared the RUN signal will be ANDed with the synchronous system enable signals, thus effectively halting execution when a HLT instruction is executed 125 MODULE idms TITLE 'Instruction Decoder and Microsequencer' DECLARATIONS CLOCK pin; START pin; " asynchronous START pushbutton OP0..OP2 pin; " opcode bits (input from IR5..IR7) " State counter SQ node istype 'reg_D,buffer'; " RUN/HLT state RUN node istype 'reg_D,buffer'; " Memory control signals MSL,MOE,MWE pin istype 'com'; " PC control signals PCC,POA,ARS pin istype 'com'; " IR control signals IRL,IRA pin istype 'com'; " ALU control signals (not using flags yet) ALE,ALX,ALY,AOE pin istype 'com'; 126 " Decoded opcode definitions LDA STA ADD SUB AND HLT = = = = = = !OP2&!OP1&!OP0; !OP2&!OP1& OP0; !OP2& OP1&!OP0; !OP2& OP1& OP0; OP2&!OP1&!OP0; OP2&!OP1& OP0; " " " " " " LDA STA ADD SUB AND HLT opcode opcode opcode opcode opcode opcode = = = = = = 000 001 010 011 100 101 " Decoded state definitions S0 = !SQ.q; " fetch S1 = SQ.q; " execute EQUATIONS " State counter SQ.d = RUN.q&!SQ.q; " if RUN negated, resets SQ SQ.clk = CLOCK; SQ.ar = START; " start in fetch state " Run/stop (equivalent of SR latch) RUN.ap = START; " start with RUN set to 1 RUN.clk = CLOCK; RUN.d = RUN.q; RUN.ar = S1&HLT; " RUN is cleared when HLT executed 127 " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 128 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 129 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 130 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 131 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 132 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 133 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 134 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 135 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 136 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 137 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 138 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 139 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 140 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 141 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 142 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 143 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 144 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 145 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 146 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 147 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 148 System Control Signals MWE MOE POA AOE PCC MSL ALE ALX H H S0 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L ALY 149 IRA IRL Decoded State Instruction Mnemonic " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY END = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); 150 Get the picture? Hahahahaha... 151 System Data Flow and Timing Analysis General procedure Understand operation of individual functional units Memory Program counter Instruction register Arithmetic logic unit Instruction decoder and microsequencer (New functional blocks to be added) 152 System Data Flow and Timing Analysis General procedure Understand function ("data processing") performed by each instruction Identify address and data flow required to execute each instruction Identify micro-operations required to microexecute each instruction Identify control signals that need to be asserted to generate the required sequence of micro-operations for each instruction micro Examine timing relationship of control signals 153 System Data Flow and Timing Analysis Basic hardware-imposed constraints hardware Only one device is allowed to drive a bus during any machine cycle (i.e., "bus fighting" must be avoided) Data cannot pass through more than one (edge(edge-triggered) flip-flop or latch per cycle flip- 154 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 155 Previous S1 Execute S0 Fetch S1 Execute IR loaded with instruction on data bus before this point PC incremented after this point PC Instruction PC = PC+1 Instruction Loaded in IR 156 Clicker Quiz 157 Q1. The increment of the program counter (PC) needs to occur as part of the "fetch" cycle because: A. if it occurred on the "execute" cycle, the new value would not be stable in time for the subsequent "fetch" cycle B. if it occurred on the "execute" cycle, it would not be possible to execute an "STA" instruction C. if it occurred on the "execute" cycle, it would not be possible to read an operand from memory D. if it occurred on the "execute" cycle, it would not be possible to read an instruction from memory E. none of the above 158 Q2. The program counter (PC) can be incremented on the same cycle that its value is used to fetch an instruction from memory because: A. B. C. the synchronous actions associated with the IRL and PCC control signals occur on different fetch cycle phases the IRL and PCC control signals are not asserted simultaneously by the IDMS the load of the instruction register is based on the data bus value prior to the system CLOCK edge, while the increment of the PC occurs after the CLOCK edge the load of the instruction register occurs on the negative CLOCK edge, while the increment of the PC occurs on the positive CLOCK edge none of the above 159 D. E. Q3. Incrementing the program counter (PC) on the same clock edge that loads the instruction register (IR) does not cause a problem because: A. the memory will ignore the new address the PC places on the address bus B. the output buffers in the PC will not allow the new PC value to affect the address bus until the next fetch cycle C. the IR will be loaded with the value on the data bus prior to the clock edge while the contents of the PC will increment after the clock edge D. the value in the PC will change in time for the correct value to be output on the address bus (and fetch the correct instruction), before the IR load occurs 160 E. none of the above Q4. The hardware constraint that "data cannot pass through more than one edge-triggered flip-flop per clock cycle" is based on the fact that: A. only a single entity can drive a bus on a given clock cycle B. the system clock has limited driving capability C. the flip-flops that comprise a register do not change state simultaneously, so additional time must be provided before the register's output can be used D. for a D flip-flop with clocking period , Q(t+)=D(t) E. none of the above 161 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-D Basic Extensions 162 Reading Assignment: 3rd Ed., pp. 712-717; 4th Ed., pp. 727-731; 712727Meyer Supplemental Text, pp. 42-50 Text, 42Instructional Objective: To learn how to add basic extensions to the simple computer architecture Outline: Adding Shift Instructions Adding I/O Instructions Adding Transfer of Control Instructions 163 Extensions to Basic Machine We will use the two available opcodes (110 and 111) to add new instructions to the basic machine, a pair at a time Opcode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mnemonic LDA addr STA addr ADD addr SUB addr AND addr HLT Function Performed Load A with contents of location addr Store contents of A at location addr Add contents of addr to contents of A Subtract contents of addr from contents of A AND contents of addr with contents of A Halt Stop, discontinue execution 164 Extensions to Basic Machine We will add rows to the system control table to add the new instructions and add columns to add new control signals MWE MOE POA AOE MSL PCC ALE ALX ALY IRA IRL Decoded State Instruction Mnemonic S0 S1 S1 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H L L 165 Adding Shift Instructions Definition: Definition: A shift instruction translates the bits in a register (here, the "A" register) one place to the left or to the right Definition: Definition: An end off shift discards the bit that gets shifted out Definition: Definition: A preserving shift retains the bit shifted out (typically in the CF condition code bit) Definition: Definition: A logical shift is a "zero fill" shift Definition: Definition: An arithmetic shift is a "sign preserving" shift (i.e., the sign bit gets replicated as the data is shifted right) 166 Shift Instruction Examples Given: (A) = 10011010 After logical shift left: After logical shift right: After arithmetic shift left: After arithmetic shift right: 00110100 00110100 01001101 00110100 00110100 11001101 CF=1 CF=1 CF=0 CF=0 CF=1 CF=1 CF=0 CF=0 Note: The arithmetic left shift is identical to the logical left shift 167 Adding Shift Instructions Modify the ALU to function as follows: ALX ALY 0 0 1 1 0 1 0 1 Function Performed Load Logical Shift Right Arithmetic/Logical Shift Left Arithmetic Shift Right Use the CF condition code bit to preserve the bit that gets shifted out 168 Modified Instruction Set Opcode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mnemonic LDA addr STA addr LSR ASL ASR HLT Function Performed Load A with contents of location addr Store contents of A at location addr Logically shift contents of A right Arithmetically/Logically shift contents of A left Arithmetically shift contents of A right Halt Stop, discontinue execution 169 Modified System Control Table MWE MOE POA AOE PCC MSL ALE ALX S0 S1 S1 S1 S1 S1 S1 S1 S1 LDA STA LSR ASL ASR HLT H H H H H H H H H H H H H H H H L H H H H L L L ALY IRA IRL Decoded State Instruction Mnemonic 170 MODULE alum TITLE 'ALU Module Modified for Shift Instructions' " " " " " " " " " " " " " " " " " " " " 8-bit, 4-function ALU with bi-directional data bus LDA: LSR: ASL: ASR: OUT: AOE === 0 0 0 0 1 0 (Q7..Q0) (Q7..Q0) (Q7..Q0) (Q7..Q0) Value in ALE === 1 1 1 1 0 0 ALX === 0 0 1 1 d d <- DB7..DB0 <- 0 Q7 Q6 Q5 Q4 Q3 Q2 Q1, CF <- Q0 <- Q6 Q5 Q4 Q3 Q2 Q1 Q0 0, CF <- Q7 <- Q7 Q7 Q6 Q5 Q4 Q3 Q2 Q1, CF <- Q0 Q7..Q0 output on data bus DB7..DB0 ALY === 0 1 0 1 d d Function ======== LDA LSR ASL ASR OUT <none> CF == X X X ZF == X X X X NF == X X X X VF == X -> flag affected -> flag not affected Note: If ALE = 0, the state of all register bits should be retained 171 DECLARATIONS CLOCK pin; " ALU control lines (enable & function select) ALE AOE ALX ALY pin; " overall ALU enable pin; " data bus tri-state output enable pin; " function select pin; " Combinational ALU outputs (D flip-flop inputs) " Used for flag generation (declare as internal nodes) ALU0..ALU7 node istype 'com'; " Bi-directional 8-bit data bus (also, accumulator register bits) DB0..DB7 pin istype 'reg_d,buffer'; " Condition code register bits CF VF NF ZF pin pin pin pin istype istype istype istype 'reg_d,buffer'; 'reg_d,buffer'; 'reg_d,buffer'; 'reg_d,buffer'; " " " " carry flag overflow flag negative flag zero flag 172 EQUATIONS " LDA ALU0 = !ALX&!ALY&DB0.pin ALU1 = !ALX&!ALY&DB1.pin ALU2 = !ALX&!ALY&DB2.pin ALU3 = !ALX&!ALY&DB3.pin ALU4 = !ALX&!ALY&DB4.pin ALU5 = !ALX&!ALY&DB5.pin ALU6 = !ALX&!ALY&DB6.pin ALU7 = !ALX&!ALY&DB7.pin # # # # # # # # LSR !ALX&ALY&DB1.q !ALX&ALY&DB2.q !ALX&ALY&DB3.q !ALX&ALY&DB4.q !ALX&ALY&DB5.q !ALX&ALY&DB6.q !ALX&ALY&DB7.q !ALX&ALY& 0 # # # # # # # # ASL ALX&!ALY& 0 ALX&!ALY&DB0.q ALX&!ALY&DB1.q ALX&!ALY&DB2.q ALX&!ALY&DB3.q ALX&!ALY&DB4.q ALX&!ALY&DB5.q ALX&!ALY&DB6.q # # # # # # # # ASR ALX&ALY&DB1.q; ALX&ALY&DB2.q; ALX&ALY&DB3.q; ALX&ALY&DB4.q; ALX&ALY&DB5.q; ALX&ALY&DB6.q; ALX&ALY&DB7.q; ALX&ALY&DB7.q; " Register bit and data bus control equations [DB0..DB7].d = !ALE&[DB0..DB7].q # ALE&[ALU0..ALU7]; [DB0..DB7].clk = CLOCK; [DB0..DB7].oe = AOE; " Flag register state equations CF.d = !ALE&CF.q # ALE&(!ALX&!ALY&CF.q # !ALX&ALY&DB0.q # ALX&!ALY&DB7.q # ALX&ALY&DB0.q); " LDA LSR ASL ASR CF.clk = CLOCK; ZF.d = !ALE&ZF.q # ALE&(!ALU7&!ALU6&!ALU5&!ALU4&!ALU3&!ALU2&!ALU1&!ALU0); ZF.clk = CLOCK; NF.d = !ALE&NF.q # ALE&ALU7; NF.clk = CLOCK; VF.d = !ALE&VF.q # ALE&VF.q; " NOTE: NOT AFFECTED VF.clk = CLOCK; END 173 Adding I/O Instructions When we first drew the "big picture" of our simple computer, we included a switch "input port" and an LED "output port" LED Output Port Switch Input Port Start Clock 174 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address Instruction Register Flags Data Data Bus Memory Address Data ALU I/O 175 Address Bus Adding I/O Instructions Need two new instructions: IN addr input data from port addr and load into the A register OUT addr output data in A register to port addr Here, the address field of the instruction is used to specify a port address (or, I/O device ID) Also need two new control signals: IOR asserted when IN ("I/O read") occurs IOW asserted when OUT ("I/O write") occurs 176 MODULE io TITLE 'Input/Output Port 00000' DECLARATIONS DB0..DB7 pin istype 'com'; AD0..AD4 pin; IN0..IN7 pin; OUT0..OUT7 pin istype 'com'; IOR pin; " Input port read IOW pin; " Output port write " " " " data bus address bus input port output port " Port select equation for port address 00000 PS = !AD4&!AD3&!AD2&!AD1&!AD0; EQUATIONS [DB0..DB7] = [IN0..IN7]; [DB0..DB7].oe = IOR&PS; [OUT0..OUT7] = [DB0..DB7]; [OUT0..OUT7].oe = IOW&PS; END Issue: Output port bits are valid only as long as IOW&PS is asserted (Hi-Z otherwise) 177 MODULE iol TITLE 'Input/Output Port 00000 - With Output Latch' DECLARATIONS DB0..DB7 pin istype 'com'; AD0..AD4 pin; IN0..IN7 pin; OUT0..OUT7 pin istype 'com'; IOR pin; " Input port read IOW pin; " Output port write " " " " data bus address bus input port output port " Port select equation for port address 00000 PS = !AD4&!AD3&!AD2&!AD1&!AD0; EQUATIONS [DB0..DB7] = [IN0..IN7]; [DB0..DB7].oe = IOR&PS; " Transparent latch for output port [OUT0..OUT7] = !(IOW&PS)&[OUT0..OUT7] # IOW&PS&[DB0..DB7]; END 178 Adding I/O Instructions Modified system control table: MWE MOE POA AOE PCC MSL ALE ALX ALY IOW H IOR H IRA H H H H H L L H H H IRL H H H H H H L H H H H Decoded State Instruction Mnemonic S0 S1 S1 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT IN OUT H H H H H H L H H H H H H H H H H Equations that need to be updated: IRA, AOE, ALE, ALX Equations that need to be added: IOR, IOW 179 " System control equations (IDMS) MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND # IN # OUT); S1&(STA # OUT); RUN.q&S1&(LDA # ADD # SUB # AND # IN); S1&(LDA # AND # IN); S1&(SUB # AND); IOR = S1&IN; IOW = S1&OUT; END 180 Clicker Quiz 181 Q1. If the output port pins are latched, data written to the port will remain on its pins: A. only during the execute cycle of the OUT instruction B. only when the clock signal is high C. until another OUT instruction writes different data to the port D. until the next instruction is executed E. none of the above 182 Q2. If the output port pins are not latched, data written to the port will remain on its pins: A. only during the execute cycle of the OUT instruction B. only when the clock signal is high C. until another OUT instruction writes different data to the port D. until the next instruction is executed E. none of the above 183 Adding Transfer of Control Instructions There are two basic types of transfer-oftransfer-ofcontrol instructions: absolute: the operand field contains the address in memory at which execution should continue ("jump") relative: the operand field contains the signed offset that should be added to the PC to determine the location at which execution should continue ("branch") Jumps or branches can be unconditional ("always happen") or conditional ("happen only when a specified condition is met") 184 Adding Transfer of Control Instructions For the purpose of illustration, we will add an unconditional jump ("JMP") instruction to ("JMP") our simple computer along with a single conditional jump ("Jcond") ("Jcond") The conditional jump illustrated will be a jump if ZF set ("JZF") instruction ("JZF") To execute a jump instruction, the operand field (from the IR) will be loaded into the PC via the address bus when PLA is asserted Note that, for the conditional jump instruction, that if the condition is not met, the execute cycle will be a "no-operation" "no-operation" (or, "NOP") cycle 185 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address Instruction Register Flags Data Memory Address Data ALU Data Bus Address Bus 186 MODULE pc TITLE 'Program Counter with Load Capability' DECLARATIONS CLOCK pin; PC0..PC4 pin istype 'reg_D,buffer'; PCC PLA POA ARS pin; pin; pin; pin; " " " " PC count enable PC load from address bus enable PC output on address bus tri-state enable asynchronous reset (connected to START) " Note: Assume PCC and PLA are mutually exclusive EQUATIONS " PC0.d PC1.d PC2.d PC3.d PC4.d retain state !PCC&!PLA&PC0.q !PCC&!PLA&PC1.q !PCC&!PLA&PC2.q !PCC&!PLA&PC3.q !PCC&!PLA&PC4.q load PLA&PC0.pin PLA&PC1.pin PLA&PC2.pin PLA&PC3.pin PLA&PC4.pin count up by 1 PCC&!PC0.q; PCC&(PC1.q $ PC0.q); PCC&(PC2.q $ (PC1.q&PC0.q)); PCC&(PC3.q $ (PC2.q&PC1.q&PC0.q)); PCC&(PC4.q $ (PC3.q&PC2.q&PC1.q&PC0.q)); = = = = = # # # # # # # # # # [PC0..PC4].oe = POA; [PC0..PC4].ar = ARS; [PC0..PC4].clk = CLOCK; END 187 Adding Transfer of Control Instructions Modified system control table: MWE MOE POA AOE PCC MSL PLA H ZF 188 ALE ALX H H S0 S1 S1 S1 S1 S1 S1 S1 S1 LDA STA ADD SUB AND HLT JMP JZF H H H H H H L H H H H H H H H H H H H H H H H H H H L H H L L H ZF Equation that needs to be updated: IRA Equation that needs to be added: PLA ALY IRA IRL Decoded State Instruction Mnemonic " System control equations (IDMS) MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); S0 # S1&(LDA # ADD # SUB # AND); S1&STA; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND # JMP # JZF&ZF); S1&I1; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); PLA = S1&(JMP # JZF&ZF); END 189 Clicker Quiz 190 Q1. Implementation of "branch" instructions (that perform a relative transfer of control) requires the following modification to the program counter: A. add a bi-directional path to the data bus B. use the ALU to compute the address of the next instruction C. make it an up/down counter D. add a two's complement N-bit adder circuit (where N is the address bus width) E. none of the above 191 Q2. Whether or not a conditional branch is taken or not taken depends on: A. B. C. D. E. the value of the program counter the state of the condition code bits the cycle of the state counter the value in the accumulator none of the above 192 Thought Questions What would be required to add a jump if less than ("JLT") or a jump if greater than or equal ("JLT") ("JGE") to ("JGE") instruction? These jump conditions can be determined based on the ALU flags (N, C, Z, V) JLT condition = NV + NV =NV JGE condition = (N V) 193 C 0 4 12 C 8 0 N 1 5 0 d 7 d 13 9 0 d 11 V 1 3 d 15 V d N 2 6 d d Z d 14 0 10 1 Z d 1 Z V Derivation of Signed Comparisons R1 R0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 (R) M1 M0 (M) ? C Z N V 0 0 0 0 (R) = (M) 0 1 0 0 0 0 1 +1 (R) < (M) 1 0 1 0 0 1 0 -2 (R) > (M) 1 0 1 1 0 1 1 -1 (R) > (M) 1 0 0 0 +1 0 0 0 (R) > (M) 0 0 0 0 +1 0 1 +1 (R) = (M) 0 1 0 0 +1 1 0 -2 (R) > (M) 1 0 1 1 +1 1 1 -1 (R) > (M) 1 0 1 1 -2 0 0 0 (R) < (M) 0 0 1 0 -2 0 1 +1 (R) < (M) 0 0 0 1 -2 1 0 -2 (R) = (M) 0 1 0 0 -2 1 1 -1 (R) < (M) 1 0 1 0 -1 0 0 0 (R) < (M) 0 0 1 0 -1 0 1 +1 (R) < (M) 0 0 1 0 -1 1 0 -2 (R) > (M) 0 0 0 0 -1 1 1 -1 (R) = (M) 0 1 0 0 Z=1 (R) = (M) Z + (N V) = 0 (R) > (M) NV=1 (R) < (M) 194 Thought Questions How could a compare ("CMP") instruction be implemented? How is this different than a subtract ("SUB")? ("SUB")? A "CMP" works the same as "SUB" except that the result of (A) (addr) is not stored in the A register (i.e., only the flags are affected) 195 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-E Advanced Extensions 196 Reading Assignment: Meyer Supplemental Text, pp. 50-64 Text, 50Instructional Objectives: To learn how to extend the control structure of the simple computer to accommodate instructions with multiple execute cycles To learn how to add a stack mechanism to the simple computer To learn how to add stack manipulation instructions to the simple computer To learn how a subroutine linkage mechanism works To learn how to augment the stack mechanism to add subroutine linkage instructions 197 Outline Modifications to state counter and instruction decoder to accommodate instructions with multiple execute cycles Introduction of a stack mechanism Use of a stack to implement "push" (PSH) and "pop" (POP) instructions Identification of micro-operations that can microbe overlapped Modifications to the system architecture necessary to implement subroutine linkage instructions Implementation of subroutine "call" (JSR) and "return" (RTS) instructions 198 State Counter Modifications All of the "simple computer" instructions discussed thus far have required only two states: a fetch cycle followed by a single execute cycle Many "real world" instructions require more than a single execute state to achieve their desired functionality We wish to extend the state counter (and the instruction decoder) to accommodate instructions that require multiple execute cycles (here, up to three) three) 199 State Counter Modifications In the process of adding this capability, we want to make sure our original "shorter" instructions do not incur a "penalty" (i.e., execute slower) slower) To accomplish this, we need to design the state counter so that the number of execute cycles can be dynamically changed based on the opcode of the instruction being executed To provide up to three execute cycles, we will replace the state counter flip-flop with a twofliptwobit binary counter that has a synchronous reset input (in addition to an asynchronous clear) 200 State Counter Modifications The "state names" will now be: S0 (fetch) S1 (first execute) S2 (second execute) S3 (third execute) We will also add a new system control signal "RST" (connected to the synchronous reset of the binary counter) that will be asserted on the last execute state of each instruction, thereby synchronously resetting the state counter to zero (so that the next cycle will be a "fetch") "fetch") 201 MODULE idmsr TITLE 'Instruction Decoder and Microsequencer with Multi-Execution States' DECLARATIONS CLOCK pin; START pin; " asynchronous START pushbutton OP0..OP2 pin; " opcode bits (input from IR5..IR7) " State counter SQA node istype 'reg_D,buffer'; " low bit of state counter SQB node istype 'reg_D,buffer'; " high bit of state counter " Synchronous state counter reset RST node istype 'com'; " RUN/HLT state RUN node istype 'reg_D,buffer'; " Memory control signals MSL,MOE,MWE pin istype 'com'; " PC control signals PCC,POA,ARS pin istype 'com'; 202 " IR control signals IRL,IRA pin istype 'com'; " ALU control signals ALE,ALX,ALY,AOE pin istype 'com'; " Decoded opcode definitions LDA = !OP2&!OP1&!OP0; " opcode STA = !OP2&!OP1& OP0; " opcode ADD = !OP2& OP1&!OP0; " opcode SUB = !OP2& OP1& OP0; " opcode AND = OP2&!OP1&!OP0; " opcode HLT = OP2&!OP1& OP0; " opcode " Decoded state S0 = !SQB&!SQA; S1 = !SQB& SQA; S2 = SQB&!SQA; S3 = SQB& SQA; 000 001 010 011 100 101 definitions " fetch state " first execute state " second execute state " third execute state 203 EQUATIONS " State counter SQA.d = !RST & RUN.q & !SQA.q; " if RUN negated or RST asserted, SQB.d = !RST & RUN.q & (SQB.q $ SQA.q); " state counter is reset SQA.clk = CLOCK; SQB.clk = CLOCK; SQA.ar = START; " start in fetch state SQB.ar = START; " Run/stop (equivalent of SR latch) RUN.ap = START; " start with RUN set to 1 RUN.clk = CLOCK; RUN.d = RUN.q; RUN.ar = S1&HLT; " RUN is cleared when HLT executed " System control equations (for base machine) MSL = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND)); MOE = S0 # S1&(LDA # ADD # SUB # AND); MWE = S1&STA; ARS = START; PCC = RUN.q&S0; POA = S0; IRL = RUN.q&S0; IRA = S1&(LDA # STA # ADD # SUB # AND); AOE = S1&STA; ALE = RUN.q&S1&(LDA # ADD # SUB # AND); ALX = S1&(LDA # AND); ALY = S1&(SUB # AND); RST = S1&(LDA # STA # ADD # SUB # AND); END 204 Clicker Quiz 205 Q1. The state counter in the "extended" machine's instruction decoder and micro-sequencer needs both a synchronous reset (RST) and an asynchronous reset (ARS) because: A. we want to make sure the state counter gets reset B. the ARS signal allows the state counter to be reset to the "fetch" state when START is pressed, while the RST allows the state counter to be reset when the last execute cycle of an instruction is reached C. the RST signal allows the state counter to be reset to the "fetch" state when START is pressed, while ARS allows the state counter to be reset when the last execute cycle of an instruction is reached D. the state counter is not always clocked 206 E. none of the above Q2. Adding a third bit to the state counter would allow up to ___ execute states: A. B. C. D. E. 3 5 7 8 none of the above 207 Stack Mechanism Definition: Definition: A stack is a last-in, first-out (LIFO) last- firstdata structure Primary uses of stacks in computers: subroutine linkage saving return address parameter passing saving machine context (or state) state) especially when processing interrupts or exceptions expression evaluation 208 Stack Mechanism Conventions: the stack area is generally placed at the "top" of memory (i.e., starting at the highest address in memory) a stack pointer (SP) register is used to indicate the address of the top stack item stack growth is toward decreasing addresses (note that this is in contrast to program growth, which is toward growth, increasing addresses) addresses) Note: An alternate convention for the stack could also be used, namely, to have the SP register point to the next available location 209 Illustration of Stack Growth Initial condition (stack empty): SP Register 11100 11101 11110 11111 "Top" of Memory 210 00000 Addr Illustration of Stack Growth After first item pushed onto stack: SP Register 11100 11101 11110 Addr 11111 <item #1> "Top" of Memory 11111 211 Illustration of Stack Growth After second item pushed onto stack: SP Register 11100 11110 <item #2> <item #1> "Top" of Memory 11101 11110 11111 Addr 212 Illustration of Stack Growth After third item pushed onto stack: SP Register 11100 11101 <item #3> <item #2> <item #1> "Top" of Memory 11101 11110 11111 Addr 213 Illustration of Stack Growth After fourth item pushed onto stack: SP Register 11100 <item #4> <item #3> <item #2> <item #1> "Top" of Memory 11100 11101 11110 11111 Addr 214 Illustration of Stack Growth After top item removed: SP Register 11101 <item #4> <item #3> <item #2> <item #1> "Top" of Memory 11100 11101 11110 11111 Addr 215 Illustration of Stack Growth After top item removed: SP Register 11110 <item #4> <item #3> <item #2> <item #1> "Top" of Memory 11100 11101 11110 11111 Addr 216 Illustration of Stack Growth After top item removed: SP Register 11111 <item #4> <item #3> <item #2> <item #1> "Top" of Memory 11100 11101 11110 11111 Addr 217 Illustration of Stack Growth After top item removed (stack empty): SP Register 00000 <item #4> <item #3> <item #2> <item #1> "Top" of Memory 11100 11101 11110 11111 Addr 218 Stack Mechanism To add a stack mechanism to our simple computer, we need a Stack Pointer (SP) register connected to the address bus that has the following control signals: SPI: Stack Pointer Increment SPD: Stack Pointer Decrement SPA: Stack Pointer output on Address bus ARS: Asynchronous ReSet Note: The stack empty condition corresponds to the SP register being cleared to "00000" 219 MODULE sp TITLE 'Stack Pointer' DECLARATIONS CLOCK pin; SP0..SP4 pin istype 'reg_D,buffer'; SPI pin; " SP increment enable SPD pin; " SP decrement enable SPA pin; " SP output on address bus tri-state enable ARS pin; " asynchronous reset (connected to START) " Note: Assume SPI and SPD are mutually exclusive EQUATIONS " retain state increment/decrement SP0.d = !SPI&!SPD&SP0.q # SPI&!SP0.q # SPD&!SP0.q; SP1.d = !SPI&!SPD&SP1.q # SPI&(SP1.q$SP0.q) # SPD&(SP1.q$!SP0.q); SP2.d = !SPI&!SPD&SP2.q # SPI&(SP2.q$(SP1.q&SP0.q)) # SPD&(SP2.q$(!SP1.q&!SP0.q)); SP3.d = !SPI&!SPD&SP3.q # SPI&(SP3.q$(SP2.q&SP1.q&SP0.q)) # SPD&(SP3.q$(!SP2.q&!SP1.q&!SP0.q)); SP4.d = !SPI&!SPD&SP4.q # SPI&(SP4.q$(SP3.q&SP2.q&SP1.q&SP0.q)) # SPD&(SP4.q$(!SP3.q&!SP2.q&!SP1.q&!SP0.q)); [SP0..SP4].oe = SPA; [SP0..SP4].ar = ARS; [SP0..SP4].clk = CLOCK; END 220 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP Memory Address Data Instruction Register Flags ALU Data Data Bus Address Bus 221 Adding Stack Manipulation Instructions The most common stack operations are "push" and "pop" here, the value that will be pushed and popped is the A register PSH save value in A register on stack Step 1: Decrement SP register Step 2: Store value in A register at the location pointed to by SP register POP load A with value on stack Step 1: Load A register from memory location pointed to by SP register Step 2: Increment SP register Note: The PSH and POP instructions can be used to implement expression evaluation 222 Adding Stack Manipulation Instructions The opcodes that will be used for PSH and POP are as follows: Opcode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mnemonic LDA addr STA addr ADD addr SUB addr AND addr HLT PSH POP Function Performed Load A with contents of location addr Store contents of A at location addr Add contents of addr to contents of A Subtract contents of addr from contents of A AND contents of addr with contents of A Halt Stop, discontinue execution Save (A) on stack Restore (A) from stack 223 Adding Stack Manipulation Instructions At first glance, it would appear that two execute cycles are required to implement both the PSH and POP instructions As good computer engineers*, however, we engineers* always need to be on the lookout for operations that can be overlapped (subject, of course, to the "rules" we learned earlier): Only one device is allowed to drive a bus during any machine cycle (i.e., "bus fighting" must be avoided) Data cannot pass through more than one (edge(edge-triggered) flip-flop or latch per cycle flip*a.k.a. "astute digijocks and digijockettes" 224 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP = SP-1 Instruction Register Flags Data Memory Address Data ALU Data Bus PSH: Step 1 Address Bus 225 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP Memory Address Data Instruction Register Flags ALU Data Data Bus PSH: Step 2 Address Bus 226 Adding Stack Manipulation Instructions Implementation of PSH requires two execute cycles: first execute cycle: decrement SP register* (SPD) SPD) second execute cycle: output "new" value of SP on address bus (SPA), enable a (SPA), memory write operation (MSL and MWE), (MSL MWE), and tell the ALU to output value in the A register on the data bus (AOE) (AOE) *Note: The "new" value of SP must be available (and stable) before it can be used to address memory 227 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP Memory Address Data Instruction Register Flags ALU Data Data Bus POP: Step 1 Address Bus 228 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP = SP+1 Instruction Register Flags Data Memory Address Data ALU Data Bus POP: Step 2 Address Bus 229 Adding Stack Manipulation Instructions Implementation of POP requires only one execute cycle: first execute cycle: output value of SP on address bus (SPA), enable a memory read (SPA), operation (MSL and MOE), tell the ALU to (MSL MOE), load the A register with the value on the data bus (ALE and ALX), and tell the SP (ALE ALX), register to increment* (SPI) (SPI) *Note: The SP register will be incremented after the A register is loaded with the contents of the location pointed to by the SP register, i.e., the SP increment is overlapped with the fetch of the next instruction 230 Adding Stack Manipulation Instructions Modified system control table: MWE MOE POA AOE PCC MSL SPD SPA H H RST H H H H H H H H H H H H H H H H ALE ALX ALY H H IRA SPI IRL H H H H H H L L H H H H H L H Decoded State Instruction Mnemonic S0 S1 S1 S1 S1 S1 S1 S1 S1 S2 LDA STA ADD SUB AND HLT PSH POP PSH H H H H H H L H H H H H H H H H Note: Recall that the RST signal is used to synchronously reset the state counter on the final execute cycle of each instruction 231 " System control equations MSL MOE MWE ARS PCC POA IRL IRA AOE ALE ALX ALY = = = = = = = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND # POP)# S2&PSH); S0 # S1&(LDA # ADD # SUB # AND # POP); S1&STA # S2&PSH; START; RUN.q&S0; S0; RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA # S2&PSH; RUN.q&S1&(LDA # ADD # SUB # AND # POP); S1&(LDA # AND # POP); S1&(SUB # AND); SPI = S1&POP; SPD = S1&PSH; SPA = S1&POP # S2&PSH; RST = S1&(LDA # STA # ADD # SUB # AND # POP) # S2&PSH; END 232 Clicker Quiz 233 Q1. If a program contains more POP instructions than PSH instructions, the following is likely to occur: A. stack overflow (stack collides with end of program space) B. stack underflow (stack collides with beginning of program space) C. program counter overflow (program counter wraps to beginning of program space) D. program counter underflow (program counter wraps to end of program space) E. none of the above 234 Q2. If a program contains more PSH instructions than POP instructions, the following is likely to occur: A. stack overflow (stack collides with end of program space) B. stack underflow (stack collides with beginning of program space) C. program counter overflow (program counter wraps to beginning of program space) D. program counter underflow (program counter wraps to end of program space) E. none of the above 235 2011 Edition by D. G. Meyer Introduction to Digital System Design Module 6-E, continued Advanced Extensions 236 Adding Subroutine Linkage Instructions Why use a stack as a subroutine linkage mechanism? There are several important capabilities that a stack affords: arbitrary nesting of subroutine calls passing parameters to subroutines recursion (the ability of a subroutine to call itself) made possible by passing parameters via the stack reentrancy (the ability of a code module to be shared among quasi-simultaneously quasiexecuting tasks) made possible by storing temporary local variables on the stack 237 Adding Subroutine Linkage Instructions The opcodes that will be used for JSR ("jump to subroutine") and RTS ("return from subroutine") are as follows: Opcode 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mnemonic LDA addr STA addr ADD addr SUB addr AND addr HLT JSR addr RTS Function Performed Load A with contents of location addr Store contents of A at location addr Add contents of addr to contents of A Subtract contents of addr from contents of A AND contents of addr with contents of A Halt Stop, discontinue execution Jump to subroutine at location addr Return from subroutine 238 Subroutine Linkage in Action MAIN start of main program JSR SUBA (next instruction) HLT end of main program SUBA start of subroutine A JSR SUBB (next instruction) RTS end of subroutine A SUBB start of subroutine B RTS end of subroutine B 239 Adding Subroutine Linkage Instructions Subroutine "CALL" and "RETURN" JSR addr jump to subroutine at memory location addr Step 1: Decrement SP register Step 2: Store return address* at location pointed to by SP register Step 3: Load PC with value in IR address field RTS return from subroutine Step 1: Load PC from memory location pointed to by SP register Step 2: Increment SP register *current value in PC, which was incremented during the fetch cycle (points to next instruction)240 Adding Subroutine Linkage Instructions The astute digijock(ette) will realize at this point that the program counter needs to be modified a way to save its value on the stack, and subsequently restore it, must be provided Two new PC control signals need to be implemented: POD: output value of PC on data bus PLD: load PC with value on data bus 241 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP Memory Address Data Instruction Register Flags ALU Data Data Bus Address Bus 242 MODULE pcr TITLE 'Program Counter with Data Bus Interface' DECLARATIONS CLOCK pin; PC0..PC4 node istype 'reg_D,buffer'; " PC register bits AB0..AB4 pin; " address bus (5-bits wide) DB0..DB7 pin; " data bus (8-bits wide) PCC pin; " PC count enable PLA pin; " PC load from address bus enable PLD pin; " PC load from data bus enable POA pin; " PC output on address bus tri-state enable POD pin; " PC output on data bus tri-state enable ARS pin; " asynchronous reset (connected to START) " Note: Assume PCC, PLA, and EQUATIONS " retain state PC0.d = !PCC&!PLA&!PLD&PC0.q PC1.d = !PCC&!PLA&!PLD&PC1.q PC2.d = !PCC&!PLA&!PLD&PC2.q PC3.d = !PCC&!PLA&!PLD&PC3.q PC4.d = !PCC&!PLA&!PLD&PC4.q [AB0..AB4] = [PC0..PC4].q; [DB0..DB4] = [PC0..PC4].q; PLD are mutually exclusive load from AB # PLA&AB0.pin # PLA&AB1.pin # PLA&AB2.pin # PLA&AB3.pin # PLA&AB4.pin load from DB # PLD&DB0.pin # PLD&DB1.pin # PLD&DB2.pin # PLD&DB3.pin # PLD&DB4.pin increment PCC&!PC0.q; PCC&(PC1.q$PC0.q); PCC&(PC2.q$(PC1.q&PC0.q)); PCC&(PC3.q$(PC2.q&PC1.q&PC0.q)); PCC&(PC4.q$(PC3.q&PC2.q&PC1.q&PC0.q)); # # # # # " Output logic zero on upper 3-bits of data bus [DB5..DB7] = 0; [AB0..AB4].oe = POA; [DB0..DB7].oe = POD; [PC0..PC4].ar = ARS; [PC0..PC4].clk = CLOCK; END 243 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP=SP-1 Memory Address Data Instruction Register Flags ALU Data Data Bus JSR: Step 1 Address Bus 244 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP Memory Address Data Instruction Register Flags ALU Data Data Bus JSR: Step 2 Address Bus 245 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP Memory Address Data Instruction Register Flags ALU Data Data Bus JSR: Step 3 Address Bus 246 Adding Subroutine Linkage Instructions Implementation of JSR requires three execute cycles: first execute cycle: decrement SP register (SPD) SPD) second execute cycle: output "new" value of SP on address bus (SPA), enable a (SPA), memory write operation (MSL and MWE), (MSL MWE), and tell the PC register to output its value on the data bus (POD) (POD) third execute cycle: tell IR register to output its operand field on the address bus (IRA), and tell the PC register to load the IRA), value on the address bus (PLA) (PLA) 247 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP Memory Address Data Instruction Register Flags ALU Data Data Bus RTS: Step 1 Address Bus 248 Instruction Decoder and Micro-Sequencer Start Clock Program Counter Opcode Address SP=SP+1 Memory Address Data Instruction Register Flags ALU Data Data Bus RTS: Step 2 Address Bus 249 Adding Subroutine Linkage Instructions At first glance, it would appear that two execute cycles are required to implement the RTS instruction As astute digijock(ette)s, however, we always need to be on the lookout for operations that can be overlapped (subject, of course, to the "rules" we learned earlier): Only one device is allowed to drive a bus during any machine cycle (i.e., "bus fighting" must be avoided) Data cannot pass through more than one (edge(edge-triggered) flip-flop or latch per cycle flip250 Adding Subroutine Linkage Instructions Implementation of RTS requires only one execute cycle: first execute cycle: output value of SP on address bus (SPA), enable a memory read (SPA), operation (MSL and MOE), tell the PC to (MSL MOE), load the value on the data bus (PLD), and (PLD), tell the SP register to increment* (SPI) (SPI) *Note: The SP register will be incremented after the PC register is loaded with the contents of the location pointed to by the SP register, i.e., the SP increment is overlapped with the fetch of the next instruction 251 Adding Subroutine Linkage Instructions Modified system control table: MWE MOE POA POD AOE PCC MSL SPD SPA H H H PLA PLD RST H H H H H H H H H H H H H H H H ALE ALX ALY IRA SPI IRL H H H H H H L L H H H H H L H H H Dec. State S0 S1 S1 S1 S1 S1 S1 S1 S1 S2 S3 Instr. Mnem. LDA STA ADD SUB AND HLT JSR RTS JSR JSR H H H H H H L H H H H H H H H H Note: Recall that the RST signal is used to synchronously reset the state counter on the final execute cycle of each instruction 252 " System control equations MSL MOE MWE ARS PCC POA = = = = = = RUN.q&(S0 # S1&(LDA # STA # ADD # SUB # AND # RTS) # S2&JSR); S0 # S1&(LDA # ADD # SUB # AND # RTS); S1&STA # S2&JSR; START; RUN.q&S0; S0; PLA = S3&JSR; POD = S2&JSR; PLD = S1&RTS; IRL IRA AOE ALE ALX ALY = = = = = = RUN.q&S0; S1&(LDA # STA # ADD # SUB # AND); S1&STA; RUN.q&S1&(LDA # ADD # SUB # AND); S1&(LDA # AND); S1&(SUB # AND); SPI = S1&RTS; SPD = S1&JSR; SPA = S1&RTS # S2&JSR; RST = S1&(LDA # STA # ADD # SUB # AND # RTS) # S3&JSR; END 253 Clicker Quiz 254 Q1. The following control signal is not asserted on a fetch cycle: A. B. C. D. E. PCC POA IRL IRA none of the above 255 Q2. Assuming a standard stack convention (in which the SP register points to the top stack item), the following SP control signal(s) will be asserted on the first execute cycle of a JSR instruction: A. B. C. D. E. SPI SPD SPI and SPA SPD and SPA none of the above 256 Q3. Assuming a standard stack convention (in which the SP register points to the top stack item), the following PC control signal(s) will be asserted on the last execute cycle of a JSR instruction: A. B. C. D. E. POA POD PLA PLD none of the above 257 Q4. Assuming a standard stack convention (in which the SP register points to the top stack item), the following SP control signal(s) will be asserted on the first execute cycle of an RTS instruction: A. B. C. D. E. SPI SPD SPI and SPA SPD and SPA none of the above 258 Q5. Assuming a standard stack convention (in which the SP register points to the top stack item), the following PC control signal(s) will be asserted on the last execute cycle of an RTS instruction: A. B. C. D. E. POA POD PLA PLD none of the above 259 Fun Things to Think About... What kinds of new instructions would be useful in writing "real" programs? What new kinds of registers would be good to add to the machine? What new kinds of addressing modes would be nice to have? What would we have to change if we wanted "branch" transfer-of-control instructions transfer-ofinstead of "jump" instructions? These are all good reasons to "continue your `digital life' beyond this course"! 260 ...
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