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Unformatted text preview: ree Lead-F ge a P a c k ns Optio le! b Availa GAL16V8 High Performance E2CMOS PLD Generic Array LogicTM Features HIGH PERFORMANCE E2CMOS TECHNOLOGY -- 3.5 ns Maximum Propagation Delay -- Fmax = 250 MHz -- 3.0 ns Maximum from Clock Input to Data Output -- UltraMOS Advanced CMOS Technology 50% to 75% REDUCTION IN POWER FROM BIPOLAR -- 75mA Typ Icc on Low Power Device -- 45mA Typ Icc on Quarter Power Device ACTIVE PULL-UPS ON ALL PINS E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention EIGHT OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs -- Programmable Output Polarity -- Also Emulates 20-pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability APPLICATIONS INCLUDE: -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Standard Logic Speed Upgrade ELECTRONIC SIGNATURE FOR IDENTIFICATION LEAD-FREE PACKAGE OPTIONS Functional Block Diagram I/CLK CLK 8 I 8 I OLMC I/O/Q OLMC I/O/Q PROGRAMMABLE AND-ARRAY (64 X 32) 8 OLMC I/O/Q I 8 OLMC I/O/Q I 8 OLMC I/O/Q I 8 OLMC I/O/Q I 8 I 8 I OLMC OE OLMC I/O/Q I/O/Q I/OE Pin Configuration PLCC I I 2 I/CLK Vcc 20 18 I/O/Q I/O/Q 16 I/O/Q I/O/Q 8 14 9 I GND 11 I/OE I/O/Q 13 I/O/Q I/O/Q I/O/Q I I I I I 6 4 Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. DIP I/CLK I I I I I 5 15 1 20 Vcc I/O/Q I/O/Q GAL16V8 Top View GAL 16V8 I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q SOIC I/CLK I I I I I I I I GND 10 5 1 20 Vcc I/O/Q I/O/Q I/O/Q I/O/Q 15 I/O/Q I/O/Q I/O/Q I/O/Q 11 I/OE I I I GND 10 11 GAL 16V8 Top View I/OE Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com August 2006 16v8_11 1 Specifications GAL16V8 GAL16V8 Ordering Information Conventional Packaging Commercial Grade Specifications Tpd (ns) 3.5 5 7.5 Tsu (ns) 2.5 3 7 Tco (ns) 3.0 4 5 Icc (mA) 115 115 115 115 115 Ordering # GAL16V8D-3LJ GAL16V8D-5LJ GAL16V8D-7LP GAL16V8D-7LJ GAL16V8D-7LS GAL16V8D-10QP GAL16V8D-10QJ GAL16V8D-10LP GAL16V8D-10LJ GAL16V8D-10LS GAL16V8D-15QP GAL16V8D-15QJ GAL16V8D-15LP GAL16V8D-15LJ GAL16V8D-15LS GAL16V8D-25QP GAL16V8D-25QJ GAL16V8D-25LP GAL16V8D-25LJ GAL16V8D-25LS Package 20-Lead PLCC 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin SOIC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin SOIC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin SOIC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin SOIC 10 10 7 55 55 115 115 115 15 12 10 55 55 90 90 90 25 15 12 55 55 90 90 90 Industrial Grade Specifications Tpd (ns) 7.5 Tsu (ns) 7 Tco (ns) 5 Icc (mA) 130 130 Ordering # GAL16V8D-7LPI GAL16V8D-7LJI GAL16V8D-10LPI GAL16V8D-10LJI GAL16V8D-15LPI GAL16V8D-15LJI GAL16V8D-20QPI GAL16V8D-20QJI GAL16V8D-25QPI GAL16V8D-25QJI GAL16V8D-25LPI GAL16V8D-25LJI Package 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 10 10 7 130 130 15 12 10 130 130 20 13 11 65 65 25 15 12 65 65 130 130 2 Specifications GAL16V8 Lead-Free Packaging Commercial Grade Specifications Tpd (ns) 3.5 5 7.5 Tsu (ns) 2.5 3 7 Tco (ns) 3.0 4 5 Icc (mA) 115 115 115 115 Ordering # GAL16V8D-3LJN GAL16V8D-5LJN GAL16V8D-7LPN GAL16V8D-7LJN GAL16V8D-10QPN GAL16V8D-10QJN GAL16V8D-10LPN GAL16V8D-10LJN GAL16V8D-15QPN GAL16V8D-15QJN GAL16V8D-15LPN GAL16V8D-15LJN GAL16V8D-25QPN GAL16V8D-25QJN GAL16V8D-25LPN GAL16V8D-25LJN Package Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC 10 10 7 55 55 115 115 15 12 10 55 55 90 90 25 15 12 55 55 90 90 Industrial Grade Specifications Tpd (ns) 7.5 Tsu (ns) 7 Tco (ns) 5 Icc (mA) 130 130 Ordering # GAL16V8D-7LJNI GAL16V8D-7LPNI GAL16V8D-10LJNI GAL16V8D-10LPNI GAL16V8D-15LJNI GAL16V8D-15LPNI GAL16V8D-20QJNI GAL16V8D-20QPNI GAL16V8D-25QJNI GAL16V8D-25QPNI GAL16V8D-25LJNI GAL16V8D-25LPNI Package Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP Lead-Free 20-Lead PLCC Lead-Free 20-Pin Plastic DIP 10 10 7 130 130 15 12 10 130 130 20 13 11 65 65 25 15 12 65 65 130 130 Part Number Description XXXXXXXX _ XX X XX X GAL16V8D Device Name Grade Blank = Commercial I = Industrial Speed (ns) L = Low Power Power Q = Quarter Power Package P = Plastic DIP PN = Lead-free Plastic DIP J = PLCC JN = Lead-free PLCC S = SOIC 3 Specifications GAL16V8 Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16V8 . The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL16V8 can emulate. It also shows the OLMC mode under which the GAL16V8 emulates the PAL architecture. PAL Architectures Emulated by GAL16V8 16R8 16R6 16R4 16RP8 16RP6 16RP4 16L8 16H8 16P8 10L8 12L6 14L4 16L2 10H8 12H6 14H4 16H2 10P8 12P6 14P4 16P2 GAL16V8 Global OLMC Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Compiler Support for OLMC Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Registered ABEL CUPL LOG/iC OrCAD-PLD PLDesigner TANGO-PLD P16V8R G16V8MS GAL16V8_R "Registered"1 P16V8R2 G16V8R Complex P16V8C G16V8MA GAL16V8_C7 "Complex"1 P16V8C2 G16V8C Simple P16V8AS G16V8AS GAL16V8_C8 "Simple"1 P16V8C2 G16V8AS3 Auto Mode Select P16V8 G16V8 GAL16V8 GAL16V8A P16V8A G16V8 1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later. 4 Specifications GAL16V8 Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/O's are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function. Registered outputs have eight product terms per output. I/O's have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. CLK Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered outputs. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. D Q Q XOR OE Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 5 Specifications GAL16V8 Registered Mode Logic Diagram DIP & PLCC Package Pinouts 1 0 4 8 12 16 20 24 28 2128 PTD 0000 OLMC 0224 19 2 0256 XOR-2048 AC1-2120 OLMC 0480 18 3 0512 XOR-2049 AC1-2121 OLMC 0736 17 4 0768 XOR-2050 AC1-2122 OLMC 0992 16 5 1024 XOR-2051 AC1-2123 OLMC 1248 15 6 1280 XOR-2052 AC1-2124 OLMC 1504 14 7 1536 XOR-2053 AC1-2125 OLMC 1760 13 8 1792 XOR-2054 AC1-2126 OLMC 2016 12 9 2191 XOR-2055 AC1-2127 OE 11 SYN-2192 AC0-2193 6 Specifications GAL16V8 Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell. Up to six I/O's are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 12 & 19) do not have input capability. Designs requiring eight I/O's can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1 and 11 are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 13 through Pin 18 are configured to this function. XOR Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 12 and Pin 19 are configured to this function. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 7 Specifications GAL16V8 Complex Mode Logic Diagram DIP & PLCC Package Pinouts 1 2128 0 0000 4 8 12 16 20 24 28 PTD OLMC 0224 19 2 0256 XOR-2048 AC1-2120 OLMC 0480 18 3 0512 XOR-2049 AC1-2121 OLMC 0736 17 4 0768 XOR-2050 AC1-2122 OLMC 0992 16 5 1024 XOR-2051 AC1-2123 OLMC 1248 15 6 1280 XOR-2052 AC1-2124 OLMC 1504 14 7 1536 XOR-2053 AC1-2125 OLMC 1760 13 8 1792 XOR-2054 AC1-2126 OLMC 2016 12 9 XOR-2055 AC1-2127 11 2191 SYN-2192 AC0-2193 8 Specifications GAL16V8 Simple Mode In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of generic output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used as input or I/O pins, and are only available as dedicated outputs. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. Vcc Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. XOR Combinatorial Output Configuration for Simple Mode Vcc XOR - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 15 & 16 are permanently configured to this function. Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 9 Specifications GAL16V8 Simple Mode Logic Diagram DIP & PLCC Package Pinouts 1 2128 0 0000 4 8 12 16 20 24 28 PTD OLMC XOR-2048 AC1-2120 19 0224 2 0256 OLMC XOR-2049 AC1-2121 18 0480 3 0512 OLMC XOR-2050 AC1-2122 17 0736 4 0768 OLMC XOR-2051 AC1-2123 16 0992 5 1024 OLMC XOR-2052 AC1-2124 15 1248 6 1280 OLMC XOR-2053 AC1-2125 14 1504 7 1536 OLMC XOR-2054 AC1-2126 13 1760 8 1792 OLMC XOR-2055 AC1-2127 12 11 2016 9 2191 SYN-2192 AC0-2193 10 Specifications GAL16V8D Absolute Maximum Ratings(1) Supply voltage VCC ...................................... 0.5 to +7V Input voltage applied .......................... 2.5 to VCC +1.0V Off-state output voltage applied ......... 2.5 to VCC +1.0V Storage Temperature ................................ 65 to 150C Ambient Temperature with Power Applied ........................................ 55 to 125C 1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Recommended Operating Conditions Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ........................... 40 to 85C Supply voltage (VCC) with Respect to Ground ..................... +4.50 to +5.50V DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH L-3/-5 & -7 (Ind. PLCC) L-7 (Except Ind. PLCC)/-10/-15/-25 Q-10/-15/-20/-25 CONDITION MIN. Vss 0.5 TYP.3 -- -- -- -- -- -- -- -- MAX. 0.8 Vcc+1 100 10 0.5 -- 16 24 UNITS V V A A V V mA mA VIL VIH IIL1 IIH VOL VOH IOL 2.0 -- -- -- 2.4 -- -- IOH IOS2 High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25C -- 30 -- -- 3.2 150 mA mA COMMERCIAL ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open L -3/-5/-7/-10 L-15/-25 Q-10/-15/-25 -- -- -- 75 75 45 115 90 55 mA mA mA INDUSTRIAL ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open L -7/-10/-15/-25 Q -20/-25 -- -- 75 45 130 65 mA mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C 11 Specifications GAL16V8D AC Switching Characteristics Over Recommended Operating Conditions COM PARAMETER COM COM / IND TEST COND1. A A -- -- -- A DESCRIPTION Input or I/O to Comb. Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled 1 1 -- 2.5 0 182 -3 -5 -7 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd tco tcf2 tsu th 3.5 3 2.5 -- -- 1 1 -- 3 0 5 4 3 -- -- 1 1 -- 5 0 100 7.5 5 3 -- -- -- ns ns ns ns ns MHz -- 142.8 -- fmax3 A A 200 250 -- -- 166 166 -- -- 125 125 -- -- MHz MHz twh twl ten tdis -- -- B B C C 24 2 4 -- -- 4.5 4.5 4.5 4.5 34 3 4 -- -- 6 6 5 5 4 4 1 1 1 1 -- -- 9 6 9 6 ns ns ns ns ns ns -- -- -- -- 1 1 1 1 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not 100% tested. 4) Characterized but not 100% tested. Capacitance (TA = 25C, f = 1.0 MHz) SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 12 Specifications GAL16V8D Specifications GAL16V8 AC Switching Characteristics Over Recommended Operating Conditions COM / IND PARAM. TEST COND1. COM / IND IND COM / IND DESCRIPTION Input or I/O to Comb. Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled 3 2 -- -10 MIN. -15 -20 -25 UNITS MAX. MAX. MIN. MAX. MIN. MAX. MIN. tpd tco tcf2 tsu th A A -- -- -- A 10 7 6 -- -- -- 3 2 -- 12 0 45.5 15 10 8 -- -- -- 3 2 -- 13 0 41.6 20 11 9 -- -- -- 3 2 -- 15 0 37 25 12 10 -- -- -- ns ns ns ns ns MHz 7.5 0 66.7 fmax3 A A 71.4 83.3 -- -- 50 62.5 -- -- 45.4 50 -- -- 40 41.6 -- -- MHz MHz twh twl ten t tdis t -- -- B B C C 6 6 1 1 1 1 -- -- 10 10 10 10 8 8 -- -- -- -- -- -- 15 15 15 15 10 10 -- -- -- -- -- -- 18 18 18 18 12 12 -- -- -- -- -- -- 20 20 20 20 ns ns ns ns ns ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25C, f = 1.0 MHz) SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 13 Specifications GAL16V8 Switching Waveforms INPUT or I/O FEEDBACK VALID INPUT tsu CLK INPUT or I/O FEEDBACK VALID INPUT th tco REGISTERED OUTPUT 1/fmax (external fdbk) tpd COMBINATIONAL OUTPUT Combinatorial Output Registered Output INPUT or I/O FEEDBACK OE tdis COMBINATIONAL OUTPUT ten REGISTERED OUTPUT tdis ten Input or I/O to Output Enable/Disable OE to Output Enable/Disable twh CLK 1/ fmax (w/o fb) twl CLK 1/ fmax (internal fdbk) tcf REGISTERED FEEDBACK tsu Clock Width fmax with Feedback 14 Specifications GAL16V8 fmax Descriptions CLK LOGIC ARRAY CLK REGISTER LOGIC ARRAY tsu tco REGISTER fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK t cf t pd fmax with Internal Feedback 1/(tsu+tcf) LOGIC ARRAY REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. Switching Test Conditions Input Pulse Levels GAL16V8D-10 (and slower) GAL16V8D-3/-5/-7 Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 2 3ns 10% 90% +5V Input Rise and Fall Times 1.5ns 10% 90% R1 1.5V 1.5V See figure at right Table 2-0003/16V8 FROM OUTPUT (O/Q) UNDER TEST TEST POINT R2 C L* GAL16V8D (except -3) Output Load Conditions (see figure above) Test Condition A B C Active High Active Low Active High Active Low R1 200 200 200 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 15 Specifications GAL16V8 Switching Test Conditions (Continued) GAL16V8D-3 Output Load Conditions (see figure at right) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 50 50 50 50 50 CL 35pF 35pF 35pF 35pF 35pF TEST POINT R1 +1.45V FROM OUTPUT (O/Q) UNDER TEST Z0 = 50, CL = 35pF* *CL includes test fixture and probe capacitance. Electronic Signature An electronic signature is provided in every GAL16V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GAL16V8 devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. Security Cell A security cell is provided in the GAL16V8 devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Input Buffers GAL16V8 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL16V8 input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, VCC, or Ground. Doing this will tend to improve noise immunity and reduce ICC for the device. Latch-Up Protection GAL16V8 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Typical Input Pull-up Characteristic I n p u t C u r r e n t (u A ) 0 -20 -40 -60 0 1.0 2.0 3.0 4.0 5.0 In p u t V o lt ag e ( V o lt s) 16 Specifications GAL16V8 Power-Up Reset Vcc (min.) Vcc t su CLK t wl t pr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" FEEDBACK/EXTERNAL OUTPUT REGISTER Device Pin Reset to Logic "1" Circuitry within the GAL16V8 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics INPUT/OUTPUT EQUIVALENT SCHEMATICS PIN Feedback PIN Vcc Active Pull-up Circuit Active Pull-up Circuit Vcc ESD Protection Circuit Vref Vcc Tri-State Control Vcc Vref PIN Data Output PIN ESD Protection Circuit Typ. Vref = 3.2V Typical Input Typ. Vref = 3.2V Feedback (To Input Buffer) Typical Output 17 Specifications GAL16V8 GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.2 Normalized Tco vs Vcc 1.2 Normalized Tsu vs Vcc Normalized Tpd 1.1 Normalized Tco Normalized Tsu PT H->L PT L->H 1.1 RISE FALL 1.1 PT H->L PT L->H 1 1 1 0.9 0.9 0.9 0.8 4.50 4.75 5.00 5.25 5.50 0.8 4.50 4.75 5.00 5.25 5.50 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 Normalized Tco vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 Normalized Tsu vs Temp Normalized Tpd Normalized Tco -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Normalized Tsu PT H->L PT L->H RISE FALL PTH->L PT L->H -25 0 25 50 75 1 00 1 25 Temperature (deg. C) Temperature (deg. C) Temperature (deg. C) Delta Tpd vs # of Outputs Switching 0 0 Delta Tco vs # of Outputs Switching Delta Tpd (ns) -0.1 Delta Tco (ns) -0.1 -0.2 -0.2 RISE FALL -0.3 -0.3 RISE FALL -0.4 1 2 3 4 5 6 7 8 -0.4 1 2 3 4 5 6 7 8 Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading 14 12 14 12 Delta Tco vs Output Loading Delta Tpd (ns) 10 8 6 4 2 0 -2 0 50 Delta Tco (ns) RISE FALL 10 8 6 4 2 0 -2 RISE FALL 100 150 200 250 3 00 0 50 100 150 200 250 3 00 Output Loading (pF) Output Loading (pF) 18 Specifications GAL16V8 GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams Vol vs Iol 1 5 Voh vs Ioh 3.25 Voh vs Ioh 0.75 4 3 Voh (V) Vol (V) 3 0.5 2 Voh (V) 0 10 20 30 40 50 2.75 0.25 1 0 0 10 20 30 40 0 2.5 0 1 2 3 4 Iol (mA) Normalized Icc vs Vcc 1.2 1.3 Ioh (mA) Normalized Icc vs Temp 1.2 1.15 Ioh (mA) Normalized Icc vs Freq. 1.2 Normalized Icc Normalized Icc Normalized Icc -25 0 25 50 75 100 125 1.1 1.1 1.05 1 0.95 0.9 0 25 50 75 1 00 1.1 1 1 0.9 0.9 0.8 4.50 4.75 5.00 5.25 5.50 0.8 -55 Supply Voltage (V) Delta Icc vs Vin (1 input) 10 0 10 8 Temperature (deg. C) Input Clamp (Vik) Frequency (MHz) Delta Icc (mA) 20 6 Iik (mA) 30 40 50 60 70 80 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 90 -2 -1.5 -1 -0.5 0 Vin (V) Vik (V) 19 Specifications GAL16V8 GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.15 1.15 Normalized Tco vs Vcc 1.2 Normalized Tsu vs Vcc Normalized Tpd 1.1 RISE FALL 1.05 Normalized Tco Normalized Tsu 1.1 RISE FALL 1.1 RISE FALL 1.05 1 1 1 0.95 0.9 0.95 0.9 4.5 0.9 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5 0.8 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 -55 1.3 Normalized Tco vs Temp 1.3 Normalized Tsu vs Temp Normalized Tpd Normalized Tco 1.1 1 0.9 0.8 -55 Normalized Tsu RISE FALL 1.2 RISE FALL 1.2 1.1 1 0.9 0.8 -55 RISE FALL -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 -25 0 25 50 75 1 00 1 25 Temperature (deg. C) Temperature (deg. C) Temperature (deg. C) Delta Tpd vs # of Outputs Switching 0 -0.1 -0.2 Delta Tco vs # of Outputs Switching 0 -0.1 -0.2 Delta Tpd (ns) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 1 2 3 4 5 6 7 8 Delta Tco (ns) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 1 2 3 4 5 6 7 8 RISE FALL RISE FALL Number of Outputs Switching Delta Tpd vs Output Loading 12 12 Number of Outputs Switching Delta Tco vs Output Loading Delta Tpd (ns) Delta Tco (ns) 8 RISE FALL 8 RISE FALL 4 4 0 0 -4 0 50 100 150 200 250 3 00 -4 0 50 100 150 200 250 3 00 Output Loading (pF) Output Loading (pF) 20 Specifications GAL16V8 GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams Vol vs Iol 0.5 4 Voh vs Ioh 4 Voh vs Ioh 0.4 3 Voh (V) 3.5 2 Vol (V) 0.3 0.2 Voh (V) 0 5 10 15 20 25 3 1 0.1 0 1 6 11 16 21 26 0 2.5 0.00 1.00 2.00 3.00 4.00 5.00 Iol (mA) Normalized Icc vs Vcc 1.1 1.2 Ioh (mA) Normalized Icc vs Temp 1.15 Ioh (mA) Normalized Icc vs Freq Normalized Icc Normalized Icc 1 1 Normalized Icc -25 0 25 50 88 1 00 1 25 1.1 1.1 1.05 0.9 0.9 1 0.8 3 3.15 3.3 3.45 3.6 0.8 -55 0.95 1 15 25 50 75 1 00 Supply Voltage (V) Temperature (deg. C) Frequency (MHz) Delta Icc vs Vin (1 input) 9 8 0 10 20 30 Input Clamp (Vik) Delta Icc (mA) 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Iik (mA) 40 50 60 70 80 90 -3 -2.5 -2 -1.5 -1 -0.5 0 Vin (V) Vik (V) 21 Specifications GAL16V8 GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.2 RISE FALL Normalized Tco vs Vcc 1.2 Normalized Tsu vs Vcc Normalized Tpd 1.1 PT H->L PT L->H Normalized Tco Normalized Tsu 1.1 1.1 PT H->L PT L->H 1 1 1 0.9 0.9 0.9 0.8 4.50 4.75 5.00 5.25 5.50 0.8 4.50 4.75 5.00 5.25 5.50 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.3 Normalized Tco vs Temp 1.3 Normalized Tsu vs Temp Normalized Tpd Normalized Tco 1.1 1 0.9 0.8 0.7 -55 1.1 1 0.9 0.8 0.7 -55 Normalized Tsu PT H->L PT L->H 1.2 RISE FALL 1.2 1.1 1 0.9 0.8 0.7 -55 PT H->L PT L->H -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Temperature (deg. C) Temperature (deg. C) Temperature (deg. C) Delta Tpd vs # of Outputs Switching 0 -0.2 0 -0.2 Delta Tco vs # of Outputs Switching Delta Tpd (ns) -0.4 -0.6 -0.8 -1 -1.2 1 2 3 4 5 6 7 8 Delta Tco (ns) -0.4 -0.6 -0.8 -1 -1.2 1 2 3 4 5 6 7 8 RISE FALL RISE FALL Number of Outputs Switching Delta Tpd vs Output Loading 12 10 12 10 Number of Outputs Switching Delta Tco vs Output Loading Delta Tpd (ns) Delta Tco (ns) 8 6 4 2 0 -2 -4 -6 0 50 RISE FALL 8 6 4 2 0 -2 -4 RISE FALL 100 150 200 250 300 0 50 100 150 200 250 300 Output Loading (pF) Output Loading (pF) 22 Specifications GAL16V8 GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams Vol vs Iol 0.6 5 4 Voh vs Ioh 4 Voh vs Ioh 3.8 Voh (V) Voh (V) 0 10 20 30 40 50 0.4 Vol (V) 3 2 3.6 3.4 3.2 0.2 1 0 0 10 20 30 40 0 3 0 1 2 3 4 Iol (mA) Normalized Icc vs Vcc 1.2 1.3 1.2 Ioh (mA) Normalized Icc vs Temp 1.4 1.3 Ioh (mA) Normalized Icc vs Freq. Normalized Icc Normalized Icc 1.1 1 0.9 0.8 Normalized Icc -25 0 25 50 75 100 125 1.1 1.2 1.1 1 0.9 0.8 0 25 50 75 100 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 0.7 -55 Supply Voltage (V) Temperature (deg. C) Frequency (MHz) Delta Icc vs Vin (1 input) 8 0 10 Input Clamp (Vik) Delta Icc (mA) 6 4 Iik (mA) 0 0.5 1 1.5 2 2.5 3 3.5 4 20 30 40 50 2 0 60 -2 -1.5 -1 -0.5 0 Vin (V) Vik (V) 23 Specifications GAL16V8 Revision History Date August 2006 Version 16v8_10 16v8_11 Change Summary Previous Lattice release. Updated for lead-free package options. 24 ...
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