L14.sp11 - Announcement Announcement s s Mid-term exam will...

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Announcement s Announcement s Mid-term exam will be on material covered through March 4 , 2011 and the relevant readings. Final Exam on May 9 at 7 p.m. Let us know if you have a conflict with the final exam. See UIUC policy on conflicts.
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Distributed Systems CS 425 / CSE 424 / ECE 428 Fall 2010 Distributed Systems CS 425 / CSE 424 / ECE 428 Fall 2010 Distributed Shared Memory Required Reading: Sections 18.1.1, 18.2.3, 18.2.4, 18.2.5, 18.3.1, 18.3.2, 18.3.3 Recommended Reading: Rest of Chapter 18. 010, I . Gupta, K. Nahrtstedt, S. Mitra, N. Vaidya, M. T. Harandi, J. Hou
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The Basic Model of DSM The Basic Model of DSM 0 1 2 3 4 5 6 7 8 9 0 2 1 4 7 5 3 6 8 9 P1 P2 P3 Shared Address Space 0 1 2 3 4 5 6 7 8 9 0 2 1 4 7 5 3 6 8 9 Shared Address Space 9 Page Transfer 0 1 2 3 4 5 6 7 8 9 0 2 1 4 7 5 3 6 8 9 Shared Address Space 9 Read-only replicated page
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Shared Memory vs. Message Passing Shared Memory vs. Message Passing In a multiprocessor , two or more processors share a common main memory. Any process on a processor can read/write any word in the shared memory. All communication through a bus. E.g., Cray supercomputer Called Shared Memory In a multicomputer , each processor has its own private memory. All communication using a network. E.g., CSIL PC cluster Easier to build: One can take a large number of single-board computers, each containing a processor, memory, and a network interface, and connect them together. (called COTS=“Components off the shelf” ) Uses Message passing Message passing can be implemented over shared memory. Shared memory can be implemented over message passing. Let’s look at shared memory by itself.
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Bus-Based Multiprocessors with Shared Memory Bus-Based Multiprocessors with Shared Memory When any of the CPUs wants to read a word from the memory, it puts the address of the requested word on the address line, and asserts the bus control (read) line. To prevent two CPUs from accessing the memory at the same time, a bus arbitration mechanism is used, i.e., if the control line is already asserted, wait. To improve performance, each CPU can be equipped with a snooping cache . Snooping used in both (a) write-through and (b) write-once models CPU CPU Memory CPU CPU CPU CPU Cache Cache Cache Memory Bus Bus
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Cache Consistency – Write Through Cache Consistency – Write Through Event Action taken by a cache in response to its own operation Action taken by other caches in response (to a remote operation) Read hit Fetch data from local cache (no action) Read miss Fetch data from memory and store in cache (no action) Write miss Update data in memory and store in cache Invalidate cache entry Write hit Update memory and cache Invalidate cache entry All the other caches see the write (because they are snooping on the bus) and check to see if they are also holding the word being modified. If so, they invalidate the cache entries.
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Cache Consistency – Write Once Cache Consistency – Write
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This note was uploaded on 02/08/2012 for the course ECE 428 taught by Professor Hu during the Spring '08 term at University of Illinois, Urbana Champaign.

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L14.sp11 - Announcement Announcement s s Mid-term exam will...

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