AS7C34096 - March 2002 AS7C4096 AS7C34096 5V/3.3V 512K 8...

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March 2002 Copyright © Alliance Semiconductor. All rights reserved. AS7C4096 AS7C34096 5V/3.3V 512K × 8 CMOS SRAM ® 5/23/02; v.1.8 Alliance Semiconductor P. 1 of 10 Features • AS7C4096 (5V version) • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: ACTIVE - 1375 mW (AS7C4096) / max @ 12 ns - 468 mW (AS7C34096) / max @ 12 ns • Low power consumption: STANDBY - 110 mW (AS7C4096) / max CMOS - 72 mW (AS7C34096) / max CMOS • Equal access and cycle times • Easy memory expansion with CE , OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2 • ESD protection 2000 volts • Latch-up current 200 mA Logic block diagram 524,288 × 8 Array (4,194,304) Sense amp Input buffer I/O8 I/O1 OE CE WE Column decoder Row decoder Control Circuit A0 A1 A2 A3 A4 A5 A6 A7 V CC GND A8 A10 A11 A12 A13 A14 A15 A16 A17 A18 A9 Pin arrangement s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A15 OE I/O8 I/O7 GND V CC I/O6 I/O5 A14 A13 A12 A11 A10 NC A0 A1 A2 A3 A4 CE I/O1 I/O2 V CC GND I/O3 I/O4 WE A5 A6 A7 17 18 A8 A9 36 35 34 33 NC A18 A17 A16 GND V CC I/O6 I/O5 NC A14 A13 A12 A11 A10 A4 CE I/O1 I/O2 V CC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 I/O8 I/O7 A1 A2 A3 A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 A16 A15 A17 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 NC NC NC NC NC NC NC NC NC OE A18 36-pin SOJ (400 mil) 44-pin TSOP 2 48-pin BGA Package 1 2 3 4 5 6 A A 0 A 1 NC A 3 A 6 A 8 B I/O 5 A 2 WE A 4 A 7 I/O 1 C I/O 6 NC NC A 5 NC I/O 2 D V SS NC NC NC NC V CC E V CC NC NC NC NC V SS F I/O 7 NC A 18 A 17 NC I/O 3 G I/O 8 OE CE A 16 A 15 I/O 4 H A 9 A 10 A 11 A 12 A 13 A 14 Selection guide –10 –12 –15 –20 Unit Maximum address access time 10 12 15 20 ns Maximum outputenable access time 5 6 7 9 ns Maximum operating current AS7C4096 250 220 180 mA AS7C34096 160 130 110 100 mA Maximum CMOS standby current AS7C4096 20 20 20 mA AS7C34096 20 20 20 20 mA
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® AS7C4096 AS7C34096 5/23/02; v.1.8 Alliance Semiconductor P. 2 of 10 Functional description The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t AA , t RC , t WC ) of 10/12/15/20 ns with output enable access times (t OE ) of 5/6/7/8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The AS7C4096 is guaranteed not to exceed 110 mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE ) and chip enable (CE ). Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE ) or write enable (WE ).
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This note was uploaded on 02/08/2012 for the course ECE 412 taught by Professor Chen during the Fall '08 term at University of Illinois, Urbana Champaign.

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AS7C34096 - March 2002 AS7C4096 AS7C34096 5V/3.3V 512K 8...

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