XAPP967 (v1.1) February 26, 2007
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Adding custom logic to an embedded design targeting the Xilinx FPGA can be achieved using
different methods and techniques. This application note focuses on using the EDK OPB IPIF
Interface to achieve such integration.
This document contains guidelines for choosing the required OPB IPIF Services to use to
interface the user logic to the OPB without having to create all the provided IPIF Services.
Initially, the Create IPIF Wizard is used to generate a user core template, then the user logic
HDL is integrated to the template according to the core requirements. Finally, the IPIF Wizard
will be used to import the newly created core back into the EDK environment.
The IPIF Wizard generates a drivers template for the IP. The template is used to access the
Custom OPB Core from the System SW Application.
An example design targeting the Xilinx Reference Platform ML403 is provided to illustrate the
design flow, understand the hardware and software implementations, and to test the generated
system on the ML403 demonstration board.
Included with this application note is one reference system:
Adding custom logic to an embedded design can be done using different approaches.
Custom logic can communicate with the embedded system using the OCM bus in a
PowerPC™ based system. For MicroBlaze™ systems, the FSL interfaces are an excellent way
to make logic directly visible to the processor. Using the OPB/PLB GPIOs with an indexed
addressing (if required) can help in integrating user logic to an embedded design.
The second port, Port B, of the BRAM memories connected to the OCM, PLB, LMB, or OPB