FV_Summer_School2011__HW_Verif

FV_Summer_School2011__HW_Verif - Summer Formal 2011...

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May 2011 Summer Formal 2011 Summer Formal 2011 Jason Baumgartner www.research.ibm.com/sixthsense IBM Corporation Hardware Verification Foundations
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2 Outline Class 1: Hardware Verification Foundations Hardware and Hardware Modeling Hardware Verification and Specification Methods Algorithms for Reasoning about Hardware Class 2: Hardware Verification Challenges and Solutions Moore’s Law v. Verification Complexity Coping with Verification Complexity via Transformations Class 3: Industrial Hardware Verification In Practice Evolution of Model Checking Testbench Authoring Concepts Case Studies
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3 Outline Hardware and Hardware Modeling Hardware Verification and Specification Methods Algorithms for Reasoning about Hardware Falsification Techniques Proof Techniques Reductions
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4 Introduction to Hardware Integrated circuits (ICs) are ubiquitous in modern life Computers, Audio/Video devices, Transportation, Medical devices, Communications, Appliances, … Many types of ICs Processors, GPUs, RAM, Caches, Networking / Data Routing, Digital Signal Processors, Encryption, … Hardware refers to fabricated ICs – or their origins
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5 Introduction to Hardware Contemporary hardware design often begins as a Hardware Description Language (Verilog, VHDL) Taken through a series of synthesis steps into gate-level netlist representation, then a transistor-based representation Mapped to a physical layout, lithography masks, … finally silicon! always @(posedge clk) begin if ( r ) then p <= 0 else p <= p+1; end if; end HDL Netlist Schematic Layout IC
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6 Introduction to Hardware Verification Numerous types of verification relevant to hardware design Also timing analysis, circuit analysis, protocol analysis, … always @(posedge clk) begin if ( r ) then p <= 0 else p <= p+1; end if; end HDL Netlist Schematic Layout IC Equivalence Checking Equivalence Checking Layout vs Schematic Wafer Test
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7 Introduction to Hardware Verification We focus solely upon logical implementation verification Including functional verification , i.e. model checking Though the techniques we discuss may also be applied to architectural models, protocol models, software-like models … As long as they are synthesizable always @(posedge clk) begin if ( r ) then p <= 0 else p <= p+1; end if; end HDL Netlist Equivalence Checking IEEE Standard 754-2008 Functional Verification
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8 Introduction to Hardware Hardware may be represented as a program Or as a gate-level netlist We hereafter assume a netlist view of hardware Finite, discrete (Boolean), no combinational cycles r p0 p1 always @(posedge clk) begin if ( r ) then p <= 0 else p <= p+1; end if; end
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9 Netlist Formats: Numerous Types Logic synthesis usually follows a structured flow Word-level netlist directly correlating to HDL constructs Adder: a <= b + c; Multiplexor: a <= if sel then data1 else data0; Then a sequence of steps into simpler logic primitives For silicon flows, primitives are dictated by fabrication technology Various libraries are possible; often NAND and NOR gates For verification flows, the And / Inverter Graph is popular
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This note was uploaded on 02/07/2012 for the course CS 4322 taught by Professor Martinrinard during the Spring '11 term at MIT.

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FV_Summer_School2011__HW_Verif - Summer Formal 2011...

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