Patterson

Patterson - Futureof Computer Architecture DavidA.Patterson

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1 Future of  Computer  Architecture David A. Patterson Pardee Professor of Computer Science, U.C. Berkeley President, Association for Computing Machinery February, 2006
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2 High Level Message Everything is changing; Old conventional  wisdom is out We DESPERATELY need a new  architectural solution for microprocessors  based on parallelism Need to create a “watering hole” to bring  everyone together to quickly find that solution architects, language designers, application experts, numerical  analysts, algorithm designers, programmers, …
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3 Outline Part I: A New Agenda for Computer  Architecture Old Conventional Wisdom  vs. New Conventional Wisdom Part II: A “Watering Hole” for Parallel  Systems Research Accelerator for Multiple Processors Conclusion
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4 Old CW: Chips reliable internally, errors at pins New CW: ≤65 nm  Old CW: Demonstrate new ideas by building chips New CW: Mask costs, ECAD costs, GHz clock  rates   researchers can’t build believable  prototypes Old CW: Innovate via compiler optimizations +  architecture New: Takes > 10 years before new optimization at  leading conference gets into production compilers Old: Hardware is hard to change, SW is flexible Conventional Wisdom (CW)  in Computer Architecture
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5 Old CW: Power is free, Transistors expensive New CW:  “Power wall”  Power expensive, Xtors free  (Can put more on chip than can afford to turn on) Old: Multiplies are slow, Memory access is fast New:  “Memory wall”  Memory slow, multiplies fast  (200 clocks to DRAM memory, 4 clocks for FP multiply) Old : Increasing Instruction Level Parallelism via  compilers, innovation (Out-of-order, speculation, VLIW, …) New CW:  “ILP wall”  diminishing returns on more ILP  New: Power Wall + Memory Wall + ILP Wall =  Brick Wall Old CW: Uniprocessor performance 2X / 1.5 yrs New CW: Uniprocessor performance only 2X / 5 yrs? Conventional Wisdom (CW)  in Computer Architecture
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6 1 10 100 1000 10000 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 Performance (vs. VAX-11/780) 25%/year 52%/year ??%/year Uniprocessor Performance (SPECint) VAX : 25%/year 1978 to 1986 RISC + x86: 52%/year 1986 to 2002 RISC + x86: ??%/year 2002 to present From Hennessy and Patterson, Computer Architecture: A Quantitative Approach , 4th edition, 2006 Sea change in chip design: multiple “cores” or processors per chip 3X
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7 Sea Change in Chip Design Intel 4004 (1971): 4-bit processor, 2312 transistors, 0.4 MHz,  10 micron PMOS, 11 mm chip  Processor is the new transistor? RISC II (1983): 32-bit, 5 stage 
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This note was uploaded on 02/09/2012 for the course ECE 565 taught by Professor Lee during the Spring '11 term at IUP.

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Patterson - Futureof Computer Architecture DavidA.Patterson

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