01_isa - Instruction Set Architecture (ISA) App App App...

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CIS 371 (Roth/Martin): Instruction Set Architectures 1 CSE 371 Computer Organization and Design Unit 1: Instruction Set Architectures CIS 371 (Roth/Martin): Instruction Set Architectures 2 Instruction Set Architecture (ISA) • What is an ISA? • And what is a good ISA? • Aspects of ISAs • With examples: LC3, MIPS, x86 • RISC vs. CISC • Compatibility is a powerful force • Tricks: binary translation, μ ISAs CPU Mem I/O System software App App App CIS 371 (Roth/Martin): Instruction Set Architectures 3 Readings • P+H • Chapter 2 CIS 371 (Roth/Martin): Instruction Set Architectures 4 What Is An ISA? ISA (instruction set architecture) • A well-defined hardware/software interface • The “contract” between software and hardware Functional definition of operations, modes, and storage locations supported by hardware Precise description of how to invoke, and access them • Not in the “contract” • How operations are implemented • Which operations are fast and which are slow and when • Which operations take more power and which take less • Instruction ! Insn • ‘Instruction’ is too long to write in slides
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CIS 371 (Roth/Martin): Instruction Set Architectures 5 A Language Analogy for ISAs Communication • Person-to-person ! software-to-hardware Similar structure Narrative ! program • Sentence ! insn • Verb ! operation (add, multiply, load, branch) • Noun ! data item (immediate, register value, memory value) • Adjective ! addressing mode Many different languages, many different ISAs Similar basic structure, details differ (sometimes greatly) • Key differences between languages and ISAs Languages evolve organically, many ambiguities, inconsistencies ISAs are explicitly engineered and extended, unambiguous CIS 371 (Roth/Martin): Instruction Set Architectures 6 The Sequential Model • Basic structure of all modern ISAs • Processor logically executes loop at left Atomically : insn X finishes before insn X+1 starts Program order : total order on dynamic insns • Order and named storage define computation • Value flows from insn X to Y via storage A iff… • A=X’s output, X=Y’s input, Y after X in program order • No interceding insn Z where A=Z’s output • Convenient feature: program counter (PC) Insn itself at memory[PC] • Next PC is PC++ unless insn says otherwise Fetch Fetch Decode Decode Read Inputs Read Inputs Execute Execute Write Output Next Insn CIS 371 (Roth/Martin): Instruction Set Architectures 7 LC3 • LC3 highlights • 1 datatype: 16-bit 2C integer • Addressible of memory locations: 16 bits • Instructions are 16 bits • 3 arithmetic operations: add, and, not • Build everything else from these • 8 registers, load-store model, three addressing modes • Condition codes for branches • Support for traps and interrupts • Why is LC3 this way? (and not some other way?) • What are some other options? CIS 371 (Roth/Martin): Instruction Set Architectures
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01_isa - Instruction Set Architecture (ISA) App App App...

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