xx - Ted Borys - CSI 404 3/2/2004 Section 5 Page 5-1...

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Unformatted text preview: Ted Borys - CSI 404 3/2/2004 Section 5 Page 5-1 Mano’s Basic Computer Memory unit with 4096 16-bit words Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, SC Flip-flops: I, S, E, R, IEN, FGI, FGO 3 x 8 op decoder and 4 x 16 timing decoder 16-bit common bus Control logic gates Adder and logic circuit connected to input of AC Basic Computer Organization and Design Slides with white background courtesy of Mano text for this class 1 Instruction Code 2 Stored Program Organization Computer instruction is binary code that specifies a sequence of microoperations Operation code + Address One processor register AC – accumulator Instruction format Op code must have n bits for ≤ 2n operations Op code sometimes called a macrooperation Address is register or memory location 4-bit op code 12-bit address (for 212 = 4096 memory words) Instruction execution cycle Memory location is operand address Shorten “instruction code” to “instruction” Instructions and data in memory Read 16-bit instruction from memory Use 12-bit address to fetch operand from memory Execute 4-bit op code 3 Stored Program Organization 4 Address Types 12-bit instruction address Immediate Actual data value Direct Memory address where data (operand) resides Indirect Memory address where memory address of data (operand) resides Effective address is the address of the operand Lead bit of instruction used as indirect flag 5 © 2004 by Ted Borys. All rights reserved. 6 Ted Borys - CSI 404 3/2/2004 Direct / Indirect Address Page 5-2 Basic Computer Registers 7 Program Counter (PC) 8 Registers + Memory Layout Holds memory address of next instruction Next instruction is fetched after current instruction completes execution cycle PC is incremented right after instruction is fetched from memory PC value can be replaced by new address when executing a branch instruction 9 Register Control Inputs 10 Common Bus Connects registers and memory Specific output selected by S2S1S0 Load (LD) Increment (INR) Clear (CLR) When register has < 16 bits, high-order bus bits are set to 0 Register with LD enabled reads data from bus Memory with Write enabled reads bus Memory with Read enabled puts data on bus When S2S1S0 = 111 11 © 2004 by Ted Borys. All rights reserved. 12 Ted Borys - CSI 404 3/2/2004 Address Register (AR) Page 5-3 Accumulator (AC) Always used to specify address within memory unit Dedicated register eliminates need for separate address bus Content of any register output connected to the bus can be written to memory Any register input connected to bus can be target of memory read Input comes from adder and logic circuit Adder and logic circuit Input 16-bit output of AC 16-bit data register (DR) 8-bit input register (INPR) Output 16-bit input of AC E flip-flop (extended AC bit, aka overflow) As long as its LD is enabled 13 Timing Is Everything DR and AC input used for arithmetic and logic microoperations 14 Bus Connections Content of any register output connected to the bus can be applied to the bus and content of any register input connected to the bus can be loaded from the bus during the same clock cycle These 2 microoperations can be executed at the same time DR ← AC and AC ← DR 15 Basic Instruction Formats 16 Instruction Format Only 3 bits used for op code Looks like only 8 different op codes are possible Wrong! For op code 111, one of the low-order 12 bits is turned on to extend the op code definition 17 © 2004 by Ted Borys. All rights reserved. 18 Ted Borys - CSI 404 3/2/2004 Basic Instructions Page 5-4 Instruction Set Completeness Arithmetic, logical, and shift Move data from and to memory and registers Program control and status check Input and output (I/O, I/O, it’s off to the bus we go…) 19 Control Unit 20 Control Unit Instruction read from memory and put in IR Leftmost bit put in I flip-flop 3-bit op code decoded with 3 x 8 decoder into D0 to D7 4-bit sequence counter (SC) decoded with 4 x 16 decoder into T0 to T15 (timing signals) I, D0 to D7, T0 to T15, rightmost 12 bits of IR, and other inputs are fed into control and logic gates 21 Sequence Counter (SC) 22 Timing Diagram Inputs are increment (INR) and clear (CLR) Example SC incremented to provide T0, T1, T2, T3, and T4 At time T4, SC is cleared to 0 if D3 is active Written as: D3T4: SC ← 0 23 © 2004 by Ted Borys. All rights reserved. 24 Ted Borys - CSI 404 3/2/2004 Instruction Cycle Page 5-5 Fetch And Decode Fetch instruction from memory Decode the instruction Read effective address from memory if indirect address Execute the instruction SC cleared to 0, generating timing signal T0 After each clock pulse, SC is incremented Fetch and decode microoperations T0: AR ← PC T1: IR ← M[AR], PC ← PC + 1 T2: D0,…D7 ← decode IR(12-14), AR ← IR(0-11), I ← IR(15) 25 Fetch Phase 26 Instruction Cycle Flowchart 27 Instruction Paths D′7IT3: D′7I′T3: D7I′T3: D7IT3: 28 Register-Reference Instructions AR ← M[AR] Do nothing Execute a register-reference instruction Execute an I/O instruction 29 © 2004 by Ted Borys. All rights reserved. 30 Ted Borys - CSI 404 3/2/2004 Page 5-6 AND to AC Memory-Reference Instructions D0T4: DR ← M[AR] D0T5: AC ← AC ⋀ DR, SC ← 0 31 ADD to AC 32 LDA: Load AC D1T4: DR ← M[AR] D1T5: AC ← AC + DR, E ← Cout, SC ← 0 D2T4: DR ← M[AR] D2T5: AC ← DR, SC ← 0 33 STA: Store AC BUN: Branch Unconditionally D3T4: M[AR] ← AC, SC ← 0 D4T4: PC ← AR, SC ← 0 35 © 2004 by Ted Borys. All rights reserved. 34 36 3/2/2004 Ted Borys - CSI 404 BSA: Branch & Save Return Address Page 5-7 BSA Example D5T4: M[AR] ← PC, AR ← AR + 1 D5T5: PC ← AR, SC ← 0 37 ISZ: Increment & Skip if Zero 38 Memory-Reference Instructions Increment word specified by effective address If value = 0, increment PC D6T4: DR ← M[AR] D6T5: DR ← DR + 1 D6T6: M[AR] ← DR, SC ← 0, if (DR = 0) then (PC ← PC + 1) 39 40 Input Register INPR Output Register OUTR 1-bit input flip-flop FGI 1-bit output flip-flop FGO Initially cleared to 0 Initially set to 1 When key hit on keyboard Computer checks FGO, when set to 1 8-bit alphanumeric code is shifted into INPR Input flag FGI set to 1 No more input can be accepted from keyboard Parallel transfer from AC to OUTR FGO cleared to 0 No more output can be sent from computer Computer checks FGI, when set to 1 Output device accepts 8-bit character Parallel transfer from INPR to AC FGI cleared to 0 More input can now be accepted from keyboard FGO set to 1 More output can now be sent from computer 41 © 2004 by Ted Borys. All rights reserved. 42 3/2/2004 Ted Borys - CSI 404 Input-Output Configuration Page 5-8 Input-Output Instructions 43 Interrupt Enable IEN 44 Interrupt Flowchart Having computer constantly check FGI and FGO via an executable instruction is a waste of time Instead, IEN is programmatically set, effectively saying “let me know if you need me” Meanwhile, it keeps executing instructions During each execution cycle, if computer detects FGI or FGO is set, then R is set to 1 The interrupt happens when the computer is ready to fetch the next instruction R = 0 means go through instruction cycle R = 1 means go through interrupt cycle 45 Interrupt Cycle Example 46 Interrupt Cycle Condition for setting R to 1 T′0T′1T′2(IEN)(FGI + FGO): R ← 1 Fetch phase modified to service interrupt RT0: AR ← 0, TR ← PC RT1: M[AR] ← TR, PC ← 0 RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0 47 © 2004 by Ted Borys. All rights reserved. 48 Ted Borys - CSI 404 3/2/2004 Computer Operation Flowchart Page 5-9 Inputs To Control Logic Gates Two decoders 8-bit instruction and 16-bit sequence Seven flip-flops: I, S, E, R, IEN, FGI, FGO IR bits 0 through 11 AC bits 0 through 15 Check if AC = 0 and check sign bit DR bits 0 through 15 Check if DR = 0 49 Outputs Of Control Logic Gates 50 AR Control Gates Control inputs of nine registers Control read & write inputs of memory Set, clear, or complement flip-flops S2, S1, and S0 to select a register for the bus Control AC adder and logic circuit Register control inputs: LD, INR, and CLR Find all statements that alter AR contents AR ← PC LD R′T0: AR ← IR(0-11) LD R′T2: AR ← M[AR] LD D′7IT3: RT0: AR ← 0 CLR AR ← AR + 1 INR D5T4: 51 AR Control Gates 52 IEN Control Gates Find all statements that change IEN D7IT3B7: IEN ← 1 D7IT3B6: IEN ← 0 IEN ← 1 RT2: 53 © 2004 by Ted Borys. All rights reserved. 54 Ted Borys - CSI 404 3/2/2004 IEN Control Gates Page 5-10 Encoder For Bus Selection Circuit 55 Boolean Functions For Encoder 56 Boolean Function For x1 S0 = x1 + x3 + x5 + x7 S1 = x2 + x3 + x6 + x7 S2 = x4 + x5 + x6 + x7 Find logic that makes x1 = 1 by finding instructions that have AR as a source PC ← AR D4T4: PC ← AR D5T5: Therefore x1 = D4T4 + D5T5 Repeat for other six inputs 57 Circuits Associated With AC 58 AC Control Gates Find all statements that alter AC contents AC ← AC ⋀ DR D0T5: AC ← AC + DR D1T5: D2T5: AC ← DR D7IT3B11: AC(0-7) ← INPR D7I′T3B9: AC ← AC D7I′T3B7: AC ← shr AC, AC(15) ← E D7I′T3B6: AC ← shl AC, AC(0) ← E D7I′T3B11: AC ← 0 D7I′T3B5: AC ← AC + 1 59 © 2004 by Ted Borys. All rights reserved. 60 3/2/2004 Ted Borys - CSI 404 AC Control Gates Adder And Logic Circuit 61 Mano’s Basic Computer Memory unit with 4096 16-bit words Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, SC Flip-flops: I, S, E, R, IEN, FGI, FGO 3 x 8 op decoder and 4 x 16 timing decoder 16-bit common bus Control logic gates Adder and logic circuit connected to input of AC 63 © 2004 by Ted Borys. All rights reserved. Page 5-11 62 ...
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This note was uploaded on 02/09/2012 for the course CSCI 504 taught by Professor Jon during the Spring '11 term at IUP.

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