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7794-driller-pipelining-ilp

# Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)

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Register Help Remember Me? Forum Today's Posts FAQ Calendar Community Member List Forum Actions Mark Forums Read Quick Links View Forum Leaders Forum Rules Blogs What's New? Advanced Search Forum Test preparation GRE Subject Tests GRE Computer Science Driller for pipelining & ILP !! 1. What are the Urch forums? Ask a question right now. The Urch forums are a side project of the education website TestMagic and are dedicated to discussions of academic matters, including college admissions , test prep (including the GMAT , GRE , SAT , and more), and yes, Economics . And now, no registration is required! You may ask a question right now . (Try it!) Of course, if you'd like the benefits of a free membership, feel free to create an account now. Object 1 Object 2 Object 5 Log in

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Switch to Hybrid Mode Switch to Threaded Mode 1. 11-05-2003, 11:15 PM #1 wood An Urch Guru Pundit Swami Sage Join Date Jul 2003 Location Brazil Posts 1,360 Rep Power 14 Good post? | Hey... some of them are damn easy... but that's what I'm afraid of... get all the difcicult ones and make hasty decision on easy ones. So, let's go. Q1) What are the limits on how much a processor's performance can be improved using pipelining?? Q2) Given an unpipelined processor with a 10ns cycle time and pipeline latches with 0.5ns latency: (a) what are the cycle times of pipelined versions of the processor with 2, 4, 8, and 16 stages (b) how many stages of pipelining are required to achieve a cycle time of 2ns? 1ns? (c) what is the minimum cycle time achievable with a 4-stage pipeline if additional logic is assigned to the final stage to balance the additional latency of the pipeline latches in the other stages?

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