AppendixA

Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)

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Appendix A Pipelining: Basic and Intermediate Concepts
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Overview Introduction Pipeline concepts Basics of RISC instruction set Classic 5-stage pipeline Pipeline Hazards Stalls, structural hazards, data hazards Branch hazards Pipeline Implementation Simple MIPS pipeline Implementation Difficulties for Pipelines Exceptions, instruction set complications Extending MIPS Pipeline to Multicycle operations Example: MIPS R4000 Pipeline
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Pipelining Similar to an assembly line Add partA Widget Definition Add partB Add partC Add partD Add partA, then B, then C, then D Widget Definition
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CPU Pipelining Fetch Instruction 1 Decode Execute Memory Fetch, then decode, then execute then access memory if needed then write results if needed Instruction 2 multiple clock cycles, or one LONG clock cycle Write Results Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 1 1 cycle 1 cycle 1 cycle 1 cycle 1 cycle
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Performance and Pipelining For the following assumptions: N stages in the pipeline Unpipelined execution time for 1 instruction is T Pipeline stages are equal and perfectly balanced Then Execution time for pipelined version = Throughput increase is N T N
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Advantages of Pipelining Significant speedup without much additional hardware. Invisible to the programmer
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RISC (MIPS) Pipeline All ALU operations operate on registers Only load and store affect memory Load and store of 8,16,32-bit items available Few instruction formats All instructions the same size
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Non-pipelined Implementation Multi-cycle implementation Simplified to better understand transition to pipelined version Not the most efficient implementation Datapath Control
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Simplified Datapath Memory (instructions and data) I n s t r u c i o R e g Register File ALU Program Counter Branch Target Multiplexors not shown Control signals not shown Sign extend and shift modules not shown
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Simplified Control State Diagram IFetch IDecode AddrCal LWmem LWwrite SWmem Rexec Rfinish ImmExec ImmFinish Brcomplete lw/sw branch Immed Rtype
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Multi-cycle Implementation At most 5 cycles to implement an instruction Branch – 3 cycles Load – 5 cycles Others – 4 cycles Assume the following instruction frequencies: Branch – 12% Load – 10% Others – 78% CPI = (.12*3)+(.1*5)+(.78*4) = 3.98 cycles instruction
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Pipelined Version Each of the 5 clock cycles becomes a pipe stage IF, ID, EX, MEM, WB Use separate data and instruction memories implemented with two caches eliminates conflicts between instruction fetch and memory access
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Stages IF – use PC to address current instruction from memory; update PC ID – decode instruction and read registers from register file; do equality test on register; sign extend offset field; compute possible branch target EX – ALU operates on operands (memory address calculation, register-register operation, register-
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This document was uploaded on 02/09/2012.

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AppendixA - Appendix A Pipelining: Basic and Intermediate...

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