MIPS-R10K-uman1

Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)

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MIPS R10000 Microprocessor User’s Manual Version 2.0
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Version 2.0 of October 10, 1996 MIPS R10000 Microprocessor User's Manual viii Table of Contents 1 Introduction to the R10000 Processor MIPS Instruction Set Architecture (ISA). .................................................................................... 2 What is a Superscalar Processor?. ................................................................................................ 3 Pipeline and Superpipeline Architecture. ......................................................................... 3 Superscalar Architecture. .................................................................................................... 3 What is an R10000 Microprocessor?. ........................................................................................... 4 R10000 Superscalar Pipeline. .............................................................................................. 5 Instruction Queues. .............................................................................................................. 6 Execution Pipelines. ............................................................................................................. 6 64-bit Integer ALU Pipeline. ..................................................................................... 6 Load/Store Pipeline. .................................................................................................. 7 64-bit Floating-Point Pipeline. .................................................................................. 7 Functional Units . .................................................................................................................. 9 Primary Instruction Cache (I-cache). ................................................................................. 9 Primary Data Cache (D-cache) . .......................................................................................... 9 Instruction Decode And Rename Unit. ............................................................................. 10 Branch Unit . .......................................................................................................................... 10 External Interfaces. ............................................................................................................... 10 Instruction Queues. ........................................................................................................................ 11 Integer Queue . ...................................................................................................................... 11 Floating-Point Queue. .......................................................................................................... 11 Address Queue. .................................................................................................................... 12 Program Order and Dependencies. ............................................................................................. 13 Instruction Dependencies. ................................................................................................... 13 Execution Order and Stalling . ............................................................................................ 13 Branch Prediction and Speculative Execution . ................................................................ 14 Resolving Operand Dependencies. .................................................................................... 14 Resolving Exception Dependencies. .................................................................................. 15 Strong Ordering. ................................................................................................................... 15 An Example of Strong Ordering . ............................................................................. 16 R10000 Pipelines. ............................................................................................................................ 17 Stage 1 . ................................................................................................................................... 17 Stage 2 . ................................................................................................................................... 17 Stage 3 . ................................................................................................................................... 18 Stages 4-6 . .............................................................................................................................. 18 Floating-Point Multiplier (3-stage Pipeline). .......................................................... 18 Floating-Point Divide and Square-Root Units. ...................................................... 18 Floating-Point Adder (3-stage Pipeline) . ................................................................ 18 Integer ALU1 (1-stage Pipeline). .............................................................................. 18 Integer ALU2 (1-stage Pipeline). .............................................................................. 18 Address Calculation and Translation in the TLB . ................................................. 19 Implications of R10000 Microarchitecture on Software. ........................................................... 20
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MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 1 1. Introduction to the R10000 Processor This user’s manual describes the R10000 superscalar microprocessor for the system designer, paying special attention to the external interface and the transfer protocols. This chapter describes the following: MIPS ISA what makes a generic superscalar microprocessor specifics of the R10000 superscalar microprocessor implementation-specific CPU instructions
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Version 2.0 of October 10, 1996 MIPS R10000 Microprocessor User's Manual 2 Chapter 1. 1.1 MIPS Instruction Set Architecture (ISA) MIPS has defined an instruction set architecture (ISA), implemented in the following sets of CPU designs: MIPS I, implemented in the R2000 and R3000 MIPS II, implemented in the R6000 MIPS III, implemented in the R4400 MIPS IV, implemented in the R8000 and R10000 The original MIPS I CPU ISA has been extended forward three times, as shown in Figure 1-1; each extension is backward compatible. The ISA extensions are inclusive; each new architecture level (or version) includes the former levels. Figure 1-1 MIPS ISA with Extensions The practical result is that a processor implementing MIPS IV is also able to run MIPS I, MIPS II, or MIPS III binary programs without change. † For more ISA information, please refer to the MIPS IV Instruction Set Architecture , published by MIPS Technologies, and written by Charles Price. Contact information is provided both in the Preface , and inside the front cover, of this manual.
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MIPS-R10K-uman1 - MIPS R10000 Microprocessor Users Manual...

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