Practice_Set_5_Solution

Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)

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CS433g: Computer System Organization – Fall 2005 Practice Set 5 Memory Hierarchy Please refer to the newsgroup message for instructions on obtaining EXTRA CREDIT for this homework. Problem 1 Consider a system with 4-way set associative cache of 256 KB. The cache line size is 8 words (32 bits per word). The smallest addressable unit is a byte, and memory addresses are 64 bits long. a. Show the division of the bits in a memory address and how they are used to access the cache. Solution: We are given that the block size is 8 words (32 bytes). Therefore, the number of bytes required to specify the block offset is log 2 32 = 5 bits. The number of sets is 256 KB / (32 * 4) = 2048 sets. Therefore, the index field would require 11 bits. The remaining 64 – 11 – 5 = 48 bits are used for the tag field. b. Draw a diagram showing the organization of the cache and, using your answer from part (a), indicate how physical addresses are related to cache locations. Solution: The diagram would look similar to Figures 5.4 and/or 5.5 from H&P. We know that any physical address with the same index bits will map to the same set in the cache. The tag is used to distinguish between these physical locations. c. What memory addresses can map to set 289 of the cache? Solution: Memory locations with index bits 00100100001 will map to set 289. d. What percentage of the cache memory is used for tag bits? Solution: For each cache line (block), we have 1 tag entry. The size of the cache line is 32 * 8 = 256 bits. Therefore, the percentage of cache memory used for tag bits is 48 / (48 + 256) = 15.8%. Problem 2 You are building a computer system around a processor with in-order execution that runs at 1 GHz and has a CPI of 1, excluding memory accesses. The only instructions that read or write data from/to memory are loads (20% of all instructions) and stores (5% of all instructions).
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The memory system for this computer has a split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each. The I-cache has a 2% miss rate and 64 byte blocks, and the D-cache is a write-through, no-write-allocate cache with a 5% miss rate and 64 byte blocks. The hit time for both the I-cache and the D-cache is 1 ns. The L1 cache has a write buffer. 95% of writes to L1 find a free entry in the write buffer immediately. The other 5% of the writes have to wait until an entry frees up in the write buffer (assume that such writes arrive just as the write buffer initiates a request to L2 to free up its entry and the entry is not freed up until the L2 is done with the request). The processor is stalled on a write until a free write buffer entry is available. The L2 cache is a unified write-back, write-allocate cache with a total size of 512 KB and a block size of 64-bytes. The hit time of the L2 cache is 15ns. Note that this is also the time taken to write a word to the L2 cache. The local hit rate of the L2 cache is 80%. Also, 50% of all L2 cache blocks replaced are dirty. The 64-bit wide main memory has an access latency of 20ns (including
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Practice_Set_5_Solution - CS433g: Computer System...

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