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# Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)

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G2. Interleaved Memory and Caches Problem G2.A An eight-way (eight banks) interleaved memory is used with a cache. T_a (access time of a bank) is 80 nS. T_t (transfer time between main memory and the cache) is 20 nS/word. Assuming parallel access, serial transfer, how long does it take to access an entire line from memory on a cache miss, for the following cache organizations? (K = 16, N = 1, L = 1) 80 nS + 20 nS = 100 nS (100 nS) (K = 1, N = 128, L = 8) 80 nS + 8 * 20 nS = 240 nS (240 nS) (K = 8, N = 16, L = 32) 240 nS * 4 = 960 nS (720 nS) (K = 1, N = 8, L = 128) 240 nS * 16 = 3.84 microS (2.64 microS) Problem G2.B A pipelined processor w/ a separate instruction and data cache has five stages, a cycle time of 30 nS, and can start a new instruction on every cycle when there are no hazards. It is used with a copy-back data cache with a line size of one word, T_cache = 30 nS, and T_main = 80 nS. The hit rate in the cache is 90%. In this cache, a missed word is not passed to the processor until the entire line is received from main memory. Ignore write-backs of dirty pages. 25% of all instructions are LOADs and STORES.

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solns3 - = CS/CmpE 4760 Advanced Computer Architecture...

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