solns3

Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)

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=========================================================================== CS/CmpE 4760 Advanced Computer Architecture Winter 1998 Study Problem Set 3 - Solutions =========================================================================== G1. Tomasulo Algorithm Here is a snapshot of a system employing Tomasulo's dynamic scheduling algorithm. Assume ADDF and SUBF take 10 cycles, MULTF takes 3 cycles, and DIVF takes 5 cycles. Instruction Issue Execute Write Result LF F6, 34(R2) * * * LF F2, 45(R3) * * MULTF F0, F2, F4 * SUBF F8, F6, F2 * DIVF F10,F0, F6 * ADDF F6, F8, F2 * Name Busy? Op SV1 SV2 Producer1 Producer2 Add1 Yes SUB (Load1) Load2 Add2 Yes ADD Add1 Load2 Add3 No Mult1 Yes MULT (F4) Load2 Mult2 Yes DIV (Load1) Mult1 Register F0 F2 F4 F6 F8 F10 F12 Producer Mult1 Load2 Add2 Add1 Mult2 Busy Yes Yes No Yes Yes Yes No Part G1.A If the second load instruction is about to write its result, what is the status of the reservation stations and registers when the SUBF instruction is ready to write its result? Name Busy? Op SV1 SV2 Producer1 Producer2 Add1 Yes SUB (Load1) (Load2) Add2 Yes ADD (Load2) Add1 Mult1 No (MULT) (Load2) (F4) Mult2 No (DIV) (Mult1) (Load1) Register F0 F2 F4 F6 F8 F10 F12 Producer Add2 Add1 Busy No No No Yes Yes No No Part G1.B Return to the initial snapshot above. Suppose the instruction SUBF F8, F12, F6 issues BEFORE the second load instruction writes its results. What is the status of the reservation stations and registers AFTER the new instruction issues, but BEFORE the second load instruction writes it results? Name Busy? Op SV1 SV2 Producer1 Producer2 Add3 Yes SUB (F12) Add2 Register F6 F8 F12 Producer Add2 Add3 Busy Yes Yes No
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G2. Interleaved Memory and Caches Problem G2.A An eight-way (eight banks) interleaved memory is used with a cache. T_a (access time of a bank) is 80 nS. T_t (transfer time between main memory and the cache) is 20 nS/word. Assuming parallel access, serial transfer, how long does it take to access an entire line from memory on a cache miss, for the following cache organizations? (K = 16, N = 1, L = 1) 80 nS + 20 nS = 100 nS (100 nS) (K = 1, N = 128, L = 8) 80 nS + 8 * 20 nS = 240 nS (240 nS) (K = 8, N = 16, L = 32) 240 nS * 4 = 960 nS (720 nS) (K = 1, N = 8, L = 128) 240 nS * 16 = 3.84 microS (2.64 microS) Problem G2.B A pipelined processor w/ a separate instruction and data cache has five stages, a cycle time of 30 nS, and can start a new instruction on every cycle when there are no hazards. It is used with a copy-back data cache with a line size of one word, T_cache = 30 nS, and T_main = 80 nS. The hit rate in the cache is 90%. In this cache, a missed word is not passed to the processor until the entire line is received from main memory. Ignore write-backs of dirty pages. 25% of all instructions are LOADs and STORES.
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solns3 - = CS/CmpE 4760 Advanced Computer Architecture...

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