HW 4

HW 4 - Homework 4 CS 211 Fall 2008:Ques 1 a A 64KB direct...

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Homework 4: CS 211 Fall 2008 Ques. 1 : ) a) A 64KB, direct mapped cache has 16 byte blocks. If addresses are 32 bits, how many bits are used the tag, index, and offset in this cache ? ) b) How would the address be divided if the cache were 4-way set associative instead ? ) c) How many bits is the index for a fully associative cache. Explain your answer . Ques.2: An 8 byte, 2-way set associative (using LRU replacement) with 2 byte blocks receives requests for the following addresses (represented in binary :( 0110 , 0000 , 0010 , 0001 , 0011 , 0100 , 1001 , 0000 , 1010 , 1111 , 0111 For each access, determine the address in the cache (after the access), whether each access hits or misses, and the categorization of each miss under the “3 C” model. Fill in the worksheet in the format shown below with your answer to this question (Note that the first access is done for you). You should fill in the cache lines with the tags that reside there, with the most recently used tag first
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HW 4 - Homework 4 CS 211 Fall 2008:Ques 1 a A 64KB direct...

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