hw4_su10_sol - ECE 442 Summer 2010 Homework 4 Solutions...

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Unformatted text preview: ECE 442 Summer 2010 Homework # 4 Solutions 4.36 3 .5 V ] R = 115 [[μA] = 30.4 [k Ω] iD = 1 (μ Cox ) × W × (VGS − Vt )2 2 L iD = 115 × 10−6 = ⇒ W = 4.2 [μm] 1 2 × 60 × 10−6 × W 0.8×10−6 × [(3.5 − 5) − (−0.7)]2 4.37 VGS1 = 1.5 − 0 = 1.5 [V ] iD = 120 [μA] = 1 × 120 × 10−6 × 2 ⇒ W1 = 8 [μm] VGS2 = 3.5 − 1.5 = 2 [V ] 120 [μA] = 1 2 × 120 × 10−6 × ⇒ W1 = 2 [μm] R = 5 [V ]−[3.5 V ] = 12.5 [k Ω] 120 μA W1 1×10−6 W2 1×10−6 1 × (1.5 − 1)2 × (2 − 1)2 4.41 VI = VGS = 5 [V ], Vo = VDS = 0.05 [V ] .05 rDS = 50 [Ω] = ViDS ⇒ iD = 050 = 0.001 = 1 [mA] D VDD −Vo 5−0.05 R= = 1 = 4.95 [k Ω] iD VDS < VGS − Vt ⇒triode region V2 iD = kn W (VGS − Vt ) × VDS − DS L 2 1 × 10−3 = 100 × 10−6 W (5 − 1) × 0.05 − L 0.052 2 ⇒ 4.44 a) 2 −(− VGS2 = −V2 , I = V1×1035) = 1 × 2 × (−V2 − 1)2 2 ⇒ V2 + 5 = V22 + 2 × V2 + 1 ⇒ V22 + V2 − 4 = 0 ⇒ 2 W L = 50 V21 = 1.55 [V ], V22 = −2.56 [V ] V2 = 1.55 [V ] is not acceptable because that is not possible for an NMOS it results in VGS < 0 ⇒ V2 = −2.56 [V ] VGS1 = 5 − V1 2 −(− iD1 = iD2 ⇒ V1×1035) = 1 × 2 × (VGS1 − 1)2 ⇒ 2 2.44 = (4 − V1 )2 ⇒ 4 − V1 = ±1.56 ⇒ ⇒ V11 = 2.44 [V ], V12 = 5.56 [V ] V12 = 5.56 [V ]- is ⇒ V1 = 2.44 [V ] not acceptable because it results in VGS < 0 b) V5 3 ID = 10−V3 = 1×103 ⇒ 10 − V3 = V5 (1) 1×10 V5 iD1 = 1×103 = 1 × 2 × 10−3 × (VGS1 − Vt )2 2 ⇒ V5 = (VGS1 − 1)2 = (V3 − V4 − 1)2 (2) V5 iD2 = 1×103 = 1 × 2 × 10−3 × (VGS2 − Vt )2 2 ⇒ V5 = (V4 − V5 − 1)2 (2) and (3) (3) ⇒ (V3 − V4 − 1)2 = (V4 − V5 − 1)2 ⇒ V5 = 2 V4 − V3 (4) (1) and (4) ⇒ 10 − V3 = 2 V4 − V3 ⇒ V4 = 5 [V ] 2 (3) ⇒ V5 = (V5 − 4) ⇒ V51 = 6.55 [V ], V52 = 2.45 [V ] V51 = 6.55 [V ] is not good ⇒ V5 = 2.45 [V ] (1) ⇒ 10 − V3 = V5 ⇒ V 3 = 7.55 [V ] 4.48 3 a) VGS1 = VGS2 = 0 − V3 = −V3 Assuming that transistors are in saturation, since kn and the same for both devices, we can write: W L are [ iD1 = iD2 = 200 2μA] = 100 [μA] 100 × 10−6 = 1 × 100 × 10−6 × 20 × (VGS − 1)2 ⇒ 0.1 = (VGS − 1)2 2 ⇒ VGS = 1.32 [V ] = −V3 ⇒ V3 = −1.32 V V1 = V − R × iD = 5 − 40 × 103 × 100 × 10−6 = 1 [V ] V2 = V1 = 1 [V ] b) W L1 = 1.5 × W L2 = 20 Again, assume transistor are saturated: VGS1 = VGS2 = −V3 ( W )1 iD1 L iD2 = ( W ) = 1.5 ⇒ iD1 = 1.5 × iD2 (1) L2 iD1 + iD2 = 200 [μA] (2) (1) and (2) ⇒ iD1 = 120 [μA], iD2 = 80 [μA] iD1 = 120 [μA] = 1 2 × 100 × 10−6 × 20 × (VGS − 1)2 ⇒ VGS = 1.35 [V ] ⇒ V3 = −1.35 [V ] V1 = V − R × iD1 = 5 − 40 × 103 × 120 × 10−6 = 0.2 [V ] V2 = V − R × iD2 = 5 − 40 × 103 × 80 × 10−6 = 1.8 [V ] VDS1 = 0.2 + 1.35 = 1.55 > VGS − Vt VDS2 = 1.8 + 1.35 = 3.15 > VGS − Vt This conrms that both transistors are indeed saturated and our assumption was correct. 4 10.25 For Y = A + B (C + D), the PDN can be drawn directly, and then the PUN as dual: 10.32 ¯¯ ¯¯ ¯¯ ¯¯ ¯ ¯¯ Sum: S = AB C + AB C + ABC + ABC = A(B C + BC ) + A(B C + BC ) ¯ ¯ ¯ Carry: C = AB C + ABC + ABC + ABC = AB + AC + BC = A(B + C )+ BC 5 ...
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