hw10_su10_sol - VVDD VDD 0 DC 5 RB VR 0 78k M3 VO VR VDD...

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The circuit schematic is as shown: V V V V V V V L W k V V L W k I A I L W L W I I ov tp GS ov ov p t GS p ref ref ref bias 078 . 1 ) 378 . 0 ( 7 . 0 378 . 0 10 70 50 2 ) / ( 2 1 ) ( ) / ( 2 1 50 ) / ( ) / ( 2 3 ' 2 3 ' 4 3 The other solution of the quadratic equation is discarded, since PMOS must have VGS<-0.7V to be on. k E I V R V V V V V ref D S GS G D 78 6 50 922 . 3 922 . 3 5 078 . 1
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The circuit file in HSPICE is as follows: *Homework 13 - Cascode AC analysis .lib 'models15.txt' MOS .OPTIONS LIST NODE POST
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Unformatted text preview: VVDD VDD 0 DC 5 RB VR 0 78k M3 VO VR VDD VDD PCH W=15u L=1.5u M4 VR VR VDD VDD PCH W=15u L=1.5u M1 VX VG1 0 0 NCH W=15u L=1.5u M2 VO VG2 VX 0 NCH W=15u L=1.5u V1 VG2 0 2 V2 VG1 VI0 AC 1 V4 VI0 0 DC 1 .AC DEC 5 100k 100MEG .PRINT AC VDB(VO) .OPTION POST .END The HSPICE simulation results are as shown in the plot, with 3-dB bandwidth of around 40MHz....
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This note was uploaded on 02/08/2012 for the course ECE 342 taught by Professor Nareshshanbhag during the Spring '11 term at University of Illinois, Urbana Champaign.

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hw10_su10_sol - VVDD VDD 0 DC 5 RB VR 0 78k M3 VO VR VDD...

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