1_blackfin_expectations1_0Release

1_blackfin_expectations1_0Release - Device and Roadmap...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
Support Across The Board
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Blackfin ® Speedway Workshop Support Across The Board
Background image of page 2
Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. Welcome Workshop Expectations Designed to give a technical overview and hands-on experience through labs with the Blackfin ADSP-BF537 device Provide highlights and an overview of the architecture Create a starting point of information Grow familiarity with available software and hardware tools
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. Welcome Workshop Expectations (What it is NOT) Comprehensive know-it-all course that covers the Blackfin architecture from beginning to end (too time limited!) “How to” code or “how to” design seminar
Background image of page 4
Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. Agenda
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Device and Roadmap Introduction Device Architecture VisualDSP++ Kernel (VDK) Light-Weight Internet Protocol (LwIP) 3 Labs (dispersed throughout the day) Copyright Avnet, Inc., Analog Devices, Inc. All rights reserved. 9:00 9:10 10 mins Welcome and Introductions 9:10 9:45 35 mins Blackfin Introduction and Product Roadmap 9:45 10:15 30 mins Lab 1 Bubble Sort 10:15 10:30 15 mins Break 10:30 12:00 90 mins Blackfin Core, Memory, and Peripherals 12:00 1:00 60 mins Lunch 1:00 1:45 45 mins Lab 2 Instructor-Led FIR Filter 1:45 2:15 30 mins VDK Kernel 2:15 2:30 15 mins Break 2:30 3:00 30 mins Light-Weight IP (LwIP) 3:00 3:45 45 mins Lab 3 TCP/IP Stack 3:45 4:00 15 mins Closing Comments Schedule...
View Full Document

Page1 / 6

1_blackfin_expectations1_0Release - Device and Roadmap...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online