3_BFCore1_0Release

3_BFCore1_0Release - Support Across The Board ™ Blackfin Speedway Presentation Core Memory and Peripherals Copyright © Avnet Inc Analog Devices

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Unformatted text preview: Support Across The Board ™ Blackfin Speedway Presentation Core, Memory, and Peripherals Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. Blackfin as a Convergent Processor Commonly asked questions: What makes Blackfin a “convergent” processor? What architectural features enable convergent processing? What type of performance can Blackfin achieve from a networking standpoint? Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. Agenda • Blackfin “Convergent Processing” • Blackfin Core Details – Registers – ALU, MAC, Shifter – Sequencer, Pipeline, Event Controller • Blackfin Memory – Memory Architecture – Cache • Peripherals – General Peripherals (UART,SPORT, SPI, TWI, WD, RTC) – Ethernet, CAN – PPI – DMA Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. What architectural features enable convergent processing? • Integrated instruction set architecture – Single instruction set for signal processing and control • Programmable interrupt levels – Real-time tasks get the highest priority level • Memory protection with an MMU – Regions of memory can be protected from access • Networked peripherals in addition high speed connectivity to ADC, DAC and video peripherals • Unified address space and byte addressable • Support for User and Supervisor modes • Robust ALU including both signal processing functions as well as traditional MPC/MPU functions Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. What makes Blackfin a Convergent Processor? • Blackfin has a mature compiler that produces highly optimized code (with an option to produce “dense code” for control applications) • Blackfin processors come with a full suite of C-based device drivers for peripherals – Fully documented, common APIs • Blackfin beats the competition in terms of DSP benchmarks and it is on par with ARM code density benchmarks • Blackfin is scalable across a broad set of applications – ADSP-BF531 on the low end – Dual-core ADSP-BF561 on the high end • Latest peripheral integration expands connectivity to network-based applications • Large set of options for OS and kernel support, including uCLinux Support Across The Board ™ Blackfin ADSP-BF536/537 Architecture Overview Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. Blackfin Architecture Basics Core Registers ALU, MAC, Shifter Data Addressing Modes Program Sequencer Event Controller Peripherals Instruction Set Overview Memory Architecture Cache Support Across The Board ™ Section 1 Register File Copyright © Avnet, Inc., Analog Devices, Inc. All rights reserved. Accessing Registers • Blackfin processors are register-intensive devices – All computations are performed on data contained in registers – All peripherals are setup using registers – Memory is accessed using pointers in address registers • There are two types of Blackfin processor registers – Core registers – Memory-mapped registers (MMRs) Copyright © Avnet, Inc., Analog Devices, Inc. Copyright © Avnet, Inc....
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This note was uploaded on 02/10/2012 for the course ECE 3551 taught by Professor Staff during the Spring '11 term at FIT.

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3_BFCore1_0Release - Support Across The Board ™ Blackfin Speedway Presentation Core Memory and Peripherals Copyright © Avnet Inc Analog Devices

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