195925639ADSP_BF536_7_pre - a FEATURES Preliminary...

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a Preliminary Technical Data TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Blackfin ® Embedded Processor ADSP-BF536/ADSP-BF537 Rev. PrE Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 www.analog.com Fax:781/461-3113 © 2005 Analog Devices, Inc. All rights reserved. FEATURES Up to 600 MHz High-Performance Blackfin Processor Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of Programming and Compiler-Friendly Support Advanced Debug, Trace, and Performance-Monitoring 0.8V±to ±1.2V±Core±V DD with On-chip Voltage Regulation 2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins 182-Ball MBGA and 208-Ball Sparse MBGA Packages Lead Bearing and Lead Free Package Choices MEMORY Up to 132K Bytes of On-Chip Memory: 16K Bytes of Instruction SRAM/Cache 48K Bytes of Instruction SRAM 32K Bytes of Data SRAM/Cache 32K Bytes of Data SRAM 4K Bytes of Scratchpad SRAM External Memory Controller with Glueless Support for SDRAM and Asynchronous 8/16-Bit Memories Flexible Booting Options from External Flash, SPI and TWI Memory or from SPI, TWI, and UART Host Devices Two Dual-Channel Memory DMA Controllers Memory Management Unit Providing Memory Protection PERIPHERALS IEEE 802.3-Compliant 10/100 Ethernet MAC Controller Area Network (CAN) 2.0B Interface Parallel Peripheral Interface (PPI), Supporting ITU-R 656 Video Data Formats Two Dual-Channel, Full-Duplex Synchronous Serial Ports (SPORTs), Supporting Eight Stereo I 2 S Channels 12 Peripheral DMAs, 2 Mastered by the Ethernet MAC Two Memory-to-Memory DMAs With External Request Lines Event Handler With 32 Interrupt Inputs Serial Peripheral Interface (SPI)-Compatible Two UARTs with IrDA® Support Two-Wire Interface (TWI) Controller Eight 32-Bit Timer/Counters with PWM Support Real-Time Clock (RTC) and Watchdog Timer 32-Bit Core Timer 48 General-Purpose I/Os (GPIOs), 8 with High Current Drivers On-Chip PLL Capable of 1x to 63x Frequency Multiplication Debug/JTAG Interface Figure 1. Functional Block Diagram VOLTAGE REGULATOR DMA CONTROLLER EVENT CONTROLLER/ CORE TIMER ETHERNET MAC UART 0-1 TIMERS 0-7 PPI SPORT1 SPI EXTERNAL PORT FLASH, SDRAM CONTROL BOOT ROM JTAG TEST AND EMULATION WATCHDOG TIMER L1 INSTRUCTION MEMORY L1 DATA MEMORY MMU B CORE / SYSTEM BUS INTERFACE RTC TWI CAN SPORT0 GPIO PORT F GPIO PORT H GPIO PORT G PORT J
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Rev. PrE | Page 2 of 64 | July 2005 ADSP-BF536/BF537 Preliminary Technical Data TABLE OF CONTENTS General Description .
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  • Spring '11
  • Staff
  • Serial Peripheral Interface Bus, Central processing unit, Interrupt, Interrupt handler, Direct memory access

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195925639ADSP_BF536_7_pre - a FEATURES Preliminary...

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